TWI827618B - 電漿蝕刻方法 - Google Patents

電漿蝕刻方法 Download PDF

Info

Publication number
TWI827618B
TWI827618B TW108120518A TW108120518A TWI827618B TW I827618 B TWI827618 B TW I827618B TW 108120518 A TW108120518 A TW 108120518A TW 108120518 A TW108120518 A TW 108120518A TW I827618 B TWI827618 B TW I827618B
Authority
TW
Taiwan
Prior art keywords
during
gas
substrate
etching
mask
Prior art date
Application number
TW108120518A
Other languages
English (en)
Other versions
TW202002073A (zh
Inventor
乎瑪 哈許拉夫
凱文 瑞德爾
艾力克斯 伍德
Original Assignee
英商Ｓｐｔｓ科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英商Ｓｐｔｓ科技公司 filed Critical 英商Ｓｐｔｓ科技公司
Publication of TW202002073A publication Critical patent/TW202002073A/zh
Application granted granted Critical
Publication of TWI827618B publication Critical patent/TWI827618B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

根據本發明提供有一種電漿蝕刻矽基化合物半導體基材的方法，該方法包含提供該基材於一蝕刻腔室內且在該基材上執行循環程序，每個循環包含：將一蝕刻劑氣體供給至該腔室中，激發該氣體成一電漿，且使用該電漿在該基材上執行一蝕刻步驟；以及執行一脫附步驟，其中在該脫附步驟期間，所供給至該蝕刻腔室中之唯一氣體係一惰性氣體，以便使在該蝕刻步驟期間已吸附於該基材之表面的反應性物種得以自該基材之表面脫附。

Description

電漿蝕刻方法
發明領域 本發明係關於一種電漿蝕刻方法，特別地係關於一種電漿蝕刻矽基化合物半導體基材的方法。
發明背景 微溝槽化(micro-trenching)係一術語，用以指稱於電漿蝕刻特徵之側壁基底處之局部蝕刻，其會導致所述特徵之整個底部蝕刻深度的大差異。微溝槽化會在蝕刻離子以擦角抵達所述側壁時被引發。這些離子反射離開所述側壁且堆積在溝槽之角落，導致一局部較高的蝕刻率。圖4顯示在使用SF6 /O2 /He程序氣體之SiC電漿蝕刻期間一典型經微溝槽化之結構。微溝槽化係不受歡迎的，因為其會導致有缺陷的半導體裝置，尤其若其微溝槽穿透至下方電極時。
用於避免微溝槽化之典型方法不是依賴於調整DC自偏壓以降低離子能量，就是依賴於使用一聚合反應氣體(如，SiF4 、C4F8 、CHF3 )。然而，這些方法並非總是保證避免微溝槽化，且視蝕刻需求而定可能會造成一不夠理想的蝕刻表現，諸如低蝕刻率或選擇性。使用一聚合物形成氣體也會對蝕刻腔室之清潔具有不利的影響，使得該腔室需要頻繁的機械清潔。
US 2007/0281462揭露一種用於克服微溝槽化問題之方法，其中一第一電漿蝕刻步驟係由一第二電漿蝕刻步驟接續以移除在該第一電漿蝕刻步驟期間所生成的任何微溝槽。
本發明之一目的係要避免或至少降低在電漿蝕刻期間的微溝槽化。
發明概要 根據本發明之一態樣，提供有一種電漿蝕刻矽基化合物半導體基材的方法，該方法包含： (a) 提供該基材於一蝕刻腔室內； (b) 在該基材上執行循環程序，該循環程序的每個循環包含： i. 將一蝕刻劑氣體供給至該蝕刻腔室中，激發該蝕刻劑氣體成一電漿且使用該電漿在該基材上執行一蝕刻步驟；以及 ii. 執行一脫附步驟，其中在該脫附步驟期間，所供給至該蝕刻腔室中之唯一氣體係一惰性氣體，以便使在該蝕刻步驟期間已吸附於該基材之表面的反應性物種得以自該基材之表面脫附。
本案發明人已發現藉由在進入下一個步驟或循環前提供一脫附步驟，在該脫附步驟中停止任何反應性物種流入該蝕刻腔室且僅有一惰性氣體被供給至該腔室中達一預定時間量，可實質降低或完全消除微溝槽化。據假設，該脫附步驟提供時間以供任何反應性物種自該基材之表面脫附，從而降低反應性物種的數目至低於微溝槽形成所需的臨限位準。
以此方式，可降低或消除微溝槽化，而無需聚合反應氣體來生成一鈍化層，其如以上所解釋會對腔室清潔具有不利的影響。
術語「化合物半導體」指稱一由二或更多元素製成的半導體。術語「矽基化合物半導體」指稱複數元素中之一者為矽的一化合物半導體。
在所述蝕刻步驟期間，該蝕刻劑氣體可包含一含氟氣體。例如，該蝕刻劑氣體可包含六氟化硫(SF6 )。任擇地，或此外，該蝕刻劑氣體可包含CF4 或C4 F8 。該含氟氣體提供所述電漿中氟根(fluorine radicals)來源，所述氟根於所述基材之表面反應以執行所述蝕刻。
該蝕刻步驟期間之含氟氣體的流率可為約10-50 sccm (每分鐘標準立方公分)。
在每個循環中之蝕刻步驟的持續時間可為約0.5-5秒。
所述蝕刻劑氣體可進一步包含一惰性氣體，如氦、氬、氪或氙。該惰性氣體的流率在該蝕刻步驟期間可為約15-40 sccm。
在一些具體例中，該蝕刻劑氣體由一含氟氣體(如，SF6 )及一惰性氣體(如，He、Ar、Kr或Xe)組成；即，在該蝕刻步驟期間所供給至該蝕刻腔室之僅有的氣體係一含氟氣體及一惰性氣體。
在一些具體例中，該蝕刻劑氣體可進一步包含一含氧氣體(如，O2 或O3 )。該含氧氣體的流率可小於所述含氟氣體的流率。該含氧氣體可在所述蝕刻步驟期間流動達僅該蝕刻步驟總時間之一部份，及/或達僅總循環數目之一子集。
在所述脫附步驟期間，供給至該蝕刻腔室之惰性氣體可為，例如，氦、氬、氪或氙、或具複數惰性氣體之一混合物。該惰性氣體在該脫附步驟期間的流率可為約15-40 sccm。
每個循環中之脫附步驟的持續時間可為至少0.5秒。在一些具體例中，該脫附步驟之持續時間可為至少1秒。在一些具體例中，該脫附步驟之持續時間可為至少1.5秒。在一些具體例中，該脫附步驟之持續時間可為至少2秒。最大持續時間將由生產力考量來控制，但可例如為約5秒。該脫附步驟之持續時間可例如為約0.5-5秒。一較短脫附步驟將造成一較快之循環，但若該脫附步驟太短時，微溝槽化可能再次發生或微溝槽化之程度可能係不可接受的。
在執行所述循環程序之前，用於保護所述基材在該蝕刻步驟期間擬不被蝕刻之區域的一遮罩層，如一SiO2 遮罩層，可被提供於該基材上。在此事例中，該循環程序之每個循環可進一步包含： iii. 執行一遮罩強化步驟以供強化該遮罩層，其中在該遮罩強化步驟期間，僅有一含氧氣體及，可選地(optionally)，一惰性氣體被供給至所述蝕刻腔室中； 其中該蝕刻步驟、該脫附步驟及該遮罩強化步驟可在每個循環期間以任一順序執行。
該遮罩強化步驟對於降低微溝槽化係非必要的且通常不影響微溝槽化的範圍。然而，藉由提供一遮罩強化步驟，該遮罩層之劣化可於每個循環期間被減輕，從而容許較大的蝕刻深度。
該等步驟不需以任一特別順序執行。例如，在一個具體例中，該蝕刻步驟可先執行，隨後為該脫附步驟，隨後為該遮罩強化步驟。在另一具體例中，該蝕刻步驟可先執行，隨後為該遮罩強化步驟，隨後為該脫附步驟。在一另外具體例中，該脫附步驟可先執行，隨後為該蝕刻步驟，隨後為該遮罩強化步驟。
在該遮罩強化步驟期間，該含氧氣體可為O2 或O3 。
在一具體例中，在該遮罩強化步驟期間供給至該蝕刻腔室之氣體由下列組成：一含氧氣體(如，O2 或O3 )及，可選地，一惰性氣體，如氦、氬、氪或氙。若一惰性氣體在該遮罩強化步驟期間被供給時，在該遮罩強化步驟期間該惰性氣體的流率可為約15-40 sccm。
在該遮罩強化步驟期間該含氧氣體的流率可小於或等於30 sccm。在一些具體例中，在該遮罩強化步驟期間該含氧氣體的流率可小於或等於25 sccm。在一些具體例中，在該遮罩強化步驟期間該含氧氣體的流率可小於或等於20 sccm。在一些具體例中，在該遮罩強化步驟期間該含氧氣體的流率可小於或等於15 sccm。在一些具體例中，在該遮罩強化步驟期間該含氧氣體的流率可為約 3-12 sccm。
每個循環中之該遮罩強化步驟之持續時間可為約0.5-5秒。
本發明方法可為一種電漿蝕刻矽基化合物半導體基材的方法，其中該基材係由SiC製成。
較佳實施例之詳細說明 圖1顯示一要使用本發明方法蝕刻的基材110。基材110在此範例中係由碳化矽(SiC)製成。在基材110之頂部上有一由二氧化矽(SiO2 )製成的遮罩120。在所述蝕刻程序期間，因材料之差異，遮罩120之蝕刻率將低於基材110之蝕刻率。遮罩120因此作為基材110上方之一屏障以保護基材110之擬不被蝕刻的部分。基材110之擬被蝕刻的部分係在該頂部上保持暴露。
基材110係在一典型電漿蝕刻設備(未顯示)中蝕刻，該設備包含一蝕刻腔室，基材110係在該蝕刻腔室中被支撐於一平台上。一能蝕刻SiC基材之示範性高密度電漿蝕刻工具可為一SPTS Omega® Synapse™。該蝕刻腔室包含一氣體入口及一氣體出口，氣體可通過該氣體入口被引入該腔室，且氣體可通過該氣體出口離開該腔室。
圖2顯示一根據本發明之範例循環程序的流程圖。在所描述的此具體例中，一蝕刻步驟210係先執行，隨後為一遮罩強化步驟220，隨後為一脫附步驟230。然而，該等步驟不需以此順序執行，而能以任一順序重新安排。再者，遮罩強化步驟220對於降低或避免微溝槽化之目的而言係可選的(optional)。遮罩強化步驟220有利地容許一較大的蝕刻深度被達成。
表1顯示每個步驟的典型參數。典型操作壓力可為1-50 mTorr(大約0.13-6.67 Pa)，且一典型RF偏功率可為250-1000 W。表1
在蝕刻步驟210期間，具SF6 及He之一蝕刻劑氣體混合物係供給至蝕刻腔室。該蝕刻劑氣體混合物接著被激發成電漿而用來蝕刻基材110之一部分以開始形成一溝槽。雖此範例中蝕刻步驟210期間沒有O2 流，但在一些具體例中，該蝕刻劑氣體混合物可進一步包含O2 。在該蝕刻步驟期間添加O2 可增加F*根，因而有利地增加蝕刻率。然而，F*根之增加也將使微溝槽化更可能發生。若O2 係要併入該蝕刻劑氣體混合物時，O2 之流率可典型地小於SF6 之流率。在一些具體例中，O2 可僅於該蝕刻步驟210之總時間的一部分期間及/或僅於總循環數目之一子集期間添加。在該蝕刻步驟210期間該O2 之流率及該O2 流之持續時間可被最佳化以在不發生微溝槽化下增加蝕刻率。
在遮罩強化步驟220期間，停止供給SF6 至該蝕刻腔室，反而是供給具O2 及He的一氣體混合物至該蝕刻腔室。該O2 氣體促進化合物之形成以強化遮罩層120，以致該溝槽可被蝕刻至一較大的深度。此步驟對微溝槽化不具有顯著影響且係可選的。
在脫附步驟230期間，所供給至該蝕刻腔室之唯一氣體係He。在此步驟期間供給僅一惰性氣體得以使已吸附至基材110之經蝕刻表面的任何反應性蝕刻物種有時間自該表面脫附，其降低微溝槽化。
就該脫附步驟而言，增加He之流率對降低微溝槽化並不具有大影響。該脫附步驟之步驟時間係降低微溝槽化的更重要因子。增加該脫附步驟之步驟時間導致降低的微溝槽化或無微溝槽化；然而，這卻帶來增加執行每個循環之總時間的成本。超過2秒之脫附步驟時間典型地造成一無微溝槽之蝕刻。
步驟210、220及230形成一個循環，其可被重複直到所欲的蝕刻深度已被達到。例如，使用顯示於表1之程序參數，該程序可被重複達20個循環以產生具有大約1µm之深度的一溝槽。較大之蝕刻深度可使用本發明來達成，同時降低或避免微溝槽化。
圖3顯示使用根據本發明之使用表1程序參數之一種3步驟循環程序來電漿蝕刻的一溝槽之橫截面。所例示之溝槽顯示出無微溝槽化。
110‧‧‧基材 120‧‧‧遮罩、遮罩層 210、220、230‧‧‧步驟
僅作為範例，本發明現將參照隨附圖式來描述，其中： 圖1顯示一基材之示意圖，在該基材上可執行本發明方法。 圖2顯示依照本發明之一循環程序的示意圖。 圖3顯示使用根據本發明之一方法的電漿蝕刻溝槽的橫截面。 圖4顯示微溝槽化已發生之一電漿蝕刻溝槽的橫截面。
210、220、230‧‧‧步驟

Claims (20)

  1. 一種電漿蝕刻矽基化合物半導體基材的方法，該方法包含：(a)提供該基材於一蝕刻腔室內；(b)在該基材上執行循環程序，該循環程序的每個循環包含：i.將一蝕刻劑氣體供給至該蝕刻腔室中，激發該蝕刻劑氣體成一電漿且使用該電漿在該基材上執行一蝕刻步驟；以及ii.執行一脫附(desorption)步驟，其中在該脫附步驟期間，所供給至該蝕刻腔室中之唯一氣體係一惰性氣體，以便使在該蝕刻步驟期間已吸附於該基材之表面的反應性物種得以自該基材之表面脫附。
  2. 如請求項1之方法，其中該蝕刻劑氣體包含一含氟氣體。
  3. 如請求項2之方法，其中在該蝕刻步驟期間該含氟氣體的流率係約10-50sccm。
  4. 如請求項2或3之方法，其中該含氟氣體係SF6。
  5. 如請求項1至3中任一項之方法，其中該蝕刻劑氣體進一步包含一惰性氣體。
  6. 如請求項5之方法，其中在該蝕刻步驟期間該惰性氣體的流率係約15-40sccm。
  7. 如請求項5之方法，其中在該蝕刻劑氣體 中之該惰性氣體係He。
  8. 如請求項1至3中任一項之方法，其中該蝕刻劑氣體由SF6及一惰性氣體組成。
  9. 如請求項1至3中任一項之方法，其中在每個循環中之該蝕刻步驟之持續時間係約0.5-5秒。
  10. 如請求項1至3中任一項之方法，其中在該脫附步驟期間所供給之該惰性氣體係He。
  11. 如請求項1至3中任一項之方法，其中在該脫附步驟期間該惰性氣體的流率係約15-40sccm。
  12. 如請求項1至3中任一項之方法，其中在每個循環中之該脫附步驟之持續時間係約0.5-5秒。
  13. 如請求項1至3中任一項之方法，其中在每個循環中之該脫附步驟之持續時間係至少2秒。
  14. 如請求項1至3中任一項之方法，其中在執行該循環程序之前，用於保護該基材在該蝕刻步驟期間擬不被蝕刻之區域的一SiO2遮罩層係提供於該基材上；且其中該循環程序之每個循環進一步包含：iii.執行一遮罩強化步驟以供強化該遮罩層，其中在該遮罩強化步驟期間，僅一含氧氣體及，可選地(optionally)，一惰性氣體被供給至該蝕刻腔室中；其中該蝕刻步驟、該脫附步驟以及該遮罩強化步驟可在每個循環期間以任一順序執行。
  15. 如請求項14之方法，其中在該遮罩強化步驟期間所供給之該含氧氣體係O2或O3。
  16. 如請求項14之方法，其中在該遮罩強化步驟期間，所供給至該蝕刻腔室之氣體由O2及，可選地，一惰性氣體組成。
  17. 如請求項14之方法，其中在該遮罩強化步驟期間該含氧氣體的流率係小於或等於30sccm。
  18. 如請求項14之方法，其中在該遮罩強化步驟期間該含氧氣體的流率係約3-12sccm。
  19. 如請求項14之方法，其中在每個循環中之該遮罩強化步驟之持續時間係約0.5-5秒。
  20. 如請求項1至3中任一項之方法，其中該基材係由SiC製成。
TW108120518A 2018-06-25 2019-06-13 電漿蝕刻方法 TWI827618B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB1810387.9A GB201810387D0 (en) 2018-06-25 2018-06-25 Method of plasma etching
GB1810387.9 2018-06-25

Publications (2)

Publication Number Publication Date
TW202002073A TW202002073A (zh) 2020-01-01
TWI827618B true TWI827618B (zh) 2024-01-01

Family

ID=63042490

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108120518A TWI827618B (zh) 2018-06-25 2019-06-13 電漿蝕刻方法

Country Status (6)

Country Link
US (1) US11037793B2 (zh)
EP (1) EP3588537B1 (zh)
KR (1) KR102517020B1 (zh)
CN (1) CN110634738A (zh)
GB (1) GB201810387D0 (zh)
TW (1) TWI827618B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130115772A1 (en) * 2010-07-12 2013-05-09 Spp Technologies Co., Ltd. Etching Method
TW201528367A (zh) * 2013-12-25 2015-07-16 Advanced Micro Fabrication Equipment Shanghai Co Ltd 電漿蝕刻方法和系統
US20160293432A1 (en) * 2015-03-30 2016-10-06 Tokyo Electron Limited Method for atomic layer etching
US20180114700A1 (en) * 2016-10-24 2018-04-26 Samsung Electronics Co., Ltd. Method of atomic layer etching and method of fabricating semiconductor device using the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5624529A (en) * 1995-05-10 1997-04-29 Sandia Corporation Dry etching method for compound semiconductors
ATE251341T1 (de) 1996-08-01 2003-10-15 Surface Technology Systems Plc Verfahren zur ätzung von substraten
KR20040096377A (ko) 2003-05-09 2004-11-16 삼성전자주식회사 산화막 및 산질화막 형성 방법
JP5061506B2 (ja) 2006-06-05 2012-10-31 富士電機株式会社 炭化珪素半導体装置の製造方法
JP5135879B2 (ja) 2007-05-21 2013-02-06 富士電機株式会社 炭化珪素半導体装置の製造方法
JP5135885B2 (ja) * 2007-05-24 2013-02-06 富士電機株式会社 炭化珪素半導体装置の製造方法
US8278513B2 (en) 2009-07-17 2012-10-02 Monsanto Technology Llc Soybean variety A1016281
US8901554B2 (en) 2011-06-17 2014-12-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including channel formation region including oxide semiconductor
KR101745686B1 (ko) * 2014-07-10 2017-06-12 도쿄엘렉트론가부시키가이샤 기판의 고정밀 에칭을 위한 방법
TWI687970B (zh) * 2016-02-22 2020-03-11 東京威力科創股份有限公司 圖案化層之循環式蝕刻的方法
TWI749099B (zh) 2016-11-09 2021-12-11 日商東京威力科創股份有限公司 碳基膜之自限性循環蝕刻方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130115772A1 (en) * 2010-07-12 2013-05-09 Spp Technologies Co., Ltd. Etching Method
TW201528367A (zh) * 2013-12-25 2015-07-16 Advanced Micro Fabrication Equipment Shanghai Co Ltd 電漿蝕刻方法和系統
US20160293432A1 (en) * 2015-03-30 2016-10-06 Tokyo Electron Limited Method for atomic layer etching
US20180114700A1 (en) * 2016-10-24 2018-04-26 Samsung Electronics Co., Ltd. Method of atomic layer etching and method of fabricating semiconductor device using the same

Also Published As

Publication number Publication date
EP3588537A1 (en) 2020-01-01
US11037793B2 (en) 2021-06-15
TW202002073A (zh) 2020-01-01
GB201810387D0 (en) 2018-08-08
EP3588537B1 (en) 2022-02-16
KR102517020B1 (ko) 2023-03-31
US20190393044A1 (en) 2019-12-26
CN110634738A (zh) 2019-12-31
KR20200000817A (ko) 2020-01-03

Similar Documents

Publication Publication Date Title
KR101330650B1 (ko) 에칭 방법
JP4852196B2 (ja) 深開口部を形成するためにプラズマ処理室内でシリコン層をエッチングする方法
JP2915807B2 (ja) 六弗化イオウ、臭化水素及び酸素を用いる珪化モリブデンのエッチング
US9318341B2 (en) Methods for etching a substrate
TWI416609B (zh) 電漿處理系統之用於將遮罩底切及凹口減至最少的方法
CN107644812B (zh) 基片刻蚀方法
KR20020061004A (ko) 실리콘의 금속 마스크 에칭
US20240006159A1 (en) Post-processing of Indium-containing Compound Semiconductors
KR101337832B1 (ko) 플라즈마 처리 시스템의 노치 스탑 펄싱 공정
EP1599894A2 (en) Method to improve profile control and n/p loading in dual doped gate applications
TWI827618B (zh) 電漿蝕刻方法
US11443954B2 (en) Method and apparatus for controlling a shape of a pattern over a substrate
US10586696B2 (en) Halogen abatement for high aspect ratio channel device damage layer removal for EPI growth
JP2007134660A (ja) ドライエッチング方法
KR20220082979A (ko) 기판 처리 장치를 이용한 기판 처리 방법
JP2017079273A (ja) プラズマ処理方法
JP2006060089A (ja) シリコン材のエッチング方法とその装置並びにシリコン成形体
KR20020050917A (ko) 반도체 소자의 제조방법