TWI816801B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI816801B
TWI816801B TW108118467A TW108118467A TWI816801B TW I816801 B TWI816801 B TW I816801B TW 108118467 A TW108118467 A TW 108118467A TW 108118467 A TW108118467 A TW 108118467A TW I816801 B TWI816801 B TW I816801B
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Taiwan
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germanium
fin
layer
silicon
semiconductor layer
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TW108118467A
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TW202002043A (zh
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林哲宇
陳建鴻
蕭文助
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台灣積體電路製造股份有限公司
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Abstract

在一實施例中，裝置包括：基板；第一半導體層，自基板延伸，且第一半導體層包括矽；第二半導體層，位於第一半導體層上，且第二半導體層包括矽鍺，其中第二半導體層的邊緣部份具有第一鍺濃度，第二半導體層的中心部份具有第二鍺濃度，第二鍺濃度小於第一鍺濃度，且第二半導體層的邊緣部份包括第二半導體層的側部與上表面；閘極堆疊，位於第二半導體層上；輕摻雜源極/汲極區，位於第二半導體層中，且輕摻雜源極/汲極區與閘極堆疊相鄰；以及源極與汲極區，延伸至輕摻雜源極/汲極區中。

Description

半導體裝置與其形成方法
本發明實施例關於半導體裝置，更特別關於增加鰭狀物通道區中的鍺濃度的方法。
半導體裝置用於多種電子應用，比如個人電腦、手機、數位相機、與其他電子設備。半導體裝置的製作方法通常為依序沉積絕緣或介電層、導電層、與半導體層的材料於半導體基板上，並採用微影圖案化多種材料層，以形成電路構件與單元於半導體基板上。
半導體產業持續減少最小結構尺寸以持續改良多種電子構件(如電晶體、二極體、電阻、電容、或類似物)的積體密度，以整合更多構件至給定面積。然而隨著最小結構尺寸縮小，需解決額外產生的問題。
本發明一實施例提供之半導體裝置的形成方法，包括：成長半導體層於基板上，基板包括矽，且半導體層包括矽鍺；蝕刻多個溝槽於半導體層與該基板中，以自溝槽之間的半導體層與基板的部份形成鰭狀物；在鰭狀物的上表面與側部上進行氫自由基處理製程，且在氫自由基處理製程之後減少鰭狀物的上表面與側部之矽濃度；以及沿著鰭狀物的上表面與側部形成金屬閘極堆疊。
本發明一實施例提供之半導體裝置的形成方法，包括：形成自基板延伸的鰭狀物，且鰭狀物包括含矽的下側部份與含矽鍺的上側部份；自鰭狀物的側部與上表面同時移除矽與鍺，其以第一速率移除矽，以第二速率移除鍺，且第二速率小於第一速率；以及形成源極區與汲極區於鰭狀物中。
本發明一實施例提供之半導體裝置，包括：基板；第一半導體層，自基板延伸，且第一半導體層包括矽；第二半導體層，位於第一半導體層上，且第二半導體層包括矽鍺，其中第二半導體層的邊緣部份具有第一鍺濃度，第二半導體層的中心部份具有第二鍺濃度，第二鍺濃度小於第一鍺濃度，第二半導體層的邊緣部份包括第二半導體層的側部與上表面；閘極堆疊，位於第二半導體層上；輕摻雜源極/汲極區，位於第二半導體層中，且輕摻雜源極/汲極區與閘極堆疊相鄰；以及源極與汲極區，延伸至輕摻雜源極/汲極區中。
A-A、B-B、C/D-C/D:參考剖面
D1:距離
T1:厚度
W1:第一寬度
W2:第二寬度
W3:第三寬度
10、12:區域
50:基板
52:半導體層
56:溝槽
60:鰭狀物
60A:第一部份
60B:第二部份
62:絕緣材料
64:淺溝槽隔離區
66:鍺凝結製程
68:富鍺層
74:虛置介電層
76:虛置閘極層
78:遮罩層
80:遮罩
82:虛置閘極
84:虛置閘極介電層
90:輕摻雜源極/汲極區
92:閘極密封間隔物
94:閘極間隔物
96:源極/汲極區
100、110:層間介電層
102:凹陷
104:閘極介電層
106:閘極
112:源極/汲極接點
114:閘極接點
圖1係一些實施例中，鰭狀場效電晶體的三維圖。
圖2、3、4、5、6、7、8、9、10A、10B、11A、11B、11C、11D、12A、12B、13A、13B、14A、14B、15、16A、16B、17A、與17B係一些實施例中，形成鰭狀場效電晶體的中間階段之剖視圖。
圖18係一些其他實施例中，鰭狀場效電晶體的剖視圖。
圖19、20、21、與22係一些其他實施例中，鰭狀場效電晶體的剖視圖。
下述內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明內容而非侷限本發明。舉例來 說，形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例，或兩者之間隔有其他額外構件而非直接接觸的實施例。另一方面，本發明之多個實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外，本發明實施例之結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構中，結構可直接接觸另一結構，或可形成額外結構於結構及另一結構之間。此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
在一些實施例中，提供第一半導體材料如矽的基板，並形成第二半導體材料層如矽鍺於基板上。第二半導體材料可具有低鍺濃度。蝕刻溝槽以自第一半導體材料及第二半導體材料形成鰭狀物。進行鍺凝結製程，包括暴露鰭狀物的第一半導體材料與第二半導體材料至氫自由基。在鍺凝結製程時，可增加沿著鰭狀物側壁的鍺濃度。沿著鰭狀物側壁凝結鍺，可增加鰭狀物通道區中的鍺濃度。由於一開始形成的鰭狀物時具有低鍺濃度，其具有較低的壓縮應力，因此在蝕刻溝槽時可減少鰭狀物變形。
圖1係一些實施例中，鰭狀場效電晶體的三維圖。鰭狀場效電晶體包括鰭狀物60於基板50(如半導體基板)上。淺溝槽隔離區64位於基板50中，而鰭狀物60自相鄰的淺溝槽隔離區64之間凸起高於淺溝槽隔離區64。閘極介電層104沿著鰭狀物60的側壁及上表面上，而閘極106位於閘極介電層104上。源極/汲極區96位於鰭狀物60的兩側上(相對於閘極介電層104與閘極106)。
圖1亦顯示後續圖式所用的參考剖面。參考剖面A-A沿著鰭狀場效 電晶體的通道、閘極介電層104、與閘極106。參考剖面B-B垂直於參考剖面A-A，並沿著鰭狀物60的縱軸及鰭狀場效電晶體的源極/汲極區96之間的電流方向。參考剖面C/D-C/D平行於參考剖面A-A，並延伸穿過鰭狀場效電晶體的源極/汲極區96。後續圖式將依據這些參考剖面，以達圖式清楚的目的。
此處所述的一些實施例內容為閘極後製製程所形成的鰭狀場效電晶體。在其他實施例中，可採用閘極優先製程。此外，一些實施例可實施於平面裝置如平面場效電晶體。
可由任何合適方法圖案化鰭狀物。舉例來說，可採用一或多道光微影製程圖案化鰭狀物，比如雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距可小於採用單一直接的光微影製程所得的圖案間距。舉例來說，一實施例形成犧牲層於基板上，並採用光微影製程圖案化犧牲層。採用自對準製程，沿著圖案化的犧牲層之側部形成間隔物。接著移除犧牲層，而保留的間隔物可用於圖案化鰭狀物。
圖2至17B係一些實施例中，形成鰭狀場效電晶體的中間階段之剖視圖。圖2至9沿著圖1中的參考剖面A-A，差別在於圖2至9具有多個鰭狀物或鰭狀場效電晶體。在圖10A至17B中，圖式末尾標號A者沿著圖1的參考剖面A-A，圖式末尾標號B者沿著圖1的參考剖面B-B，而圖式末尾標號C或D者沿著圖1的參考剖面C/D-C/D，差別在圖10A至17B具有多個鰭狀物或鰭狀場效電晶體。
在圖2中，提供基板50。基板50可為半導體基板如基體半導體、絕緣層上半導體基板、或類似物，其可摻雜(比如摻雜p型或n型摻質)或未摻雜。基板50可為晶圓如矽晶圓。一般而言，絕緣層上半導體基板為半導體材料層形成於絕緣層上。舉例來說，絕緣層可為埋置氧化物層、氧化矽層、或類似物。提供絕緣層於基板上，且基板通常為矽或玻璃基板。亦可採用其他基板如多層基 板或組成漸變基板。在一些實施例中，基板50可包含矽，比如矽基板(矽晶圓)。在一些實施例中，基板50的半導體材料亦可包含鍺、半導體化合物(包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、半導體合金(包括矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、或上述之組合。
圖式中為基板50的一區域。圖示的區域可用於形成n型裝置如n型金氧半電晶體(比如n型鰭狀場效電晶體)，或用於形成p型裝置如p型金氧半電晶體(比如p型鰭狀場效電晶體)。此處所述的一些實施例內容為形成p型裝置於圖示區域中。N型裝置可形成於基板50的其他區域中。在形成p型裝置的製程時，遮罩如光阻可覆蓋用於形成n型裝置的區域。
在一些實施例中，摻雜基板50使其具有合適的摻雜區(有時稱作井區)。在形成p型裝置於所示區域的實施例中，可形成n型摻雜區於基板50中。在一些實施例中，n型摻雜區的形成方法可為佈植n型雜質至基板50的區域中。在一些實施例中，可預摻雜n型雜質至基板50。n型雜質可為磷、砷、或類似物，且形成於區域中的n型雜質濃度可小於或等於1018cm-3，比如介於約1017cm-3至約1018cm-3之間。在形成n型裝置於所示區域的實施例中，可形成p型摻雜區於基板50中。在一些實施例中，p型摻雜區的形成方法可為佈植p型雜質至基板50的區域中。在一些實施例中，可預摻雜p型雜質至基板50。p型雜質可為硼、二氟化硼、或類似物，且形成於區域中的p型雜質濃度可小於或等於1018cm-3，比如介於約1017cm-3至約1018cm-3之間。
在圖3中，半導體層52形成於基板50上。半導體層52可磊晶成長於基板50上。在形成p型裝置的實施例中，半導體層52的半導體材料包括鍺，比如矽鍺(SixGe1-x，其中x可為0至1)。矽與矽鍺可具有不同晶格常數。如此一來，半導體層52與基板50具有不匹配的晶格常數。晶格常數不匹配取決於半導體層52 中的鍺濃度，越大的鍺濃度會造成越大的晶格常數不匹配。晶格常數不匹配誘發半導體層52中的壓縮應力，其可增加半導體層52的載子遷移率，進而改善後續形成的p型裝置之通道區遷移率。由於半導體層52的鍺濃度低，壓縮應力與晶格不匹配的程度也低。
在一些實施例中，在成長半導體層52時進行原位摻雜，使半導體層52具有合適的摻雜區(有時稱作井區)。半導體層52的摻雜區可與下方基板50的摻雜區具有相同的摻質型態。半導體層52的摻雜區與下方的基板50之摻雜區，可具有相同或不同的摻雜濃度。
在圖4中，溝槽56形成於半導體層52中，且視情況可形成於基板50中。溝槽56的形成方法可為採用光阻作為蝕刻遮罩的一或多道的蝕刻製程。蝕刻製程可包含濕蝕刻、乾蝕刻、反應性離子蝕刻、中性束蝕刻、上述之組合、或類似方法，且可為非等向。溝槽56可部份地延伸至半導體層52中，或者可延伸穿過半導體層52至基板50中。保留於溝槽56之間的半導體層52的部份(及視情況保留於溝槽56之間的基板50)稱作鰭狀物60。鰭狀物60包含第一部份60A與第二部份60B，第一部份60A包括基板50的部份(如第一半導體材料的第一層)，而第二部份60B包括半導體層52的部份(如第二半導體材料的第二層)。一開始形成的鰭狀物60具有第一寬度W1。在一些實施例中，第一寬度W1介於約7nm至約15nm之間。此鰭狀物寬度在蝕刻鰭狀物(如下述)之後，可讓鰭狀物維持足夠厚度。可以理解的是，鰭狀物60可由其他方法形成。舉例來說，可形成圖案化遮罩(如光阻、硬遮罩、或類似物)於基板50上，並可成長對應鰭狀物60的磊晶區於圖案化遮罩的開口中。
鰭狀物60可為半導體帶。在蝕刻半導體層52以形成鰭狀物60的第二部份60B時，將露出且未橫向限制鰭狀物60的側壁(比如露出鰭狀物60的側壁至自由空間，而其他結構或材料未支撐露出的側壁)。如上述強調的內容，半導 體層52具有應力。由於蝕刻時未限制鰭狀物60的側壁，蝕刻時會釋放半導體層52中的應力。在釋放應力時，會改變半導體材料的形狀，使鰭狀物60變形而不具有所需的鰭狀物形狀。具體而言，鰭狀物60會變形，使半導體帶的上視形狀非直線帶狀。變形的鰭狀物60在沿著基板50延伸時會彎曲。鰭狀物60的變形程度，取決於自半導體層52釋放的應力量。當鰭狀物的寬度越窄且高度越大時，鰭狀物60的變形風險可能惡化。多餘變形會降低鰭狀物60的良率，亦會減少鰭狀物60的載子遷移率。半導體層可形成為具有低初始鍺濃度。由於半導體層52形成為具有低鍺濃度，因此具有低應力釋放量。在一些實施例中，初始鍺濃度可介於約15%至約40%之間，其可提供足夠的通道遷移率而不造成明顯變形。藉由形成低初始鍺濃度的半導體層52以避免鰭狀物變形所增益的載子遷移率，可大於減少鍺濃度所損失載子遷移率。
在圖5中，絕緣材料62形成於基板50之上及相鄰的鰭狀物60之間。絕緣材料62的額外部份可覆蓋鰭狀物60。絕緣材料62可為氧化物如氧化矽、氮化物、類似物、或上述之組合，且其形成方法可為高密度電漿化學氣相沉積、可流動的化學氣相沉積、類似方法、或上述之組合。可流動的化學氣相沉積可在遠端電漿系統中沉積化學氣相沉積為主的材料，之後硬化沉積的材料以將其轉變成另一材料如氧化物。此外亦可採用任何可接受的製程所形成的其他絕緣材料。在所述實施例中，絕緣材料62為可流動的化學氣相沉積製程所形成的氧化矽。一旦形成絕緣材料，可進行退火製程。
在圖6中，使絕緣材料62凹陷以形成淺溝槽隔離區64。使絕緣材料62凹陷，因此鰭狀物60的第二部份60B上側部份自相鄰的淺溝槽隔離區64之間凸起。使絕緣材料62的凹陷方法可為進行平坦化製程後，進行可接受的蝕刻製程。在一些實施例中，平坦化製程包括化學機械研磨、回蝕刻製程、上述之組合、或類似方法。平坦化製程可露出鰭狀物60。在平坦化製程之後，鰭狀物60與絕 緣材料62的上表面可齊平。接著可採用可接受的蝕刻製程如對絕緣材料62的材料具有選擇性的蝕刻製程，使淺溝槽隔離區64凹陷。舉例來說，可採用氫源(如氨)與氟源(如三氟化氮)的化學氧化物移除、或稀釋氫氟酸的化學氧化物移除。藉由蝕刻製程，可使淺溝槽隔離區64具有平坦、凸起、及/或凹陷的上表面。
在圖7中，在鰭狀物60上進行鍺凝結製程66。圖8係圖7中的區域10之細節圖，其顯示鍺凝結製程66之後的鰭狀物60之額外結構。鍺凝結製程66形成富鍺層68於鰭狀物60的第二部份60B中。最終的富鍺層68在鰭狀物60的第二部份60B之側壁中。如此一來，鰭狀物60的第二部份60B之邊緣部份的鍺濃度，高於鰭狀物60的第二部份60B之中心部份的鍺濃度。邊緣部份包括鰭狀物60的第二部份60B的側壁與上表面。在一些實施例中，鰭狀物60的第二部份60B中的富鍺層68其鍺濃度介於約20%至約45%之間，以改善最終鰭狀場效電晶體的載子遷移率。在一些實施例中，鍺凝結製程66增加鰭狀物60的富鍺層68的鍺濃度高達4%。在一裝置中，處理前的整個鰭狀物60的鍺濃度為約29%，處理後的鰭狀物60之中心部份的鍺濃度為約29%，而處理後的鰭狀物60之邊緣部份的鍺濃度為約35%。
鍺凝結製程66為氫自由基處理製程，其中鰭狀物60的第二部份60B暴露至氫自由基。氫自由基可與IV族材料明顯反應，以形成四氫化物化合物。可在腔室如蝕刻腔室中進行氫自由基處理製程。配送氣體源至每一腔室中。氣體源包含前驅物氣體與鈍氣。前驅物氣體包括氫氣，而鈍氣可包含氬氣、氦氣、或上述之組合。不過亦可採用其他鈍氣如氙氣、氖氣、氪氣、氡氣、類似物、或上述之組合。在一些實施例中，前驅物氣體為氣體源的約3%至約20%，而載氣可為氣體源的約80%至約97%。氣體源的配送流速可介於約10每分鐘標準立方公分(sccm)至約5000sccm之間。當配送氣體時，可自氫氣、氬氣、及/或氦氣產生電漿。在電漿產生製程中，可由電漿產生器(如變壓器耦合電漿產生器、感應耦合電漿系統、磁性增強反應性離子蝕刻系統、電子迴旋共振系統、遠端 電漿產生器、或類似物)產生電漿。電漿產生器可產生射頻功率，其自氫氣、氬氣、及/或氦氣產生電漿，比如施加高於擊穿電壓的電壓至腔室(含有氬氣、氦氣、氬氣與氦氣、或氦氣與氫氣)中的電極。產生電漿時，氫氣將分成兩個氫自由基H‧。鰭狀物60的第二部份60B之表面的矽鍺材料暴露至氫電漿時，將斷裂並與氫自由基H‧再結合以形成矽烷與鍺烷，因此可移除鰭狀物60的表面材料。上述矽烷與鍺烷為氣體，且可在形成矽烷與鍺烷時自蝕刻腔室移除矽烷與鍺烷，比如以真空移除。矽與氫之間的反應速率，大於鍺與氫之間的反應速率。舉例來說，矽與氫之間的反應速率，為鍺與氫之間的反應速率的約2至10倍。可以理解的是，反應速率的差異可依製程參數與初始鍺濃度而改變。鍺表面比矽表面更易脫附氫。因此鰭狀物60之表面的矽比鰭狀物60之表面的鍺更快被移除。如此一來，在鍺凝結製程66之後，鰭狀物60的表面矽濃度下降，而鰭狀物60的表面鍺濃度上升。在一些實施例中，氫自由基處理製程的溫度介於約100℃至約600℃之間，時間小於約100秒(如小於約50秒)，且壓力介於約0.1Torr至約6Torr之間。與其他鍺凝結製程(如熱氧化製程)相較，氫自由基處理製程的優點在於可在較低溫度、較短時間、與較低壓力下進行。這些改良的程參數亦可改善製程速度並減少熱預算的考量。
由於氫自由基處理製程移除鰭狀物60之表面的一些材料以形成矽烷與鍺烷，其亦蝕刻一些鰭狀物60。如此一來，在鍺凝結之後的鰭狀物60之上側部份具有第二寬度W2，且第二寬度W2小於鰭狀物60的下側部份之第一寬度W1。此外，當鰭狀物60的第二部份60B延伸於相鄰的淺溝槽隔離區64之間時，鰭狀物60的第二部份60B可具有不同的上側寬度與下側寬度。鰭狀物60的寬度縮減，取決於鍺凝結製程66的參數。在一些實施例中，第二寬度W2介於約7nm至約15nm之間。富鍺層68的厚度亦取決於鍺凝結製程66的參數。藉由改變鍺凝結製程66的參數，富鍺層68的厚度T1可由幾個單層改變至鰭狀物60的實質上所有 寬度。在一些實施例中，厚度T1小於約2nm，比如介於約0.5nm至約1nm之間，進而增加電洞遷移率。進行越多鍺凝結製程，則富鍺層68的厚度T1越大、富鍺層68的鍺濃度越大、且鰭狀物60的第二寬度W2越小。
雖然圖式中的富鍺層68為鰭狀物60的分開區域，但應理解富鍺層68與鰭狀物60的第二部份60B包括相同元素，差別在富鍺層68具有較大鍺濃度。此外，應理解鰭狀物60的鍺濃度可漸變增加，且增加的方向自鰭狀物60的中心部份延伸至鰭狀物60的邊緣部份。
雖然半導體層52在形成時具有低鍺濃度，形成富鍺層68可增加鰭狀物60的鍺濃度。形成低初始鍺濃度的鰭狀物60，有助於在形成鰭狀物60時避免鰭狀物60變形，亦有助於改善半導體層52的結晶品質。形成鰭狀物60之後，再增加鰭狀物60的鍺濃度，可增加鰭狀物60的載子遷移率，但不會增加鰭狀物變形的缺點。此外，由於富鍺層68靠近鰭狀物60的側壁，其可靠近後續形成的p型裝置之閘極，以增加後續形成的p型裝置之通道區遷移率。鰭狀物60的最終應力亦高於鰭狀物60的初始應力。
在圖9中，虛置介電層74形成於鰭狀物60上，比如形成於鰭狀物60的第二部份60B上。舉例來說，虛置介電層74可為氧化矽、氮化矽、上述之組合、或類似物，且其形成方法可為依據可接受的技術之沉積或熱成長。虛置閘極層76形成於虛置介電層74上，而遮罩層78形成於虛置閘極層76上。可沉積虛置閘極層76於虛置介電層74上，接著平坦化(如化學機械研磨)虛置閘極層76。虛置閘極層76可為導電材料，其可包含多晶矽、多晶矽鍺、金屬氮化物、金屬矽化物、金屬氧化物、或金屬。在一實施例中，沉積並再結晶非晶矽以產生多晶矽。虛置閘極層76的沉積方法可為物理氣相沉積、化學氣相沉積、濺鍍沉積、或本技術領域用於沉積導電材料的已知其他技術。虛置閘極層76的組成可為其他材料，其對蝕刻隔離區的步驟具有高蝕刻選擇性。可沉積遮罩層78於虛置閘極層 76上。
在圖10A與10B中，可採用可接受的光微影與蝕刻技術圖案化遮罩層78，以形成遮罩80。接著可採用可接受的蝕刻技術，將遮罩80的圖案分別轉移至虛置閘極層76與虛置介電層74，以形成虛置閘極82與虛置閘極介電層84。虛置閘極82與虛置閘極介電層84覆蓋鰭狀物60的個別通道區。遮罩80的圖案可用於使相鄰的虛置閘極82彼此物理分隔。虛置閘極82的縱向亦可實質上垂直於個別鰭狀物60之縱向。
在圖11A、11B、11C、與11D中，可進行輕摻雜源極/汲極區90所用的佈植。合適型態(如n型或p型)的雜質可佈植至露出的鰭狀物60。n型雜質可為前述的任何n型雜質，而p型雜質可為前述的任何p型雜質。輕摻雜源極/汲極區90的雜質濃度可介於約1015cm-3至約1016cm-3之間。可採用退火以活化佈植的雜質。
此外，閘極密封間隔物92可形成於虛置閘極82及/或鰭狀物60的露出表面上。閘極密封間隔物92的形成方法可為熱氧化或沉積之後進行非等向蝕刻。在一些實施例中，閘極密封間隔物92的組成可為氮化物如氮化矽、氮氧化矽、碳化矽、碳氮化矽、類似物、或上述之組合。閘極密封間隔物92密封後續形成之閘極堆疊的側壁，且可作為額外的閘極間隔物層。
此外，閘極間隔物94形成於沿著虛置閘極82之側壁的閘極密封間隔物92上及輕摻雜源極/汲極區90上。閘極間隔物94的形成方法可為順應性沉積材料，之後非等向蝕刻材料。在一些實施例中，閘極間隔物94的材料可為氮化矽、碳氮化矽、上述之組合、或類似物。蝕刻步驟可對閘極間隔物94的材料具有選擇性，因此在形成閘極間隔物94時不蝕刻輕摻雜源極/汲極區90。
此外，磊晶的源極/汲極區96形成於鰭狀物60中。磊晶的源極/汲極區96形成於鰭狀物60中，使每一虛置閘極82位於個別且相鄰之一對磊晶的源極/ 汲極區96之間。在一些實施例中，磊晶的源極/汲極區96可延伸穿過輕摻雜源極/汲極區90。在一些實施例中，閘極密封間隔物92與閘極間隔物94用於使磊晶的源極/汲極區96與虛置閘極82分隔合適的橫向距離，以避免磊晶的源極/汲極區96向外短接至最終鰭狀場效電晶體之後續形成的閘極。
磊晶的源極/汲極區96之形成方法，可為蝕刻鰭狀物60的源極/汲極區，以形成凹陷於鰭狀物60中。這些凹陷可限制至鰭狀物60的第二部份60B，或者延伸至鰭狀物60的第一部份60A中。接著磊晶成長磊晶的源極/汲極區96於凹陷中。磊晶的源極/汲極區96可包含任何可接受的材料，比如適用於p型或n型鰭狀場效電晶體的材料。舉例來說，形成p型裝置的一些實施例中，磊晶的源極/汲極區96可包括矽鍺、硼化矽鍺、鍺、鍺錫、或類似物。磊晶的源極/汲極區96可具有自鰭狀物60的個別表面隆起的表面，並可具有晶面。
在成長磊晶的源極/汲極區96時可進行原位摻雜，以形成源極/汲極區。磊晶的源極/汲極區96與個別的輕摻雜源極/汲極區90可具有相同摻雜型態，且可摻雜相同或不同的摻質。磊晶的源極/汲極區96的雜質濃度可介於約1019cm-3至約1021cm-3之間。源極/汲極區所用的n型與p型雜質可為前述的任何雜質。由於成長磊晶的源極/汲極區96時進行原位摻雜，因此不需佈植摻雜。然而一些實施例形成之輕摻雜源極/汲極區90的摻雜輪廓與濃度，可與佈植摻雜磊晶的源極/汲極區96所產生的摻雜輪廓與濃度類似。改善輕摻雜源極/汲極區的摻雜濃度與輪廓，可改善最終半導體裝置的效能與可信度。
以磊晶製程形成磊晶的源極/汲極區96，造成磊晶的源極/汲極區的上側表面具有晶面，其橫向擴大超出鰭狀物60的側壁。在一些實施例中，這些晶面使相同鰭狀場效電晶體之相鄰的磊晶的源極/汲極區96合併，如圖11C所示的實施例。其他實施例在完成磊晶製程之後，相鄰之磊晶的源極/汲極區96維持分開，如圖11D所示的實施例。
在圖12A與12B中，沉積層間介電層100於鰭狀物60上。層間介電層100的組成可為介電材料，且其沉積方法可為任何合適方法如化學氣相沉積、電漿增強化學氣相沉積、或可流動的化學氣相沉積。介電材料可包含磷矽酸鹽玻璃、硼矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物。此外亦可採用任何可接受的製程所形成的其他絕緣材料。在一些實施例中，接點蝕刻停止層位於層間介電層100與磊晶的源極/汲極區96、閘極間隔物94、閘極密封間隔物92、及遮罩80之間。
在圖13A與13B中，可進行平坦化製程如化學機械研磨，使層間介電層100的上表面及虛置閘極82與閘極密封間隔物92的上表面齊平。平坦化製程亦可移除虛置閘極82上的遮罩80，以及沿著遮罩80之側壁的閘極密封間隔物92與閘極間隔物94的部份。在平坦化製程之後，虛置閘極82、閘極密封間隔物92、閘極間隔物94、與層間介電層100的上表面齊平。綜上所述，虛置閘極82的上表面自層介電層100露出。
在圖14A與14B中，在蝕刻步驟中移除虛置閘極82與直接位於露出的虛置閘極82下的虛置閘極介電層84，以形成凹陷102。在一些實施例中，以非等向蝕乾蝕刻製程移除虛置閘極82，而不移除閘極密封間隔物92或層間介電層100。舉例來說，蝕刻製程可包含乾蝕刻製程，其採用的反應氣體可選擇性地蝕刻虛置閘極82而不蝕刻層間介電層100或閘極間隔物94。每一凹陷102露出個別鰭狀物60的通道區。每一通道區可侷限在個別鰭狀物60的第二部份60B。每一通道區位於相鄰的一對磊晶的源極/汲極區96之間。在移除虛置閘極82的蝕刻步驟時，虛置閘極介電層84可作為蝕刻停止層。在移除虛置閘極82之後，可接著移除虛置閘極介電層84。
圖15係圖14B中的區域12之細節圖，其顯示凹陷102形成之後的鰭狀物60的其他結構。富鍺層68位於最終鰭狀場效電晶體中即將作為通道區的整 體，並延伸於輕摻雜源極/汲極區90之間。輕摻雜源極/汲極區90亦形成於具有富鍺層68之鰭狀物60的部份中。如此一來，輕摻雜源極/汲極區90的上側部份之鍺濃度，高於輕摻雜源極/汲極區90的下側部份之鍺濃度。輕摻雜源極/汲極區90及通道區中的富鍺層68的厚度T1(如上述)可一致。
在圖16A與16B中，形成閘極介電層104與閘極106於凹陷102中。順應性地形成界面層於鰭狀物60上及凹陷102中。界面層亦可覆蓋層間介電層100的上表面。界面層的形成方法可為沉積製程如化學氣相沉積製程、物理氣相沉積製程、原子層沉積製程、或類似製程。閘極介電層104可形成於界面層上。閘極介電層104可順應性地沉積於凹陷102中，比如沉積於鰭狀物60的上表面與側壁上。閘極介電層104亦可沿著層間介電層100的上表面形成。閘極介電層104可為高介電常數的介電材料，其介電常數大於約7.0，且可包含鉿、鋁、鋯、鑭、鎂、鋇、鈦、鉛、或上述之組合的金屬氧化物或金屬矽酸鹽。閘極介電層104的形成方法可包括分子束沉積、原子層沉積、電漿增強化學氣相沉積、或類似方法。接著沉積閘極層於閘極介電層104上及凹陷102中。閘極層可為含金屬材料如氮化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、上述之組合、或上述之多層。閘極層可包含任意數目的功函數調整層。可進行平坦化製程如化學機械研磨，以移除層間介電層100的上表面上的閘極介電層104與閘極層的多餘部份。閘極層的保留部份形成閘極106，其可與其他層狀物組恆以形成最終鰭狀場效電晶體的置換閘極。閘極介電層104與閘極106可一起稱作最終鰭狀場效電晶體的閘極或閘極堆疊。閘極堆疊可沿著鰭狀物60的通道區側壁延伸。
在圖17A與17B中，層間介電層110沉積於閘極堆疊與層間介電層100上。在一實施例中，層間介電層110為可流動的化學氣相沉積法所形成的可流動膜。在一些實施例中，層間介電層110的組成為介電材料，比如磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、或類似物，且其 沉積方法可為任何合適方法如化學氣相沉積或電漿增強化學氣相沉積。
此外，形成源極/汲極接點112與閘極接點114以穿過層間介電層100與110。形成穿過層間介電層100與110的開口以用於源極/汲極接點112，並形成穿過層間介電層110的開口以用於閘極接點114。開口的形成方法可採用可接受的光微影與蝕刻技術。襯墊層(如擴散阻障層、黏著層、或類似物)與導電材料形成於開口中。襯墊層可包含鈦、氮化鈦、鉭、氮化鉭、或類似物。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或類似物。可進行平坦化製程以自層間介電層110的表面移除多餘材料。保留的襯墊層與導電材料形成源極/汲極接點112及閘極接點114於開口中。可進行退火製程以形成矽化物於磊晶的源極/汲極區96與源極/汲極接膽112之間的界面。源極/汲極接點112物理與電性耦接至磊晶的源極/汲極區96，而閘極接點114物理與電性耦接至閘極106。源極/汲極接點112與閘極接點114可由不同製程形成，或者由相同製程形成。雖然圖式中的源極/汲極接點112與閘極接點114形成於相同剖面中，但應理解其可形成於不同剖面中以避免接點短路。
在上述實施例中，在形成淺溝槽隔離區64之後進行鍺凝結製程66。然而應理解的是，可在形成p型裝置所用的其他製程步驟之後進行鍺凝結製程66。
在一些實施例中，在形成淺溝槽隔離區64之前進行鍺凝結製程66。圖18係圖7中的區域10之細節圖，顯示在形成淺溝槽隔離區64之前進行鍺凝結製程66的鰭狀物60之額外結構。在這些實施例中，鰭狀物60的第二部份60B可具有一致的第二寬度W2，而鰭狀物60的第一部份60A可具有一致的第三寬度W3。在淺溝槽隔離區64的上表面下，可能改變鰭狀物寬度。由於鍺凝結製程66時亦可蝕刻第一部份60A，第三寬度W3可小於第一寬度W1(見圖8)且可大於第二寬度W2。
在一些其他實施例中，移除虛置閘極82與虛置閘極介電層84之後，再進行鍺凝結製程66。圖19係圖14B中區域12的細節圖，顯示形成凹陷102之後，再進行鍺凝結製程66的鰭狀物60之額外結構。在這些實施例中，富鍺層68只沿著凹陷102所露出的鰭狀物60之部份延伸(比如沿著最終鰭狀場效電晶體的通道區延伸)，而輕摻雜源極/汲極區90可具有一致的鍺濃度。此外，只有凹陷102露出的鰭狀物60之部份具有第二寬度W2(見圖20)。鰭狀物60的其他區域(比如閘極密封間隔物92與閘極間隔物94下的其他區域)仍維持第一寬度W1(見圖21)。最後，鍺凝結製程66可使凹陷102延伸距離D1，以減少最終鰭狀場效電晶體的通道區中的鰭狀物60之高度。如此一來，閘極介電層104的下表面低於鰭狀物60的最頂部表面(比如輕摻雜源極/汲極區90的最頂部表面)，見圖22。
實施例可達一些優點。形成低鍺濃度的半導體層52(見圖3)，在形成鰭狀物60的蝕刻製程(見圖4)時有助於避免鰭狀物側壁變形。在形成鰭狀物60的蝕刻製程後進行鍺凝結製程66(見圖7)以增加鰭狀物60的鍺濃度，可增加鰭狀物60的載子遷移率。因此可增加最終p型裝置的通道區遷移率，並可降低形成鰭狀物時的鰭狀物變形風險。
在一實施例中，方法包括：成長半導體層於基板上，基板包括矽，且半導體層包括矽鍺；蝕刻溝槽於半導體層與基板中，以自溝槽之間的半導體層與基板的部份形成鰭狀物；在鰭狀物的上表面與側部上進行氫自由基處理製程，且在氫自由基處理製程之後減少鰭狀物的上表面與側部之矽濃度；以及沿著鰭狀物的上表面與側部形成金屬閘極堆疊。
在方法的一些實施例中，進行氫自由基處理製程的步驟包括：配送包括第一氣體與第二氣體的氣體源至鰭狀物的上表面與側部上，第一氣體為氫氣，且第二氣體為鈍氣；以及產生氫電漿以轉換第一氣體成氫自由基。在方法的一些實施例中，進行氫自由基處理製程的步驟更包括：由氫自由基與鰭狀 物的矽鍺形成矽烷，以及由氫自由基與鰭狀物的矽鍺形成鍺烷，且形成鍺烷的第二速率小於形成矽烷的第一速率。在方法的一些實施例中，進行氫自由基處理製程的步驟更包括：以氫電漿蝕刻鰭狀物的上表面與側部。在方法的一些實施例中，在蝕刻腔室中進行氫自由基處理製程，且進行氫自由基處理製程的步驟更包括：在形成矽烷與鍺烷時，自蝕刻腔室移除矽烷與鍺烷。在方法的一些實施例中，氫自由基處理製程的溫度介於約100℃至約600℃之間。在方法的一些實施例中，氫自由基處理製程的時間小於約100秒。在方法的一些實施例中，氫自由基處理製程的壓力介於約0.1Torr至約6Torr之間。
在一實施例中，方法包括：形成自基板延伸的鰭狀物，且鰭狀物包括含矽的下側部份與含矽鍺的上側部份；自鰭狀物的側部與上表面同時移除矽與鍺，其以第一速率移除矽，以第二速率移除鍺，且第二速率小於第一速率；以及形成源極區與汲極區於鰭狀物中。
在一些實施例中，方法更包括：在移除矽與鍺之前，形成隔離區於鰭狀物周圍。在一些實施例中，方法更包括：在移除矽與鍺之後，形成隔離區於鰭狀物周圍。在一些實施例中，方法更包括：在移除矽與鍺之前，沿著鰭狀物的上表面與側部形成金屬閘極堆疊。在一些實施例中，方法更包括：在移除矽與鍺之後，沿著鰭狀物的上表面與側部形成金屬閘極堆疊。在方法的一些實施例中，移除矽與鍺的步驟包括：暴露鰭狀物的上表面與側部至氫自由基，氫自由基與鰭狀物的矽以第一速率反應形成矽烷，氫自由基與鰭狀物的鍺以第二速率反應形成鍺烷。
在一實施例中，裝置包括：基板；第一半導體層，自基板延伸，且第一半導體層包括矽；第二半導體層，位於第一半導體層上，且第二半導體層包括矽鍺，其中第二半導體層的邊緣部份具有第一鍺濃度，第二半導體層的中心部份具有第二鍺濃度，第二鍺濃度小於第一鍺濃度，第二半導體層的邊緣 部份包括第二半導體層的側部與上表面；閘極堆疊，位於第二半導體層上；輕摻雜源極/汲極區，位於第二半導體層中，且輕摻雜源極/汲極區與閘極堆疊相鄰；以及源極與汲極區，延伸至輕摻雜源極/汲極區中。
在裝置的一些實施例中，整個輕摻雜源極/汲極區具有第二鍺濃度。在裝置的一些實施例中，輕摻雜源極/汲極區的上側部份具有第一鍺濃度，且輕摻雜源極/汲極區的下側部份具有第二鍺濃度。在裝置的一些實施例中，第一半導體層具有第一寬度，第二半導體層的下側部份具有第一寬度，第二半導體層的上側部份具有第二寬度，且第二寬度小於第一寬度。在裝置的一些實施例中，第一半導體層具有第一寬度，第二半導體層的上側部份與下側部份具有第二寬度，且第二寬度小於第一寬度。在裝置的一些實施例中，閘極堆疊包括：閘極介電層，位於第二半導體層上，且閘極介電層的下表面低於輕摻雜源極/汲極區的上表面；以及閘極，位於閘極介電層上。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
T1:厚度
W1:第一寬度
W2:第二寬度
10:區域
60A:第一部份
60B:第二部份
64:淺溝槽隔離區
68:富鍺層

Claims (10)

  1. 一種半導體裝置的形成方法，包括：成長一半導體層於一基板上，該基板包括矽，且該半導體層包括矽鍺；蝕刻多個溝槽於該半導體層與該基板中，以形成含一第一部分與一第二部分的一鰭狀物，該第一部分包括該些溝槽之間的該基板的一部分，該第二部分包括該些溝槽之間的該半導體層的一部分，該第一部分具有一第一寬度，而該第二部分具有一第二寬度；在蝕刻該些溝槽於該半導體層與該基板中之後，在該鰭狀物的上表面與側部上進行一氫自由基處理製程，且在該氫自由基處理製程之後減少該鰭狀物的上表面與側部之矽濃度，並在該氫自由基處理製程之後減少該鰭狀物的該第二部分的該第二寬度；以及沿著該鰭狀物的上表面與側部形成一金屬閘極堆疊。
  2. 如請求項1之半導體裝置的形成方法，其中進行該氫自由基處理製程的步驟包括：配送包括一第一氣體與一第二氣體的一氣體源至該鰭狀物的上表面與側部上，該第一氣體為氫氣，且該第二氣體為鈍氣；以及產生一氫電漿以轉換該第一氣體成多個氫自由基。
  3. 一種半導體裝置的形成方法，包括：以一蝕刻製程形成自一基板延伸的一鰭狀物，且該鰭狀物包括含矽的一下側部份與含矽鍺的一上側部份；以一氫自由基處理製程自該鰭狀物的側部與上表面同時移除矽與鍺，且該氫自由基處理製程與該蝕刻製程不同，該氫自由基處理製程以一第一速率移除矽並以一第二速率移除鍺，且該第二速率小於該第一速率；形成一輕摻雜源極/汲極區於該鰭狀物中，其中該輕摻雜源極/汲極區的上側 部分具有一第一鍺濃度，該輕摻雜源極/汲極區的下側部分具有一第二鍺濃度，且該第二鍺濃度小於該第一鍺濃度；以及形成一源極區與一汲極區於該鰭狀物中，且該源極區或該汲極區延伸至該輕摻雜源極/汲極區中。
  4. 如請求項3之半導體裝置的形成方法，更包括：在移除矽與鍺之前，形成一隔離區於該鰭狀物周圍。
  5. 一種半導體裝置，包括：一基板；一第一半導體層，自該基板延伸，且該第一半導體層包括矽；一第二半導體層，位於該第一半導體層上，且該第二半導體層包括矽鍺，其中該第二半導體層的邊緣部份具有一第一鍺濃度，該第二半導體層的中心部份具有一第二鍺濃度，該第二鍺濃度小於該第一鍺濃度，該第二半導體層的邊緣部份包括該第二半導體層的側部與上表面；一閘極堆疊，位於該第二半導體層上；多個輕摻雜源極/汲極區，位於該第二半導體層中，且該些輕摻雜源極/汲極區與該閘極堆疊相鄰，其中該些輕摻雜源極/汲極區的上側部分具有該第一鍺濃度，而該些輕摻雜源極/汲極區的下側部分具有該第二鍺濃度；以及多個源極與汲極區，延伸至該輕摻雜源極/汲極區中。
  6. 如請求項5之半導體裝置，其中該第一半導體層具有一第一寬度，該第二半導體層的下側部份具有該第一寬度，該第二半導體層的上側部份具有一第二寬度，且該第二寬度小於該第一寬度。
  7. 一種半導體裝置，包括：一隔離區，位於一基板上；一鰭狀物，包括一矽層與一矽鍺層，該矽層與該矽鍺層的下側部分位於該隔 離區中，該矽鍺層的上側部分凸起高於該隔離區，且該矽鍺層的上側部分的邊緣部分的鍺濃度大於該矽鍺層的下側部分的邊緣部分的鍺濃度，且在相同水平高度處，該矽鍺層的上側部分的邊緣部分的鍺濃度大於該矽鍺層的上側部分的中心部分的鍺濃度；以及一閘極堆疊，位於該矽鍺層的上側部分上。
  8. 如請求項7之半導體裝置，其中該閘極堆疊下的該矽層具有一第一寬度，該閘極堆疊下的該矽鍺層的該上側部分具有一第二寬度，且該第二寬度小於該第一寬度。
  9. 一種半導體裝置，包括：一隔離區，位於一基板上；一矽鍺層，具有一井區與一通道區，該井區低於該隔離區的上表面，該通道區凸起高於該隔離區的上表面，該通道區的寬度小於該井區的寬度，且該通道區的鍺濃度大於該井區的鍺濃度；一源極/汲極區，與該矽鍺層的該通道區相鄰；以及一閘極堆疊，位於該矽鍺層的該通道區上。
  10. 一種半導體裝置，包括：一矽鍺鰭狀物，自一基板延伸，該矽鍺鰭狀物具有下側部分與下側部分之上的上側部分，在一水平高度處的該矽鍺鰭狀物的上側部分的側壁具有一第一鍺濃度，該矽鍺鰭狀物的下側部分的側壁與在該水平高度處的該矽鍺鰭狀物的上側部分的中心具有一第二鍺濃度，且該第一鍺濃度大於該第二鍺濃度；一隔離區，位於該矽鍺鰭狀物的下側部分的周圍，且該矽鍺鰭狀物的上側部分凸起高於該隔離區；一閘極堆疊，位於該隔離區與該矽鍺鰭狀物的上側部分之上；以及一源極/汲極區，與該閘極堆疊相鄰。
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