CN110660738A - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

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Publication number
CN110660738A
CN110660738A CN201910440377.1A CN201910440377A CN110660738A CN 110660738 A CN110660738 A CN 110660738A CN 201910440377 A CN201910440377 A CN 201910440377A CN 110660738 A CN110660738 A CN 110660738A
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fin
germanium
semiconductor layer
layer
gate
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林哲宇
陈建鸿
萧文助
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在一实施例中，装置包括：基板；第一半导体层，自基板延伸，且第一半导体层包括硅；第二半导体层，位于第一半导体层上，且第二半导体层包括硅锗，其中第二半导体层的边缘部分具有第一锗浓度，第二半导体层的中心部分具有第二锗浓度，第二锗浓度小于第一锗浓度，且第二半导体层的边缘部分包括第二半导体层的侧部与上表面；栅极堆叠，位于第二半导体层上；轻掺杂源极/漏极区，位于第二半导体层中，且轻掺杂源极/漏极区与栅极堆叠相邻；以及源极与漏极区，延伸至轻掺杂源极/漏极区中。

Description

半导体装置的形成方法
技术领域
本发明实施例关于半导体装置，更特别关于增加鳍状物通道区中的锗浓度的方法。
背景技术
半导体装置用于多种电子应用，比如个人电脑、手机、数码相机、与其他电子设备。半导体装置的制作方法通常为依序沉积绝缘或介电层、导电层、与半导体层的材料于半导体基板上，并采用微影图案化多种材料层，以形成电路构件与单元于半导体基板上。
半导体产业持续减少最小结构尺寸以持续改良多种电子构件(如晶体管、二极管、电阻、电容、或类似物)的集成密度，以整合更多构件至给定面积。然而随着最小结构尺寸缩小，需解决额外产生的问题。
发明内容
本发明一实施例提供的半导体装置的形成方法，包括：成长半导体层于基板上，基板包括硅，且半导体层包括硅锗；蚀刻多个沟槽于半导体层与该基板中，以自沟槽之间的半导体层与基板的部分形成鳍状物；在鳍状物的上表面与侧部上进行氢自由基处理制程，且在氢自由基处理制程之后减少鳍状物的上表面与侧部的硅浓度；以及沿着鳍状物的上表面与侧部形成金属栅极堆叠。
本发明一实施例提供的半导体装置的形成方法，包括：形成自基板延伸的鳍状物，且鳍状物包括含硅的下侧部分与含硅锗的上侧部分；自鳍状物的侧部与上表面同时移除硅与锗，其以第一速率移除硅，以第二速率移除锗，且第二速率小于第一速率；以及形成源极区与漏极区于鳍状物中。
本发明一实施例提供的半导体装置，包括：基板；第一半导体层，自基板延伸，且第一半导体层包括硅；第二半导体层，位于第一半导体层上，且第二半导体层包括硅锗，其中第二半导体层的边缘部分具有第一锗浓度，第二半导体层的中心部分具有第二锗浓度，第二锗浓度小于第一锗浓度，第二半导体层的边缘部分包括第二半导体层的侧部与上表面；栅极堆叠，位于第二半导体层上；轻掺杂源极/漏极区，位于第二半导体层中，且轻掺杂源极/漏极区与栅极堆叠相邻；以及源极与漏极区，延伸至轻掺杂源极/漏极区中。
附图说明
图1是一些实施例中，鳍状场效晶体管的三维图。
图2、3、4、5、6、7、8、9、10A、10B、11A、11B、11C、11D、12A、12B、13A、13B、14A、14B、15、16A、16B、17A、与17B是一些实施例中，形成鳍状场效晶体管的中间阶段的剖视图。
图18是一些其他实施例中，鳍状场效晶体管的剖视图。
图19、20、21、与22是一些其他实施例中，鳍状场效晶体管的剖视图。
其中，附图标记说明如下：
A-A、B-B、C/D-C/D 参考剖面
D1 距离
T1 厚度
W1 第一宽度
W2 第二宽度
W3 第三宽度
10、12 区域
50 基板
52 半导体层
56 沟槽
60 鳍状物
60A 第一部分
60B 第二部分
62 绝缘材料
64 浅沟槽隔离区
66 锗凝结制程
68 富锗层
74 虚置介电层
76 虚置栅极层
78 遮罩层
80 遮罩
82 虚置栅极
84 虚置栅极介电层
90 轻掺杂源极/漏极区
92 栅极密封间隔物
94 栅极间隔物
96 源极/漏极区
100、110 层间介电层
102 凹陷
104 栅极介电层
106 栅极
112 源极/漏极接点
114 栅极接点
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例是用以简化本发明内容而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触的实施例，或两者之间隔有其他额外构件而非直接接触的实施例。另一方面，本发明的多个实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中，结构可直接接触另一结构，或可形成额外结构于结构及另一结构之间。此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
在一些实施例中，提供第一半导体材料如硅的基板，并形成第二半导体材料层如硅锗于基板上。第二半导体材料可具有低锗浓度。蚀刻沟槽以自第一半导体材料及第二半导体材料形成鳍状物。进行锗凝结制程，包括暴露鳍状物的第一半导体材料与第二半导体材料至氢自由基。在锗凝结制程时，可增加沿着鳍状物侧壁的锗浓度。沿着鳍状物侧壁凝结锗，可增加鳍状物通道区中的锗浓度。由于一开始形成的鳍状物时具有低锗浓度，其具有较低的压缩应力，因此在蚀刻沟槽时可减少鳍状物变形。
图1是一些实施例中，鳍状场效晶体管的三维图。鳍状场效晶体管包括鳍状物60于基板50(如半导体基板)上。浅沟槽隔离区64位于基板50中，而鳍状物60自相邻的浅沟槽隔离区64之间凸起高于浅沟槽隔离区64。栅极介电层104沿着鳍状物60的侧壁及上表面上，而栅极106位于栅极介电层104上。源极/漏极区96位于鳍状物60的两侧上(相对于栅极介电层104与栅极106)。
图1亦显示后续附图所用的参考剖面。参考剖面A-A沿着鳍状场效晶体管的通道、栅极介电层104、与栅极106。参考剖面B-B垂直于参考剖面A-A，并沿着鳍状物60的纵轴及鳍状场效晶体管的源极/漏极区96之间的电流方向。参考剖面C/D-C/D平行于参考剖面A-A，并延伸穿过鳍状场效晶体管的源极/漏极区96。后续附图将依据这些参考剖面，以达附图清楚的目的。
此处所述的一些实施例内容为栅极后制制程所形成的鳍状场效晶体管。在其他实施例中，可采用栅极优先制程。此外，一些实施例可实施于平面装置如平面场效晶体管。
可由任何合适方法图案化鳍状物。举例来说，可采用一或多道光微影制程图案化鳍状物，比如双重图案化或多重图案化制程。一般而言，双重图案化或多重图案化制程结合光微影与自对准制程，其产生的图案间距可小于采用单一直接的光微影制程所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光微影制程图案化牺牲层。采用自对准制程，沿着图案化的牺牲层的侧部形成间隔物。接着移除牺牲层，而保留的间隔物可用于图案化鳍状物。
图2至17B是一些实施例中，形成鳍状场效晶体管的中间阶段的剖视图。图2至9沿着图1中的参考剖面A-A，差别在于图2至9具有多个鳍状物或鳍状场效晶体管。在图10A至17B中，附图末尾标号A者沿着图1的参考剖面A-A，附图末尾标号B者沿着图1的参考剖面B-B，而附图末尾标号C或D者沿着图1的参考剖面C/D-C/D，差别在图10A至17B具有多个鳍状物或鳍状场效晶体管。
在图2中，提供基板50。基板50可为半导体基板如基体半导体、绝缘层上半导体基板、或类似物，其可掺杂(比如掺杂p型或n型掺质)或未掺杂。基板50可为晶圆如硅晶圆。一般而言，绝缘层上半导体基板为半导体材料层形成于绝缘层上。举例来说，绝缘层可为埋置氧化物层、氧化硅层、或类似物。提供绝缘层于基板上，且基板通常为硅或玻璃基板。亦可采用其他基板如多层基板或组成渐变基板。在一些实施例中，基板50可包含硅，比如硅基板(硅晶圆)。在一些实施例中，基板50的半导体材料亦可包含锗、半导体化合物(包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、半导体合金(包括硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。
附图中为基板50的一区域。图示的区域可用于形成n型装置如n型金属氧化物半导体晶体管(比如n型鳍状场效晶体管)，或用于形成p型装置如p型金属氧化物半导体晶体管(比如p型鳍状场效晶体管)。此处所述的一些实施例内容为形成p型装置于图示区域中。N型装置可形成于基板50的其他区域中。在形成p型装置的制程时，遮罩如光刻胶可覆盖用于形成n型装置的区域。
在一些实施例中，掺杂基板50使其具有合适的掺杂区(有时称作井区)。在形成p型装置于所示区域的实施例中，可形成n型掺杂区于基板50中。在一些实施例中，n型掺杂区的形成方法可为布植n型杂质至基板50的区域中。在一些实施例中，可预掺杂n型杂质至基板50。n型杂质可为磷、砷、或类似物，且形成于区域中的n型杂质浓度可小于或等于1018cm-3，比如介于约1017cm-3至约1018cm-3之间。在形成n型装置于所示区域的实施例中，可形成p型掺杂区于基板50中。在一些实施例中，p型掺杂区的形成方法可为布植p型杂质至基板50的区域中。在一些实施例中，可预掺杂p型杂质至基板50。p型杂质可为硼、二氟化硼、或类似物，且形成于区域中的p型杂质浓度可小于或等于1018cm-3，比如介于约1017cm-3至约1018cm-3之间。
在图3中，半导体层52形成于基板50上。半导体层52可外延成长于基板50上。在形成p型装置的实施例中，半导体层52的半导体材料包括锗，比如硅锗(SixGe1-x，其中x可为0至1)。硅与硅锗可具有不同晶格常数。如此一来，半导体层52与基板50具有不匹配的晶格常数。晶格常数不匹配取决于半导体层52中的锗浓度，越大的锗浓度会造成越大的晶格常数不匹配。晶格常数不匹配诱发半导体层52中的压缩应力，其可增加半导体层52的载子迁移率，进而改善后续形成的p型装置的通道区迁移率。由于半导体层52的锗浓度低，压缩应力与晶格不匹配的程度也低。
在一些实施例中，在成长半导体层52时进行原位掺杂，使半导体层52具有合适的掺杂区(有时称作井区)。半导体层52的掺杂区可与下方基板50的掺杂区具有相同的掺质型态。半导体层52的掺杂区与下方的基板50的掺杂区，可具有相同或不同的掺杂浓度。
在图4中，沟槽56形成于半导体层52中，且视情况可形成于基板50中。沟槽56的形成方法可为采用光刻胶作为蚀刻遮罩的一或多道的蚀刻制程。蚀刻制程可包含湿蚀刻、干蚀刻、反应性离子蚀刻、中性束蚀刻、上述的组合、或类似方法，且可为非等向。沟槽56可部分地延伸至半导体层52中，或者可延伸穿过半导体层52至基板50中。保留于沟槽56之间的半导体层52的部分(及视情况保留于沟槽56之间的基板50)称作鳍状物60。鳍状物60包含第一部分60A与第二部分60B，第一部分60A包括基板50的部分(如第一半导体材料的第一层)，而第二部分60B包括半导体层52的部分(如第二半导体材料的第二层)。一开始形成的鳍状物60具有第一宽度W1。在一些实施例中，第一宽度W1介于约7nm至约15nm之间。此鳍状物宽度在蚀刻鳍状物(如下述)之后，可让鳍状物维持足够厚度。可以理解的是，鳍状物60可由其他方法形成。举例来说，可形成图案化遮罩(如光刻胶、硬遮罩、或类似物)于基板50上，并可成长对应鳍状物60的外延区于图案化遮罩的开口中。
鳍状物60可为半导体带。在蚀刻半导体层52以形成鳍状物60的第二部分60B时，将露出且未横向限制鳍状物60的侧壁(比如露出鳍状物60的侧壁至自由空间，而其他结构或材料未支撑露出的侧壁)。如上述强调的内容，半导体层52具有应力。由于蚀刻时未限制鳍状物60的侧壁，蚀刻时会释放半导体层52中的应力。在释放应力时，会改变半导体材料的形状，使鳍状物60变形而不具有所需的鳍状物形状。具体而言，鳍状物60会变形，使半导体带的上视形状非直线带状。变形的鳍状物60在沿着基板50延伸时会弯曲。鳍状物60的变形程度，取决于自半导体层52释放的应力量。当鳍状物的宽度越窄且高度越大时，鳍状物60的变形风险可能恶化。多余变形会降低鳍状物60的良率，亦会减少鳍状物60的载子迁移率。半导体层可形成为具有低初始锗浓度。由于半导体层52形成为具有低锗浓度，因此具有低应力释放量。在一些实施例中，初始锗浓度可介于约15％至约40％之间，其可提供足够的通道迁移率而不造成明显变形。通过形成低初始锗浓度的半导体层52以避免鳍状物变形所增益的载子迁移率，可大于减少锗浓度所损失载子迁移率。
在图5中，绝缘材料62形成于基板50之上及相邻的鳍状物60之间。绝缘材料62的额外部分可覆盖鳍状物60。绝缘材料62可为氧化物如氧化硅、氮化物、类似物、或上述的组合，且其形成方法可为高密度等离子体化学气相沉积、可流动的化学气相沉积、类似方法、或上述的组合。可流动的化学气相沉积可在远端等离子体系统中沉积化学气相沉积为主的材料，之后硬化沉积的材料以将其转变成另一材料如氧化物。此外亦可采用任何可接受的制程所形成的其他绝缘材料。在所述实施例中，绝缘材料62为可流动的化学气相沉积制程所形成的氧化硅。一旦形成绝缘材料，可进行退火制程。
在图6中，使绝缘材料62凹陷以形成浅沟槽隔离区64。使绝缘材料62凹陷，因此鳍状物60的第二部分60B上侧部分自相邻的浅沟槽隔离区64之间凸起。使绝缘材料62的凹陷方法可为进行平坦化制程后，进行可接受的蚀刻制程。在一些实施例中，平坦化制程包括化学机械研磨、回蚀刻制程、上述的组合、或类似方法。平坦化制程可露出鳍状物60。在平坦化制程之后，鳍状物60与绝缘材料62的上表面可齐平。接着可采用可接受的蚀刻制程如对绝缘材料62的材料具有选择性的蚀刻制程，使浅沟槽隔离区64凹陷。举例来说，可采用氢源(如氨)与氟源(如三氟化氮)的化学氧化物移除、或稀释氢氟酸的化学氧化物移除。通过蚀刻制程，可使浅沟槽隔离区64具有平坦、凸起、及/或凹陷的上表面。
在图7中，在鳍状物60上进行锗凝结制程66。图8是图7中的区域10的细节图，其显示锗凝结制程66之后的鳍状物60的额外结构。锗凝结制程66形成富锗层68于鳍状物60的第二部分60B中。最终的富锗层68在鳍状物60的第二部分60B的侧壁中。如此一来，鳍状物60的第二部分60B的边缘部分的锗浓度，高于鳍状物60的第二部分60B的中心部分的锗浓度。边缘部分包括鳍状物60的第二部分60B的侧壁与上表面。在一些实施例中，鳍状物60的第二部分60B中的富锗层68其锗浓度介于约20％至约45％之间，以改善最终鳍状场效晶体管的载子迁移率。在一些实施例中，锗凝结制程66增加鳍状物60的富锗层68的锗浓度高达4％。在一装置中，处理前的整个鳍状物60的锗浓度为约29％，处理后的鳍状物60的中心部分的锗浓度为约29％，而处理后的鳍状物60的边缘部分的锗浓度为约35％。
锗凝结制程66为氢自由基处理制程，其中鳍状物60的第二部分60B暴露至氢自由基。氢自由基可与IV族材料明显反应，以形成四氢化物化合物。可在腔室如蚀刻腔室中进行氢自由基处理制程。配送气体源至每一腔室中。气体源包含前驱物气体与钝气。前驱物气体包括氢气，而钝气可包含氩气、氦气、或上述的组合。不过亦可采用其他钝气如氙气、氖气、氪气、氡气、类似物、或上述的组合。在一些实施例中，前驱物气体为气体源的约3％至约20％，而载气可为气体源的约80％至约97％。气体源的配送流速可介于约10每分钟标准立方公分(sccm)至约5000sccm之间。当配送气体时，可自氢气、氩气、及/或氦气产生等离子体。在等离子体产生制程中，可由等离子体产生器(如变压器耦合等离子体产生器、感应耦合等离子体系统、磁性增强反应性离子蚀刻系统、电子回旋共振系统、远端等离子体产生器、或类似物)产生等离子体。等离子体产生器可产生射频功率，其自氢气、氩气、及/或氦气产生等离子体，比如施加高于击穿电压的电压至腔室(含有氩气、氦气、氩气与氦气、或氦气与氢气)中的电极。产生等离子体时，氢气将分成两个氢自由基H·。鳍状物60的第二部分60B的表面的硅锗材料暴露至氢等离子体时，将断裂并与氢自由基H·再结合以形成硅烷与锗烷，因此可移除鳍状物60的表面材料。上述硅烷与锗烷为气体，且可在形成硅烷与锗烷时自蚀刻腔室移除硅烷与锗烷，比如以真空移除。硅与氢之间的反应速率，大于锗与氢之间的反应速率。举例来说，硅与氢之间的反应速率，为锗与氢之间的反应速率的约2至10倍。可以理解的是，反应速率的差异可依制程参数与初始锗浓度而改变。锗表面比硅表面更易脱附氢。因此鳍状物60的表面的硅比鳍状物60的表面的锗更快被移除。如此一来，在锗凝结制程66之后，鳍状物60的表面硅浓度下降，而鳍状物60的表面锗浓度上升。在一些实施例中，氢自由基处理制程的温度介于约100℃至约600℃之间，时间小于约100秒(如小于约50秒)，且压力介于约0.1Torr至约6Torr之间。与其他锗凝结制程(如热氧化制程)相较，氢自由基处理制程的优点在于可在较低温度、较短时间、与较低压力下进行。这些改良的程参数亦可改善制程速度并减少热预算的考量。
由于氢自由基处理制程移除鳍状物60的表面的一些材料以形成硅烷与锗烷，其亦蚀刻一些鳍状物60。如此一来，在锗凝结之后的鳍状物60的上侧部分具有第二宽度W2，且第二宽度W2小于鳍状物60的下侧部分的第一宽度W1。此外，当鳍状物60的第二部分60B延伸于相邻的浅沟槽隔离区64之间时，鳍状物60的第二部分60B可具有不同的上侧宽度与下侧宽度。鳍状物60的宽度缩减，取决于锗凝结制程66的参数。在一些实施例中，第二宽度W2介于约7nm至约15nm之间。富锗层68的厚度亦取决于锗凝结制程66的参数。通过改变锗凝结制程66的参数，富锗层68的厚度T1可由几个单层改变至鳍状物60的实质上所有宽度。在一些实施例中，厚度T1小于约2nm，比如介于约0.5nm至约1nm之间，进而增加空穴迁移率。进行越多锗凝结制程，则富锗层68的厚度T1越大、富锗层68的锗浓度越大、且鳍状物60的第二宽度W2越小。
虽然附图中的富锗层68为鳍状物60的分开区域，但应理解富锗层68与鳍状物60的第二部分60B包括相同元素，差别在富锗层68具有较大锗浓度。此外，应理解鳍状物60的锗浓度可渐变增加，且增加的方向自鳍状物60的中心部分延伸至鳍状物60的边缘部分。
虽然半导体层52在形成时具有低锗浓度，形成富锗层68可增加鳍状物60的锗浓度。形成低初始锗浓度的鳍状物60，有助于在形成鳍状物60时避免鳍状物60变形，亦有助于改善半导体层52的结晶品质。形成鳍状物60之后，再增加鳍状物60的锗浓度，可增加鳍状物60的载子迁移率，但不会增加鳍状物变形的缺点。此外，由于富锗层68靠近鳍状物60的侧壁，其可靠近后续形成的p型装置的栅极，以增加后续形成的p型装置的通道区迁移率。鳍状物60的最终应力亦高于鳍状物60的初始应力。
在图9中，虚置介电层74形成于鳍状物60上，比如形成于鳍状物60的第二部分60B上。举例来说，虚置介电层74可为氧化硅、氮化硅、上述的组合、或类似物，且其形成方法可为依据可接受的技术的沉积或热成长。虚置栅极层76形成于虚置介电层74上，而遮罩层78形成于虚置栅极层76上。可沉积虚置栅极层76于虚置介电层74上，接着平坦化(如化学机械研磨)虚置栅极层76。虚置栅极层76可为导电材料，其可包含多晶硅、多晶硅锗、金属氮化物、金属硅化物、金属氧化物、或金属。在一实施例中，沉积并再结晶非晶硅以产生多晶硅。虚置栅极层76的沉积方法可为物理气相沉积、化学气相沉积、溅镀沉积、或本技术领域用于沉积导电材料的已知其他技术。虚置栅极层76的组成可为其他材料，其对蚀刻隔离区的步骤具有高蚀刻选择性。可沉积遮罩层78于虚置栅极层76上。
在图10A与10B中，可采用可接受的光微影与蚀刻技术图案化遮罩层78，以形成遮罩80。接着可采用可接受的蚀刻技术，将遮罩80的图案分别转移至虚置栅极层76与虚置介电层74，以形成虚置栅极82与虚置栅极介电层84。虚置栅极82与虚置栅极介电层84覆盖鳍状物60的个别通道区。遮罩80的图案可用于使相邻的虚置栅极82彼此物理分隔。虚置栅极82的纵向亦可实质上垂直于个别鳍状物60的纵向。
在图11A、11B、11C、与11D中，可进行轻掺杂源极/漏极区90所用的布植。合适型态(如n型或p型)的杂质可布植至露出的鳍状物60。n型杂质可为前述的任何n型杂质，而p型杂质可为前述的任何p型杂质。轻掺杂源极/漏极区90的杂质浓度可介于约1015cm-3至约1016cm-3之间。可采用退火以活化布植的杂质。
此外，栅极密封间隔物92可形成于虚置栅极82及/或鳍状物60的露出表面上。栅极密封间隔物92的形成方法可为热氧化或沉积之后进行非等向蚀刻。在一些实施例中，栅极密封间隔物92的组成可为氮化物如氮化硅、氮氧化硅、碳化硅、碳氮化硅、类似物、或上述的组合。栅极密封间隔物92密封后续形成的栅极堆叠的侧壁，且可作为额外的栅极间隔物层。
此外，栅极间隔物94形成于沿着虚置栅极82的侧壁的栅极密封间隔物92上及轻掺杂源极/漏极区90上。栅极间隔物94的形成方法可为顺应性沉积材料，之后非等向蚀刻材料。在一些实施例中，栅极间隔物94的材料可为氮化硅、碳氮化硅、上述的组合、或类似物。蚀刻步骤可对栅极间隔物94的材料具有选择性，因此在形成栅极间隔物94时不蚀刻轻掺杂源极/漏极区90。
此外，外延的源极/漏极区96形成于鳍状物60中。外延的源极/漏极区96形成于鳍状物60中，使每一虚置栅极82位于个别且相邻的一对外延的源极/漏极区96之间。在一些实施例中，外延的源极/漏极区96可延伸穿过轻掺杂源极/漏极区90。在一些实施例中，栅极密封间隔物92与栅极间隔物94用于使外延的源极/漏极区96与虚置栅极82分隔合适的横向距离，以避免外延的源极/漏极区96向外短接至最终鳍状场效晶体管的后续形成的栅极。
外延的源极/漏极区96的形成方法，可为蚀刻鳍状物60的源极/漏极区，以形成凹陷于鳍状物60中。这些凹陷可限制至鳍状物60的第二部分60B，或者延伸至鳍状物60的第一部分60A中。接着外延成长外延的源极/漏极区96于凹陷中。外延的源极/漏极区96可包含任何可接受的材料，比如适用于p型或n型鳍状场效晶体管的材料。举例来说，形成p型装置的一些实施例中，外延的源极/漏极区96可包括硅锗、硼化硅锗、锗、锗锡、或类似物。外延的源极/漏极区96可具有自鳍状物60的个别表面隆起的表面，并可具有晶面。
在成长外延的源极/漏极区96时可进行原位掺杂，以形成源极/漏极区。外延的源极/漏极区96与个别的轻掺杂源极/漏极区90可具有相同掺杂型态，且可掺杂相同或不同的掺质。外延的源极/漏极区96的杂质浓度可介于约1019cm-3至约1021cm-3之间。源极/漏极区所用的n型与p型杂质可为前述的任何杂质。由于成长外延的源极/漏极区96时进行原位掺杂，因此不需布植掺杂。然而一些实施例形成的轻掺杂源极/漏极区90的掺杂轮廓与浓度，可与布植掺杂外延的源极/漏极区96所产生的掺杂轮廓与浓度类似。改善轻掺杂源极/漏极区的掺杂浓度与轮廓，可改善最终半导体装置的效能与可信度。
以外延制程形成外延的源极/漏极区96，造成外延的源极/漏极区的上侧表面具有晶面，其横向扩大超出鳍状物60的侧壁。在一些实施例中，这些晶面使相同鳍状场效晶体管的相邻的外延的源极/漏极区96合并，如图11C所示的实施例。其他实施例在完成外延制程之后，相邻的外延的源极/漏极区96维持分开，如图11D所示的实施例。
在图12A与12B中，沉积层间介电层100于鳍状物60上。层间介电层100的组成可为介电材料，且其沉积方法可为任何合适方法如化学气相沉积、等离子体增强化学气相沉积、或可流动的化学气相沉积。介电材料可包含磷硅酸盐玻璃、硼硅酸盐玻璃、未掺杂的硅酸盐玻璃、或类似物。此外亦可采用任何可接受的制程所形成的其他绝缘材料。在一些实施例中，接点蚀刻停止层位于层间介电层100与外延的源极/漏极区96、栅极间隔物94、栅极密封间隔物92、及遮罩80之间。
在图13A与13B中，可进行平坦化制程如化学机械研磨，使层间介电层100的上表面及虚置栅极82与栅极密封间隔物92的上表面齐平。平坦化制程亦可移除虚置栅极82上的遮罩80，以及沿着遮罩80的侧壁的栅极密封间隔物92与栅极间隔物94的部分。在平坦化制程之后，虚置栅极82、栅极密封间隔物92、栅极间隔物94、与层间介电层100的上表面齐平。综上所述，虚置栅极82的上表面自层介电层100露出。
在图14A与14B中，在蚀刻步骤中移除虚置栅极82与直接位于露出的虚置栅极82下的虚置栅极介电层84，以形成凹陷102。在一些实施例中，以非等向蚀干蚀刻制程移除虚置栅极82，而不移除栅极密封间隔物92或层间介电层100。举例来说，蚀刻制程可包含干蚀刻制程，其采用的反应气体可选择性地蚀刻虚置栅极82而不蚀刻层间介电层100或栅极间隔物94。每一凹陷102露出个别鳍状物60的通道区。每一通道区可局限在个别鳍状物60的第二部分60B。每一通道区位于相邻的一对外延的源极/漏极区96之间。在移除虚置栅极82的蚀刻步骤时，虚置栅极介电层84可作为蚀刻停止层。在移除虚置栅极82之后，可接着移除虚置栅极介电层84。
图15是图14B中的区域12的细节图，其显示凹陷102形成之后的鳍状物60的其他结构。富锗层68位于最终鳍状场效晶体管中即将作为通道区的整体，并延伸于轻掺杂源极/漏极区90之间。轻掺杂源极/漏极区90亦形成于具有富锗层68的鳍状物60的部分中。如此一来，轻掺杂源极/漏极区90的上侧部分的锗浓度，高于轻掺杂源极/漏极区90的下侧部分的锗浓度。轻掺杂源极/漏极区90及通道区中的富锗层68的厚度T1(如上述)可一致。
在图16A与16B中，形成栅极介电层104与栅极106于凹陷102中。顺应性地形成界面层于鳍状物60上及凹陷102中。界面层亦可覆盖层间介电层100的上表面。界面层的形成方法可为沉积制程如化学气相沉积制程、物理气相沉积制程、原子层沉积制程、或类似制程。栅极介电层104可形成于界面层上。栅极介电层104可顺应性地沉积于凹陷102中，比如沉积于鳍状物60的上表面与侧壁上。栅极介电层104亦可沿着层间介电层100的上表面形成。栅极介电层104可为高介电常数的介电材料，其介电常数大于约7.0，且可包含铪、铝、锆、镧、镁、钡、钛、铅、或上述的组合的金属氧化物或金属硅酸盐。栅极介电层104的形成方法可包括分子束沉积、原子层沉积、等离子体增强化学气相沉积、或类似方法。接着沉积栅极层于栅极介电层104上及凹陷102中。栅极层可为含金属材料如氮化钛、氮化钽、碳化钽、钴、钌、铝、上述的组合、或上述的多层。栅极层可包含任意数目的功函数调整层。可进行平坦化制程如化学机械研磨，以移除层间介电层100的上表面上的栅极介电层104与栅极层的多余部分。栅极层的保留部分形成栅极106，其可与其他层状物组恒以形成最终鳍状场效晶体管的置换栅极。栅极介电层104与栅极106可一起称作最终鳍状场效晶体管的栅极或栅极堆叠。栅极堆叠可沿着鳍状物60的通道区侧壁延伸。
在图17A与17B中，层间介电层110沉积于栅极堆叠与层间介电层100上。在一实施例中，层间介电层110为可流动的化学气相沉积法所形成的可流动膜。在一些实施例中，层间介电层110的组成为介电材料，比如磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、或类似物，且其沉积方法可为任何合适方法如化学气相沉积或等离子体增强化学气相沉积。
此外，形成源极/漏极接点112与栅极接点114以穿过层间介电层100与110。形成穿过层间介电层100与110的开口以用于源极/漏极接点112，并形成穿过层间介电层110的开口以用于栅极接点114。开口的形成方法可采用可接受的光微影与蚀刻技术。衬垫层(如扩散阻障层、粘着层、或类似物)与导电材料形成于开口中。衬垫层可包含钛、氮化钛、钽、氮化钽、或类似物。导电材料可为铜、铜合金、银、金、钨、钴、铝、镍、或类似物。可进行平坦化制程以自层间介电层110的表面移除多余材料。保留的衬垫层与导电材料形成源极/漏极接点112及栅极接点114于开口中。可进行退火制程以形成硅化物于外延的源极/漏极区96与源极/漏极接胆112之间的界面。源极/漏极接点112物理与电性耦接至外延的源极/漏极区96，而栅极接点114物理与电性耦接至栅极106。源极/漏极接点112与栅极接点114可由不同制程形成，或者由相同制程形成。虽然附图中的源极/漏极接点112与栅极接点114形成于相同剖面中，但应理解其可形成于不同剖面中以避免接点短路。
在上述实施例中，在形成浅沟槽隔离区64之后进行锗凝结制程66。然而应理解的是，可在形成p型装置所用的其他制程步骤之后进行锗凝结制程66。
在一些实施例中，在形成浅沟槽隔离区64之前进行锗凝结制程66。图18是图7中的区域10的细节图，显示在形成浅沟槽隔离区64之前进行锗凝结制程66的鳍状物60的额外结构。在这些实施例中，鳍状物60的第二部分60B可具有一致的第二宽度W2，而鳍状物60的第一部分60A可具有一致的第三宽度W3。在浅沟槽隔离区64的上表面下，可能改变鳍状物宽度。由于锗凝结制程66时亦可蚀刻第一部分60A，第三宽度W3可小于第一宽度W1(见图8)且可大于第二宽度W2。
在一些其他实施例中，移除虚置栅极82与虚置栅极介电层84之后，再进行锗凝结制程66。图19是图14B中区域12的细节图，显示形成凹陷102之后，再进行锗凝结制程66的鳍状物60的额外结构。在这些实施例中，富锗层68只沿着凹陷102所露出的鳍状物60的部分延伸(比如沿着最终鳍状场效晶体管的通道区延伸)，而轻掺杂源极/漏极区90可具有一致的锗浓度。此外，只有凹陷102露出的鳍状物60的部分具有第二宽度W2(见图20)。鳍状物60的其他区域(比如栅极密封间隔物92与栅极间隔物94下的其他区域)仍维持第一宽度W1(见图21)。最后，锗凝结制程66可使凹陷102延伸距离D1，以减少最终鳍状场效晶体管的通道区中的鳍状物60的高度。如此一来，栅极介电层104的下表面低于鳍状物60的最顶部表面(比如轻掺杂源极/漏极区90的最顶部表面)，见图22。
实施例可达一些优点。形成低锗浓度的半导体层52(见图3)，在形成鳍状物60的蚀刻制程(见图4)时有助于避免鳍状物侧壁变形。在形成鳍状物60的蚀刻制程后进行锗凝结制程66(见图7)以增加鳍状物60的锗浓度，可增加鳍状物60的载子迁移率。因此可增加最终p型装置的通道区迁移率，并可降低形成鳍状物时的鳍状物变形风险。
在一实施例中，方法包括：成长半导体层于基板上，基板包括硅，且半导体层包括硅锗；蚀刻沟槽于半导体层与基板中，以自沟槽之间的半导体层与基板的部分形成鳍状物；在鳍状物的上表面与侧部上进行氢自由基处理制程，且在氢自由基处理制程之后减少鳍状物的上表面与侧部的硅浓度；以及沿着鳍状物的上表面与侧部形成金属栅极堆叠。
在方法的一些实施例中，进行氢自由基处理制程的步骤包括：配送包括第一气体与第二气体的气体源至鳍状物的上表面与侧部上，第一气体为氢气，且第二气体为钝气；以及产生氢等离子体以转换第一气体成氢自由基。在方法的一些实施例中，进行氢自由基处理制程的步骤还包括：由氢自由基与鳍状物的硅锗形成硅烷，以及由氢自由基与鳍状物的硅锗形成锗烷，且形成锗烷的第二速率小于形成硅烷的第一速率。在方法的一些实施例中，进行氢自由基处理制程的步骤还包括：以氢等离子体蚀刻鳍状物的上表面与侧部。在方法的一些实施例中，在蚀刻腔室中进行氢自由基处理制程，且进行氢自由基处理制程的步骤还包括：在形成硅烷与锗烷时，自蚀刻腔室移除硅烷与锗烷。在方法的一些实施例中，氢自由基处理制程的温度介于约100℃至约600℃之间。在方法的一些实施例中，氢自由基处理制程的时间小于约100秒。在方法的一些实施例中，氢自由基处理制程的压力介于约0.1Torr至约6Torr之间。
在一实施例中，方法包括：形成自基板延伸的鳍状物，且鳍状物包括含硅的下侧部分与含硅锗的上侧部分；自鳍状物的侧部与上表面同时移除硅与锗，其以第一速率移除硅，以第二速率移除锗，且第二速率小于第一速率；以及形成源极区与漏极区于鳍状物中。
在一些实施例中，方法还包括：在移除硅与锗之前，形成隔离区于鳍状物周围。在一些实施例中，方法还包括：在移除硅与锗之后，形成隔离区于鳍状物周围。在一些实施例中，方法还包括：在移除硅与锗之前，沿着鳍状物的上表面与侧部形成金属栅极堆叠。在一些实施例中，方法还包括：在移除硅与锗之后，沿着鳍状物的上表面与侧部形成金属栅极堆叠。在方法的一些实施例中，移除硅与锗的步骤包括：暴露鳍状物的上表面与侧部至氢自由基，氢自由基与鳍状物的硅以第一速率反应形成硅烷，氢自由基与鳍状物的锗以第二速率反应形成锗烷。
在一实施例中，装置包括：基板；第一半导体层，自基板延伸，且第一半导体层包括硅；第二半导体层，位于第一半导体层上，且第二半导体层包括硅锗，其中第二半导体层的边缘部分具有第一锗浓度，第二半导体层的中心部分具有第二锗浓度，第二锗浓度小于第一锗浓度，第二半导体层的边缘部分包括第二半导体层的侧部与上表面；栅极堆叠，位于第二半导体层上；轻掺杂源极/漏极区，位于第二半导体层中，且轻掺杂源极/漏极区与栅极堆叠相邻；以及源极与漏极区，延伸至轻掺杂源极/漏极区中。
在装置的一些实施例中，整个轻掺杂源极/漏极区具有第二锗浓度。在装置的一些实施例中，轻掺杂源极/漏极区的上侧部分具有第一锗浓度，且轻掺杂源极/漏极区的下侧部分具有第二锗浓度。在装置的一些实施例中，第一半导体层具有第一宽度，第二半导体层的下侧部分具有第一宽度，第二半导体层的上侧部分具有第二宽度，且第二宽度小于第一宽度。在装置的一些实施例中，第一半导体层具有第一宽度，第二半导体层的上侧部分与下侧部分具有第二宽度，且第二宽度小于第一宽度。在装置的一些实施例中，栅极堆叠包括：栅极介电层，位于第二半导体层上，与门极介电层的下表面低于轻掺杂源极/漏极区的上表面；以及栅极，位于栅极介电层上。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范围，并可在未脱离本发明的精神与范围的前提下进行改变、替换、或变动。

Claims (1)

1.一种半导体装置的形成方法，包括：
成长一半导体层于一基板上，该基板包括硅，且该半导体层包括硅锗；
蚀刻多个沟槽于该半导体层与该基板中，以自所述沟槽之间的该半导体层与该基板的部分形成一鳍状物；
在该鳍状物的上表面与侧部上进行一氢自由基处理制程，且在该氢自由基处理制程之后减少该鳍状物的上表面与侧部的硅浓度；以及
沿着该鳍状物的上表面与侧部形成一金属栅极堆叠。
CN201910440377.1A 2018-06-29 2019-05-24 半导体装置的形成方法 Pending CN110660738A (zh)

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