TWI814951B - 有可控制的通道長度的半導體裝置 - Google Patents

有可控制的通道長度的半導體裝置 Download PDF

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TWI814951B
TWI814951B TW108143081A TW108143081A TWI814951B TW I814951 B TWI814951 B TW I814951B TW 108143081 A TW108143081 A TW 108143081A TW 108143081 A TW108143081 A TW 108143081A TW I814951 B TWI814951 B TW I814951B
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TW202119633A (zh
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申鉉光
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南韓商啟方半導體有限公司
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Abstract

一種半導體裝置包括環形閘極電極，其具有安置在基板上之開口區域；源極區域及塊狀分接頭區域，其安置於該開口區域中；井區域，其經安置以重疊該環形閘極電極；漂移區域，其經安置以與該井區域接觸；第一絕緣隔離區域，其安置在該漂移區域上以部分地重疊該閘極電極；第二絕緣隔離區域，其圍封該塊狀分接頭區域；汲極區域，其經安置以與該環形閘極電極間隔開；以及深溝渠隔離區域，其鄰近於該汲極區域地安置。

Description

有可控制的通道長度的半導體裝置
本揭示內容係關於一種半導體裝置，且更特定言之，係關於一種有可控制的通道長度的高電壓半導體裝置以及其製造方法。
相關申請案之交叉參考
本申請案主張2019年7月24日在韓國智慧財產局申請的韓國專利申請案第10-2019-0089840號的益處，出於所有目的將其全部揭示內容以引用之方式併入本文中。
大體而言，一或多個高電壓電晶體安置在同一晶片上之積體電路連同低電壓電路廣泛用於多種電性應用。在此類積體電路中，延伸汲極MOS(Extended Drain MOS；EDMOS)電晶體、橫向雙擴散MOS(Laterally Double Diffused MOS；LDMOS)電晶體及其類似物對於高電壓半導體裝置為至關重要的。
隨著半導體裝置的整合程度提高，熟知在高電壓半導體裝置之設計中，需要不斷的按比例縮小且將確保充足操作特性。
替代技術在藉由矩形型nEDMOS實施高電壓時具有限制。另外，當接面隔離用於塊狀晶圓中時，晶片大小歸因於經接面隔離區域佔據的區域而增大。此外，接面隔離技術在實施高崩潰電壓(breakdown voltage；BVDSS)時 具有限制。另外，矩形型nEDMOS具有限制，其中由於電場可集中於每一拐角處，所以無法獲得高崩潰電壓。
提供此發明內容來以簡化形式介紹下文在實施方式中進一步描述之一系列概念。此發明內容並不意欲識別所主張之主題之關鍵特徵或基本特徵，亦不意欲在判定所主張的主題之範疇中用作輔助。
在一個通用態樣中，半導體裝置包括：環形閘極電極，其具有安置在基板上之開口區域；源極區域及塊狀分接頭區域，其安置於開口區域中；井區域，其經安置以重疊環形閘極電極；漂移區域，其經安置以與井區域接觸；第一絕緣隔離區域，其安置在漂移區域上以部分地重疊閘極電極；第二絕緣隔離區域，其圍封塊狀分接頭區域；汲極區域，其經安置以與環形閘極電極間隔開；以及深溝渠隔離區域，其鄰近於汲極區域地安置。
第二絕緣隔離區域可經塑形以部分地圍封源極區域。
半導體裝置可進一步包括安置於井區域之下的深井區域。
半導體裝置可進一步包括安置在基板上之掩埋氧化物膜及安置在掩埋氧化物膜上之掩埋雜質層。深溝渠隔離區域可比第一絕緣隔離區域更深且經安置以與掩埋氧化物膜之上部表面接觸。
深井區域、井區域以及環形閘極電極可彼此重疊。
在另一通用態樣中，半導體裝置包括：環形閘極電極，其具有在基板上之開口區域；源極區域，其安置於開口區域中；井區域，其經安置以重疊環形閘極電極；以及汲極區域，其經安置與環形閘極電極間隔開。環形閘極電極之每一拐角具有第一曲率半徑，井區域之每一拐角具有第二曲率半徑，且第一曲率半徑大於第二曲率半徑。
半導體裝置可進一步包括井區域之下的深井區域。深井區域之每一拐角可具有第三曲率半徑，且第二曲率半徑可大於第三曲率半徑。
半導體裝置可進一步包括：第一絕緣隔離區域，其經安置以重疊環形閘極電極；及深溝渠隔離區域，其圍封環形閘極電極。深溝渠隔離區域之深度可比第一絕緣隔離區域之深度更深。
深井區域、井區域以及環形閘極電極可彼此重疊。
在另一通用態樣中，半導體裝置包括：掩埋氧化物膜，其在基板上；掩埋雜質層，其安置於掩埋氧化物膜中；深井區域，其經安置以與掩埋雜質層接觸；井區域，其安置在深井區域上且具有與深井區域相同的導電性類型；第一及第二漂移區域，其經安置以與井區域接觸；閘極電極，其經安置以重疊第一及第二漂移區域中之每一者；源極區域及塊狀分接頭區域，其安置於閘極電極之間且安置於井區域中；以及汲極區域，其經安置以與閘極電極間隔開預定距離。
閘極電極可具有帶開口區域的環形形狀。
半導體裝置可進一步包括第一絕緣隔離區域，其安置在漂移區域上且與閘極電極重疊；第二絕緣隔離區域，其完全地包圍塊狀分接頭區域；以及深溝渠隔離區域，其靠近汲極區域安置。
第二隔離區域可經塑形以部分地圍封源極區域。
深溝渠隔離區域可比絕緣隔離區域更深且可經安置以與掩埋氧化物膜接觸。
深井區域、井區域以及閘極電極可彼此重疊。
在俯視圖中，深井區域、井區域以及閘極電極各自拐角具有彎曲形的拐角。
半導體裝置的通道長度可藉由橫向地移位虛擬線越過彼此間呈重疊關係的深井區域、井區域及閘極電極來控制。
半導體裝置的通道長度可藉由橫向地移位虛擬線越過彼此間呈重疊關係的井區域及閘極電極來控制。
在另一通用態樣中，半導體裝置包括：閘極電極，其具有安置在基板上的開口區域；絕緣隔離區域；井區域；漂移區域；汲極區域；以及深溝渠隔離區域。安置於開口區域中之絕緣隔離區域具有描繪源極區域及塊狀分接頭區域之輪廓。井區域經安置以重疊閘極電極。漂移區域經安置以與井區域接觸。汲極區域經安置以與閘極電極間隔開。深溝渠隔離區域鄰近於汲極區域地安置。
絕緣隔離區域可經構形(contoured)以部分地圍封源極區域中之每一者。
井區域及閘極電極中之每一者可具有圓化矩形輪廓。
自以下實施方式、圖式以及申請專利範圍將顯而易見其他特徵及態樣。
3RA、3RB、4RR、5RR、6RR、7RR:曲率半徑
10:基板
10A、10B、10C、10D、10K:長度
20:掩埋氧化物層/掩埋氧化物膜
30、31、32:N型掩埋雜質層
40:P型磊晶層
50:N型深井
60:P型深井
72:第一絕緣隔離區域
73:第二絕緣隔離區域
75:深溝渠隔離區域
76:第三絕緣隔離區域
81L、81R:N型井
83L、83R:源極區域
85L、85R:汲極區域
87:高度摻雜P型(P+)塊狀分接頭區域
90:漂移區域
90L、90R:N型漂移區域
100:P型井
105:閘極絕緣膜
110、126:閘極電極
115:開口區域
124、130:矽化物層
B:塊狀端子
D1、D2:汲極區域
G:閘極端子
K:曲率
L1、L1'、L2、L3:通道長度
S1、S2:源極端子
R1、R2、3RA、3RB、4RR、5RR、6RR、7RR:曲率半徑
YY1、YY1'、YY2、YY2'、YY3、YY3'、YY4、YY4':點線
[圖1]為本揭示之半導體裝置的實例之截面圖。
[圖2]為說明本揭示之半導體裝置中的源極區域及塊狀分接頭區域之實例的放大俯視圖。
[圖3A]至[圖5B]為說明一種用於製造本揭示之半導體裝置的實例之方法的截面圖。
[圖6A]為本揭示之半導體裝置的實例之俯視圖。
[圖6B]為圖6A之中心部分的放大俯視圖。
[圖7]為說明圖6A中所說明之半導體裝置的拐角曲率之俯視圖。
[圖8A]為有可控制的通道長度的半導體裝置之實例的截面圖。
[圖8B]為增大通道長度之後半導體裝置的實例之截面圖。
[圖9]至[圖11]為根據本揭示之半導體裝置的其他實例之俯視圖，其中通道長度為可控制的。
[圖12]展示根據本揭示之半導體裝置的操作之電壓-電流曲線圖。
貫穿圖式及實施方式的相同元件符號係指相同元件。圖式可未按比例繪製，且為了清晰性、說明以及便利起見，可放大圖式中的元件的相對大小、比例以及描繪。
提供以下實施方式以幫助讀者獲得對本文中所描述的方法、設備及/或系統的全面理解。然而，在理解本申請案之揭示內容之後，本文中所描述的方法、設備及/或系統的各種變化、修改以及等效物將顯而易見。舉例而言，除必定以某一次序出現的操作之外，本文中所描述之操作順序僅為實例，且不限於本文中所闡述之彼等，但如將在理解本申請案的揭示內容之後顯而易見，可改變。又，出於提高清晰性及簡潔性之目的，可省略此項技術中已知的特徵之描述。
本文中所描述的特徵可以不同形式體現，且不應將所述特徵解釋為限於本文中所描述的實例。實情為，已提供本文中所描述之實例，僅為說明在理解本申請案的揭示內容之後將顯而易見的實施本文中所描述之方法、設備及/或系統的許多可能方式中的一些。
在本說明書通篇中，當諸如層、區域或基板之元件被描述為「在另一元件上」、「連接至另一元件」或「耦接至另一元件」時，該元件可「在另一元件正上方」、「直接連接至另一元件」或「直接耦接至另一元件」，或其間可介入一或多個其他元件。相反地，當元件被描述為「在另一元件正上方」、「直接連接至另一元件」或「直接耦接至另一元件」時，其間可不介入其他元件。
如本文中所使用，術語「及/或」包括相關聯之所列出條目中之任何兩者或兩者以上的任何一個及任何組合。
儘管諸如「第一」、「第二」及「第三」之術語可在本文中用以描述各個構件、組件、區域、層或區段，但此等構件、組件、區域、層或區段並不受限於此等術語。實情為，此等術語僅用於區分一個構件、組件、區域、層或區段與另一構件、組件、區域、層或區段。因此，在不背離實例之教示的情況下，本文中所描述之實例中所指的第一構件、組件、區域、層或區段亦可稱作第二構件、組件、區域、層或區段。
為易於描述，本文中可使用諸如「在...上方」、「上部」、「在...下方」及「下部」之空間相對術語來描述如圖式中所示的一個元件與另一元件的關係。除圖式中所描繪之定向以外，此等空間相對術語意欲涵蓋裝置在使用或操作中之不同定向。舉例而言，若圖式中之裝置翻轉，則描述為相對於另一元件在「上方」或「上部」的元件將隨後相對於該另一元件在「下方」或「下部」。因此，術語「在...上方」涵蓋視裝置之空間定向而定的上方及下方定向兩者。裝置亦可以其他方式定向(舉例而言，旋轉90度或呈其他定向)，且因此解譯本文中所使用之空間相對術語。
本文中所使用之術語僅用於描述各種實例，且並非用以限制本揭示。除非上下文以其他方式明確指示，否則冠詞「一(a/an)」及「該」意欲同樣包括複數形式。術語「包含」、「包括」及「具有」指定存在所陳述之特徵、數值、操作、構件、元件及/或其組合，但並不排除存在或添加一或多個其他特徵、數值、操作、構件、元件及/或其組合。
歸因於製造技術及/或容限，可出現圖式中所示之形狀的變化形式。因此，本文中所描述之實例不限於圖式中所示之特定形狀，但包括製造期間出現的形狀變化。
在本文中，應注意術語「可」相對於實例或具體實例之使用(例如關於可包括或實施何種實例或具體實例)意謂存在包括或實施此類特徵的至少一個實例或具體實例，但所有實例及具體實例不限於此。
在下文中，本揭示之實例將參考隨附圖式進行描述。將聚焦於理解根據本揭示之操作及動作所必需的部分進行詳細描述。在描述本揭示之實例時，將省略技術領域中已熟知且與本揭示不直接相關的技術性特徵之描述。此藉由省略不必要描述來更清晰地傳遞想法而不混淆本揭示之主題。
另外，在描述本揭示之組件時，不同元件符號可根據圖式給定至具有相同名稱的組件，且相同元件符號可給定至不同圖式。然而，即使在此類情況下，並不意謂對應組件根據實例具有不同功能，或並不意謂所述組件在不同實例中具有相同功能。基於每一組件之描述進行判斷。
根據本揭示之實例，將在半導體裝置經施加至具有N通道之延伸汲極MOS(EDMOS)電晶體的情況下描述該半導體裝置。在以下描述中，P型可稱為第一導電性類型，且N型可稱為第二導電性類型。當然，本揭示之技術性要點可同樣施加至具有P通道之EDMOS電晶體，且在pEDMOS之情況下，第一導電性類型可為N型且第二導電性類型可為P型。
另外，在以下描述中，當半導體裝置之基板為P型時，井區域可為N型，且根據另一實例，當基板為N型時，井區域可為P型。
本揭示在有可控制的通道長度的高電壓半導體裝置中提供半導體裝置，其能夠確保充足操作電壓，提高整合程度且確保崩潰電壓高於操作電壓。
圖1為本揭示之半導體裝置的實例之截面圖。圖6A為本揭示之半導體裝置的俯視圖。
參看圖1及圖6A，半導體裝置包括基板10、掩埋氧化物層20、N 型掩埋雜質層(N-type buried layers；NBL)30、31及32、P型磊晶層(P-epi)40及N型深井(N-type deep well；DNW)50、P型深井(P-type deep well；DPW)60、N型井(N-type well；NW)81L及81R、P型井(P-type well；PW)100、閘極絕緣膜105以及閘極電極110。
參看圖1，半導體裝置可包括：掩埋氧化物膜(buried oxide film；BOX)20，其安置在基板10上；NBL 30，其安置在BOX 20上；以及P-epi 40，其安置在NBL 30上。半導體裝置進一步包含在平面圖中在P-epi 40上呈拐角圓化矩形形狀的PW 100(參見圖6A)。NW 81L及81R在水平方向上以預定距離與P-epi 40上之PW 100間隔開且包圍PW 100的外部。需要P-epi 40以便維持崩潰電壓(BVDSS，例如260V)高於操作電壓(例如，200V)。P-epi 40的區域藉由DNW 50之熱擴散變小，但並未消除。
參看圖1，DNW 50及DPW 60分別安置在NW 81L及81R的下部表面及PW 100的下部表面上。如所示，PW 100的水平區域(直徑)大於DPW 60的水平區域(直徑)。另外，PW 100之濃度經設計以高於DPW 60之濃度。NW 81L及81R分別安置在DNW 50之上部表面的一部分上。DNW 50及DPW 60分別深入地形成使得每一深井之底面接觸NBL 30。當需要時，DPW 60可不與NBL 30接觸。
另外，參看圖1，半導體裝置可包括安置在PW 100之上部表面的一部分上的高度摻雜P型(P+)塊狀分接頭區域87。高度摻雜N型(N+)源極區域83L及83R以預定距離與PW 100之上部表面上之塊狀分接頭區域87的兩側間隔開。高度摻雜N型(N+)汲極區域85L及85R分別安置在NW 81L及81R、N型漂移區域90L及90R、閘極絕緣膜105以及閘極電極110之上部表面的一部分上。
參看圖1，兩個對稱EDMOS裝置圍繞塊狀分接頭區域87形成。儘管僅兩個EDMOS裝置示出於本揭示中，但可配置超過兩個EDMOS裝置。 EDMOS裝置愈多，則愈多電流可流動。P型可稱為第一導電性類型，且N型可稱為第二導電性類型。反之亦為可能的。
參看圖1，N型漂移(N漂移)區域90L及90R的側面經形成以分別地接觸NW 81之一個側面以及PW 100之側面。如圖1中所說明，N漂移區域90L及90R形成為四邊形形狀，該四邊形形狀接界(border)NW 81之一個側面以及PW 100的側面。
參看圖1，閘極絕緣膜105及閘極電極110經形成以覆蓋N型漂移區域90L及90R之上部表面的相應部分以及PW 100之上部表面的一部分。在平面圖中，閘極電極110在每一拐角處經形成為圓化的(參見圖6A)。由於閘極電極110具有環形形狀，因此開口區域115形成於中心中。源極區域83L及83R以及塊狀分接頭區域87形成於閘極電極110之開口區域115中。閘極電極110重疊DPW區域60及PW區域100兩者。
參看圖1，半導體裝置之上部表面的部分覆蓋有第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76。第一絕緣隔離區域72經形成以重疊閘極電極110。第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76可通過淺溝渠隔離(Shallow Trench Isolation；STI)製程形成。第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76具有用於藉由塊狀分接頭區域87、源極區域83L及83R以及汲極區域85L及85R的開口部分將相應區域有效隔離的結構。在下文中，在本說明書中，絕緣隔離區域之塊狀分接頭區域的開口區域稱為第二隔離區域73。第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76分別比塊狀分接頭區域87、源極區域83L及83R以及汲極區域85L及85R更深地形成，且比N型漂移區域90L及90R、NW區域81L及81R以及PW區域100更淺地形成。
參看圖1，半導體裝置經深溝渠隔離區域75隔離。深溝渠隔離區 域75經深入地且垂直地形成以自絕緣隔離區域76之上部表面與掩埋氧化物膜20接觸。此外，如圖6A中所示，自俯視圖查看，深溝渠隔離區域75經形成為閉合迴路。深溝渠隔離區域75之閉合迴路可具有諸如四邊形之多邊形形狀，其包括開口區域115，或可具有根據各種實例的環形形狀。深溝渠隔離區域75可通過深溝渠隔離(Deep Trench Isolation；DTI)製程形成。亦即，半導體裝置經分割成掩埋氧化物膜20、第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76以及深溝渠隔離區域75以與鄰近之半導體裝置隔離。絕緣隔離區域76藉由與深溝渠隔離區域75彼此重疊而形成。為最小化晶片區域，深溝渠隔離區域75通過絕緣隔離區域76形成。因此，絕緣隔離區域76藉由與深溝渠隔離區域75彼此重疊而形成。
總體而言，參看圖1及圖6A，本揭示之半導體裝置包括：環形閘極電極110，其具有在基板上之開口區域115；源極區域83L及83R以及塊狀分接頭區域87，其形成於開口區域中；隔離區域73，其完全地包圍塊狀分接頭區域87；PW區域，其經形成以重疊閘極電極；漂移區域90，其經形成以與PW區域接觸；第一絕緣隔離區域72，其形成於漂移區域上且與閘極電極重疊；汲極區域，其經形成以與閘極電極間隔開預定距離；以及深溝渠隔離區域，其包圍汲極區域。
參看圖1及圖6A，絕緣隔離區域73具有形狀Ⅱ且包括：掩埋氧化物膜及掩埋雜質層，其形成於基板上；DPW區域，其經形成以與PW區域及掩埋雜質層接觸；以及DNW區域，其經形成以與漂移區域及掩埋雜質層接觸。
深溝渠隔離區域比絕緣隔離區域更深且經形成以與掩埋氧化物層接觸。
圖2為說明本揭示之半導體裝置中之源極區域及塊狀分接頭區域的放大俯視圖。
參考圖2，第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕 緣隔離區域76經圖案化以具有用於塊狀分接頭區域87以及源極區域83L及83R的開口。不同於LDMOS，EDMOS需要塊狀分接頭區域87與源極區域83L及83R隔離。為此，第二絕緣隔離區域73形成於源極區域83L及83R與塊狀分接頭區域87之間。第二絕緣隔離區域73完全地包圍塊狀分接頭區域87。此處，第一源極區域83L及第二源極區域83R分別地形成於塊狀分接頭區域87之兩側上。
參考圖2，在俯視圖中，第二絕緣隔離區域73具有形狀『Ⅱ』。第二絕緣隔離區域73具有閉合迴路以將塊狀分接頭區域87與源極區域83L及83R隔離。塊狀分接頭區域87安置於閉合迴路內部。連接至塊狀分接頭區域87之複數個塊狀端子B亦安置於閉合迴路內部。源極區域83L及83R安置於閉合迴路外部。源極區域83L及83R經連接至複數個源極端子S1及S2。
第二絕緣隔離區域73形成於DPW區域60及磊晶層40上方。淺溝渠隔離或中等溝渠隔離或LOCOS用於第二絕緣隔離區域73。將諸如氧化矽、HDP等的絕緣材料填充至淺溝渠隔離中。
圖3A至圖5B為說明一種用於製造本揭示之半導體裝置之方法的實例之截面圖。
參看圖3A，掩埋氧化物膜(BOX)20形成於基板10上，且NBL 30形成於BOX 20上。NBL 30用於改良EDMOS電晶體之崩潰電壓特性，且NBL 30之雜質摻雜濃度理想地高於DPW區域60及DNW區域50的雜質摻雜濃度。
參看圖3A，P-epi 40形成於NBL 30上。磊晶層40之厚度高於NBL 30之厚度。
參看圖3A，DPW區域60垂直地深入形成以與P-epi 40之底面(亦即，NBL 30)接觸。DNW區域50亦自P-epi 40之頂面垂直地深入形成以與底面(亦即，NBL 30)接觸。
參看圖3A，當DPW區域60及DNW區域50經形成以與NBL 30之上 部表面接觸時，穩定地形成電位輪廓。另外，由於DNW區域50包圍半導體裝置之最外部部分，因此崩潰電壓為穩定的。
參看圖3B，第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76形成於基板10上。第一絕緣隔離區域72、第二絕緣隔離區域73及第三絕緣隔離區域76係以淺溝渠隔離(STI)類型、中等溝渠隔離(MTI)製程或LOCOS製程形成的。形成於絕緣隔離區域72、73及76之中間部中之絕緣隔離區域73經形成以隔離源極區域及塊狀分接頭區域或隔離鄰近於本發明半導體裝置地安置的另一半導體裝置。
參看圖4A，PW區域100形成於中心部分中之絕緣隔離區域73之下。PW區域100之深度經形成以接觸DPW區域60。PW區域100經形成以在平行於基板10之頂面的水平方向上具有比DPW區域60之寬度更長的寬度。在俯視圖中，PW區域100在每一拐角處具有圓形形狀(參見圖6A)。
參看圖4A，NW區域81L及81R形成於DNW區域50上。NW區域81L及81R以比DNW區域50窄的水平長度(直徑)形成。在俯視圖中，NW區域81L及81R具有矩形形狀(參見圖6A)。
另外，參看圖4A，漂移區域90L及90R分別地形成於PW區域100之兩側處。漂移區域90L及90R亦在通道長度方向上接觸NW區域90L及90R。漂移區域90L及90R由N型雜質形成，且與PW區域100形成接面區域。
參看圖4B，閘極絕緣膜105及閘極電極110安置於半導體裝置上。
閘極絕緣膜105及閘極電極110安置於PW區域100之上部表面的一部分及漂移區域90L及90R之上部表面的一部分上。閘極電極110具有環型形狀。因此，閘極電極110具有開口區域，其中絕緣隔離區域73、塊狀分接頭區域87以及源極區域83L及83R形成於其中。
參看圖5A，將P型雜質佈植至PW區域100中以形成P型塊狀分接 頭區域87來將偏壓輸入至PW區域。另外，將N型雜質佈植至基板10中之絕緣隔離區域72及76的開口中，以形成N型源極區域83L及83R以及汲極區域85L及85R。N型汲極區域85L及85R與漂移區域90L及90R之一個側面接觸。
汲極區域85L及85R、源極區域83L及83R以及塊狀分接頭區域87具有比絕緣隔離區域72、73及76、PW區域100以及NW區域81R及81L之深度更淺的深度。
參看圖5B，矽化物層130形成於汲極區域85L及85R、源極區域83L及83R以及塊狀分接頭區域87上，且形成於閘極電極110上以降低鎢(W)插頭與基板10或閘極電極110之間的接觸電阻。矽化物層130包括例如矽化鈦、或矽化鈷、或矽化鎳。
參看圖5B，半導體裝置可藉由垂直地深入形成深溝渠隔離區域75來與其他鄰近半導體裝置隔離。深溝渠隔離區域75可藉由使用深溝渠隔離(DTI)製程形成且與BOX 20接觸。深溝渠隔離區域75與第三絕緣隔離區域(或STI)76重疊。深溝渠隔離區域75通過第三絕緣隔離區域(或STI)76形成以促進製程且減小晶片區域。
此外，在閘極電極110或矽化物結構130形成於半導體裝置之製造製程中之後，執行用於隔離裝置的深溝渠隔離(DTI)製程。由於在矽化物製程之後執行形成DTI結構的製程，因此有可能防止由DTI製程之後執行的退火製程所引起的各種缺陷且有可能減小形成DTI結構之半導體裝置之製造製程的步驟數。因此，結合此實例，有可能減少製造時間及花費。
將汲極區域D1及D2、源極端子S1及S2、塊狀端子B以及閘極端子G分別地連接至汲極區域85L及85R、源極區域83L及83R、塊狀分接頭區域87以及閘極電極110。汲極區域D1及D2、源極端子S1及S2、塊狀端子B以及閘極端子G可藉由鎢插頭或Cu或Cu-Al金屬形成。
圖6A為根據本揭示之半導體裝置之實例的俯視圖，且圖6B為圖6A之中心部分的放大俯視圖。
參看圖6A，半導體裝置可包括DPW 60、P型井(PW)100、閘極電極110、NW 81L及81R以及N型深井(DNW)50。矩形之頂點可經設計為具有恆定曲率之圓化頂點，使得DPW 60、PW區域100、閘極電極110及DNW區域50在每一拐角處具有圓化矩形形狀，進而減輕每一拐角處的電場之濃度。曲率半徑愈大，則崩潰電壓(breakdown voltage；BV)維持可能愈佳。此可使得待實施之崩潰電壓潛在地大於280V或甚至400V。參看圖6A，深溝渠隔離區域75藉由閉合迴路形狀包圍半導體裝置。
參看圖6B，環型閘極電極110之俯視圖具有帶恆定曲率K之圓化拐角。該環型閘極電極經形成以在每一拐角處具有恆定曲率半徑。環型閘極電極110具有開口115。
參看圖6B，在俯視圖中，絕緣隔離區域73可具有羅馬(Roman)字符Ⅱ。絕緣隔離區域73由閉合迴路形成以將塊狀分接頭區域87與源極區域83L及83R隔離。呈羅馬字符Ⅱ形式，塊狀分接頭區域87及塊狀分接頭區域中之複數個塊狀端子B安置於閉合迴路內部。呈羅馬字符Ⅱ形式，源極區域83L及83R以及源極區域中之複數個源極端子S1及S2安置在閉合迴路外部。
圖7為說明圖6A中所說明之半導體裝置的拐角曲率之俯視圖。
參看圖7，DPW 60經形成有帶恆定曲率K之圓化輪廓，使得俯視圖之每一拐角不為矩形。舉例而言，該DPW 60經形成為圓化矩形形狀。該DPW 60經形成以在每一拐角區域中具有恆定曲率半徑3RA。
參看圖7，PW區域100亦經形成以具有帶恆定曲率K之圓化輪廓，使得俯視圖之每一拐角不為矩形。舉例而言，該PW區域100經形成為圓化矩形形狀。該PW區域100經形成以在每一拐角區域中具有恆定曲率半徑3RB。
參看圖7，閘極電極110經形成以具有帶恆定曲率K之圓化輪廓，使得在俯視圖中每一拐角不為矩形。亦即，閘極電極110具有帶開口115之圓化矩形環。該閘極電極110經形成以在每一拐角區域中具有恆定曲率半徑6RR。假定閘極電極110之拐角具有第一曲率半徑6RR，且PW區域100之拐角具有第二曲率半徑3RB，則第一曲率半徑6RR大於第二曲率半徑3RB。另外，DPW 60之拐角具有第三曲率半徑3RA。第二曲率半徑3RB大於第三曲率半徑3RA。當曲率半徑增大時，拐角之成角部分經消除使得其更易於形成於製造製程中且更易於維持崩潰電壓(BVDSS)。
參看圖7，DNW(N型深井)區域50包圍DPW(P型深井)60。DNW區域50與DPW 60間隔開。亦即，DNW區域50為在中心區域中具有開口區域的環形形狀。DNW區域50亦經形成為以恆定曲率K圓化，使得每一拐角不為矩形。DNW區域50亦經形成以在每一拐角處具有恆定曲率半徑7RR。
參看圖7，在平面圖(俯視圖)中，點線YY1或YY2垂直地穿過DPW 60、PW區域100及閘極電極110。藉由朝向左側方向延伸點線YY1來增大通道長度。亦藉由朝向右側方向延伸點線YY2來增大通道長度。點線YY1或YY2為改變通道長度之起始線。將在圖8A及圖8B中進行詳細解釋。PW區域100及閘極電極110彼此重疊的重疊部分用於延伸或收縮通道長度。
參看圖7，半導體裝置包括：環形閘極電極110，其具有在基板上之開口區域115；源極區域83L及83R，其形成於開口區域中；PW區域100，其經形成以與閘極電極重疊；以及汲極區域85L及85R，其經形成以預定距離與閘極電極間隔開，其中閘極電極之拐角具有第一曲率半徑(6RR)，PW區域100的拐角具有第二曲率半徑3RB，且第一曲率半徑6RR大於曲率半徑3RB。
參看圖7，半導體裝置進一步包括在PW區域100之下的DPW 60，且其中DPW 60之拐角具有第三曲率半徑3RA且第二曲率半徑3RB大於第三曲率 半徑3RA。半導體裝置進一步包括：絕緣隔離區域72，其經形成以重疊閘極電極110；及深溝渠隔離區域75，其包圍閘極電極，其中深溝渠隔離區域75之深度比絕緣隔離區域72之深度更深。
圖8A為有可控制的通道長度的半導體裝置之實例的截面圖。圖8B為增大通道長度之後半導體裝置的實例之截面圖。
不同於替代圓形型DMOS，本揭示之EDMOS裝置可用作類比裝置，此係因為通道長度為可容易地控制的。
參看圖8A，長度『10B』為自閘極電極110之左側邊緣至PW區域100之右側邊緣的距離。長度『10B』可對應於通道長度。有效通道長度為自源極區域83R至PW區域100之右側邊緣的距離。PW區域100之右側邊緣與N型漂移區域90R接觸。長度『10A』為自左側閘極電極110之右側邊緣至PW區域100之左側邊緣的距離。PW區域100之左側邊緣與N型漂移區域90L接觸。長度『10K』為自DPW 60之右側邊緣至PW區域100之右側邊緣的距離。長度『10D』為自閘極電極110之右側邊緣至汲極區域85R的距離。
參看圖8A及圖8B，在截面圖中，點線YY1或YY2垂直地穿過DPW 60、PW區域100及閘極電極110。藉由自點線YY1延伸至點線YY1'來增大通道長度。亦藉由自點線YY2延伸至點線YY2'來增大通道長度。因此，獲得新的通道長度L1或L1'，如圖8B中所示。點線YY1或YY2為改變裝置之通道長度的起始線。藉由在X方向上延伸DPW 60、PW區域100及閘極電極110，增大了DPW 60、PW區域100及閘極電極110之每一長度，如圖8B中所示。
通道長度不與YY1與YY2之間的間隙有關。10K及10D之長度並未改變。10K及10D之長度可具有固定值。若長度『10D』改變，則崩潰電壓(BVDSS)及導通電阻(Ron)亦變化。同理適用於10K。可固定除DPW 60、PW區域100及閘極電極110重疊的部分以外的所有部分之長度。因此，DPW 60、PW 區域100及閘極電極110可維持恆定曲率。
當曲率隨著通道長度變化而改變時，汲極電流隨著汲極電壓而逐漸增大，使得該汲極電流無法用作類比裝置。因此，即使通道長度變化，曲率亦必須保持恆定，使得汲極電流可恆定，從而該汲極電流適用作類比裝置。
圖9及圖11為本揭示之有可控制的通道長度的半導體裝置之實例的截面圖。
圖9為根據本揭示之半導體裝置的第二實例之俯視圖，圖10為根據本揭示之半導體裝置之第三實例的俯視圖，且圖11為根據本揭示之半導體裝置之第四實例的俯視圖。
根據本揭示之實例之半導體裝置可藉由將矩形頂點設計為具有帶恆定曲率的圓形型，使得DPW 60、PW區域100、閘極電極110及DNW區域50具有圓化矩形形狀來防止電場集中。
如圖9中所示，通道長度L1藉由將點線YY2延伸至點線YY2'獲得。如圖10中所示，以相同方式，通道長度L2藉由將點線YY3延伸至點線YY3'獲得。如圖11中所示，通道長度L3藉由將點線YY4延伸至點線YY4'獲得。在本文中，如圖10或圖11中所示，閘極電極110之水平長度大於閘極電極110之垂直長度。
然而，即使X軸之長度如圖9至圖11中所示地變化，正方形之拐角邊緣的曲率半徑(R1、R2)亦維持一致。舉例而言，即使通道長度增大，DNW區域50之曲率半徑R1及PW區域100之曲率半徑R2亦維持恆定。半導體裝置之電特性可依據曲率半徑而變化。因此，需要將曲率半徑維持恆定。
圖12說明根據半導體裝置之操作之電壓-電流曲線圖。
參看圖12，即使在汲極電壓穩定地施加至200V時，仍穩定地供應汲極中之電流。換言之，電流特性為極佳的，使得半導體裝置之操作特性經改良。當曲率隨著現有圓形型通道之長度變化而改變時，本揭示之半導體裝置無法用 作類比裝置，此係因為汲極電流隨著汲極電壓逐漸增大。因此，藉由即使通道長度變化亦保持曲率恆定，且將汲極電流保持在恆定值下，該半導體裝置適用作類比裝置。亦即，不同於DMOS，通道為可控制的以用作類比裝置。
本揭示之半導體裝置包括：結構上深溝渠型隔離膜，進而相較於使用接面隔離技術隔離鄰近主動區域而具有更高崩潰電壓特性。因此，可有效地改良高電壓半導體裝置之操作電壓特性及整合程度。
另外，本揭示可藉由減小半導體裝置之總面積而減小半導體裝置之導通電阻，進而改良半導體裝置的操作特性。
雖然本揭示包括特定實例，但在理解本申請案之揭示內容之後，將顯而易見的為，可在不背離申請專利範圍及其等效物之精神及範疇的情況下在此等實例中對形式及細節進行各種變化。應僅以描述性意義而非出於限制性目的考慮本文中所描述的實例。應將每一實例中的特徵或態樣的描述視為適用於其他實例中的類似特徵或態樣。若以不同次序執行所描述技術，及/或若所描述系統、架構、裝置或電路中的組件以不同方式組合及/或用其他組件或其等效物來替換或補充，則可達成適合結果。因此，本揭示的範疇並非藉由實施方式界定，而係藉由申請專利範圍及其等效物界定，且應將屬於申請專利範圍及其等效物的範疇內的所有變化形式解釋為包括於本揭示中。
10:基板
20:掩埋氧化物層/掩埋氧化物膜
30、31、32:N型掩埋雜質層
40:P型磊晶層
50:N型深井
60:P型深井
72:第一絕緣隔離區域
73:第二絕緣隔離區域
75:深溝渠隔離區域
76:第三絕緣隔離區域
81L、81R:N型井
83L、83R:源極區域
85L、85R:汲極區域
87:高度摻雜P型(P+)塊狀分接頭區域
90L、90R:N型漂移區域
100:P型井
105:閘極絕緣膜
110:閘極電極
115:開口區域
130:矽化物層
B:塊狀端子
D1、D2:汲極區域
S1、S2:源極端子

Claims (10)

  1. 一種半導體裝置，其包含：源極區域及汲極區域，其分別安置於基板中；閉合迴路的閘極電極，其具有安置在所述基板上之開口區域且圍封形成在所述開口區域中的所述源極區域；P型深井區域，其安置在所述開口區域之下；N型漂移區域，其安置成與所述汲極區域相鄰；N型井區域，其安置在所述汲極區域之下；N型深井區域，其與所述P型深井區域間隔開且與所述漂移區域和所述N型井區域重疊；以及P型井區域，其環繞所述源極區域且安置成鄰接所述N型漂移區域；其中所述P型深井區域和所述N型深井區域形成較深，使得各個深井區域的下表面接觸N型掩埋層；以及其中該P型深井區域、該P型井區域以及該閉合迴路的閘極電極彼此重疊。
  2. 如請求項1之半導體裝置，其進一步包含：第一絕緣隔離區域，其安置在所述N型漂移區域上，以與所述閉合迴路的閘極電極部分地重疊；以及第二絕緣隔離區域，其圍封安置在所述P型井區域中的塊狀分接頭區域，其中該第二絕緣隔離區域經配置以部分地圍封該源極區域。
  3. 如請求項1之半導體裝置，其中所述閉合迴路的閘極電極包括：第一拐角和第二拐角；第一直線段，其在所述第一拐角和所述第二拐角之間；第三拐角和第四拐角，所述閉合迴路的閘極電極之每個拐角具有第一曲率 半徑；第二直線段，其在所述第三拐角和所述第四拐角之間，所述第一直線段和所述第二直線段彼此平行；以及垂直軸，其同時穿過所述第一直線段和所述第二直線段並且不與所述開口區域重疊，並且其中所述半導體裝置之通道長度是繞著所述垂直軸能延伸至所需長度。
  4. 如請求項2之半導體裝置，其進一步包含：深溝渠隔離區域，其安置成鄰近所述汲極區域；以及掩埋氧化物膜，其安置在該基板上，其中所述N型掩埋層安置在該掩埋氧化物膜上，其中該深溝渠隔離區域比該第一絕緣隔離區域更深且經安置以與該掩埋氧化物膜之上部表面接觸。
  5. 一種半導體裝置，其包含：源極區域及汲極區域，其分別安置於基板中；閘極絕緣層，其形成於所述基板上；閉合迴路的閘極電極，其形成在所述閘極絕緣層上且具有在所述基板上之開口區域，所述閉合迴路的閘極電極圍封形成在所述開口區域中的所述源極區域；P型井區域，其重疊該閉合迴路的閘極電極且圍封所述源極區域；以及P型深井區域，其安置於所述開口區域之下；N型井區域，其安置於所述汲極區域之下；N型深井區域，其與所述P型深井區域間隔開且與所述N型井區域重疊；其中所述P型深井區域和所述N型深井區域形成較深，使得各個深井區域的下表面接觸N型掩埋層，以及 其中該P型深井區域、該P型井區域以及該閉合迴路的閘極電極彼此重疊。
  6. 如請求項5之半導體裝置，其進一步包含：漂移區域，其安置成鄰接該P型井區域。
  7. 如請求項6之半導體裝置，其進一步包含：第一絕緣隔離區域，其安置在所述漂移區域上以部分地重疊該閉合迴路的閘極電極；第二絕緣隔離區域，其圍封安置在所述P型井區域中的塊狀分接頭區域；以及深溝渠隔離區域，其與所述汲極區域相鄰，其中該深溝渠隔離區域之深度比該第一絕緣隔離區域之深度更深。
  8. 如請求項7之半導體裝置，其中該第二絕緣隔離區域經配置以部分地圍封該源極區域。
  9. 如請求項7之半導體裝置，其進一步包含：掩埋氧化物膜，其安置在所述N型掩埋層的下表面上，其中該深溝渠隔離區域經安置以與該掩埋氧化物膜的上表面接觸。
  10. 如請求項5之半導體裝置，其中所述閉合迴路的閘極電極包括：第一拐角和第二拐角；第一直線段，其在所述第一拐角和所述第二拐角之間；第三拐角和第四拐角，所述閉合迴路的閘極電極之每個拐角具有第一曲率半徑；第二直線段，其在所述第三拐角和所述第四拐角之間，所述第一直線段和所述第二直線段彼此平行；以及垂直軸，其同時穿過所述第一直線段和所述第二直線段並且不與所述開口 區域重疊，並且其中該半導體裝置之通道長度是繞著所述垂直軸能延伸至所需長度。
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