TWI806591B - Active device substrate - Google Patents

Abstract

An active device substrate includes a substrate, a switch device and a resistive random-access memory. The switch device includes a first metal oxide layer, a second metal oxide layer, a first gate, a source and a drain. The second metal oxide layer is in contact with the first metal oxide layer. The first gate is overlapping with the first metal oxide layer and the second metal oxide layer. The resistive random-access memory includes a first electrode, a third metal oxide layer, a fourth metal oxide layer, and a second electrode. The third metal oxide layer is electrically connected to the first electrode. The fourth metal oxide layer is in contact with the third metal oxide layer. The second electrode is electrically connected to the switch device and the fourth metal oxide layer.

Description

Active component substrate

The invention relates to an active component substrate.

Since thin film transistors containing metal oxide semiconductors are easily affected by oxygen, hydrogen and water in the environment, they are prone to performance degradation after long-term use, which affects the electrical properties of thin film transistors. For example, in a display device including a thin film transistor array, if the performance of a part of the metal oxide semiconductor of the thin film transistor is degraded, it is easy to cause the problem of non-uniformity (Mura) in the picture displayed by the display device. Generally speaking, in order to reduce this uneven problem, the pixel circuit is connected to an external chip, and a large amount of current information is stored through an external compensation memory. The aforementioned current information is calculated by an algorithm to obtain a compensation current or voltage, and then the compensation current or voltage is fed back to the pixel circuit. However, the circuit design of the external chip is complicated and costly.

The invention provides an active component substrate, the variable resistance memory of which has excellent resistance switching performance.

The invention provides an active element substrate, which can save the area required for setting the variable resistance memory.

At least one embodiment of the present invention provides an active device substrate. The active element substrate includes a substrate, a switch element, and a variable resistance memory. The switch element is disposed on the substrate and includes a first metal oxide layer, a second metal oxide layer, a first gate, a source and a drain. The second metal oxide layer contacts the first metal oxide layer. The first gate overlaps the first metal oxide layer and the second metal oxide layer in a direction normal to the top surface of the substrate. The source and the drain are electrically connected to the second metal oxide layer. The variable resistance memory is disposed on the substrate and includes a first electrode, a third metal oxide layer, a fourth metal oxide layer and a second electrode. The third metal oxide layer is electrically connected to the first electrode. The fourth metal oxide layer contacts the third metal oxide layer. The second electrode is electrically connected to the switching element and the fourth metal oxide layer, and the first electrode, the third metal oxide layer, the fourth metal oxide layer and the second electrode overlap each other in the normal direction of the top surface of the substrate .

At least one embodiment of the present invention provides an active device substrate. The active device substrate includes a substrate, a first metal oxide layer, a first gate, an interlayer dielectric layer, a second metal oxide layer, a first electrode and a second electrode. The first metal oxide layer has a source region, a drain region, and a channel region between the source region and the drain region. The first gate overlaps the channel region of the first metal oxide layer in a direction normal to the top surface of the substrate. The interlayer dielectric layer is located on the first gate. The first opening and the second opening are located in the interlayer dielectric layer, and the first opening and the second opening respectively overlap the source region and the drain region in a direction normal to the top surface of the substrate. The second metal oxide layer is located at the an opening and contacts the source region of the first metal oxide layer. The first electrode is located on the second metal oxide layer, and the first electrode, the second metal oxide layer, and the source region of the first metal oxide layer overlap with each other in a direction normal to the top surface of the substrate. The second electrode is located in the second opening and is electrically connected to the drain region.

10A, 10B, 10C, 10D: active component substrate

100: Substrate

110: first gate dielectric layer

120: second gate dielectric layer

122: gate dielectric layer

130: interlayer dielectric layer

2DEG: two-dimensional electron gas

202,236: first gate

204,243: first electrode

212,216,216': the first metal oxide layer

212a: the first doped region

212c: the second doped region

214: the third metal oxide layer

222, 222', 226: second metal oxide layer

222a, 216a: source region

222b, 216b: passage area

222c, 216c: drain area

224: the fourth metal oxide layer

232,206: second gate

234,245: Second electrode

242: source

244: drain

a: the first node

b: the second node

c: the third node

Cst: storage capacitor

EL: light emitting element

ND: normal direction

P: doping process

PX: pixel circuit

O1: first opening

O2: second opening

R1: variable resistance memory

Rc: compensation memory

ST1, ST1': the first stack structure

ST2: Second stack structure

T1: switching element

Tsw: switching transistor

Twr: write transistor

Tdr: drive transistor

Tse: sensing transistor

t1, t2: thickness

V1, V2, V3: opening

V _S1 , V _data , V _DD , V _S2 , V _sus , V _SS : Voltage

FIG. 1 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

2A to 2G are schematic cross-sectional views of the manufacturing method of the active device substrate shown in FIG. 1 .

FIG. 3 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention.

FIG. 6 is a flowchart of a pixel compensation operation of a display device under the pixel circuit setting of FIG. 5 according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

8A to 8F are schematic cross-sectional views of the manufacturing method of the active device substrate of FIG. 7 picture.

FIG. 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

FIG. 11 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention.

FIG. 1 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

The active device substrate 10A includes a substrate 100 , a switch element T1 and a variable resistance memory R1 .

The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials.

The switch element T1 and the variable resistance memory R1 are disposed on the substrate 100 . In some embodiments, one or more buffer layers (not shown) are disposed between the switch element T1 and the substrate 100 and between the variable resistance memory R1 and the substrate 100 , but the invention is not limited thereto. The switching element T1 includes a first gate 202 , a first stack structure ST1 , a second gate 232 , a source 242 and a drain 244 . The variable resistance memory R1 includes a first electrode 204 , a second stack structure ST2 and a second electrode 234 .

The first gate 202 and the first electrode 204 are disposed on the substrate 100 . In one embodiment, the first gate 202 and the first electrode 204 may be inactive metals that are not easily oxidized and have a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum /molybdenum or combinations thereof. In some embodiments, the first gate 202 and the first electrode 204 include the same or different materials. In some embodiments, the first gate 202 and the first electrode 204 include the same or different thicknesses. In some embodiments, the first gate 202 and the first electrode 204 belong to the same patterned layer, and the first gate 202 and the first electrode 204 are separated from each other.

The first gate dielectric layer 110 is located on the first gate 202 and the first electrode 204 . The first gate dielectric layer 110 covers the first gate 202 and the first electrode 204 , and the first gate dielectric layer 110 has a first opening overlapping the first electrode 204 . The material of the first gate dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other suitable materials.

The first stack structure ST1 and the second stack structure ST2 are located in the first gate on the electrical layer 110. The first stack structure ST1 includes a first metal oxide layer 212 and a second metal oxide layer 222 overlapping each other, wherein the second metal oxide layer 222 contacts the upper surface of the first metal oxide layer 212 . The second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 overlapping each other, wherein the fourth metal oxide layer 224 contacts the upper surface of the third metal oxide layer 214 .

The first metal oxide layer 212 overlaps the first gate electrode 202 in the normal direction ND of the top surface of the substrate 100, and the third metal oxide layer 214 overlaps the first gate electrode 214 in the normal direction ND of the top surface of the substrate 100. An electrode 204 . The third metal oxide layer 214 fills the first opening in the first gate dielectric layer 110 and is electrically connected to the first electrode 204 . In some embodiments, there is a Schottky contact between the third metal oxide layer 214 and the first electrode 204 . In some embodiments, the first metal oxide layer 212 and the third metal oxide layer 214 belong to the same patterned layer.

The second metal oxide layer 222 and the fourth metal oxide layer 224 respectively overlap and contact the first metal oxide layer 212 and the third metal oxide layer 214 in the normal direction ND of the top surface of the substrate 100 . The second metal oxide layer 222 includes a source region 222a, a drain region 222c, and a channel region 222b between the source region 222a and the drain region 222c, wherein the channel region 222b overlaps the first gate in the normal direction ND Pole 202. In some embodiments, the source region 222a and the drain region 222c are doped to have lower resistivity than the channel region 222b. In some embodiments, the fourth metal oxide layer 224 has substantially the same resistivity as the channel region 222 b of the second metal oxide layer 222 . In some embodiments, the second metal oxide layer 222 and the fourth metal oxide layer 224 belong to the same patterned layer.

The carrier concentration of the first metal oxide layer 212 is greater than the carrier concentration of the channel region 222 b of the second metal oxide layer 222 . The oxygen concentration of the first metal oxide layer 212 is smaller than the oxygen concentration of the channel region 222 b of the second metal oxide layer 222 . In some embodiments, the oxygen concentration of the first metal oxide layer 212 is 10 at % to 50 at %, and the oxygen concentration of the channel region 222 b of the second metal oxide layer 222 is 30 at % to 70 at %. In some embodiments, by adjusting the oxygen concentration, the energy gap (Band Gap) of the first metal oxide layer 212 is smaller than the energy gap of the second metal oxide layer 222, whereby the first metal oxide layer 212 and the The interface between the second metal oxide layers 222 forms a two-dimensional electron gas 2DEG. The thickness t2 of the second metal oxide layer 222 is smaller than or equal to the thickness t1 of the first metal oxide layer 212 , so that the two-dimensional electron gas 2DEG can be formed at the aforementioned interface more easily. In some embodiments, the thickness t1 of the first metal oxide layer 212 is 10 nm to 50 nm, and the thickness t2 of the second metal oxide layer 222 is 5 nm to 50 nm. In some embodiments, the materials of the first metal oxide layer 212 and the second metal oxide layer 222 include quaternary elements such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, etc. compound or a ternary compound containing two metal elements and oxygen in the aforementioned quaternary compounds.

The carrier concentration of the third metal oxide layer 214 is greater than the carrier concentration of the fourth metal oxide layer 224 . The oxygen concentration of the third metal oxide layer 214 is smaller than the oxygen concentration of the fourth metal oxide layer 224 . In some embodiments, the oxygen concentration of the third metal oxide layer 214 is 10 at % to 50 at %, and the oxygen concentration of the fourth metal oxide layer 224 is 30 at % to 70 at %. In some embodiments, applying a voltage to the second stack ST2 can cause the second stack ST2 to switch between states of different resistivities. In other words, the second stack structure ST2 has a plurality of states with different resistivities. Since the carrier concentration of the third metal oxide layer 214 is different from that of the fourth metal oxide layer 224, the resistivity of the different states of the second stack structure ST2 changes gradually, in other words, the variable resistance memory The volume R1 can store single-level units, multi-level units, three-level units, four-level units and even analog information. The thickness t2 of the fourth metal oxide layer 224 is less than or equal to the thickness t1 of the third metal oxide layer 214 . In some embodiments, the thickness t1 of the third metal oxide layer 214 is 10 nm to 50 nm, and the thickness t2 of the fourth metal oxide layer 224 is 5 nm to 50 nm. In some embodiments, the materials of the third metal oxide layer 214 and the fourth metal oxide layer 224 include quaternary elements such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, etc. compound or a ternary compound containing two metal elements and oxygen in the aforementioned quaternary compounds. In some embodiments, the third metal oxide layer 214 and the fourth metal oxide layer 224 include amorphous.

The second gate dielectric layer 120 is disposed on the first stack structure ST1 and the second stack structure ST2, and covers the first stack structure ST1 and the second stack structure ST2, and the second gate dielectric layer 120 has a layer overlapping the second stack structure ST2. The second opening of the stack structure ST2. The material of the second gate dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other suitable materials.

The second gate 232 and the second electrode 234 are disposed on the second gate dielectric layer 120 . The second gate 232 overlaps the channel region 222 b of the second metal oxide layer 222 in the normal direction ND of the top surface of the substrate 100 . In this embodiment, the switching element T1 is a double-gate thin film transistor, and the first metal oxide layer 212 and the second gold The metal oxide layer 222 is located between the first gate 202 and the second gate 232 . The first gate 202 is electrically connected to the second gate 232 in a region not shown in the figure. For example, the second gate 232 fills an opening (not shown) penetrating through the second gate dielectric layer 120 and the first gate dielectric layer 110 to be connected to the first gate 202 . The second electrode 234 overlaps the fourth metal oxide layer 224 in the normal direction ND of the top surface of the substrate 100 . The second electrode 234 fills the second opening of the second gate dielectric layer 120 and is electrically connected to the fourth metal oxide layer 224, wherein the first electrode 204, the third metal oxide layer 214, the fourth metal oxide layer 224 and the second electrode 234 overlap each other in the normal direction ND of the top surface of the substrate 100 . In some embodiments, there is a Schottky contact between the second electrode 234 and the fourth metal oxide layer 224 . The second stack structure ST2 is located between the first electrode 204 and the second electrode 234 and is connected to the first electrode 204 and the second electrode 234 .

In one embodiment, the second gate 232 and the second electrode 234 can be inactive metals that are not easily oxidized and have a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum, or combination. In some embodiments, the second gate 232 and the second electrode 234 include the same or different materials. In some embodiments, the second gate 232 and the second electrode 234 include the same or different thicknesses. In some embodiments, the second gate 232 and the second electrode 234 belong to the same patterned layer, and the second gate 232 and the second electrode 234 are separated from each other.

The interlayer dielectric layer 130 is disposed on the second gate 232 and the second electrode 234 and covers the second gate 232 and the second electrode 234 . The material of the interlayer dielectric layer 130 is, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

The source electrode 242 and the drain electrode 244 are located on the interlayer dielectric layer 130 , and respectively fill in openings penetrating the interlayer dielectric layer 130 and the second gate dielectric layer 120 to be electrically connected to the first stack structure ST1 . In some embodiments, the source 242 and the drain 244 are electrically connected to the source region 222 a and the drain region 222 c of the second metal oxide layer 222 , respectively. In addition, the source 242 of the switching element T1 also fills the opening penetrating through the interlayer dielectric layer 130 and is electrically connected to the second electrode 234 .

Based on the above, the switching element T1 of the active element substrate 10A has a two-dimensional electron gas 2DEG, so the output current of the switching element T1 can be increased. In addition, the variable resistance memory R1 includes the third metal oxide layer 214 and the fourth metal oxide layer 224 with different carrier concentrations, so the variable resistance memory R1 can store analog information.

2A to 2H are schematic cross-sectional views of the manufacturing method of the active device substrate shown in FIG. 1 .

Referring to FIG. 2A , a first gate 202 and a first electrode 204 are formed on the substrate 100 . In some embodiments, the method for forming the first gate 202 and the first electrode 204 includes the following steps: firstly, forming a blanket conductive material layer (not shown) on the substrate 100; A patterned photoresist (not shown) is formed on the conductive material layer; then, the conductive material layer is subjected to a wet or dry etching process using the patterned photoresist as a mask to form the first gate 202 and the first electrode 204; after that, remove the patterned photoresist. In other words, for example, the first gate 202 and the first electrode 204 are formed simultaneously.

Please refer to FIG. 2B , forming a first gate dielectric layer 110 on the first gate 202 and and above the first electrode 204 . The first gate dielectric layer 110 has a first opening O1 exposing the first electrode 204 .

Referring to FIG. 2C , a first stack structure ST1' and a second stack structure ST2 are formed on the first gate dielectric layer 110. Referring to FIG. The first stack structure ST1' includes a first metal oxide layer 212 and a second metal oxide layer 222' overlapping each other, and the second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer overlapping each other. Layer 224.

The method for forming the first stack structure ST1' and the second stack structure ST2 includes: firstly, forming a blanket of two semiconductor material layers (not shown) on the first gate dielectric layer 110; then, using a lithography process, Forming a patterned photoresist (not shown) on the upper semiconductor material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the two semiconductor material layers to form a first stack structure ST1' and the second stack structure ST2; after that, remove the patterned photoresist. In other words, the first metal oxide layer 212 and the third metal oxide layer 214 are, for example, formed simultaneously, and the second metal oxide layer 222' and the fourth metal oxide layer 224 are, for example, formed simultaneously.

In this embodiment, the first stacked structure ST1' and the second stacked structure ST2 are formed through a lithographic etching process, wherein the sidewalls of the first metal oxide layer 212 are aligned with the sidewalls of the second metal oxide layer 222', and Sidewalls of the third metal oxide layer 214 are aligned with sidewalls of the fourth metal oxide layer 224 . In other embodiments, the first stack structure ST1' and the second stack structure ST2 are formed through two photolithographic etching processes, wherein the first metal oxide layer 212 and the third metal oxide layer 214 Formed through the same lithographic etching process, and the second metal oxide layer 222' and the fourth metal oxide layer 224 are formed through another lithographic etching process. In other words, the sidewalls of the first metal oxide layer 212 may not be aligned with the sidewalls of the second metal oxide layer 222', and the sidewalls of the third metal oxide layer 214 may not be aligned with the sidewalls of the fourth metal oxide layer 224.

2D, a second gate dielectric layer 120 is formed on the first stack structure ST1' and the second stack structure ST2, the second gate dielectric layer 120 has a second opening exposing the fourth metal oxide layer 224 O2.

Referring to FIG. 2E , a second gate 232 and a second electrode 234 are formed on the second gate dielectric layer 120 . The second electrode 234 is filled into the second opening O2 of the second gate dielectric layer 120 to contact the fourth metal oxide layer 224 .

Next, using the second gate 232 and the second electrode 234 as a mask, the doping process P is performed on the second metal oxide layer 222 ′ to form a first region including the source region 222 a , the channel region 222 b and the drain region 222 c. Two metal oxide layers 222 . In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process. In this embodiment, since the fourth metal oxide layer 224 is covered by the second electrode 234 , the doping process P does not dope the fourth metal oxide layer 224 .

Referring to FIG. 2F , an interlayer dielectric layer 130 is formed on the second gate dielectric layer 120 , the second gate electrode 232 and the second electrode 234 . In some embodiments, the interlayer dielectric layer 130 is an insulating layer that does not contain hydrogen, thereby preventing the hydrogen atoms in the interlayer dielectric layer 130 from diffusing into the first stack structure ST1 and the second stack structure ST2, but the present invention does not rely on This is the limit. In some embodiments, the interlayer dielectric layer 130 contains hydrogen atoms, so Therefore, hydrogen atoms can be diffused into the first stacked structure ST1 through heat treatment, so as to adjust the resistivity of the first stacked structure ST1. In some embodiments, when hydrogen atoms in the interlayer dielectric layer 130 are used for doping the first stacked structure ST1, the doping process P of FIG. 2F may be omitted.

Please refer to FIG. 2G , forming openings V1, V2, V3, the method includes the following steps: first, using a lithography process, forming a patterned photoresist (not shown) on the interlayer dielectric layer 130; The resist is used as a mask to carry out a wet or dry etching process to form openings V1, V2 in the interlayer dielectric layer 130 and the second gate dielectric layer 120, and simultaneously form an opening V3 in the interlayer dielectric layer 130; after that, Remove the patterned photoresist. The openings V1 and V2 respectively expose the drain region 222 c and the source region 222 a of the second metal oxide layer 222 , and the opening V3 exposes the second electrode 234 .

Finally, please return to FIG. 1 , forming the drain 244 and the source 242 on the interlayer dielectric layer 130 . The drain 244 and the source 242 respectively fill the openings V1 and V2 to electrically connect the drain region 222c and the source region 222a. In addition, the source electrode 242 is also filled into the opening V3 to be electrically connected to the second electrode 234 . In some embodiments, the method for forming the drain electrode 244 and the source electrode 242 includes the following steps: first, forming a blanket conductive material layer (not shown) on the interlayer dielectric layer 130; Forming a patterned photoresist (not shown) on the conductive material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the conductive material layer to form the drain electrode 244 and the source electrode 242; Afterwards, the patterned photoresist is removed. In other words, the drain 244 and the source 242 are formed simultaneously, for example.

After the above-mentioned manufacturing process, the manufacturing of the active element substrate 10A can be substantially completed. do.

FIG. 3 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 3 uses the component numbers and parts of the content in the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the active device substrate 10B of FIG. 3 and the active device substrate 10A of FIG. 1 is that the drain 244 and the source 242 of the active device substrate 10B extend through the second metal oxide layer 222 .

Referring to FIG. 3 , the drain 244 and the source 242 extend through the second metal oxide layer 222 and contact the interface of the first metal oxide layer 212 and the second metal oxide layer 222 . In other words, the drain 244 and the source 242 directly contact the two-dimensional electron gas 2DEG, thereby increasing the output current of the switching element T1.

FIG. 4 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 4 follows the component numbers and part of the content of the embodiment in FIG. 1 , where the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the active device substrate 10C of FIG. 4 and the active device substrate 10A of FIG. 1 is that the first metal oxide layer 212 of the active device substrate 10C includes a first doped region 212 a and a second doped region 212 c.

In the present embodiment, a doping process is performed to form the second metal oxide layer 222 A source region 222 a and a drain region 222 c are formed in the first metal oxide layer 212 , and a first doped region 212 a and a second doped region 212 c are formed in the first metal oxide layer 212 by a doping process. In other words, the dopants (such as hydrogen atoms) in the doping process pass through the second metal oxide layer 222 and reach the first metal oxide layer 212, and form the first dopant in the first metal oxide layer 212. region 212a and the second doped region 212c. The first doped region 212a and the second doped region 212c are in contact with bottoms of the drain region 222c and the source region 222a respectively.

In some embodiments, the thickness of the first doped region 212 a and the thickness of the second doped region 212 c are smaller than the thickness of the first metal oxide layer 212 .

In some embodiments, the widths of the source region 222 a , the drain region 222 c , the first doped region 212 a and the second doped region 212 c gradually shrink as they approach the substrate 100 . The surfaces of the source region 222a and the drain region 222c facing the channel region 222b are arc surfaces.

FIG. 5 is a schematic diagram of an equivalent circuit of a pixel circuit PX according to an embodiment of the present invention. The pixel circuit PX in FIG. 5 is, for example, the pixel circuit PX on the active device substrates 10A˜10C in any of the aforementioned embodiments.

Please refer to FIG. 5, the pixel circuit PX may include a switching transistor Tsw, a compensation memory Rc, a writing transistor Twr, a storage capacitor Cst, a driving transistor Tdr, a sensing transistor Tse and a light emitting element EL, wherein the switching transistor Tsw is, for example, the switch element T1 in any one of the embodiments in FIGS. 1 to 4 , and the compensation memory Rc is, for example, the variable resistance memory R1 in any one of the embodiments in FIGS. 1 to 4 .

The gate of the switching transistor Tsw (for example, the first gate 202 and the second gate 232 in _FIGS . The electrode (such as the drain 244 in FIGS. 1 to 4 ) is electrically connected to the voltage V _data (such as the data line voltage), and the source of the switching transistor Tsw (such as the source 242 in FIGS. 1 to 4 Electrically connected to one end of the compensation memory Rc (such as the second electrode 234 in FIGS. 1 to 4 ), the other end of the compensation memory Rc (such as the first electrode 204 in FIGS. 1 to 4 ) can be electrically connected to At the first node a, the voltage V _S1 is used to control the switching of the switching transistor Tsw, and the compensation memory Rc is used to compensate the voltage offset generated by the driving transistor Tdr under long-time operation.

The gate of the writing transistor Twr is electrically connected to the voltage V _R , the drain of the writing transistor Twr is electrically connected to the first node a, and the source of the writing transistor Twr is connected to the voltage V _com . The writing transistor Twr can be used for writing pixel compensation information, and the voltage _VR is used to control the switching of the writing transistor Twr.

One end of the storage capacitor Cst is electrically connected to the second node b, and the other end of the storage capacitor Cst is electrically connected to the third node c. The first node a is electrically connected to the second node b.

The gate of the driving transistor Tdr is electrically connected to the second node b, the drain of the driving transistor Tdr is electrically connected to the voltage V _DD , and the source of the driving transistor Tdr is electrically connected to the third node c. Since the gate of the driving transistor Tdr is electrically connected to the storage capacitor Cst, even if the switching transistor Tsw is turned off, the driving transistor Tdr can still be turned on for a short period of time.

The gate of the sensing transistor Tse is electrically connected to the voltage V _S2 , the drain of the sensing transistor Tse is electrically connected to the third node c, and the source of the sensing transistor Tse is electrically connected to the voltage V _sus . The voltage V _S2 is used to control the switch of the sensing transistor Tse, so as to transmit the driving current information to an external chip (not shown) through the sensing transistor Tse.

One end of the light emitting element EL is electrically connected to the third node c, and the other end of the light emitting element EL is electrically connected to the voltage V _SS . The brightness of the light emitting element EL will vary due to the magnitude of the driving current passing through the driving transistor Tdr. The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting elements.

FIG. 6 is a flowchart of a pixel compensation operation of a display device under the pixel circuit setting of FIG. 5 according to an embodiment of the present invention.

The following briefly describes the operation mode of the pixel compensation of the display device under the setting of the pixel circuit PX, please refer to FIG. 5 and FIG. 6 at the same time. First, the display device is turned off, so that the pixel circuit PX performs gray level sensing in the background. The way of grayscale sensing is, for example, to turn on the driving transistor Tdr and the sensing transistor Tse, so that the driving current passing through the driving transistor Tdr can be transmitted to the external chip through the sensing transistor Tse. In some embodiments, during the grayscale sensing process, the write transistor Twr is turned off.

Then, the external chip establishes a corresponding model through signal processing and calculation, and then calculates the corresponding compensation information. Afterwards, the compensation information is written into the pixel circuit PX. For example, the write transistor Twr and the switch transistor Tsw are turned on to write the compensation information calculated by the external chip into the compensation memory Rc in the pixel circuit PX by controlling the switch transistor Tsw and the write transistor Twr. Specifically, the resistance of the compensation memory Rc will change due to the voltage difference between the first electrode and the second electrode. When the voltage difference between the first electrode and the second electrode is large, more carrier channels will be generated in the first metal oxide layer and the second metal oxide layer between the first electrode and the second electrode, Make the compensation memory Rc in a low resistance state. compensation memory When the voltage difference between the first electrode and the second electrode of Rc is small, fewer carrier channels will be generated in the first metal oxide layer and the second metal oxide layer between the first electrode and the second electrode, Make the compensation memory Rc in a high resistance state. In some embodiments, the compensation memory Rc includes a stack of the first metal oxide layer and the second metal oxide layer with different carrier concentrations, so the compensation memory Rc may include a gradually changing resistance state. The resistance of the compensation memory Rc is changed by adjusting the voltage difference between the first electrode and the second electrode of the compensation memory Rc. In some embodiments, when the compensation information is written into the pixel circuit PX, the sensing transistor Tse is turned off.

Next, turn on the display device. Since the compensation data has been written into the compensation memory Rc, the current reaching the gate of the driving transistor Tdr can be changed through the compensation memory Rc, thereby adjusting the magnitude of the driving current passing through the driving transistor Tdr to achieve pixel compensation Function. In some embodiments, when the display device is turned on, the writing transistor Twr and the sensing transistor Tse are turned off. The present invention disposes the compensation memory Rc in the pixel circuit PX, so it does not need to arrange the compensation memory in the external chip, so that the overall system is simplified and the cost is reduced.

FIG. 7 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention.

The active device substrate 10D includes a substrate 100 , a first metal oxide layer 216 , a first gate 236 , an interlayer dielectric layer 130 , a second metal oxide layer 226 , a first electrode 243 and a second electrode 245 .

The first metal oxide layer 216 is located on the substrate 100 . In this embodiment, a buffer layer 102 is further included between the first metal oxide layer 216 and the substrate 100 . slow The material of the punching layer 102 is, for example, silicon oxide, silicon nitride, silicon oxynitride or a combination of the above materials.

The first metal oxide layer 216 includes a source region 216a, a drain region 216c, and a channel region 216b between the source region 216a and the drain region 216c. In some embodiments, the source region 216a and the drain region 216c are doped to have a lower resistivity than the channel region 216b.

In some embodiments, the thickness t1 of the first metal oxide layer 216 is 10 nm to 50 nm. In some embodiments, the material of the first metal oxide layer 216 includes quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide or the like A ternary compound of two of the metal elements and oxygen. The gate dielectric layer 122 is disposed thereon, and the gate dielectric layer 122 covers the first metal oxide layer 216 .

The first gate 236 is disposed on the gate dielectric layer 122 . The first gate 236 overlaps the channel region 216 b of the first metal oxide layer 216 in the normal direction ND of the top surface of the substrate 100 .

In one embodiment, the first gate 236 may be an inactive metal that is not easily oxidized and has a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum or combinations thereof. The interlayer dielectric layer 130 is disposed on the first gate 236 and covers the first gate 236 .

The interlayer dielectric layer 130 is located on the first gate 236 and covers the first gate 236 . The material of the interlayer dielectric layer 130 is, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. The opening V1 and the opening V2 are located between the interlayer dielectric layer 130 and and the gate dielectric layer 122 , and the opening V1 and the opening V2 overlap the drain region 216 c and the source region 216 a of the first metal oxide layer 216 in the normal direction ND of the top surface of the substrate 100 .

The second metal oxide layer 226 is located on the interlayer dielectric layer 130 and located in the opening V2. The second metal oxide layer 226 contacts the source region 216 a of the first metal oxide layer 216 .

In some embodiments, the thickness t2 of the second metal oxide layer 226 is 5 nm to 50 nm. In some embodiments, the material of the second metal oxide layer 226 includes quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, etc. A ternary compound of two of the metal elements and oxygen. In some embodiments, the second metal oxide layer 226 includes amorphous.

In some embodiments, the carrier concentration of the channel region 216 b of the first metal oxide layer 216 is greater than that of the second metal oxide layer 226 . The oxygen concentration of the channel region 216 b of the first metal oxide layer 216 is smaller than the oxygen concentration of the second metal oxide layer 226 . In some embodiments, the oxygen concentration of the first metal oxide layer 212 is 10 at % to 50 at %, and the oxygen concentration of the second metal oxide layer 222 is 30 at % to 70 at %.

The first electrode 243 is located on the interlayer dielectric layer 130 and the second metal oxide layer 226, and the source region 216a of the first electrode 243, the second metal oxide layer 226 and the first metal oxide layer 216 is on the substrate 100. overlap each other in the normal direction ND of the top surface, so that the first electrode 243, the second metal oxide layer 226 and the first metal oxide layer The source region 216a of the oxide layer 216 has the function of a variable resistance memory.

The second electrode 245 is located on the interlayer dielectric layer 130 and in the opening V1 , and is electrically connected to the drain region 216 c of the first metal oxide layer 216 .

In some embodiments, the material of the first electrode 243 and the second electrode 245 can be an inactive metal that is not easily oxidized and has a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum or its combination.

Based on the above, the first electrode 243 of the active device substrate 10D, the second metal oxide layer 226 and the source region 216a of the first metal oxide layer 216 overlap with each other, so the thin film transistor and the variable resistance memory can be integrated Together, thereby saving the area required for setting the variable resistive memory.

8A to 8F are schematic cross-sectional views of the manufacturing method of the active device substrate shown in FIG. 7 .

Referring to FIG. 8A , a first metal oxide layer 216' is formed on the substrate 100 and the buffer layer 102. Referring to FIG. In some embodiments, the method for forming the first metal oxide layer 216' includes the following steps: firstly, forming a blanket semiconductor material layer (not shown) on the buffer layer 102; forming a patterned photoresist (not shown) on the material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the semiconductor material layer to form the first metal oxide layer 216'; Afterwards, the patterned photoresist is removed.

Referring to FIG. 8B, a gate dielectric layer 122 is formed on the first metal oxide layer 216'.

Referring to FIG. 8C , a first gate 236 is formed on the gate dielectric layer 122 .

Next, using the first gate 236 as a mask, the doping process P is performed on the first metal oxide layer 216 ′ to form the first metal oxide layer including the source region 216 a , the channel region 216 b and the drain region 216 c 216. In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process.

Referring to FIG. 8D , an interlayer dielectric layer 130 is formed on the gate dielectric layer 122 and the first gate electrode 236 . In some embodiments, the interlayer dielectric layer 130 is an insulating layer without hydrogen, thereby preventing the hydrogen atoms in the interlayer dielectric layer 130 from diffusing to the first metal oxide layer 216 , but the invention is not limited thereto. In some embodiments, the interlayer dielectric layer 130 contains hydrogen atoms, so the hydrogen atoms can be diffused into the first metal oxide layer 216 by heat treatment, so as to adjust the resistivity of the first metal oxide layer 216 . In some embodiments, when hydrogen atoms in the interlayer dielectric layer 130 are used for doping the first metal oxide layer 216 , the doping process P of FIG. 8C may be omitted.

Please refer to FIG. 8E , forming the openings V1, V2, the method includes the following steps: first, using a lithography process, forming a patterned photoresist (not shown) on the interlayer dielectric layer 130; then, using the patterned photoresist as A mask is used to perform a wet or dry etching process to form openings V1 and V2 in the interlayer dielectric layer 130 and the gate dielectric layer 122; after that, the patterned photoresist is removed. The openings V1 and V2 respectively expose the drain region 216 c and the source region 216 a of the first metal oxide layer 216 .

Referring to FIG. 8F , a second metal oxide layer 226 is formed on the interlayer dielectric layer 130 and in the opening V2 . The second metal oxide layer 226 contacts the source region 216a through the opening V2. In some embodiments, the source region 216 a is in contact with the second metal oxide layer 226 , and the diffusion and transfer of oxygen occurs, so that the oxygen concentration in the source region 216 a increases.

Finally, please return to FIG. 7 to form the first electrode 243 and the second electrode 245 . on the interlayer dielectric layer 130 . The first electrode 243 covers the second metal oxide layer 226 . The second electrode 245 fills the opening V1 to be electrically connected to the drain region 222c. In some embodiments, the method for forming the first electrode 243 and the second electrode 245 includes the following steps: first, forming a blanket conductive material layer (not shown) on the interlayer dielectric layer 130 and the second metal oxide layer 226 ); then, using a lithography process to form a patterned photoresist (not shown) on the conductive material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the conductive material layer, to form the first electrode 243 and the second electrode 245; after that, remove the patterned photoresist. In other words, for example, the first electrode 243 and the second electrode 245 are formed simultaneously.

After the above process, the fabrication of the active device substrate 10D can be substantially completed.

FIG. 9 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 9 uses the component numbers and partial content of the embodiment in FIG. 7 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the active device substrate 10E in FIG. 9 and the active device substrate 10A in FIG. 7 is that the first gate 236 of the active device substrate 10E is located between the substrate 100 and the first metal oxide layer 216 .

FIG. 10 is a schematic cross-sectional view of an active device substrate according to an embodiment of the present invention. It must be noted here that the embodiment of FIG. 10 follows the embodiment of FIG. 7 The same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the active device substrate 10F shown in FIG. 10 and the active device substrate 10A shown in FIG. between poles 206 .

FIG. 11 is a schematic diagram of an equivalent circuit of a pixel circuit PX according to an embodiment of the present invention. The pixel circuit PX in FIG. 11 is, for example, the pixel circuit PX on the active device substrates 10D˜10F in any of the aforementioned embodiments.

Please refer to FIG. 11, the pixel circuit PX may include a switching transistor Tsw, a compensation memory Rc, a storage capacitor Cst, a driving transistor Tdr, a sensing transistor Tse, and a light emitting element EL, wherein the switching transistor Tsw and the compensation memory Rc The structure of FIG. 7 is a semiconductor device integrating a thin film transistor and a variable resistance memory.

The gate of the switching transistor Tsw is electrically connected to the voltage V _S1 (such as the scan line voltage), the drain of the switching transistor Tsw is electrically connected to the voltage V _data (such as the data line voltage), and the source of the switching transistor Tsw The pole is electrically connected to the first node a.

The gate of the driving transistor Tdr (for example, the first gate 236 in FIGS. 7 to 10 ) is electrically connected to the first node a. The drain of the driving transistor Tdr (for example, the second electrode 245 in FIGS. 7 to 10 ) is electrically connected to the voltage V _DD , and the source of the driving transistor Tdr is electrically connected to one end of the compensation memory Rc. For example, the source of the driving transistor Tdr and one end of the compensation memory Rc share the same conductive structure, such as the source region 216 a of the first metal oxide layer 216 in FIGS. 7 to 10 .

The gate of the sensing transistor Tse is electrically connected to the voltage V _S2 , the drain of the sensing transistor Tse is electrically connected to the third node c, and the source of the sensing transistor Tse is electrically connected to the voltage V _sus . The voltage V _S2 is used to control the switch of the sensing transistor Tse, so as to transmit the driving current information to the external chip through the sensing transistor Tse.

One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the third node c. The second node b is electrically connected to the third node c. Since the gate of the driving transistor Tdr is electrically connected to the storage capacitor Cst, even if the switching transistor Tsw is turned off, the driving transistor Tdr can still be turned on for a short period of time.

One end of the light emitting element EL is electrically connected to the second node b, and the other end of the light emitting element EL is electrically connected to the voltage V _SS . The luminance of the light emitting element EL will be changed due to the difference in magnitude of the driving current passing through the driving transistor Tdr and the compensating memory Rc. The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting elements.

In this embodiment, at the first node a, the source of the switching transistor Tsw, the gate of the driving transistor Tdr, and one end of the storage capacitor Cst are electrically connected to each other. At the second node b, the other end of the compensation memory Rc (for example, the first electrode 243 in FIGS. 7 to 10 ) and one end of the light emitting element EL are electrically connected to each other. At the third node c, the drain of the sensing transistor Tse and the other end of the storage capacitor Cst are electrically connected to each other. The drain of the sensing transistor Tse is electrically connected to the other end of the compensation memory Rc through the third node c and the second node b.

The following briefly describes the pixel compensation of the display device under the setting of the pixel circuit PX For the operation method, please refer to Figure 9 and Figure 6 at the same time. First, the display device is turned off, so that the pixel circuit PX performs gray level sensing in the background. The way of grayscale sensing is, for example, to turn on the switching transistor Tsw, the driving transistor Tdr and the sensing transistor Tse, so that the driving voltage passing through the switching transistor Tsw and the driving current passing through the driving transistor Tdr and the compensation memory Rc It can be transmitted to the external chip through the sensing transistor Tse.

Then, the external chip establishes a corresponding model through signal processing and calculation, and then calculates the corresponding compensation information. Afterwards, the compensation information is written into the pixel circuit PX. For example, the switching transistor Tsw, the driving transistor Tdr and the sensing transistor Tse are turned on to write the compensation information calculated by the external chip into the compensation memory Rc. Specifically, the resistance of the compensating memory Rc will change due to the voltage difference between the two ends (for example, the voltage difference between the first electrode 243 and the source region 216 a shown in FIGS. 7 to 10 ). When the voltage difference between the two ends of the compensation memory Rc is large, more carrier channels will be generated in the second metal oxide layer between the two ends of the compensation memory Rc, so that the compensation memory Rc is in a low resistance state . When the voltage difference between the two ends of the compensation memory Rc is small, less carrier channels will be generated in the second metal oxide layer between the two ends of the compensation memory Rc, so that the compensation memory Rc is in a high resistance state. In some embodiments, the compensation memory Rc has a plurality of states of different resistances (such as a state with a resistance of 10E2 ohm, a state with a resistance of 10E3 ohm, a state with a resistance of 10E4 ohm, and a state with a resistance of 10E5 ohm), therefore, it can be The resistance of the compensation memory Rc is changed by adjusting the voltage difference between the two ends of the compensation memory Rc. In some embodiments, when the compensation information is written into the pixel circuit PX, the sensing transistor Tse is turned off.

Next, turn on the display device. Since the compensation information has been written into the compensation memory Rc, the magnitude of the driving current through the driving transistor Tdr and the compensation memory Rc can be adjusted, thereby achieving the function of pixel compensation. In some embodiments, when the display device is turned on, the sensing transistor Tse is turned off.

To sum up, the present invention does not need to set the compensation memory in the external chip, which simplifies the overall system and reduces the cost.

PX: pixel circuit

Claims (19)

An active component substrate, comprising: a substrate; A switch element is arranged on the substrate and includes: a first metal oxide layer; a second metal oxide layer contacting the first metal oxide layer; a first gate overlapping the first metal oxide layer and the second metal oxide layer in a direction normal to the top surface of the substrate; and a source and a drain electrically connected to the second metal oxide layer; and A variable resistance memory is arranged on the substrate and includes: a first electrode; a third metal oxide layer electrically connected to the first electrode; a fourth metal oxide layer contacting the third metal oxide layer; and a second electrode electrically connected to the switching element and the fourth metal oxide layer, and the first electrode, the third metal oxide layer, the fourth metal oxide layer and the second electrode are on the substrate The normal directions of the top surfaces overlap each other. The active device substrate as claimed in item 1, wherein the switch element further includes a second gate, the first metal oxide layer and the second metal oxide layer are located on the first gate and the second gate between, and the first gate is electrically connected to the second gate. The active element substrate as claimed in item 2, wherein the materials of the first electrode, the second electrode, the first gate and the second gate include tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/ Molybdenum or combinations thereof. The active device substrate as claimed in claim 1, wherein there is a Schottky contact between the second electrode and the fourth metal oxide layer. The active device substrate as claimed in claim 1, wherein the carrier concentration of the first metal oxide layer is greater than the carrier concentration of a channel region of the second metal oxide layer. The active device substrate as claimed in claim 5, wherein a two-dimensional electron gas is located at the interface between the first metal oxide layer and the second metal oxide layer. The active device substrate as claimed in item 5, wherein the oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the channel region of the second metal oxide layer, and the thickness of the second metal oxide layer is less than or equal to The thickness of the first metal oxide layer. The active device substrate as claimed in claim 1, wherein the carrier concentration of the third metal oxide layer is greater than the carrier concentration of the fourth metal oxide layer. The active element substrate as claimed in claim 8, wherein the oxygen concentration of the third metal oxide layer is less than the oxygen concentration of the fourth metal oxide layer, and the thickness of the fourth metal oxide layer is less than or equal to that of the third metal oxide layer. The thickness of the oxide layer. The active device substrate as claimed in item 8, wherein the first metal oxide layer and the third metal oxide layer belong to the same patterned layer, and the second metal oxide layer and the fourth metal oxide layer belong to Another same patterned layer. The active component substrate as described in claim 1, further comprising: a driving element, the gate of which is electrically connected to the first electrode; and A light emitting element is electrically connected to the source of the driving element. The active device substrate as claimed in claim 1, wherein the third metal oxide layer and the fourth metal oxide layer comprise amorphous. An active component substrate, comprising: a substrate; a first metal oxide layer having a source region, a drain region and a channel region between the source region and the drain region; a first gate overlapping the channel region of the first metal oxide layer in a direction normal to the top surface of the substrate; an interlayer dielectric layer located on the first gate, wherein a first opening and a second opening are located in the interlayer dielectric layer, and the first opening and the second opening are on the top surface of the substrate respectively overlap the source region and the drain region in the direction of the normal line; a second metal oxide layer located in the first opening and contacting the source region of the first metal oxide layer; a first electrode located on the second metal oxide layer, and the first electrode, the second metal oxide layer and the source region of the first metal oxide layer are on the top surface of the substrate overlap each other in the normal direction; and A second electrode is located in the second opening and electrically connected to the drain region. The active device substrate as claimed in claim 13, wherein the materials of the first electrode and the second electrode include tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum or combinations thereof. The active device substrate as claimed in claim 13, wherein there is a Schottky contact between the first electrode and the second metal oxide layer. The active device substrate as claimed in claim 13, wherein the carrier concentration of the channel region of the first metal oxide layer is greater than the carrier concentration of the second metal oxide layer. The active device substrate as claimed in claim 16, wherein the oxygen concentration of the channel region of the first metal oxide layer is smaller than the oxygen concentration of the second metal oxide layer. The active component substrate as described in claim item 13, further comprising: a switching element electrically connected to the first gate; and A light emitting element is electrically connected to the first electrode. The active device substrate as claimed in claim 13, wherein the second metal oxide layer is amorphous.

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