TW202341448A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor is disposed above the substrate and includes a first metal-oxide-semiconductor layer and a first gate. The second transistor is disposed above the substrate and includes a second metal-oxide-semiconductor layer, a second gate and a first insulating layer. The second metal-oxide-semiconductor layer and the first metal-oxide-semiconductor layer belong to the same layer, and an oxygen concentration of the first metal-oxide-semiconductor layer is lower than an oxygen concentration of the second metal-oxide-semiconductor layer. The first insulating layer encapsulates the second metal-oxide-semiconductor layer and is not located between the first metal-oxide-semiconductor layer and the first gate. A manufacturing method of a semiconductor device is also provided.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

Generally speaking, electronic devices contain many semiconductor components. For example, display devices often include many thin film transistors, which are formed by depositing various thin films (such as semiconductors, metals, dielectric layers, etc.) on a substrate. In the display device, the thin film transistor can be disposed in the pixel structure or in the driving circuit.

As the resolution of display devices increases, the size of thin film transistors continues to shrink. In order for a small-sized thin film transistor to provide a large enough current, the semiconductor layer in the thin film transistor needs to have high carrier mobility. However, thin film transistors with high carrier mobility are usually accompanied by large leakage, resulting in poor reliability, and are therefore not suitable as switching elements in pixel structures.

The present invention provides a semiconductor device, a thin film transistor with high carrier mobility and a high reliability thin film transistor.

The present invention provides a method for manufacturing a semiconductor device, and provides a thin film transistor with high carrier mobility and a high reliability thin film transistor.

One embodiment of the present invention provides a semiconductor device, including: a substrate; a first transistor disposed on the substrate, and the first transistor includes a first metal oxide semiconductor layer and a first metal oxide semiconductor layer overlapping the first metal oxide semiconductor layer. a first gate; and a second transistor disposed on the substrate, and the second transistor includes a second metal oxide semiconductor layer, a second gate overlapping the second metal oxide semiconductor layer, and a first insulating layer , wherein the second metal oxide semiconductor layer and the first metal oxide semiconductor layer belong to the same film layer, and the oxygen concentration of the first metal oxide semiconductor layer is lower than the oxygen concentration of the second metal oxide semiconductor layer, and the first insulation The layer covers the second metal oxide semiconductor and is not located between the first metal oxide semiconductor and the first gate.

One embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first metal oxide semiconductor layer and a second metal oxide semiconductor layer on a substrate, and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer. The physical semiconductor layer belongs to the same film layer; a first insulating layer is formed to cover the second metal oxide semiconductor, and the first insulating layer does not contact the first metal oxide semiconductor; an annealing treatment is performed to make the first metal oxide semiconductor The oxygen concentration is lower than the oxygen concentration of the second metal oxide; and the first gate and the second gate are formed on the substrate, and the first gate and the second gate respectively overlap the first metal oxide semiconductor layer and the second gate. Two metal oxide semiconductor layers.

1A to 1H are schematic cross-sectional views of the steps of a method of manufacturing a semiconductor device 10 according to an embodiment of the present invention. Hereinafter, the method of manufacturing the semiconductor device 10 will be described with reference to FIGS. 1A to 1H .

Referring to FIG. 1A , first, a substrate 110 is provided. For example, the material of the substrate 110 may include glass, quartz, organic polymers, or opaque/reflective materials (such as conductive materials, metals, wafers, ceramics, or other applicable materials) or other applicable materials. s material.

Next, the buffer layer 112 is formed on the substrate 110 . The method of forming the buffer layer 112 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The buffer layer 112 may be a single layer or a multi-layer insulating layer, and the insulating layer may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitrides (SiONx) or other suitable materials or stacked layers of the above materials.

Then, the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 are formed on the substrate 110 and the buffer layer 112 . For example, the method of forming the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may include the following steps: first, forming a blanket semiconductor material layer (not shown) on the substrate 110 and the buffer layer 112 ); then, use a photolithography process to form a patterned photoresist (not shown) on the semiconductor material layer; then, use the patterned photoresist as a mask to perform a wet or dry etching process on the semiconductor material layer. To form the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122; after that, the patterned photoresist is removed. That is to say, the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 can be formed by patterning the same film layer.

The first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may include the same metal element, for example, both contain at least one of indium element, zinc element, tungsten element, tin element, and gallium element. For example, the materials of the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may include indium zinc oxide (InZnO, IZO), indium tungsten oxide (InWO, IWO), indium tungsten zinc oxide (InWZnO, IWZO), indium zinc tin oxide (InZnSnO, IZTO), indium gallium tin oxide (InGaSnO, IGTO) or indium gallium zinc tin oxide (InGaZnSnO, IGZTO), but the present invention is not limited to this.

Referring to FIG. 1B , next, a first insulating layer 130 is formed on the second metal oxide semiconductor layer 122 and the buffer layer 112 . The first insulating layer 130 may completely cover the top surface and side surfaces of the second metal oxide semiconductor layer 122 , and the first insulating layer 130 does not contact the first metal oxide semiconductor 121 . For example, the method of forming the first insulating layer 130 may include the following steps: first, using a chemical vapor deposition method or other suitable methods, forming the first metal oxide semiconductor layer 121 , the second metal oxide semiconductor layer 122 and A blanket insulating material layer (not shown) is formed on the buffer layer 112; then, a photolithography process is used to form a patterned photoresist (not shown) on the insulating material layer; and then, the patterned photoresist is used as a mask. A wet or dry etching process is performed on the insulating material layer to form the first insulating layer 130; thereafter, the patterned photoresist is removed. The first insulating layer 130 may include a material that can block the escape of oxygen or provide oxygen to the metal oxide semiconductor layer. For example, in this embodiment, the first insulating layer 130 may include an oxygen barrier layer or an oxygen-containing insulating layer, such as silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide or other suitable materials. However, the present invention does not use This is the limit.

Please refer to Figure 1C, and then perform annealing TA. The annealing treatment TA can be performed at a temperature between 200°C and 500°C (for example, 280°C, 350°C or 420°C), and the time for the annealing treatment TA can be between 30 minutes and 180 minutes. However, the present invention Not limited to this. Since the first insulating layer 130 covers the second metal oxide semiconductor layer 122, during the annealing process TA, the first insulating layer 130 can block the oxygen in the second metal oxide semiconductor layer 122 from escaping, and can even prevent the second metal oxide semiconductor layer 122 from escaping. The two metal oxide semiconductor layers 122 supply oxygen. Therefore, the first metal oxide semiconductor layer 121 is easier to deoxidize than the second metal oxide semiconductor layer 122 . In other words, the annealing process TA can deoxidize the first metal oxide semiconductor layer 121 and transform it into the first metal oxide semiconductor layer 121', while the first insulating layer 130 blocks the second metal oxide semiconductor layer during the annealing process TA. The oxygen in the layer 122 escapes or supplies oxygen to the second metal oxide semiconductor layer 122 , so that the oxygen vacancy concentration of the first metal oxide semiconductor layer 121 ′ is higher than that of the second metal oxide semiconductor layer 122 Vacancy concentration. In this way, after the annealing process TA, the oxygen concentration of the first metal oxide semiconductor layer 121' will be lower than the oxygen concentration of the second metal oxide semiconductor layer 122, so that the carriers of the first metal oxide semiconductor layer 121' The carrier mobility can be greater than the 122 carrier mobility of the second metal oxide semiconductor layer.

In some embodiments, crystalline particles can be locally formed in the first metal oxide semiconductor layer 121' after deoxidation, so that the crystallinity of the first metal oxide semiconductor layer 121' is higher than that of the second metal oxide semiconductor layer 122. Crystallinity. In some embodiments, the above-mentioned crystalline particles may have a nanometer-level particle size, for example, a particle size less than 1 nm. In other words, the crystallinity of the first metal oxide semiconductor layer 121' after undergoing the annealing treatment TA In essence, it can be between amorphous and polycrystalline.

Referring to FIG. 1D, next, a second insulating layer 140 is formed on the substrate 110, and the second insulating layer 140 covers the first metal oxide semiconductor layer 121', the first insulating layer 130 and the buffer layer 112. The second insulating layer 140 may be formed using chemical vapor deposition or other suitable methods. The material of the second insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, organic polymer, or a stack of the above materials, but the invention is not limited thereto.

Please refer to FIG. 1E. Next, a first gate 151 and a second gate 152 are respectively formed on the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. The method of forming the first gate 151 and the second gate 152 may include the following steps. First, a gate metal layer (not shown) is formed on the second insulating layer 140 . Then, a photolithography process is used to form a patterned photoresist (not shown) on the gate metal layer. Next, the patterned photoresist is used as a mask to perform a wet or dry etching process on the gate metal layer to form the first gate 151 and the second gate 152 . Afterwards, the patterned photoresist is removed. In other words, the first gate 151 and the second gate 152 belong to the same film layer, and the first gate 151 and the second gate 152 are formed at the same time.

The first gate 151 overlaps the orthographic projection of the first metal oxide semiconductor layer 121 ′ on the substrate 110 , and the second gate 152 overlaps the orthographic projection of the first insulating layer 130 on the substrate 110 . projection. The materials of the first gate 151 and the second gate 152 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium ( Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or the above metals and/or alloy laminates, but not limited to this. The first gate 151 and the second gate 152 can also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other conductive materials. properties of materials.

Referring to FIG. 1F , in some embodiments, after forming the first gate 151 and the second gate 152 , a doping process IA may also be performed. The doping process IA can use the first gate 151 and the second gate 152 as masks to perform a doping process on the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. After the doping process IA, the portion of the first metal oxide semiconductor layer 121' that overlaps the first gate 151 may form a channel portion 121c, and the portion of the first metal oxide semiconductor layer 121' that does not overlap the first gate 151 can form a channel portion 121c. The first portion 121a and the second portion 121b may have a lower resistance than the channel portion 121c. Similarly, the portion of the second metal oxide semiconductor layer 122 that overlaps the second gate 152 can form the channel portion 122c, and the first portion 122a and the second portion of the second metal oxide semiconductor layer 122 that do not overlap the second gate 152 can form a channel portion 122c. Portion 122b may have a lower resistance than channel portion 122c. The doping process IA is, for example, hydrogen plasma treatment, and the doping process IA can implant hydrogen elements into the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. In the first part 122a and the second part 122b, the carriers of the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' and the first part 122a and the second part 122b of the second metal oxide semiconductor layer 122 are Migration rates rise. In some embodiments, the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 can be respectively connected with the subsequently formed first portion. An ohmic contact is formed between the source electrode 171 , the first drain electrode 172 , the second source electrode 173 and the second drain electrode 174 .

Please refer to FIG. 1G. Next, a third insulating layer 160 is formed on the first gate 151, the second gate 152 and the second insulating layer 140. The formation method of the third insulating layer 160 may include the following steps. First, a blanket dielectric material layer (not shown) is formed on the substrate 110 using a chemical vapor deposition method or a physical vapor deposition method. Next, a photolithography process is used to form a patterned photoresist (not shown) on the dielectric material layer. Then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the dielectric material layer to form the third insulating layer 160 . Afterwards, the patterned photoresist is removed. The third insulating layer 160 has through holes V1, V2, V3, and V4, wherein the through holes V1 and V2 can penetrate the third insulating layer 160 and the second insulating layer 140 and expose the third portion of the first metal oxide semiconductor layer 121' respectively. The part 121a and the second part 121b, the through holes V3 and V4 can penetrate the third insulating layer 160, the second insulating layer 140 and the first insulating layer 130 and expose the first part 122a and the second part of the second metal oxide semiconductor layer 122 respectively. Part II 122b. The material of the third insulating layer 160 includes, for example, silicon oxide, silicon oxynitride, organic polymer, or other suitable materials, or stacked layers of the above materials.

In some embodiments, the reactant used to form the third insulating layer 160 contains hydrogen, and during the process of forming the third insulating layer 160 or in the subsequent heat treatment process, the hydrogen may migrate or diffuse to the first In the metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122, the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the second portion of the second metal oxide semiconductor layer 122 are thereby adjusted. The hydrogen content in one part 122a and the second part 122b further improves their electrical conductivity.

Please refer to FIG. 1H. Next, the first source electrode 171, the first drain electrode 172, the second source electrode 173 and the second drain electrode 174 are formed on the third insulating layer 160, and the first source electrode 171 and the first drain electrode are 172 is electrically connected to the first metal oxide semiconductor layer 121', and the second source electrode 173 and the second drain electrode 174 are electrically connected to the second metal oxide semiconductor layer 122, thereby forming the first transistor T1 and the second transistor T1. The transistor T2, the first transistor T1 and the second transistor T2 are all top gate thin film transistors.

For example, a method of forming the first source 171 , the first drain 172 , the second source 173 and the second drain 174 may include the following steps. First, a conductive layer (not shown) is formed on the substrate 110 using a chemical vapor deposition method or a physical vapor deposition method. Next, a photolithography process is used to form a patterned photoresist (not shown) on the conductive layer. Then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the conductive layer to form the first source 171 , the first drain 172 , the second source 173 and the second drain 174 . Afterwards, the patterned photoresist is removed. In other words, the first source electrode 171 , the first drain electrode 172 , the second source electrode 173 and the second drain electrode 174 may belong to the same film layer. The materials of the first source electrode 171 , the first drain electrode 172 , the second source electrode 173 and the second drain electrode 174 may include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, and tantalum. , aluminum, zinc, alloys of the aforementioned metals, or stacked layers of the aforementioned metals and/or alloys, or other conductive materials.

In this embodiment, the first source electrode 171 can be electrically connected to the first portion 121a of the first metal oxide semiconductor layer 121' through the through hole V1, and the first drain electrode 172 can be electrically connected to the first drain electrode 172 through the through hole V2. The second portion 121b of the metal oxide semiconductor layer 121' and the second source electrode 173 can be electrically connected to the first portion 122a of the second metal oxide semiconductor layer 122 through the through hole V3, and the second drain electrode 174 can pass through the through hole V4. And electrically connected to the second portion 122b of the second metal oxide semiconductor layer 122.

In some embodiments, a passivation layer 180 may also be formed on the first source electrode 171 , the first drain electrode 172 , the second source electrode 173 , the second drain electrode 174 and the third insulating layer 160 . The passivation layer 180 may be formed by plasma chemical vapor deposition or other suitable processes, and the material of the passivation layer 180 may be silicon nitride or other suitable materials.

FIG. 1H is a schematic cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention. In this embodiment, the semiconductor device 10 may include a substrate 110, a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 are both disposed on the substrate 110.

In some embodiments, the semiconductor device 10 may further include a buffer layer 112 , and the buffer layer 112 may be located between the first transistor T1 and the second transistor T2 and the substrate 110 to prevent impurities in the substrate 110 from diffusing to the first transistor. in the transistor T1 and the second transistor T2.

The first transistor T1 includes at least a first metal oxide semiconductor layer 121'. For example, the first transistor T1 may include a first metal oxide semiconductor layer 121', a first gate electrode 151, a first source electrode 171 and a first drain electrode 172, and the second insulating layer 140 may be located on the first gate electrode. Between the electrode 151 and the first metal oxide semiconductor layer 121 ′, the third insulating layer 160 may be located between the first source electrode 171 and the first drain electrode 172 and the first gate electrode 151 .

The first metal oxide semiconductor layer 121' may include a first part 121a, a second part 121b and a channel part 121c. The channel part 121c overlaps the first gate 151. The first source 171 is electrically connected to the first part 121a and the first drain. 172 is electrically connected to the second part 121b, and the channel part 121c is located between the first part 121a and the second part 121b.

The second transistor T2 at least includes a second metal oxide semiconductor layer 122 and a first insulating layer 130, wherein the second metal oxide semiconductor layer 122 and the first metal oxide semiconductor layer 121' may belong to the same film layer. The first insulating layer 130 covers the second metal oxide semiconductor layer 122 . The first insulating layer 130 does not contact the first metal oxide semiconductor layer 121', and the first insulating layer 130 is not located between the first metal oxide semiconductor layer 121' and the first gate 151. For example, the second transistor T2 may include a second metal oxide semiconductor layer 122, a first insulating layer 130, a second gate 152, a second source 173 and a second drain 174, and the second insulating layer 140 Located between the second gate electrode 152 and the first insulating layer 130 , the third insulating layer 160 is located between the second source electrode 173 and the second drain electrode 174 and the second gate electrode 152 . In this embodiment, the first insulating layer 130 is sandwiched between the first metal oxide semiconductor layer 121' and the first gate 151, and the second metal oxide semiconductor layer 122 is sandwiched between the second gate 152 and the second gate 152. The first insulation layer 130 and the second insulation layer 140 . The distance between the first metal oxide semiconductor layer 121' and the first gate electrode 151 is smaller than the distance between the second metal oxide semiconductor layer 122 and the second gate electrode 152.

The second metal oxide semiconductor layer 122 may include a first part 122a, a second part 122b and a channel part 122c. The channel part 122c overlaps the second gate 152, and the second source 173 is electrically connected to the first part 122a and the second drain 174. The second part 122b is electrically connected, and the channel part 122c is located between the first part 122a and the second part 122b.

In some embodiments, the thickness of the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 may be 100Å to 500Å, such as 200Å, 300Å or 400Å, but the invention is not limited thereto. In some embodiments, the thickness of the first insulating layer 130 may be between 100Å and 1000Å, such as 300Å, 500Å or 700Å, but the invention is not limited thereto. In some embodiments, the thickness of the second insulating layer 140 may be between 300Å and 2500Å, such as 1000Å, 1500Å or 2000Å, but the invention is not limited thereto.

In some embodiments, the carrier mobility of the first metal oxide semiconductor layer 121' of the first transistor T1 is greater than 50 cm ² /Vs, and the carrier mobility of the second metal oxide semiconductor layer 122 of the second transistor T2 The mobility is approximately between 10 and 30 cm ² /Vs, and the threshold voltage of the second transistor T2 is higher than the threshold voltage of the first transistor T1. It can be seen from this that in the semiconductor device 10 , by covering the second metal oxide semiconductor layer 122 with the first insulating layer 130 and performing the annealing treatment TA, the oxygen concentration of the first metal oxide semiconductor layer 121 ′ can be made lower than The oxygen concentration of the second metal oxide semiconductor layer 122 causes the carrier mobility of the first metal oxide semiconductor layer 121' to be greater than the carrier mobility of the second metal oxide semiconductor layer 122. Thereby, the leakage current of the second transistor T2 is reduced, while the first transistor T1 has the advantage of high driving current. In this way, the first transistor T1 can be suitable as a driving element, and the second transistor T2 has High reliability and suitable for use as switching components.

2A to 2F are schematic cross-sectional views of the steps of a method of manufacturing a semiconductor device 20 according to another embodiment of the present invention. It must be noted here that the embodiment of FIGS. 2A to 2F is performed after the steps of FIG. 1C, and the embodiment of FIGS. 2A to 2F follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1H. The same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Referring to FIG. 2A , after the annealing process TA of FIG. 1C , the first insulating layer 130 may be removed to expose the second metal oxide semiconductor layer 122 . The first insulating layer 130 may be removed by etching or other suitable methods. For example, the above etching process can be performed using an etchant that has a relatively high etching selectivity for the first insulating layer 130 but is not easy to etch the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122.

Referring to FIG. 2B, next, a second insulating layer 140 is formed on the substrate 110, and the second insulating layer 140 covers the first metal oxide semiconductor layer 121', the second metal oxide semiconductor layer 122 and the buffer layer 112.

Please refer to FIG. 2C. Next, the first gate 151 and the second gate 152 are respectively formed on the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122, and the first gate 151 is formed on the substrate. The orthographic projection of 110 overlaps the orthographic projection of the first metal oxide semiconductor layer 121 ′ on the substrate 110 , and the orthographic projection of the second gate 152 overlaps the orthographic projection of the first insulating layer 130 on the substrate 110 .

Referring to FIG. 2D , after forming the first gate 151 and the second gate 152 , a doping process IA can be performed. The doping process IA can use the first gate 151 and the second gate 152 as masks to cover the first portion 121 a and the second portion 121 b of the first metal oxide semiconductor layer 121 ′ that do not overlap the first gate 151 and The first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 that do not overlap the second gate 152 are implanted with hydrogen elements, so that the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and The carrier mobility of the first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 increases. After the doping process IA, the portion of the first metal oxide semiconductor layer 121' overlapping the first gate 151 can form the channel portion 121c, and the portion of the second metal oxide semiconductor layer 122 overlapping the second gate 152 can form Channel portion 122c.

Please refer to FIG. 2E. Next, a third insulating layer 160 having through holes V1, V2, V3, and V4 is formed on the first gate 151, the second gate 152, and the second insulating layer 140, wherein the through holes V1, V2 can penetrate the third insulating layer 160 and the second insulating layer 140 and expose the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' respectively. The through holes V3 and V4 can penetrate the third insulating layer 160 and the second insulating layer 140, respectively. The second insulating layer 140 exposes the first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 respectively. During the formation of the third insulating layer 160 or in the subsequent heat treatment process, the hydrogen element may migrate or diffuse to the first portion 121 a and the second portion 121 b of the first metal oxide semiconductor layer 121 ′ and the second metal oxide semiconductor layer 121 ′. In the first part 122a and the second part 122b of the layer 122, the hydrogen content is adjusted to thereby improve the conductivity.

Please refer to FIG. 2F. Next, the first source electrode 171, the first drain electrode 172, the second source electrode 173 and the second drain electrode 174 are formed on the third insulating layer 160, and the first source electrode 171 and the first drain electrode are 172 is electrically connected to the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' through the through holes V1 and V2 respectively, and the second source electrode 173 and the second drain electrode 174 pass through the through holes V3 and V4 respectively. The first portion 122a and the second portion 122b of the second metal oxide semiconductor layer 122 are electrically connected to form the first transistor T1 and the second transistor T2A. In some embodiments, a passivation layer 180 may also be formed on the first transistor T1 and the second transistor T2A.

FIG. 2F is a schematic cross-sectional view of a semiconductor device 20 according to another embodiment of the present invention. In this embodiment, the semiconductor device 20 may include: a substrate 110, a buffer layer 112, a first transistor T1, a second transistor T2A, and a passivation layer 180, and the first transistor T1 and the second transistor T2A may be disposed on between the buffer layer 112 and the passivation layer 180 .

The main difference between the semiconductor device 20 shown in FIG. 2F and the semiconductor device 10 shown in FIG. 1H is that the semiconductor device 20 does not include a first insulating layer, and the second transistor T2A may include a second metal oxide semiconductor layer 122, a third Two gates 152 , a second source 173 and a second drain 174 . The second insulating layer 140 is located between the first gate electrode 151 and the first metal oxide semiconductor layer 121' and between the second gate electrode 152 and the second metal oxide semiconductor layer 122. In this embodiment, the distance between the first gate 151 and the first metal oxide semiconductor layer 121' is substantially equal to the distance between the second gate 152 and the second metal oxide semiconductor layer 122.

In this embodiment, the oxygen vacancy concentration of the first metal oxide semiconductor layer 121' is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer 122. In other words, the oxygen concentration of the first metal oxide semiconductor layer 121' Lower than the oxygen concentration of the second metal oxide semiconductor layer 122, and the crystallinity of the first metal oxide semiconductor layer 121' is higher than the crystallinity of the second metal oxide semiconductor layer 122, so that the first metal oxide semiconductor layer The carrier mobility of 121' is greater than the carrier mobility of the second metal oxide semiconductor layer 122. In this way, the first transistor T1 has the advantage of large driving current and can be suitable as a driving element; while the second transistor T2A has the advantage of low leakage current and can be suitable as a switching element.

3A to 3C are schematic cross-sectional views of the steps of a method of manufacturing a semiconductor device 30 according to another embodiment of the present invention. It must be noted here that the embodiment of FIGS. 3A to 3C is performed after the steps of FIG. 1F, and the embodiment of FIGS. 3A to 3C follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1H, where The same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Referring to FIG. 3A , after the doping process IA of FIG. 1F , the first gate 151 and the second gate 152 can be used as masks to pattern the first insulating layer 130 and the second insulating layer 140 . For example, a dry etching process may be used to remove the first insulating layer 130 and the second insulating layer 140 that are not covered by the first gate 151 and the second gate 152 to form the first insulating layer pattern 132 and the second insulating layer 140 . Insulating layer patterns 141, 142.

The first insulating layer pattern 132 and the second insulating layer pattern 141, 142 expose the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 122a and the second portion 122a of the second metal oxide semiconductor layer 122. Part II 122b. After the above patterning process, the first insulating layer pattern 132 and the second insulating layer pattern 141, 142 can be formed, wherein the second insulating layer pattern 141 is sandwiched between the first gate 151 and the first metal oxide semiconductor layer 121'. between the channel portion 121c, and the first insulating layer pattern 132 and the second insulating layer pattern 142 are sandwiched between the second gate 152 and the channel portion 122c of the second metal oxide semiconductor layer 122. In other words, the second insulating layer The width W1 of the layer pattern 141 may be substantially equal to or approximately the width of the channel portion 121c and the first gate 151, and the width W2 of the second insulating layer pattern 142 may be substantially equal to or approximately equal to the width of the channel portion 122c and the second gate 151. 152 and the width of the first insulating layer pattern 132 .

Please refer to FIG. 3B. Next, a third insulating layer 160 is formed on the substrate 110, and the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the second portion of the second metal oxide semiconductor layer 122 are adjusted at the same time. The hydrogen content of one part 122a and the second part 122b. The third insulating layer 160 may cover the top surface and sidewalls of the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121', and the top surfaces of the first part 122a and the second part 122b of the second metal oxide semiconductor layer 122. The surface and sidewalls, the sidewalls of the first insulating layer pattern 132 , the sidewalls of the second insulating layer patterns 141 and 142 , and the top surface and sidewalls of the first gate 151 and the second gate 152 .

In some embodiments, the reactant used to form the third insulating layer 160 contains hydrogen, and before forming the through holes V1, V2, V3, and V4 in the third insulating layer 160, the third insulating layer 160 is thermally treated. The hydrogen element in migrates or diffuses into the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' and the first part 122a and the second part 122b of the second metal oxide semiconductor layer 122, thereby adjusting The hydrogen content of the first part 121a, the second part 121b, the first part 122a and the second part 122b further improves their electrical conductivity. In some embodiments, the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 are hydrogen-doped using the hydrogen element in the third insulating layer 160. Therefore, the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122 may be omitted. The semiconductor layer 121' and the second metal oxide semiconductor layer 122 undergo a hydrogen plasma treatment step.

The through holes V1, V2, V3, and V4 of the third insulating layer 160 may respectively expose the top surfaces of the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the second metal oxide semiconductor layer 122. The top surfaces of the first portion 122a and the second portion 122b.

Please refer to FIG. 3C. Next, the first source electrode 171, the first drain electrode 172, the second source electrode 173 and the second drain electrode 174 are formed on the third insulating layer 160, and the first source electrode 171, the first drain electrode 172. The second source electrode 173 and the second drain electrode 174 are electrically connected to the first part 121a and the second part 121b of the first metal oxide semiconductor layer 121' through the through holes V1, V2, V3, and V4 respectively. The first portion 122a and the second portion 122b of the metal oxide semiconductor layer 122 can form the first transistor T1B and the second transistor T2B. In some embodiments, a passivation layer 180 may also be formed on the first transistor T1B and the second transistor T2B.

FIG. 3C is a schematic cross-sectional view of a semiconductor device 30 according to yet another embodiment of the present invention. In this embodiment, the semiconductor device 30 may include: a substrate 110, a buffer layer 112, a first transistor T1B, a second transistor T2B, and a passivation layer 180, and the first transistor T1B and the second transistor T2B may be disposed on between the buffer layer 112 and the passivation layer 180 .

The main difference between the semiconductor device 30 shown in FIG. 3C and the semiconductor device 10 shown in FIG. 1H is that the first transistor T1B of the semiconductor device 30 may include a first metal oxide semiconductor layer 121', a second insulating layer pattern 141, The first gate 151, the first source 171 and the first drain 172, and the second insulating layer pattern 141 is sandwiched between the first gate 151 and the channel portion 121c of the first metal oxide semiconductor layer 121'; semiconductor The second transistor T2B of the device 30 may include a second metal oxide semiconductor layer 122, a first insulating layer pattern 132, a second insulating layer pattern 142, a second gate electrode 152, a second source electrode 173, and a second drain electrode 174. , and the first insulating layer pattern 132 and the second insulating layer pattern 142 are sandwiched between the second gate 152 and the channel portion 122c of the second metal oxide semiconductor layer 122; and the third insulating layer 160 directly contacts the buffer layer.

In this embodiment, the oxygen vacancy concentration of the first metal oxide semiconductor layer 121' is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer 122. In other words, the oxygen concentration of the first metal oxide semiconductor layer 121' Lower than the oxygen concentration of the second metal oxide semiconductor layer 122, and the crystallinity of the first metal oxide semiconductor layer 121' is higher than the crystallinity of the second metal oxide semiconductor layer 122, so that the first metal oxide semiconductor layer The carrier mobility of 121' is greater than the carrier mobility of the second metal oxide semiconductor layer 122. In this way, the first transistor T1B can provide a relatively large driving current and is suitable as a driving element, and the second transistor T2B has a relatively small leakage current and is suitable as a switching element.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 40 according to yet another embodiment of the present invention. It must be noted here that the embodiment of FIG. 4 follows the component numbers and part of the content of the embodiment of FIGS. 1A to 1H , where the same or similar numbers are used to represent the same or similar elements, and references with the same technical content are omitted. instruction. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

In this embodiment, the semiconductor device 40 may include: a substrate 110, a buffer layer 112, a first transistor T1C, a second transistor T2C, and a passivation layer 180. The first transistor T1C and the second transistor T2C are disposed on the substrate 110. on the buffer layer 112 and the passivation layer 180 .

The main difference between the semiconductor device 40 shown in FIG. 4 and the semiconductor device 10 shown in FIG. 1H is that the first transistor T1C and the second transistor T2C of the semiconductor device 40 are bottom gate thin film transistors. .

For example, in this embodiment, the first transistor T1C may include a first metal oxide semiconductor layer 421, a first gate electrode 451, a first source electrode 471 and a first drain electrode 472, wherein the third insulating layer 460 The first source electrode 471 and the first drain electrode 472 can be located between the first source electrode 471 and the first drain electrode 472 and the first metal oxide semiconductor layer 421. The first source electrode 471 and the first drain electrode 472 pass through the through holes V1 and V2 in the third insulating layer 460 respectively. The first metal oxide semiconductor layer 421 is electrically connected; the second insulating layer 440 is located between the first metal oxide semiconductor layer 421 and the first gate 451, and the first metal oxide semiconductor layer 421 can be located on the first source. between the pole 471 and the first gate 451 and between the first drain 472 and the first gate 451 . The first gate 451 can overlap the through holes V1 and V2 to ensure that the current can normally flow from the first source 471 and the first drain without the first metal oxide semiconductor layer 421 undergoing additional hydrogen diffusion or doping processes. Extreme 472 outflow.

The second transistor T2C may include a second metal oxide semiconductor layer 422, a first insulating layer 430, a second gate electrode 452, a second source electrode 473, and a second drain electrode 474, wherein the second metal oxide semiconductor layer 422 and The first metal oxide semiconductor layer 421 of the first transistor T1C may belong to the same film layer; the first insulating layer 430 covers the second metal oxide semiconductor layer 422; the third insulating layer 460 and the first insulating layer 430 are located in the second Between the source electrode 473 and the second drain electrode 474 and the second metal oxide semiconductor layer 422, the second source electrode 473 and the second drain electrode 474 pass through the through holes V3 in the third insulating layer 460 and the first insulating layer 430 respectively. , V4 to electrically connect the second metal oxide semiconductor layer 422; the second insulating layer 440 is located between the second metal oxide semiconductor layer 422 and the second gate 452; and the second metal oxide semiconductor layer 422 can be located between the second metal oxide semiconductor layer 422 and the second gate electrode 452. between the two sources 473 and the second gate 452 and between the second drain 474 and the second gate 452 . The second gate 452 can overlap the through holes V3 and V4 to ensure that the current can normally flow from the second source 473 and the second drain without the second metal oxide semiconductor layer 422 undergoing additional hydrogen diffusion or doping processes. Extremely 474 flows out.

In this embodiment, the oxygen vacancy concentration of the first metal oxide semiconductor layer 421 of the semiconductor device 40 is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer 422 , and the oxygen concentration of the first metal oxide semiconductor layer 421 is lower than that of the second metal oxide semiconductor layer 422 . The oxygen concentration of the second metal oxide semiconductor layer 422 and the crystallinity of the first metal oxide semiconductor layer 421 are higher than the crystallinity of the second metal oxide semiconductor layer 422 . In this way, the carrier mobility of the first metal oxide semiconductor layer 421 can be greater than the carrier mobility of the second metal oxide semiconductor layer 422, so that the first transistor T1C can provide a relatively large driving current and is suitable for It is suitable for use as a driving element, and the leakage current of the second transistor T2C is small, so it is suitable for use as a switching element. The threshold voltage of the second transistor T2C can be higher than the threshold voltage of the first transistor T1C.

In summary, the manufacturing method of the semiconductor device of the present invention directly stacks the first insulating layer on the second metal oxide semiconductor layer and then performs an annealing process, so that the oxygen vacancy concentration and crystallization of the first metal oxide semiconductor layer are improved. The degree can be higher than that of the second metal oxide semiconductor layer. In this way, the first metal oxide semiconductor layer can have improved carrier mobility, making the first transistor suitable as a driving element, while the second transistor can have reduced leakage current, so that the second transistor has high Reliability and suitable for use as switching components.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

10, 20, 30, 40: Semiconductor devices 110:Substrate 112:Buffer layer 121, 121’, 421: first metal oxide semiconductor layer 121a:Part 1 121b:Part 2 121c: Channel part 122, 422: Second metal oxide semiconductor layer 122a:Part 1 122b:Part 2 122c: Channel part 130, 430: First insulation layer 132: First insulation layer pattern 140, 440: Second insulation layer 141, 142: Second insulation layer pattern 151, 451: first gate 152, 452: Second gate 160, 460:Third insulation layer 171, 471: first source 172, 472: first drain 173, 473: Second source 174, 474: Second drain 180: Passivation layer IA: doping process T1, T1B, T1C: first transistor T2, T2A, T2B, T2C: second transistor TA: Annealing treatment V1, V2, V3, V4: through holes W1, W2: Width

1A to 1H are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1H is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention, wherein FIG. 2F is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 3A to 3C are schematic cross-sectional views of the steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention, wherein FIG. 3C is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention.

10:Semiconductor device

110:Substrate

112:Buffer layer

121’: first metal oxide semiconductor layer

121a:Part 1

121b:Part 2

121c: Channel part

122: Second metal oxide semiconductor layer

122a:Part 1

122b:Part 2

122c: Channel part

130: First insulation layer

140: Second insulation layer

151: first gate

152: Second gate

160:Third insulation layer

171:First Source

172: first drain

173:Second Source

174: The second drain

180: Passivation layer

T1: the first transistor

T2: Second transistor

V1, V2, V3, V4: through holes

Claims (16)

A semiconductor device including: a substrate; A first transistor is disposed on the substrate, and the first transistor includes a first metal oxide semiconductor layer and a first gate overlapping the first metal oxide semiconductor layer; and A second transistor is disposed on the substrate, and the second transistor includes: a second metal oxide semiconductor layer, wherein the second metal oxide semiconductor layer and the first metal oxide semiconductor layer belong to the same film layer, and the oxygen concentration of the first metal oxide semiconductor layer is lower than that of the second metal oxide semiconductor layer The oxygen concentration of the oxide semiconductor layer; a second gate overlapping the second metal oxide semiconductor layer; and A first insulating layer covers the second metal oxide semiconductor and is not located between the first metal oxide semiconductor and the first gate. The semiconductor device of claim 1, wherein the oxygen vacancy concentration of the first metal oxide semiconductor layer is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer, and the crystallinity of the first metal oxide semiconductor layer Higher than the crystallinity of the second metal oxide semiconductor layer. The semiconductor device of claim 1, further comprising a second insulating layer, wherein the second insulating layer covers the first metal oxide semiconductor layer and the first insulating layer, and wherein the first metal oxide semiconductor layer The second insulating layer is sandwiched between the first gate electrode and the second metal oxide semiconductor layer. The first insulating layer and the second insulating layer are sandwiched between the second metal oxide semiconductor layer and the second gate electrode. The semiconductor device of claim 1, wherein the carrier mobility of the first metal oxide semiconductor layer is greater than the carrier mobility of the second metal oxide semiconductor layer. The semiconductor device of claim 1, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer contain the same metal element. The semiconductor device of claim 1, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer include indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, and indium zinc tin oxide. , indium gallium tin oxide or indium gallium zinc tin oxide. The semiconductor device according to claim 1, wherein the thickness of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer is 100Å to 500Å. The semiconductor device of claim 1, wherein the first insulating layer includes an oxygen-containing insulating layer or an oxygen barrier layer. The semiconductor device of claim 1, wherein the threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. A method of manufacturing a semiconductor device, including: Forming a first metal oxide semiconductor layer and a second metal oxide semiconductor layer on a substrate, and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer belong to the same film layer; Forming a first insulating layer to cover the second metal oxide semiconductor, and the first insulating layer does not contact the first metal oxide semiconductor; performing an annealing treatment so that the oxygen concentration of the first metal oxide semiconductor is lower than the oxygen concentration of the second metal oxide; and A first gate and a second gate are formed on the substrate, and the first gate and the second gate overlap the first metal oxide semiconductor layer and the second metal oxide semiconductor layer respectively. The method of manufacturing a semiconductor device as claimed in claim 10, wherein the annealing process includes maintaining between 200°C and 500°C for 30 minutes to 180 minutes. The method of manufacturing a semiconductor device according to claim 10, wherein the first gate and the second gate are formed simultaneously. The method of manufacturing a semiconductor device according to claim 10, further comprising forming a second insulating layer on the substrate before forming the first gate and the second gate, and the second insulating layer is located on the first gate. between a gate and the first metal oxide semiconductor layer and between the second gate and the first insulating layer. The method of manufacturing a semiconductor device according to claim 10, further comprising: after forming the first gate and the second gate, oxidizing the first metal with the first gate and the second gate as a mask The material semiconductor and the second metal oxide semiconductor undergo a doping process. The method of manufacturing a semiconductor device according to claim 14, further comprising forming a third insulating layer on the first gate and the second gate after the doping process. The method of manufacturing a semiconductor device according to claim 15, further comprising forming a first source, a first drain, a second source and a second drain on the third insulating layer, and the third A source electrode and the first drain electrode are electrically connected to the first metal oxide semiconductor layer, and the second source electrode and the second drain electrode are electrically connected to the second metal oxide semiconductor layer.

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