TWI803311B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TWI803311B
TWI803311B TW111117309A TW111117309A TWI803311B TW I803311 B TWI803311 B TW I803311B TW 111117309 A TW111117309 A TW 111117309A TW 111117309 A TW111117309 A TW 111117309A TW I803311 B TWI803311 B TW I803311B
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metal oxide
semiconductor layer
oxide semiconductor
substrate
thick
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TW202324743A (en
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黃震鑠
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友達光電股份有限公司
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Abstract

A semiconductor device and manufacturing method thereof are provided. The semiconductor device includes a substrate, a semiconductor structure, a gate dielectric layer and a gate. The semiconductor structure is disposed above the substrate. The semiconductor structure includes two thick portions and a thin portion located between the two thick portions. A thickness of the two thick portions is larger than a thickness of the thin portion. The gate dielectric layer is disposed on the semiconductor structure. The gate is disposed on the gate dielectric layer. A width of the gate is larger than the width of the thin portion, and the gate is overlapped with a part of the two thick portions and the thin portion in a normal direction of a top surface of the substrate. A resistivity of at least a part of the two thick portions increases with proximity to the substrate.

Description

半導體裝置及其製造方法Semiconductor device and manufacturing method thereof

本發明是有關於一種半導體裝置及其製造方法，且特別是有關於一種包括金屬氧化物半導體的半導體裝置及其製造方法。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a metal oxide semiconductor and a manufacturing method thereof.

一般來說，薄膜電晶體的半導體層可分為通道區及摻雜區。若摻雜區的載子濃度高，且摻雜區與通道區之間出現突然下降的載子濃度，會使薄膜電晶體在大電流的操作過程中於靠近汲極處出現很高的橫向電場，並導致半導體裝置劣化。然而，若為了避免半導體裝置劣化而降低摻雜區的載子濃度，會使半導體裝置的操作電流不足。因此，如何使半導體裝置在保有足夠的操作電流表現下，同時減小靠近汲極處的橫向電場是目前需改善的問題。 In general, the semiconductor layer of a TFT can be divided into a channel region and a doped region. If the carrier concentration in the doped region is high, and there is a sudden drop in the carrier concentration between the doped region and the channel region, a high lateral electric field will appear near the drain of the thin film transistor during high current operation. , and cause deterioration of the semiconductor device. However, if the carrier concentration in the doped region is reduced in order to avoid deterioration of the semiconductor device, the operating current of the semiconductor device will be insufficient. Therefore, how to reduce the lateral electric field near the drain while maintaining sufficient operating current performance of the semiconductor device is a problem that needs to be improved.

本發明提供一種半導體裝置及其製造方法，可減小靠近 汲極處的橫向電場，以提升半導體裝置的可靠度。 The invention provides a semiconductor device and its manufacturing method, which can reduce the proximity The lateral electric field at the drain to improve the reliability of the semiconductor device.

本發明的半導體裝置包括基板、半導體結構、閘介電層以及閘極。半導體結構設置於基板之上，半導體結構包括兩個厚部以及位於兩個厚部之間的薄部，兩個厚部的厚度大於薄部的厚度。閘介電層設置於半導體結構上。閘極設置於閘介電層上。閘極的寬度大於薄部的寬度，且閘極在基板的頂面的法線方向上重疊於部分兩個厚部及薄部。至少部分兩個厚部的電阻率隨著靠近基板而增加。 The semiconductor device of the present invention includes a substrate, a semiconductor structure, a gate dielectric layer and a gate. The semiconductor structure is disposed on the substrate. The semiconductor structure includes two thick parts and a thin part between the two thick parts. The thickness of the two thick parts is greater than that of the thin part. The gate dielectric layer is disposed on the semiconductor structure. The gate is disposed on the gate dielectric layer. The width of the gate is greater than that of the thin part, and the gate overlaps part of the two thick parts and the thin part in the normal direction of the top surface of the substrate. The resistivity of at least some of the two thick portions increases closer to the substrate.

本發明的半導體裝置的製造方法包括以下步驟。提供基板。形成半導體結構於基板之上，其中半導體結構包括兩個厚部以及位於兩個厚部之間的薄部，兩個厚部的厚度大於薄部的厚度。形成閘介電層於半導體結構上。形成閘極於閘介電層上，其中閘極的寬度大於薄部的寬度，閘極在基板的頂面的法線方向上重疊於部分兩個厚部及薄部。調整半導體結構的電阻率，以使至少部分兩個厚部的電阻率隨著靠近基板而增加。 A method of manufacturing a semiconductor device of the present invention includes the following steps. Substrate provided. A semiconductor structure is formed on the substrate, wherein the semiconductor structure includes two thick parts and a thin part between the two thick parts, the thickness of the two thick parts is greater than the thickness of the thin part. A gate dielectric layer is formed on the semiconductor structure. The gate electrode is formed on the gate dielectric layer, wherein the width of the gate electrode is greater than that of the thin portion, and the gate electrode overlaps part of the two thick portions and the thin portion in the normal direction of the top surface of the substrate. The resistivity of the semiconductor structure is adjusted such that the resistivity of at least some of the two thick portions increases closer to the substrate.

1,2,3,4:半導體裝置 1,2,3,4: Semiconductor devices

100:基板 100: Substrate

110:緩衝層 110: buffer layer

120,120’:半導體結構 120,120': Semiconductor structure

122,122’:第一金屬氧化物半導體層 122,122': the first metal oxide semiconductor layer

122a,124a,122a’,124a’:第一島狀結構 122a, 124a, 122a', 124a': the first island structure

122b,124b,122b’,124b’:第二島狀結構 122b, 124b, 122b', 124b': the second island structure

124,124’:第二金屬氧化物半導體層 124,124': second metal oxide semiconductor layer

130:閘介電層 130: gate dielectric layer

140:閘極 140: Gate

150:層間介電層 150: interlayer dielectric layer

162:源極 162: source

164:汲極 164: drain

ch:通道區 ch: channel area

ch1:第一通道區 ch1: the first channel area

ch2:第二通道區 ch2: the second channel area

ch2’:第二部分 ch2': the second part

dp:摻雜區 dp: doped area

dp’:第一部分 dp': the first part

p1:厚部 p1: thick part

p2:薄部 p2: thin part

S1:頂面 S1: top surface

S2:底面 S2: bottom surface

t1,t2,T,T’:厚度 t1, t2, T, T': Thickness

w1,w2:寬度 w1, w2: width

ND:方向 ND: Direction

O1:第一開口 O1: first opening

O2:第二開口 O2: second opening

P1:摻雜製程 P1: Doping process

P2:退火製程 P2: Annealing process

V1,V2,V1’,V2’:貫孔 V1, V2, V1’, V2’: through holes

圖1是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.

圖2A至2C是依照本發明圖1的實施例的一種製造流程的剖面示意圖。 2A to 2C are schematic cross-sectional views of a manufacturing process according to the embodiment of FIG. 1 of the present invention.

圖3是依照本發明的另一實施例的一種半導體裝置的剖面示意圖。 FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

圖4是依照本發明圖3的實施例的一種製造流程的剖面示意圖。 FIG. 4 is a schematic cross-sectional view of a manufacturing process according to the embodiment of FIG. 3 of the present invention.

圖5是依照本發明的另一實施例的一種半導體裝置的剖面示意圖。 FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

圖6是依照本發明圖5的實施例的一種製造流程的剖面示意圖。 FIG. 6 is a schematic cross-sectional view of a manufacturing process according to the embodiment of FIG. 5 of the present invention.

圖7是依照本發明的另一實施例的一種半導體裝置的剖面示意圖。 FIG. 7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

圖8A至圖8B是依照本發明圖7的實施例的一種製造流程的剖面示意圖。 8A to 8B are schematic cross-sectional views of a manufacturing process according to the embodiment of FIG. 7 of the present invention.

圖1是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.

請參照圖1，半導體裝置1包括基板100、半導體結構120、閘介電層130以及閘極140。在本實施例中，半導體裝置1還包括緩衝層110、層間介電層150、源極162以及汲極164。 Referring to FIG. 1 , the semiconductor device 1 includes a substrate 100 , a semiconductor structure 120 , a gate dielectric layer 130 and a gate 140 . In this embodiment, the semiconductor device 1 further includes a buffer layer 110 , an interlayer dielectric layer 150 , a source 162 and a drain 164 .

基板100之材質可為玻璃、石英、有機聚合物或是不透光/反射材料(例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料)或是其他可適用的材料。若使用導電材料或金屬時，則 在基板100上覆蓋一層絕緣層(未繪示)，以避免短路問題。在一些實施例中，基板100為軟性基板，且基板100的材料例如為聚乙烯對苯二甲酸酯(polyethylene terephthalate,PET)、聚二甲酸乙二醇酯(polyethylene naphthalate,PEN)、聚酯(polyester,PES)、聚甲基丙烯酸甲酯(polymethylmethacrylate,PMMA)、聚碳酸酯(polycarbonate,PC)、聚醯亞胺(polyimide,PI)或金屬軟板(Metal Foil)或其他可撓性材質。緩衝層110位於基板100上，緩衝層110的材質可以包括氮化矽、氧化矽、氮氧化矽或其他合適的材料或上述材料的堆疊層，但本發明不以此為限。 The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, then An insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials . The buffer layer 110 is located on the substrate 100 , and the material of the buffer layer 110 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the invention is not limited thereto.

半導體結構120設置於基板100與緩衝層110之上。半導體結構120包括兩個厚部p1以及位於兩個厚部p1之間的薄部p2。半導體結構120的材料可以包括氧化銦鎵鋅(IGZO)、氧化銦錫鋅(ITZO)、氧化鋁鋅錫(AZTO)、氧化銦鎢鋅(IWZO)等四元金屬化合物或包含鎵(Ga)、鋅(Zn)、銦(In)、錫(Sn)、鋁(Al)、鎢(W)中之任三者的三元金屬構成的氧化物。半導體結構120可以為單層或多層結構。閘介電層130設置於半導體結構120及緩衝層110上，閘極140設置於閘介電層130上。層間介電層150設置於閘介電層130上，並覆蓋閘極140。層間介電層150與閘介電層130的材料例如為氧化矽、氮化矽、氮氧化矽或其他合適的材料。貫孔V1、V2貫穿層間介電層150及閘介電層130，且分別重疊於兩個厚部p1。源極162以及汲極164位於層間介電層150上，且分別填入貫孔V1、V2以電性連接至半導體結構120。 The semiconductor structure 120 is disposed on the substrate 100 and the buffer layer 110 . The semiconductor structure 120 includes two thick portions p1 and a thin portion p2 between the two thick portions p1. The material of the semiconductor structure 120 may include quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or gallium (Ga), An oxide composed of a ternary metal of any three of zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W). The semiconductor structure 120 may be a single-layer or multi-layer structure. The gate dielectric layer 130 is disposed on the semiconductor structure 120 and the buffer layer 110 , and the gate 140 is disposed on the gate dielectric layer 130 . The interlayer dielectric layer 150 is disposed on the gate dielectric layer 130 and covers the gate 140 . Materials of the interlayer dielectric layer 150 and the gate dielectric layer 130 are, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. The vias V1 and V2 penetrate through the interlayer dielectric layer 150 and the gate dielectric layer 130 and overlap the two thick portions p1 respectively. The source 162 and the drain 164 are located on the interlayer dielectric layer 150 and are respectively filled in the vias V1 and V2 to be electrically connected to the semiconductor structure 120 .

在本實施例中，兩個厚部p1的厚度T大於薄部p2的厚度T’。舉例來說，兩個厚部p1的厚度T可以在7nm至120nm之間，薄部p2的厚度T’可以在2nm至60nm之間。至少部分兩個厚部p1的電阻率隨著靠近基板100而增加。舉例來說，在兩個厚部p1中，靠近兩個厚部p1的頂面S1的電阻率小於靠近兩個厚部p1的底面S2的電阻率。其中兩個厚部p1的電阻率可透過摻雜濃度的變化或氧空缺濃度的變化來改變。舉例來說，在一些實施例中，至少部分兩個厚部p1的銦濃度隨著靠近基板100而減少。在一些實施例中，至少部分兩個厚部p1的氧濃度隨著靠近基板100而增加。在一些實施例中，至少部分兩個厚部p1(例如厚部p1的摻雜區dp)的氫濃度隨著靠近基板100而減少。由於半導體結構120的兩個厚部p1的厚度T大於薄部p2的厚度T’，且至少部分兩個厚部p1的電阻率隨著靠近基板100而增加，可減少半導體結構120在靠近汲極164處(於後述說明)因橫向電場而產生的熱載子效應。 In this embodiment, the thickness T of the two thick portions p1 is larger than the thickness T' of the thin portion p2. For example, the thickness T of the two thick portions p1 may be between 7nm and 120nm, and the thickness T' of the thin portion p2 may be between 2nm and 60nm. The resistivities of at least some of the two thick portions p1 increase as they get closer to the substrate 100 . For example, among the two thick portions p1 , the resistivity of the top surface S1 close to the two thick portions p1 is smaller than the resistivity of the bottom surface S2 close to the two thick portions p1 . The resistivity of the two thick portions p1 can be changed by changing the doping concentration or changing the oxygen vacancy concentration. For example, in some embodiments, the indium concentration of at least part of the two thick portions p1 decreases as the substrate 100 approaches. In some embodiments, the oxygen concentration of at least part of the two thick portions p1 increases as one approaches the substrate 100 . In some embodiments, the hydrogen concentration of at least part of the two thick portions p1 (for example, the doped region dp of the thick portion p1 ) decreases as it approaches the substrate 100 . Since the thickness T of the two thick portions p1 of the semiconductor structure 120 is greater than the thickness T′ of the thin portion p2, and the resistivity of at least part of the two thick portions p1 increases as the approach to the substrate 100 increases, the semiconductor structure 120 can be reduced near the drain. 164 (to be described later) due to the hot carrier effect generated by the transverse electric field.

在本實施例中，閘極140的寬度w1大於薄部p2的寬度w2，且閘極140在基板100的頂面的法線方向ND上可重疊於部分兩個厚部p1及薄部p2。舉例來說，薄部p2在基板100的頂面的法線方向ND上可以完全重疊於閘極140，兩個厚部p1在基板100的頂面的法線方向ND上可分別部分重疊於閘極140。在一些實施例中，閘極140的寬度w1與薄部p2的寬度w2比(w1/w2)為1.05~3。 In this embodiment, the width w1 of the gate 140 is greater than the width w2 of the thin portion p2 , and the gate 140 can partially overlap the two thick portions p1 and the thin portion p2 in the normal direction ND of the top surface of the substrate 100 . For example, the thin portion p2 can completely overlap the gate electrode 140 in the normal direction ND of the top surface of the substrate 100 , and the two thick portions p1 can partially overlap the gate electrode 140 in the normal direction ND of the top surface of the substrate 100 respectively. Pole 140. In some embodiments, the ratio (w1/w2) of the width w1 of the gate electrode 140 to the width w2 of the thin portion p2 is 1.05˜3.

半導體結構120的薄部p2可構成第一通道區ch1，半導體結構120的兩個厚部p1各自包括摻雜區dp以及第二通道區ch2。在一些實施例中，兩個厚部p1在基板100的頂面的法線方向ND上不與閘極140重疊的部分可為摻雜區dp，兩個厚部p1在基板100的頂面的法線方向ND上與閘極140重疊的部分可為第二通道區ch2，兩個厚部p1靠近薄部p2的部分(第二通道區ch2)的氫濃度低於兩個厚部p1遠離薄部p2的部分(摻雜區dp)的氫濃度。摻雜區dp的電阻率隨著靠近基板100而增加。舉例而言，摻雜區dp的氫濃度隨著靠近基板100而減少，摻雜區dp的氧空缺濃度隨著靠近基板100而減少。由於摻雜區dp的電阻率隨著靠近基板100而增加，在汲極164處之摻雜區dp靠近基板100的下部可以作為低摻雜汲極(Lightly Doped Drain，LDD)結構，進而減小通道區ch(包含第一通道區ch1以及第二通道區ch2)與摻雜區dp之間因為橫向電場而產生的熱載子效應，以提升半導體裝置1的可靠度。此外，由於源極162與汲極164接觸了摻雜區dp中電阻率較低的上部，因此，源極162與摻雜區dp之間的界面電阻以及汲極164與摻雜區dp之間的界面電阻可以被減小，藉此提升半導體裝置1的操作電流。 The thin portion p2 of the semiconductor structure 120 may constitute a first channel region ch1 , and the two thick portions p1 of the semiconductor structure 120 each include a doped region dp and a second channel region ch2 . In some embodiments, the part of the two thick parts p1 not overlapping with the gate 140 in the normal direction ND of the top surface of the substrate 100 may be a doped region dp, and the two thick parts p1 on the top surface of the substrate 100 The part overlapping with the gate electrode 140 in the normal direction ND can be the second channel region ch2, and the hydrogen concentration of the part (second channel region ch2) where the two thick parts p1 are close to the thin part p2 is lower than that of the two thick parts p1 away from the thin part. The hydrogen concentration of the part (doped region dp) of part p2. The resistivity of the doped region dp increases as it approaches the substrate 100 . For example, the hydrogen concentration of the doped region dp decreases as it approaches the substrate 100 , and the oxygen vacancy concentration of the doped region dp decreases as it approaches the substrate 100 . Since the resistivity of the doped region dp increases as it gets closer to the substrate 100, the lower part of the doped region dp near the substrate 100 at the drain 164 can be used as a low-doped drain (Lightly Doped Drain, LDD) structure, thereby reducing The hot carrier effect generated between the channel region ch (including the first channel region ch1 and the second channel region ch2 ) and the doped region dp due to the lateral electric field improves the reliability of the semiconductor device 1 . In addition, since the source 162 and the drain 164 are in contact with the lower resistivity upper part of the doped region dp, the interface resistance between the source 162 and the doped region dp and the interface resistance between the drain 164 and the doped region dp The interfacial resistance of the semiconductor device 1 can be reduced, thereby increasing the operating current of the semiconductor device 1 .

圖2A至2C是依照本發明圖1的實施例的一種製造流程的剖面示意圖。 2A to 2C are schematic cross-sectional views of a manufacturing process according to the embodiment of FIG. 1 of the present invention.

請參照圖2A，提供基板100，形成半導體結構120’於基板100之上。舉例來說，可先形成緩衝層110於基板100上，之 後形成半導體結構120’於緩衝層110上。半導體結構120’的形成方法例如可透過沉積一金屬氧化物半導體材料層(未繪示)於緩衝層110上，再透過蝕刻製程圖案化金屬氧化物半導體材料層，以形成半導體結構120’，其中半導體結構120’包括兩個厚部p1以及位於兩個厚部p1之間的一薄部p2，兩個厚部p1的厚度T大於薄部p2的厚度T’。 Referring to FIG. 2A, a substrate 100 is provided, and a semiconductor structure 120' is formed on the substrate 100. Referring to FIG. For example, the buffer layer 110 can be formed on the substrate 100 first, then Afterwards, a semiconductor structure 120' is formed on the buffer layer 110. The semiconductor structure 120' can be formed by, for example, depositing a metal oxide semiconductor material layer (not shown) on the buffer layer 110, and then patterning the metal oxide semiconductor material layer through an etching process to form the semiconductor structure 120', wherein The semiconductor structure 120 ′ includes two thick portions p1 and a thin portion p2 located between the two thick portions p1 , the thickness T of the two thick portions p1 is greater than the thickness T′ of the thin portion p2 .

請參照圖2B，形成閘介電層130於半導體結構120’上。舉例來說，閘介電層130是共形地形成於半導體結構120’及緩衝層110上，也就是說，閘介電層130可覆蓋半導體結構120’的頂面及側壁。 Referring to FIG. 2B, a gate dielectric layer 130 is formed on the semiconductor structure 120'. For example, the gate dielectric layer 130 is conformally formed on the semiconductor structure 120' and the buffer layer 110, that is, the gate dielectric layer 130 may cover the top surface and sidewalls of the semiconductor structure 120'.

請參照圖2C，形成閘極140於閘介電層130上。閘極140的形成方法例如是先沉積一閘極材料層(未繪示)於閘介電層130上，之後再透過蝕刻製程形成閘極140。閘極140的寬度w1大於薄部p2的寬度w2，閘極140在基板100的頂面的法線方向ND上可重疊於部分兩個厚部p1及薄部p2。 Referring to FIG. 2C , a gate electrode 140 is formed on the gate dielectric layer 130 . The gate electrode 140 is formed by, for example, depositing a gate material layer (not shown) on the gate dielectric layer 130 first, and then forming the gate electrode 140 through an etching process. The width w1 of the gate 140 is greater than the width w2 of the thin portion p2 , and the gate 140 can partially overlap the two thick portions p1 and the thin portion p2 in the normal direction ND of the top surface of the substrate 100 .

請繼續參照圖2C，調整半導體結構120的電阻率，以使至少部分兩個厚部p1的電阻率隨著靠近基板100而增加。舉例來說，以閘極140為遮罩，對半導體結構120’進行摻雜製程P1，以形成包括摻雜區dp、第一通道區ch1以及第二通道區ch2的半導體結構120。半導體結構120的兩個厚部p1未被閘極140覆蓋的部分透過摻雜製程P1形成摻雜區dp，兩個厚部p1被閘極140覆蓋的部分則構成第二通道區ch2，且摻雜區dp的電阻率隨著靠近 100基板而增加。舉例來說，在一些實施例中，在進行摻雜製程P1之後，至少部分兩個厚部p1的銦濃度隨著靠近基板100而減少或使至少部分兩個厚部p1的氫濃度隨著靠近基板100而減少，進而使至少部分兩個厚部p1的電阻率隨著靠近100基板而增加。半導體結構120中與閘極140在基板100的頂面的法線方向ND上重疊的薄部p2可構成第一通道區ch1。 Please continue to refer to FIG. 2C , the resistivity of the semiconductor structure 120 is adjusted so that the resistivity of at least part of the two thick portions p1 increases as the substrate 100 approaches. For example, using the gate electrode 140 as a mask, the semiconductor structure 120' is subjected to a doping process P1 to form the semiconductor structure 120 including the doped region dp, the first channel region ch1 and the second channel region ch2. The parts of the two thick parts p1 not covered by the gate 140 of the semiconductor structure 120 form the doped region dp through the doping process P1, and the parts of the two thick parts p1 covered by the gate 140 form the second channel region ch2, and the doped region dp is formed by the doping process P1. The resistivity of impurity region dp increases with the approach 100 substrates and increase. For example, in some embodiments, after the doping process P1 is performed, the indium concentrations of at least some of the two thick portions p1 decrease as they get closer to the substrate 100 or the hydrogen concentrations of at least some of the two thick portions p1 get closer to the substrate 100 . The substrate 100 decreases, so that the resistivity of at least part of the two thick portions p1 increases as the substrate 100 approaches. The thin portion p2 of the semiconductor structure 120 overlapping with the gate 140 in the normal direction ND of the top surface of the substrate 100 may constitute the first channel region ch1 .

在一些實施例中，由於閘極140的寬度w1大於薄部p2的寬度w2，且閘極140在基板100的頂面的法線方向ND上重疊於部分兩個厚部p1及薄部p2，在進行摻雜製程P1後可以形成厚度不同的第一通道區ch1以及第二通道區ch2，其中第二通道區ch2的厚度大於第一通道區ch1的厚度。 In some embodiments, since the width w1 of the gate electrode 140 is greater than the width w2 of the thin portion p2, and the gate electrode 140 overlaps part of the two thick portion p1 and the thin portion p2 in the normal direction ND of the top surface of the substrate 100, After the doping process P1 is performed, the first channel region ch1 and the second channel region ch2 with different thicknesses can be formed, wherein the thickness of the second channel region ch2 is greater than the thickness of the first channel region ch1 .

之後，請參照圖1，形成層間介電層150於閘介電層130上，並覆蓋閘極140。接著，形成貫穿層間介電層150及閘介電層130的貫孔V1、V2，且貫孔V1、V2分別在基板100的頂面的法線方向ND上重疊於兩個厚部p1的摻雜區dp。然後，形成源極162以及汲極164於層間介電層150之上，並填入貫孔V1、V2中，以與厚部p1的摻雜區dp電性連接。 After that, referring to FIG. 1 , an interlayer dielectric layer 150 is formed on the gate dielectric layer 130 and covers the gate electrode 140 . Next, through-holes V1 and V2 penetrating the interlayer dielectric layer 150 and the gate dielectric layer 130 are formed, and the through-holes V1 and V2 respectively overlap the doped holes of the two thick portions p1 in the normal direction ND of the top surface of the substrate 100 . Miscellaneous area dp. Then, a source electrode 162 and a drain electrode 164 are formed on the interlayer dielectric layer 150 and filled into the through holes V1 and V2 to be electrically connected to the doped region dp of the thick portion p1.

經過上述製程後可大致上完成半導體裝置1的製作。 After the above process, the fabrication of the semiconductor device 1 can be substantially completed.

圖3是依照本發明的另一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分 的說明可參考前述實施例，在此不贅述。 FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. It must be noted here that the embodiment in FIG. 3 uses the component numbers and parts of the content in the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. About omitted parts For description, reference may be made to the foregoing embodiments, and details are not repeated here.

請參考圖3，圖3的半導體裝置2與圖1的半導體裝置1的主要差異在於：半導體裝置2的半導體結構120包括第一金屬氧化物半導體層122及第二金屬氧化物半導體層124，第一金屬氧化物半導體層122位於基板100與第二金屬氧化物半導體層124之間。第一金屬氧化物半導體層122及第二金屬氧化物半導體層124的堆疊可構成半導體結構120的兩個厚部p1。舉例來說，在本實施例中，第一金屬氧化物半導體層122包括互相分離的第一島狀結構122a以及第二島狀結構122b。第一島狀結構122a與第二金屬氧化物半導體層124堆疊以構成其中一個厚部p1，且第二島狀結構122b與第二金屬氧化物半導體層124堆疊以構成其中另一個厚部p1。第二金屬氧化物半導體層124位於兩個厚部p1之間的區域可構成薄部p2。 Please refer to FIG. 3, the main difference between the semiconductor device 2 in FIG. 3 and the semiconductor device 1 in FIG. A metal oxide semiconductor layer 122 is located between the substrate 100 and the second metal oxide semiconductor layer 124 . The stack of the first metal oxide semiconductor layer 122 and the second metal oxide semiconductor layer 124 can constitute two thick portions p1 of the semiconductor structure 120 . For example, in this embodiment, the first metal oxide semiconductor layer 122 includes a first island structure 122 a and a second island structure 122 b that are separated from each other. The first island structure 122 a is stacked with the second metal oxide semiconductor layer 124 to form one of the thick portions p1 , and the second island structure 122 b is stacked with the second metal oxide semiconductor layer 124 to form the other thick portion p1 . A region of the second metal oxide semiconductor layer 124 between the two thick portions p1 may constitute the thin portion p2.

在本實施例中，第一金屬氧化物半導體層122的厚度t1大於第二金屬氧化物半導體層124的厚度t2。舉例來說，第一金屬氧化物半導體層122的厚度t1可以在5nm至60nm之間，第二金屬氧化物半導體層124的厚度t2可以在2nm至60nm之間。半導體結構120的兩個厚部p1的厚度T基本上為第一金屬氧化物半導體層122的厚度t1與第二金屬氧化物半導體層124的厚度t2的總和，半導體結構120的薄部p2的厚度T’基本上等於第二金屬氧化物半導體層124的厚度t2。 In this embodiment, the thickness t1 of the first metal oxide semiconductor layer 122 is greater than the thickness t2 of the second metal oxide semiconductor layer 124 . For example, the thickness t1 of the first metal oxide semiconductor layer 122 may be between 5 nm and 60 nm, and the thickness t2 of the second metal oxide semiconductor layer 124 may be between 2 nm and 60 nm. The thickness T of the two thick portions p1 of the semiconductor structure 120 is basically the sum of the thickness t1 of the first metal oxide semiconductor layer 122 and the thickness t2 of the second metal oxide semiconductor layer 124, and the thickness T of the thin portion p2 of the semiconductor structure 120 T′ is substantially equal to the thickness t2 of the second metal oxide semiconductor layer 124 .

在一些實施例中，第一金屬氧化物半導體層122與第二 金屬氧化物半導體層124可包括相同的金屬元素，但本發明不以此為限。在其他實施例中，第一金屬氧化物半導體層122與第二金屬氧化物半導體層124可包括不同的金屬元素。 In some embodiments, the first metal oxide semiconductor layer 122 and the second The metal oxide semiconductor layer 124 may include the same metal element, but the invention is not limited thereto. In other embodiments, the first metal oxide semiconductor layer 122 and the second metal oxide semiconductor layer 124 may include different metal elements.

在一些實施例中，第一金屬氧化物半導體層122的氧濃度高於第二金屬氧化物半導體層124的氧濃度，第一金屬氧化物半導體層122的銦濃度低於第二金屬氧化物半導體層124的銦濃度，第一金屬氧化物半導體層122的氫濃度低於第二金屬氧化物半導體層124的氫濃度，因此，部分半導體結構120的兩個厚部p1的電阻率隨著靠近基板100而增加，使在汲極164處之摻雜區dp靠近基板100的下部可以作為低摻雜汲極(Lightly Doped Drain，LDD)結構，進而可有效減小通道區ch(包含第一通道區ch1以及第二通道區ch2)與摻雜區dp之間因為橫向電場而產生的熱載子效應，以提升半導體裝置2的可靠度。 In some embodiments, the oxygen concentration of the first metal oxide semiconductor layer 122 is higher than the oxygen concentration of the second metal oxide semiconductor layer 124, and the indium concentration of the first metal oxide semiconductor layer 122 is lower than that of the second metal oxide semiconductor layer. The indium concentration of the layer 124, the hydrogen concentration of the first metal oxide semiconductor layer 122 is lower than the hydrogen concentration of the second metal oxide semiconductor layer 124, therefore, the resistivity of the two thick parts p1 of the partial semiconductor structure 120 increases with the approach to the substrate 100, so that the doped region dp at the drain 164 can be used as a low-doped drain (Lightly Doped Drain, LDD) structure near the bottom of the substrate 100, thereby effectively reducing the channel region ch (including the first channel region The hot carrier effect generated between ch1 and the second channel region ch2 ) and the doped region dp due to the lateral electric field can improve the reliability of the semiconductor device 2 .

圖4是依照本發明圖3的實施例的一種製造流程的剖面示意圖。 FIG. 4 is a schematic cross-sectional view of a manufacturing process according to the embodiment of FIG. 3 of the present invention.

請參考圖4，提供基板100，形成半導體結構120’於基板100之上。舉例來說，可先形成緩衝層110於基板100上，之後形成半導體結構120’於緩衝層110上。半導體結構120’的形成方法例如可包括以下步驟。首先，形成第一金屬氧化物半導體層122’於緩衝層110及基板100之上，其中第一金屬氧化物半導體層122’具有第一開口O1，以使第一金屬氧化物半導體層122’包括互相分離的第一島狀結構122a以及第二島狀結構122b。然後，形成第二 金屬氧化物半導體層124’於第一金屬氧化物半導體層122’上，並填入第一開口O1中，其中第一金屬氧化物半導體層122’的厚度t1大於第二金屬氧化物半導體層124’的厚度t2。如此一來，位於第一開口O1中的部分第二金屬氧化物半導體層124’可構成半導體結構120’的薄部p2，第一金屬氧化物半導體層122’與覆蓋於其上的另一部分第二金屬氧化物半導體層124’可構成半導體結構120’的兩個厚部p1。 Referring to FIG. 4, a substrate 100 is provided, and a semiconductor structure 120' is formed on the substrate 100. Referring to FIG. For example, the buffer layer 110 can be formed on the substrate 100 first, and then the semiconductor structure 120' can be formed on the buffer layer 110. The method for forming the semiconductor structure 120' may include the following steps, for example. First, the first metal oxide semiconductor layer 122' is formed on the buffer layer 110 and the substrate 100, wherein the first metal oxide semiconductor layer 122' has a first opening O1, so that the first metal oxide semiconductor layer 122' includes The first island structure 122a and the second island structure 122b are separated from each other. Then, form the second The metal oxide semiconductor layer 124' is on the first metal oxide semiconductor layer 122' and fills in the first opening O1, wherein the thickness t1 of the first metal oxide semiconductor layer 122' is greater than that of the second metal oxide semiconductor layer 124 'thickness t2. In this way, the part of the second metal oxide semiconductor layer 124' located in the first opening O1 can constitute the thin part p2 of the semiconductor structure 120', and the first metal oxide semiconductor layer 122' and another part of the second metal oxide semiconductor layer covering it The two metal oxide semiconductor layers 124' can constitute two thick portions p1 of the semiconductor structure 120'.

請參考圖3，半導體結構120’形成之後，可以接續類似於上述圖2B至2C及圖1的製造流程，以完成半導體裝置2的製作。詳細流程可參考前述實施例，在此不贅述。 Please refer to FIG. 3 , after the semiconductor structure 120' is formed, the manufacturing process similar to the above-mentioned FIGS. 2B to 2C and FIG. 1 can be continued to complete the fabrication of the semiconductor device 2 . For the detailed process, reference may be made to the aforementioned embodiments, and details are not repeated here.

圖5是依照本發明的另一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖5的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. It must be noted here that the embodiment in FIG. 5 follows the component numbers and part of the content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

請參考圖5，圖5的半導體裝置3與圖1的半導體裝置1的主要差異在於：半導體裝置3的半導體結構120包括第一金屬氧化物半導體層122及第二金屬氧化物半導體層124，第一金屬氧化物半導體層122位於基板100與第二金屬氧化物半導體層124之間。第一金屬氧化物半導體層122及第二金屬氧化物半導體層124的堆疊構成半導體結構120的兩個厚部p1。舉例來說，在本實施例中，第二金屬氧化物半導體層124包括互相分離的第一島 狀結構124a以及第二島狀結構124b。第一島狀結構124a與第一金屬氧化物半導體層122堆疊以構成其中一個厚部p1，且第二島狀結構124b與第一金屬氧化物半導體層122堆疊以構成其中另一個厚部p1。第一金屬氧化物半導體層122位於兩個厚部p1之間的區域可構成薄部p2。 Please refer to FIG. 5, the main difference between the semiconductor device 3 in FIG. 5 and the semiconductor device 1 in FIG. A metal oxide semiconductor layer 122 is located between the substrate 100 and the second metal oxide semiconductor layer 124 . The stack of the first metal oxide semiconductor layer 122 and the second metal oxide semiconductor layer 124 constitutes two thick portions p1 of the semiconductor structure 120 . For example, in this embodiment, the second metal oxide semiconductor layer 124 includes first islands separated from each other. The island-shaped structure 124a and the second island-shaped structure 124b. The first island structure 124 a is stacked with the first metal oxide semiconductor layer 122 to form one of the thick portions p1 , and the second island structure 124 b is stacked with the first metal oxide semiconductor layer 122 to form the other thick portion p1 . A region of the first metal oxide semiconductor layer 122 between two thick portions p1 may constitute a thin portion p2.

在本實施例中，第一金屬氧化物半導體層122的厚度t1小於第二金屬氧化物半導體層124的厚度t2。舉例來說，第一金屬氧化物半導體層122的厚度t1可以在2nm至60nm之間，第二金屬氧化物半導體層124的厚度t2可以在5nm至60nm之間。半導體結構120的兩個厚部p1的厚度T基本上為第一金屬氧化物半導體層122的厚度t1與第二金屬氧化物半導體層124的厚度t2的總和，半導體結構120的薄部p2的厚度T’基本上等於第一金屬氧化物半導體層122的厚度t1。 In this embodiment, the thickness t1 of the first metal oxide semiconductor layer 122 is smaller than the thickness t2 of the second metal oxide semiconductor layer 124 . For example, the thickness t1 of the first metal oxide semiconductor layer 122 may be between 2 nm and 60 nm, and the thickness t2 of the second metal oxide semiconductor layer 124 may be between 5 nm and 60 nm. The thickness T of the two thick portions p1 of the semiconductor structure 120 is basically the sum of the thickness t1 of the first metal oxide semiconductor layer 122 and the thickness t2 of the second metal oxide semiconductor layer 124, and the thickness T of the thin portion p2 of the semiconductor structure 120 T′ is substantially equal to the thickness t1 of the first metal oxide semiconductor layer 122 .

在一些實施例中，第一金屬氧化物半導體層122與第二金屬氧化物半導體層124可包括相同的金屬元素，但本發明不以此為限。在其他實施例中，第一金屬氧化物半導體層122與第二金屬氧化物半導體層124可包括不同的金屬元素。 In some embodiments, the first metal oxide semiconductor layer 122 and the second metal oxide semiconductor layer 124 may include the same metal element, but the invention is not limited thereto. In other embodiments, the first metal oxide semiconductor layer 122 and the second metal oxide semiconductor layer 124 may include different metal elements.

在一些實施例中，第一金屬氧化物半導體層122的氧濃度高於第二金屬氧化物半導體層124的氧濃度，第一金屬氧化物半導體層122的銦濃度低於第二金屬氧化物半導體層124的銦濃度，第一金屬氧化物半導體層122的氫濃度低於第二金屬氧化物半導體層124的氫濃度，因此，部分半導體結構120的兩個厚部 p1的電阻率隨著靠近基板100而增加，使在汲極164處之摻雜區dp靠近基板100的下部可以作為低摻雜汲極(Lightly Doped Drain，LDD)結構，進而可有效減小通道區ch(包含第一通道區ch1以及第二通道區ch2)與摻雜區dp之間因為橫向電場而產生的熱載子效應，以提升半導體裝置3的可靠度。 In some embodiments, the oxygen concentration of the first metal oxide semiconductor layer 122 is higher than the oxygen concentration of the second metal oxide semiconductor layer 124, and the indium concentration of the first metal oxide semiconductor layer 122 is lower than that of the second metal oxide semiconductor layer. The indium concentration of the layer 124, the hydrogen concentration of the first metal oxide semiconductor layer 122 is lower than the hydrogen concentration of the second metal oxide semiconductor layer 124, therefore, the two thick parts of the partial semiconductor structure 120 The resistivity of p1 increases as it gets closer to the substrate 100, so that the lower part of the doped region dp at the drain 164 close to the substrate 100 can be used as a lightly doped drain (Lightly Doped Drain, LDD) structure, which can effectively reduce the channel. The hot carrier effect generated between the region ch (including the first channel region ch1 and the second channel region ch2 ) and the doped region dp due to the lateral electric field improves the reliability of the semiconductor device 3 .

圖6是依照本發明圖5的實施例的一種製造流程的剖面示意圖。 FIG. 6 is a schematic cross-sectional view of a manufacturing process according to the embodiment of FIG. 5 of the present invention.

請參考圖6，提供基板100，形成半導體結構120’於基板100之上。舉例來說，可先形成緩衝層110於基板100上，之後形成半導體結構120’於緩衝層110上。半導體結構120’的形成方法例如可包括以下步驟。首先，形成第一金屬氧化物半導體層122’於緩衝層110及基板100之上。然後，形成第二金屬氧化物半導體層124’於第一金屬氧化物半導體層122’上，其中第二金屬氧化物半導體層124’具有第二開口O2，以暴露出部分第一金屬氧化物半導體層122’，並使第二金屬氧化物半導體層124’包括互相分離的第一島狀結構124a’以及第二島狀結構124b’。第一金屬氧化物半導體層122’的厚度t1小於第二金屬氧化物半導體層124’的厚度t2。如此一來，被第二開口O2暴露出的部分第一金屬氧化物半導體層122’可構成半導體結構120’的薄部p2，第二金屬氧化物半導體層124’與被其覆蓋的另一部分第一金屬氧化物半導體層122’可構成半導體結構120’的兩個厚部p1。 Referring to FIG. 6, a substrate 100 is provided, and a semiconductor structure 120' is formed on the substrate 100. Referring to FIG. For example, the buffer layer 110 can be formed on the substrate 100 first, and then the semiconductor structure 120' can be formed on the buffer layer 110. The method for forming the semiconductor structure 120' may include the following steps, for example. Firstly, the first metal oxide semiconductor layer 122' is formed on the buffer layer 110 and the substrate 100. Then, a second metal oxide semiconductor layer 124' is formed on the first metal oxide semiconductor layer 122', wherein the second metal oxide semiconductor layer 124' has a second opening O2 to expose part of the first metal oxide semiconductor layer. layer 122 ′, and the second metal oxide semiconductor layer 124 ′ includes a first island structure 124 a ′ and a second island structure 124 b ′ separated from each other. The thickness t1 of the first metal oxide semiconductor layer 122' is smaller than the thickness t2 of the second metal oxide semiconductor layer 124'. In this way, the part of the first metal oxide semiconductor layer 122 ′ exposed by the second opening O2 can constitute the thin portion p2 of the semiconductor structure 120 ′, and the second metal oxide semiconductor layer 124 ′ is covered by the second metal oxide semiconductor layer 124 ′. A metal oxide semiconductor layer 122' can constitute two thick portions p1 of the semiconductor structure 120'.

請參考圖5，半導體結構120’形成之後，可以接續類似於 上述圖2B至2C及圖1的製造流程，以完成半導體裝置3的製作。詳細流程可參考前述實施例，在此不贅述。 Please refer to FIG. 5, after the semiconductor structure 120' is formed, it may be followed by 2B to 2C and the manufacturing process of FIG. 1 are used to complete the fabrication of the semiconductor device 3 . For the detailed process, reference may be made to the aforementioned embodiments, and details are not repeated here.

圖7是依照本發明的另一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖7的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。 FIG. 7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. It must be noted here that the embodiment in FIG. 7 uses the component numbers and parts of the content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

請參考圖7，圖7的半導體裝置4與圖1的半導體裝置1的主要差異在於：半導體裝置4的閘介電層130位於閘極140與半導體結構120之間，但兩個厚部p1在基板100的頂面的法線方向ND上與閘極140不重疊之部分不被閘介電層130覆蓋。貫孔V1’、V2’分離於閘介電層130，且貫孔V1’、V2’分別在基板100的頂面的法線方向ND上重疊於兩個厚部p1。源極162以及汲極164位於層間介電層150上，且分別填入貫孔V1’、V2’以電性連接至半導體結構120。 Please refer to FIG. 7, the main difference between the semiconductor device 4 in FIG. 7 and the semiconductor device 1 in FIG. The portion of the top surface of the substrate 100 in the normal direction ND that does not overlap with the gate electrode 140 is not covered by the gate dielectric layer 130 . The vias V1', V2' are separated from the gate dielectric layer 130, and the vias V1', V2' overlap the two thick portions p1 in the normal direction ND of the top surface of the substrate 100, respectively. The source 162 and the drain 164 are located on the interlayer dielectric layer 150, and are respectively filled in the vias V1', V2' to be electrically connected to the semiconductor structure 120.

圖8A至圖8B是依照本發明圖7的實施例的一種製造流程的剖面示意圖。圖8A可為接續圖2B的步驟的半導體裝置的製造方法的剖視示意圖。關於圖2A至2B的步驟說明可參考前述實施例，在此不贅述。 8A to 8B are schematic cross-sectional views of a manufacturing process according to the embodiment of FIG. 7 of the present invention. FIG. 8A is a schematic cross-sectional view of a semiconductor device manufacturing method following the steps of FIG. 2B . For the description of the steps in FIGS. 2A to 2B , reference may be made to the foregoing embodiments, and details are not repeated here.

請參考圖8A，形成閘極140於閘介電層130上，閘極140的寬度w1大於薄部p2的寬度w2，閘極140在基板100的頂面的法線方向ND上可重疊於部分兩個厚部p1及薄部p2。 Please refer to FIG. 8A , the gate electrode 140 is formed on the gate dielectric layer 130, the width w1 of the gate electrode 140 is greater than the width w2 of the thin portion p2, and the gate electrode 140 can overlap partly in the normal direction ND of the top surface of the substrate 100. Two thick parts p1 and thin parts p2.

請繼續參考圖8A，調整半導體結構120的電阻率，以使至少部分兩個厚部p1的電阻率隨著靠近基板100而增加。在本實施例中，先移除部分閘介電層130，以暴露出未與閘極140在基板100的頂面的法線方向ND上重疊的部分兩個厚部p1。移除部分閘介電層130的方法例如以閘極140為遮罩對閘介電層130執行乾式蝕刻或濕式蝕刻，但本發明不以此為限。接著，進行退火製程P2，退火製程P2的退火溫度可在200℃至400℃之間。由於閘介電層130暴露出未與閘極140在基板100的頂面的法線方向ND上重疊的部分兩個厚部p1，兩個厚部p1中的氧可自厚部p1被暴露出來的表面擴散至外部，藉此於部分兩個厚部p1中形成氧空缺較高且電阻率較低的第一部分dp’以及氧空缺較低且電阻率較高的第二部分ch2’，其中第二部分ch2’被閘介電層130所覆蓋，且第一部分dp’被閘介電層130暴露出來。在本實施例中，由於越靠近厚部p1的表面的氧越容易逸散至外部，因此透過退火製程P2可使兩個厚部p1的第一部分dp’中的氧濃度隨著靠近基板100而增加，且兩個厚部p1的第一部分dp’的氧空缺的數量隨著靠近基板100而減少，進而使半導體結構120的兩個厚部p1的第一部分dp’的電阻率隨著靠近基板100而增加。 Please continue to refer to FIG. 8A , the resistivity of the semiconductor structure 120 is adjusted so that the resistivity of at least part of the two thick portions p1 increases as it gets closer to the substrate 100 . In this embodiment, part of the gate dielectric layer 130 is removed first to expose the two thick portions p1 that do not overlap with the gate 140 in the normal direction ND of the top surface of the substrate 100 . The method of removing part of the gate dielectric layer 130 is, for example, performing dry etching or wet etching on the gate dielectric layer 130 using the gate electrode 140 as a mask, but the invention is not limited thereto. Next, an annealing process P2 is performed, and the annealing temperature of the annealing process P2 may be between 200° C. and 400° C. Since the gate dielectric layer 130 exposes two thick portions p1 that do not overlap with the gate electrode 140 in the normal direction ND of the top surface of the substrate 100, oxygen in the two thick portions p1 can be exposed from the thick portion p1 The surface diffuses to the outside, thereby forming a first part dp' with higher oxygen vacancies and lower resistivity and a second part ch2' with lower oxygen vacancies and higher resistivity in the two thick parts p1, wherein the first part The second portion ch2 ′ is covered by the gate dielectric layer 130 , and the first portion dp′ is exposed by the gate dielectric layer 130 . In this embodiment, since the oxygen closer to the surface of the thick portion p1 is easier to escape to the outside, the annealing process P2 can make the oxygen concentration in the first portion dp′ of the two thick portions p1 decrease as it approaches the substrate 100 increases, and the number of oxygen vacancies in the first part dp' of the two thick parts p1 decreases as it gets closer to the substrate 100 , so that the resistivity of the first part dp' of the two thick parts p1 of the semiconductor structure 120 increases as it gets closer to the substrate 100 And increase.

請參考圖8B，在進行退火製程P2之後，以閘極140為遮罩對厚部p1的第一部分dp’進行摻雜製程P1，以於厚部p1中形成摻雜區dp以及第二通道區ch2，其中摻雜區dp對應第一部分dp’且第二通道區ch2對應第二部分ch2’，但本發明不以此為限。 在其他實施例中，在進行退火製程P2之後，可以不進行摻雜製程P1。 Please refer to FIG. 8B , after the annealing process P2, the doping process P1 is performed on the first part dp' of the thick portion p1 with the gate 140 as a mask, so as to form the doped region dp and the second channel region in the thick portion p1 ch2, wherein the doped region dp corresponds to the first part dp' and the second channel region ch2 corresponds to the second part ch2', but the present invention is not limited thereto. In other embodiments, after the annealing process P2 is performed, the doping process P1 may not be performed.

請參考圖7，形成層間介電層150於緩衝層110之上，並覆蓋閘極140與半導體結構120。之後，形成貫穿層間介電層150的貫孔V1’、V2’，且貫孔V1’、V2’分別重疊於兩個厚部p1。然後，形成源極162以及汲極164於層間介電層150之上，並填入貫孔V1’、V2’中，以與半導體結構120的摻雜區dp電性連接。 Referring to FIG. 7 , an interlayer dielectric layer 150 is formed on the buffer layer 110 and covers the gate 140 and the semiconductor structure 120 . Afterwards, through-holes V1', V2' are formed through the interlayer dielectric layer 150, and the through-holes V1', V2' respectively overlap the two thick portions p1. Then, the source electrode 162 and the drain electrode 164 are formed on the interlayer dielectric layer 150, and filled into the through holes V1', V2', so as to be electrically connected with the doped region dp of the semiconductor structure 120.

雖然在本實施例中，半導體結構120是以單層結構為例，但本發明不以此為限。在其他實施例中，半導體結構120也可以是如圖4或圖6所繪示的半導體結構120。 Although in this embodiment, the semiconductor structure 120 is an example of a single-layer structure, the present invention is not limited thereto. In other embodiments, the semiconductor structure 120 may also be the semiconductor structure 120 as shown in FIG. 4 or FIG. 6 .

經過上述製程後可大致上完成半導體裝置4的製作。 After the above process, the fabrication of the semiconductor device 4 can be substantially completed.

1:半導體裝置 1: Semiconductor device

100:基板 100: Substrate

110:緩衝層 110: buffer layer

120:半導體結構 120:Semiconductor Structures

130:閘介電層 130: gate dielectric layer

140:閘極 140: Gate

150:層間介電層 150: interlayer dielectric layer

162:源極 162: source

164:汲極 164: drain

ch:通道區 ch: channel area

ch1:第一通道區 ch1: the first channel area

ch2:第二通道區 ch2: the second channel area

dp:摻雜區 dp: doped area

p1:厚部 p1: thick part

p2:薄部 p2: thin part

S1:頂面 S1: top surface

S2:底面 S2: bottom surface

T,T’:厚度 T, T': Thickness

w1,w2:寬度 w1, w2: width

ND:方向 ND: Direction

V1,V2:貫孔 V1, V2: through hole

Claims (17)

一種半導體裝置，包括： 一基板； 一半導體結構，設置於該基板之上，該半導體結構包括兩個厚部以及位於該兩個厚部之間的一薄部，其中該兩個厚部的厚度大於該薄部的厚度； 一閘介電層，設置於該半導體結構上；以及 一閘極，設置於該閘介電層上，其中該閘極的寬度大於該薄部的寬度，且該閘極在該基板的一頂面的一法線方向上重疊於部分該兩個厚部及該薄部， 其中至少部分該兩個厚部的電阻率隨著靠近該基板而增加。 A semiconductor device comprising: a substrate; A semiconductor structure disposed on the substrate, the semiconductor structure comprising two thick parts and a thin part located between the two thick parts, wherein the thickness of the two thick parts is greater than the thickness of the thin part; a gate dielectric layer disposed on the semiconductor structure; and a gate disposed on the gate dielectric layer, wherein the width of the gate is greater than the width of the thin portion, and the gate overlaps part of the two thick portions in a direction normal to a top surface of the substrate part and the thin part, Wherein the resistivity of at least part of the two thick portions increases with approaching the substrate. 如請求項1所述的半導體裝置，其中該半導體結構包括一第一金屬氧化物半導體層及一第二金屬氧化物半導體層，其中該第一金屬氧化物半導體層位於該基板與該第二金屬氧化物半導體層之間，且該第一金屬氧化物半導體層及該第二金屬氧化物半導體層的堆疊構成該兩個厚部。The semiconductor device according to claim 1, wherein the semiconductor structure includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, wherein the first metal oxide semiconductor layer is located between the substrate and the second metal oxide semiconductor layer. Between the oxide semiconductor layers, the stack of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer constitutes the two thick portions. 如請求項2所述的半導體裝置，其中該第二金屬氧化物半導體層包括互相分離的一第一島狀結構以及一第二島狀結構，其中該第一島狀結構與該第一金屬氧化物半導體層堆疊以構成其中一個厚部，且該第二島狀結構與該第一金屬氧化物半導體層堆疊以構成其中另一個厚部。The semiconductor device according to claim 2, wherein the second metal oxide semiconductor layer includes a first island structure and a second island structure separated from each other, wherein the first island structure and the first metal oxide The material semiconductor layer is stacked to form one of the thick portions, and the second island structure is stacked with the first metal oxide semiconductor layer to form the other thick portion. 如請求項3所述的半導體裝置，其中該薄部包括該第一金屬氧化物半導體層位於該兩個厚部之間的區域，該第一金屬氧化物半導體層的厚度小於該第二金屬氧化物半導體層的厚度。The semiconductor device according to claim 3, wherein the thin portion includes a region where the first metal oxide semiconductor layer is located between the two thick portions, and the thickness of the first metal oxide semiconductor layer is smaller than that of the second metal oxide semiconductor layer. the thickness of the semiconductor layer. 如請求項2所述的半導體裝置，其中該第一金屬氧化物半導體層包括互相分離的一第一島狀結構以及一第二島狀結構，其中該第一島狀結構與該第二金屬氧化物半導體層堆疊以構成其中一個厚部，且該第二島狀結構與該第二金屬氧化物半導體層堆疊以構成其中另一個厚部。The semiconductor device according to claim 2, wherein the first metal oxide semiconductor layer includes a first island structure and a second island structure separated from each other, wherein the first island structure and the second metal oxide The material semiconductor layer is stacked to form one of the thick portions, and the second island structure is stacked with the second metal oxide semiconductor layer to form the other thick portion. 如請求項5所述的半導體裝置，其中該薄部包括該第二金屬氧化物半導體層位於該兩個厚部之間的區域，該第一金屬氧化物半導體層的厚度大於該第二金屬氧化物半導體層的厚度。The semiconductor device according to claim 5, wherein the thin portion includes a region where the second metal oxide semiconductor layer is located between the two thick portions, and the thickness of the first metal oxide semiconductor layer is greater than that of the second metal oxide semiconductor layer. the thickness of the semiconductor layer. 如請求項2所述的半導體裝置，其中該第一金屬氧化物半導體層與該第二金屬氧化物半導體層包括相同的金屬元素。The semiconductor device as claimed in claim 2, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer comprise the same metal element. 如請求項2所述的半導體裝置，其中該第一金屬氧化物半導體層與該第二金屬氧化物半導體層包括不同的金屬元素。The semiconductor device as claimed in claim 2, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer comprise different metal elements. 如請求項1所述的半導體裝置，其中該兩個厚部的厚度在7 nm至120 nm之間，該薄部的厚度在2 nm至60 nm之間。The semiconductor device according to claim 1, wherein the thickness of the two thick parts is between 7 nm and 120 nm, and the thickness of the thin part is between 2 nm and 60 nm. 如請求項2所述的半導體裝置，其中該第一金屬氧化物半導體層的氧濃度高於該第二金屬氧化物半導體層的氧濃度，且該第一金屬氧化物半導體層的銦濃度低於該第二金屬氧化物半導體層的銦濃度。The semiconductor device according to claim 2, wherein the oxygen concentration of the first metal oxide semiconductor layer is higher than the oxygen concentration of the second metal oxide semiconductor layer, and the indium concentration of the first metal oxide semiconductor layer is lower than Indium concentration of the second metal oxide semiconductor layer. 如請求項1所述的半導體裝置，其中該兩個厚部靠近該薄部的部分的氫濃度低於該兩個厚部遠離該薄部的部分的氫濃度。The semiconductor device according to claim 1, wherein a hydrogen concentration of a portion of the two thick portions close to the thin portion is lower than a hydrogen concentration of a portion of the two thick portions away from the thin portion. 一種半導體裝置的製造方法，包括： 提供一基板； 形成一半導體結構於該基板之上，其中該半導體結構包括兩個厚部以及位於該兩個厚部之間的一薄部，該兩個厚部的厚度大於該薄部的厚度； 形成一閘介電層於該半導體結構上； 形成一閘極於該閘介電層上，其中該閘極的寬度大於該薄部的寬度，該閘極在該基板的頂面的法線方向上重疊於部分該兩個厚部及該薄部；以及 調整該半導體結構的電阻率，以使至少部分該兩個厚部的電阻率隨著靠近該基板而增加。 A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor structure on the substrate, wherein the semiconductor structure includes two thick parts and a thin part between the two thick parts, the thickness of the two thick parts is greater than the thickness of the thin part; forming a gate dielectric layer on the semiconductor structure; forming a gate electrode on the gate dielectric layer, wherein the width of the gate electrode is larger than the width of the thin portion, and the gate electrode overlaps part of the two thick portions and the thin portion in the normal direction of the top surface of the substrate. Department; and The resistivity of the semiconductor structure is adjusted so that the resistivity of at least part of the two thick portions increases as the substrate approaches the substrate. 如請求項12所述的半導體裝置的製造方法，其中調整該半導體結構的電阻率的步驟包括： 以該閘極為遮罩，對未與該閘極在該基板的頂面的法線方向上重疊的部分該兩個厚部進行摻雜製程。 The method for manufacturing a semiconductor device as claimed in claim 12, wherein the step of adjusting the resistivity of the semiconductor structure comprises: With the gate electrode masked, a doping process is performed on the two thick portions that do not overlap with the gate electrode in the normal direction of the top surface of the substrate. 如請求項12所述的半導體裝置的製造方法，其中調整該半導體結構的電阻率的步驟包括： 移除部分該閘介電層，以暴露出未與該閘極在該基板的頂面的法線方向上重疊的該兩個厚部的兩個第一部分；以及 進行退火製程，使該兩個第一部分中的氧自該兩個厚部的表面擴散至外部，以使該兩個第一部分的氧濃度隨著靠近該基板而增加。 The method for manufacturing a semiconductor device as claimed in claim 12, wherein the step of adjusting the resistivity of the semiconductor structure comprises: removing a portion of the gate dielectric layer to expose two first portions of the two thick portions that do not overlap with the gate electrode in a direction normal to the top surface of the substrate; and An annealing process is performed to diffuse the oxygen in the two first portions from the surface of the two thick portions to the outside, so that the oxygen concentration of the two first portions increases as they get closer to the substrate. 如請求項14所述的半導體裝置的製造方法，其中該退火製程的退火溫度在200℃至400℃之間。The method for manufacturing a semiconductor device as claimed in claim 14, wherein the annealing temperature of the annealing process is between 200°C and 400°C. 如請求項12所述的半導體裝置的製造方法，其中形成該半導體結構於該基板之上的步驟包括： 形成一第一金屬氧化物半導體層於該基板之上，其中該第一金屬氧化物半導體層具有一第一開口；以及 形成一第二金屬氧化物半導體層於該第一金屬氧化物半導體層上，並填入該第一開口中，其中該第一金屬氧化物半導體層的厚度大於該第二金屬氧化物半導體層的厚度， 其中位於該第一開口中的部分該第二金屬氧化物半導體層構成該薄部，該第一金屬氧化物半導體層與覆蓋於其上的另一部分該第二金屬氧化物半導體層構成該兩個厚部。 The method for manufacturing a semiconductor device as claimed in claim 12, wherein the step of forming the semiconductor structure on the substrate comprises: forming a first metal oxide semiconductor layer on the substrate, wherein the first metal oxide semiconductor layer has a first opening; and forming a second metal oxide semiconductor layer on the first metal oxide semiconductor layer and filling in the first opening, wherein the thickness of the first metal oxide semiconductor layer is greater than that of the second metal oxide semiconductor layer thickness, The part of the second metal oxide semiconductor layer located in the first opening constitutes the thin part, and the first metal oxide semiconductor layer and another part of the second metal oxide semiconductor layer covering it constitute the two parts. Thick part. 如請求項12所述的半導體裝置的製造方法，其中形成該半導體結構於該基板之上的步驟包括： 形成一第一金屬氧化物半導體層於該基板之上；以及 形成一第二金屬氧化物半導體層於該第一金屬氧化物半導體層上，其中該第二金屬氧化物半導體層具有一第二開口，以暴露出部分該第一金屬氧化物半導體層， 其中該第一金屬氧化物半導體層的厚度小於該第二金屬氧化物半導體層的厚度， 其中被該第二開口暴露出的部分該第一金屬氧化物半導體層構成該薄部，該第二金屬氧化物半導體層與被其覆蓋的另一部分該第一金屬氧化物半導體層構成該兩個厚部。 The method for manufacturing a semiconductor device as claimed in claim 12, wherein the step of forming the semiconductor structure on the substrate comprises: forming a first metal oxide semiconductor layer on the substrate; and forming a second metal oxide semiconductor layer on the first metal oxide semiconductor layer, wherein the second metal oxide semiconductor layer has a second opening to expose part of the first metal oxide semiconductor layer, wherein the thickness of the first metal oxide semiconductor layer is smaller than the thickness of the second metal oxide semiconductor layer, The part of the first metal oxide semiconductor layer exposed by the second opening constitutes the thin portion, and the second metal oxide semiconductor layer and the other part of the first metal oxide semiconductor layer covered by it constitute the two parts. Thick part.
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