TW202329434A - Photosensitive device substrate and manufacturing method thereof - Google Patents

Abstract

A photosensitive device substrate includes a substrate, a photosensitive device, a sensor device, a passivation layer and a light emitting diode. The photosensitive device and the sensor device are located above the substrate. The photosensitive device includes a photosensitive layer, a first gate, a first source and a first drain. The photosensitive layer includes a first metal oxide layer and a second metal oxide layer stacked on each other. The first gate overlaps with the photosensitive layer. The first source and the first drain are electrically connected to the photosensitive layer. The sensor device is electrically connected to the photosensitive device. The passivation layer covers the photosensitive device and the sensor device. The light emitting diode includes a first electrode, a light emitting layer, and a second electrode stacked on each other. The second electrode has an opening overlapping the photosensitive device.

Description

Photosensitive element substrate and manufacturing method thereof

The invention relates to a photosensitive element substrate and a manufacturing method thereof.

With the development of science and technology, the appearance rate of touch devices in the market is gradually increasing, and various related technologies are emerging in an endless stream. In some electronic devices, such as mobile phones, tablet computers, smart watches, etc., touch devices are often combined with display panels to improve the convenience of using the electronic devices.

Currently, photodiodes are often used in touch devices. The photodiode will generate a current after absorbing light. Since the finger or stylus on the touch device will block the light and reduce the photocurrent generated by the photodiode, it can be judged by detecting the current that the finger or touch The position of the pen. Common photodiodes include, for example, PN photodiodes and PIN photodiodes. Generally speaking, a PN-type photodiode includes a stack of P-type semiconductors and N-type semiconductors. PIN-type photodiodes include I-type semiconductors (essential semiconductor layers) in addition to P-type semiconductors and N-type semiconductors.

At least one embodiment of the present invention provides a photosensitive element substrate. The photosensitive element substrate includes a substrate, a photosensitive element, a sensing element, a passivation layer, and a light emitting diode. The photosensitive element and the sensing element are located on the substrate. The photosensitive element includes a photosensitive layer, a first gate, a first source and a first drain. The photosensitive layer includes a first metal oxide layer and a second metal oxide layer stacked on each other. The first gate overlaps the photosensitive layer. The second metal oxide layer is located between the first gate and the first metal oxide layer. The first source and the first drain are electrically connected to the photosensitive layer. The sensing element is electrically connected to the photosensitive element. The sensing element includes a third metal oxide layer, a second gate, a second source and a second drain. The second gate overlaps the third metal oxide layer. The second source and the second drain are electrically connected to the third metal oxide layer. The passivation layer covers the photosensitive element and the sensing element. The light emitting diode includes a first electrode, a light emitting layer and a second electrode stacked on each other. The second electrode is located on the passivation layer, and the second electrode has an opening overlapping the photosensitive element.

At least one embodiment of the present invention provides a method for manufacturing a photosensitive element substrate, comprising: forming a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer on the substrate, wherein the photosensitive layers include layers stacked on each other the first metal oxide layer and the second metal oxide layer; forming a gate dielectric layer on the second metal oxide layer and the third metal layer; forming a first gate electrode and a second gate electrode on the gate dielectric layer , wherein the first gate and the second gate respectively overlap the photosensitive layer and the third metal oxide layer, and the second metal oxide layer is located between the first gate and the first metal oxide layer; forming an electrical connection to the first source electrode and the first drain electrode of the photosensitive layer; form the second source electrode and the second drain electrode electrically connected to the third metal oxide layer; form a light emitting diode and a passivation layer, wherein the passivation layer is located at the first On a source, a first drain, a second source and a second drain, the light-emitting diode includes a first electrode, a light-emitting layer and a second electrode stacked on each other, wherein the second electrode is located on the passivation layer, and The second electrode has an opening overlapping the photosensitive layer.

FIG. 1 is a schematic cross-sectional view of a photosensitive element substrate according to an embodiment of the present invention.

Please refer to FIG. 1 , the photosensitive element substrate 10A includes a substrate 100 , a photosensitive element T _ph , a sensing element T _se , a passivation layer 140 and a light emitting diode EL. In this embodiment, the photosensitive element substrate 10A further includes a first gate dielectric layer 110 , a second gate dielectric layer 120 , an interlayer dielectric layer 130 and a driving element T _dr .

The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials .

The photosensitive element T _ph , the sensing element T _se and the driving element T _dr are located on the substrate 100 . The photosensitive element T _ph includes a first bottom gate BG1, a photosensitive layer SL, a first gate TG1, a first source S1, and a first drain D1, wherein the photosensitive layer SL includes a stacked first metal oxide layer 210 and The second metal oxide layer 212 . The sensing element T _se includes a second bottom gate BG2 , a third metal oxide layer 214 , a second gate TG2 , a second source S2 and a second drain D2 . The driving element T _dr includes a third bottom gate BG3 , a fourth metal oxide layer 216 , a third gate TG3 , a third source S3 and a third drain D3 .

The first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 are located on the substrate 100 . In some embodiments, the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 include reflective materials, such as metal. In some embodiments, one or more buffer layers are further included between the first bottom gate BG1 and the substrate 100, between the second bottom gate BG2 and the substrate 100, and between the third bottom gate BG3 and the substrate 100, but The present invention is not limited thereto.

The first gate dielectric layer 110 covers the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 . In some embodiments, the material of the first gate dielectric layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other suitable materials.

The first metal oxide layer 210 is located on the first gate dielectric layer 110 and overlaps the first bottom gate BG1 in the normal direction ND of the top surface of the substrate 100 . In some embodiments, the material of the first metal oxide layer 210 includes quaternary elements such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), etc. A metal compound or an oxide composed of a ternary metal including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W). In some embodiments, the thickness t1 of the first metal oxide layer 210 is 10 nm to 30 nm.

The second metal oxide layer 212 is located on the first metal oxide layer 210 . The third metal oxide layer 214 and the fourth metal oxide layer 216 are located on the first gate dielectric layer 110 . In some embodiments, the materials of the second metal oxide layer 212, the third metal oxide layer 214, and the fourth metal oxide layer 216 include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum oxide Zinc tin (AZTO), indium tungsten zinc oxide (IWZO) and other quaternary metal compounds or containing gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), tungsten (W) An oxide composed of any of the three ternary metals. In some embodiments, the thickness t2 of the second metal oxide layer 212 , the third metal oxide layer 214 and the fourth metal oxide layer 216 is 5 nm to 50 nm.

The second metal oxide layer 212 includes a source region sr1 , a drain region dr1 and a channel region ch1 between the source region sr1 and the drain region dr1 . The third metal oxide layer 214 includes a source region sr2 , a drain region dr2 and a channel region ch2 between the source region sr2 and the drain region dr2 . The fourth metal oxide layer 216 includes a source region sr3 , a drain region dr3 and a channel region ch3 between the source region sr3 and the drain region dr3 . In some embodiments, the source regions sr1 - sr3 and the drain regions dr1 - dr3 are doped to have lower resistivity than the channel regions ch1 - ch3 .

The oxygen concentration of the first metal oxide layer 210 is smaller than the oxygen concentration of the channel region ch1 of the second metal oxide layer 212 . In some embodiments, the oxygen concentration of the first metal oxide layer 210 is 10 at% to 50 at%, and the oxygen concentration of the channel region ch1 of the second metal oxide layer 212 is 30 at% to 70 at%. In some embodiments, the energy gap of the first metal oxide layer 210 is smaller than the energy gap of the second metal oxide layer 212 by adjusting the oxygen concentration. By adjusting the energy gap of the first metal oxide layer 210 and/or the second metal oxide layer 212, the photosensitive layer SL can absorb light (such as visible light (such as red light, green light and blue light), infrared light, Ultraviolet light or other suitable wavelength light) changes the current through the photosensitive element T _ph . In other words, in some embodiments, by adjusting the oxygen concentration of the metal oxide layer to change its energy gap, the photosensitive element T _ph can sense light.

In other embodiments, the first metal oxide layer 210 is made of low energy gap materials, such as indium tin oxide, indium zinc oxide, tin oxide or other suitable metal oxides. In other words, in other embodiments, by adjusting the composition of the metal oxide layer to change its energy gap, the photosensitive element T _ph can sense light.

The second gate dielectric layer 120 covers the photosensitive layer SL, the third metal oxide layer 214 and the fourth metal oxide layer 216 . In some embodiments, the material of the second gate dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other suitable materials.

The first gate TG1 , the second gate TG2 and the third gate TG3 are located on the second gate dielectric layer 120 . The first gate TG1 , the second gate TG2 and the third gate TG3 overlap the photosensitive layer SL, the third metal oxide layer 214 and the fourth metal oxide layer 216 respectively. The photosensitive layer SL is located between the first bottom gate BG1 and the first gate TG1 . The second metal oxide layer 212 is located between the first gate TG1 and the first metal oxide layer 210 . The third metal oxide layer 214 is located between the second bottom gate BG2 and the second gate TG2 . The fourth metal oxide layer 216 is located between the third bottom gate BG3 and the third gate TG3 . In some embodiments, the materials of the first gate TG1 , the second gate TG2 and the third gate TG3 may include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), Tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or An alloy of any combination of the above metals or a laminate of the above metals and/or alloys, but the present invention is not limited thereto. The first gate TG1, the second gate TG2 and the third gate TG3 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials or other conductive materials.

The interlayer dielectric layer 130 is disposed on the gate dielectric layer 120 . The interlayer dielectric layer 130 covers the first gate TG1 , the second gate TG2 and the third gate TG3 . In some embodiments, the material of the interlayer dielectric layer 130 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials.

The first source S1 , the first drain D1 , the second source S2 , the second drain D2 , the third source S3 and the third drain D3 are located on the interlayer dielectric layer 130 . The first source S1 and the first drain D1 are electrically connected to the source region sr1 and the drain region dr1 of the photosensitive layer SL. The second source S2 and the second drain D2 are electrically connected to the source region sr2 and the drain region dr2 of the third metal oxide layer 214 . The third source S3 and the third drain D3 are electrically connected to the source region sr3 and the drain region dr3 of the fourth metal oxide layer 216 . In some embodiments, the materials of the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3, and the third drain D3 may include metals such as chromium, Gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc or an alloy of any combination of the above metals or a laminate of the above metals and/or alloys, but the present invention does not limit. The first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 can also use other conductive materials, such as: metal nitride, metal Oxides of metals, oxynitrides of metals, stacked layers of metals and other conductive materials, or other materials with conductive properties.

The second drain D2 of the sensing element T _se is electrically connected to the first source S1 of the photosensitive element T _ph . In some embodiments, the second drain D2 is integrated with the first source S1.

The passivation layer 140 covers the photosensitive element T _ph , the sensing element T _se and the driving element T _dr . In some embodiments, the material of the passivation layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, organic insulating materials or other insulating materials. In this embodiment, the passivation layer 140 has an opening O overlapping the third source S3.

The light emitting diode EL includes a first electrode E1, a light emitting layer EM, and a second electrode E2 stacked on each other. The first electrode E1 is located at the bottom of the opening O of the passivation layer 140 and is electrically connected to the third source S3 of the driving element T _dr . In some embodiments, the material of the first electrode E1 includes indium tin oxide (ITO), indium zinc oxide (IZO) or other suitable materials. In some embodiments, the first electrode E1 and the third source S3 include different materials, but the invention is not limited thereto. In other embodiments, the first electrode E1 and the third source S3 are substantially the same conductive structure. The light emitting layer EM is located in the opening O of the passivation layer 140 and is located on the first electrode E1. In some embodiments, the light emitting layer EM includes an organic light emitting material. The second electrode E2 is located on the passivation layer 140 , and the second electrode E2 has an opening OP overlapping the photosensitive layer SL of the photosensitive element T _ph . In some embodiments, the second electrode E2 includes thin metal or other suitable transparent conductive materials.

Based on the above, the photosensitive element T _ph includes the first metal oxide layer 210 and the second metal oxide layer 212 stacked on each other, so the photosensitive element substrate can be made without setting a PN type photodiode or a PIN type photodiode. It has the function of sensing light. In addition, the first bottom gate BG1 of the photosensitive element T _ph is located between the photosensitive layer SL and the substrate 100 , so that the first bottom gate BG1 can be used to reflect light to increase the light received by the photosensitive layer SL. The second electrode E2 of the light-emitting diode EL has an opening OP overlapping the photosensitive element T _ph , which can prevent the second electrode E2 from affecting the light-receiving ability of the photosensitive element T _ph . In addition, in some embodiments, the sensing of the light and the driving of the light-emitting diodes may have scanning timings of different periods, and the signal of the driving element T _dr and the signal of the photosensitive element T _ph will not be affected by each other.

2A to 2G are schematic cross-sectional views of the manufacturing method of the photosensitive element substrate 10A of FIG. 1 .

Referring to FIG. 2A , a first bottom gate BG1 , a second bottom gate BG2 and a third bottom gate BG3 are formed on the substrate 100 . In some embodiments, the method of forming the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 includes a lithographic etching process. In some embodiments, the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 belong to the same patterned film layer, and the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG1 The bottom gate BG3 has the same material and the same thickness. Next, a first gate dielectric layer 110 is formed on the first bottom gate BG1 , the second bottom gate BG2 and the third bottom gate BG3 .

Referring to FIG. 2B and FIG. 2C , a first metal oxide layer 210 , a second metal oxide layer 212 , a third metal oxide layer 214 and a fourth metal oxide layer 216 are formed on the substrate 100 .

First, as shown in FIG. 2B , a first metal oxide layer 210 is formed on the first gate dielectric layer 110 . The method for forming the first metal oxide layer 210 includes the following steps: firstly, forming a blanket semiconductor material layer (not shown) on the first gate dielectric layer 110; forming a patterned photoresist (not shown); then, using the patterned photoresist as a mask to perform a wet or dry etching process on the semiconductor material layer to form the first metal oxide layer 210; after that, removing patterned photoresist.

Then, as shown in FIG. 2C, a second metal oxide layer 212', a third metal oxide layer 214' and a fourth metal oxide layer 216' are formed on the first metal oxide layer 210 and the first gate dielectric layer. 110 on. The method for forming the second metal oxide layer 212', the third metal oxide layer 214' and the fourth metal oxide layer 216' includes the following steps: first, the first metal oxide layer 210 and the first gate dielectric layer A blanket semiconductor material layer (not shown) is formed on 110; then, a patterned photoresist (not shown) is formed on the semiconductor material layer by using a lithography process; and then, the patterned photoresist is used as a mask, To perform a wet or dry etching process on the semiconductor material layer to form the second metal oxide layer 212', the third metal oxide layer 214' and the fourth metal oxide layer 216'; after that, remove the patterned photoresist . The second metal oxide layer 212', the third metal oxide layer 214' and the fourth metal oxide layer 216' belong to the same patterned film layer. The photosensitive layer SL' includes a first metal oxide layer 210 and a second metal oxide layer 212' stacked on each other.

Referring to FIG. 2D, the second gate dielectric layer 120 is formed on the second metal oxide layer 212', the third metal oxide layer 214' and the fourth metal oxide layer 216'. A first gate TG1 , a second gate TG2 and a third gate TG3 are formed on the second gate dielectric layer 120 . In some embodiments, the method for forming the first gate TG1 , the second gate TG2 and the third gate TG3 includes a photolithographic etching process. In some embodiments, the first gate TG1, the second gate TG2 and the third gate TG3 belong to the same patterned film layer, and the first gate TG1, the second gate TG2 and the third gate TG3 have the same The material with the same thickness.

The first gate TG1, the second gate TG2 and the third gate TG3 overlap the photosensitive layer SL', the third metal oxide layer 214' and the fourth metal oxide layer 214' respectively in the normal direction ND of the top surface of the substrate 100. The material layer 216 ′, and the second metal oxide layer 212 ′ is located between the first gate TG1 and the first metal oxide layer 210 .

Using the first gate TG1, the second gate TG2 and the third gate TG3 as masks, the doping process P is performed on the photosensitive layer SL', the third metal oxide layer 214' and the fourth metal oxide layer 216' , to form the second metal oxide layer 212 including the source region sr1, the drain region dr1 and the channel region ch1, the third metal oxide layer 214 including the source region sr2, the drain region dr2 and the channel region ch2, and the third metal oxide layer including The fourth metal oxide layer 216 of the source region sr3 , the drain region dr3 and the channel region ch3 . In this embodiment, in the normal direction ND of the top surface of the substrate 100, the channel region ch1, the channel region ch2 and the channel region ch3 overlap the first gate TG1, the second gate TG2 and the third gate TG3 respectively. . The resistivity of the source regions sr1 - sr3 and the drain regions dr1 - dr3 is reduced through the doping process P. In some embodiments, the doping process P is, for example, a hydrogen plasma process or other suitable processes.

Referring to FIG. 2E , an interlayer dielectric layer 130 is formed on the second gate dielectric layer 120 . The interlayer dielectric layer 130 covers the first gate TG1 , the second gate TG2 and the third gate TG3 .

2F, perform one or more etching processes to form the first contact hole V1, the second contact hole V2, the third contact hole V3, the fourth The contact hole V4, the fifth contact hole V5 and the sixth contact hole V6. The first contact hole V1 and the second contact hole V2 overlap and expose the drain region dr1 and the source region sr1 of the second metal oxide layer 212 . The third contact hole V3 and the fourth contact hole V4 overlap and expose the drain region dr2 and the source region sr3 of the third metal oxide layer 214 . The fifth contact hole V5 and the sixth contact hole V6 overlap and expose the drain region dr3 and the source region sr3 of the fourth metal oxide layer 216 .

Referring to FIG. 2G , a first source S1 , a first drain D1 , a second source S2 , a second drain D2 , a third source S3 and a third drain D3 are formed on the interlayer dielectric layer 130 . The first drain D1 and the first source S1 are located in the first contact hole V1 and the second contact hole V2 respectively. The second drain D2 and the second source S2 are located in the third contact hole V3 and the fourth contact hole V4 respectively. The third drain D3 and the third source S3 are located in the fifth contact hole V5 and the sixth contact hole V6 respectively.

The first source S1 and the first drain D1 are electrically connected to the source region sr1 and the drain region dr1 of the photosensitive layer SL. The second source S2 and the second drain D2 are electrically connected to the source region sr2 and the drain region dr2 of the third metal oxide layer 214 . The third source S3 and the third drain D3 are electrically connected to the source region sr3 and the drain region dr3 of the fourth metal oxide layer 216 .

Finally, please return to FIG. 1 to form a light emitting diode EL and a passivation layer 140, wherein the passivation layer 140 is located at the first source S1, the first drain D1, the second source S2, the second drain D2, the third above the source S3 and the third drain D3. The light emitting diode EL includes a first electrode E1, a light emitting layer EM and a second electrode E2 stacked on each other. The second electrode E2 is located on the passivation layer 140, and the second electrode E2 has an opening OP overlapping the photosensitive element T _ph .

So far, the photosensitive element substrate 10A is roughly completed.

FIG. 3 is a schematic cross-sectional view of a photosensitive element substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 3 uses the component numbers and parts of the content in the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the photosensitive element substrate 10B of FIG. 3 and the photosensitive element substrate 10A of FIG. 1 is that: the photosensitive element substrate 10B further includes a plurality of metal nanoparticles NP.

Referring to FIG. 3 , metal nanoparticles NP are located on the first metal oxide layer 210 . For example, metal nanoparticles NP are located between the first metal oxide layer 210 and the substrate 100 . Metal nanoparticles NPs include, for example, gold or other suitable materials. In some embodiments, the particle size of the metal nanoparticles NP is 10 nm to 60 nm.

Based on the above, the back channel effect of the T _ph of the photosensitive element can be improved by the arrangement of the metal nanoparticles NP, thereby increasing the photosensitivity of the T _ph of the photosensitive element.

FIG. 4 is a schematic cross-sectional view of a photosensitive element substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 4 follows the component numbers and partial content of the embodiment in FIG. 3 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the photosensitive element substrate 10C of FIG. 4 and the photosensitive element substrate 10B of FIG. 3 is that the metal nanoparticles NP of the photosensitive element substrate 10C are located between the first metal oxide layer 210 and the second metal oxide layer 212 .

Based on the above, the back channel effect of the T _ph of the photosensitive element can be improved by the arrangement of the metal nanoparticles NP, thereby increasing the photosensitivity of the T _ph of the photosensitive element.

FIG. 5 is a schematic diagram of an equivalent circuit of a photosensitive element substrate according to an embodiment of the present invention. FIG. 5 is, for example, a schematic diagram of an equivalent circuit of the photosensitive element substrates 10A˜10C in any of the aforementioned embodiments.

Please refer to FIG. 5 , the photosensitive element substrate includes a switching element T _sw , a storage capacitor Cst, a driving element T _dr , a light emitting element EL, a photosensitive element T _ph and a sensing element T _se .

The gate of the switching element T _sw is electrically connected to the voltage V _S1 (such as the scan line voltage), the drain of the switching element T _sw is electrically connected to the voltage V _data (such as the data line voltage), and the source of the switching element T _sw is The pole is electrically connected to the first node a. The voltage V _S1 is used to control the switching of the switching element T _sw . In some embodiments, the switching element T _sw is a double-gate thin film transistor, and both gates of the switching element T _sw are electrically connected to the voltage V _S1 .

One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the second node b.

The gate of the driving element T _dr (such as the third gate TG3 in FIGS. 1 to 4 ) is electrically connected to the first node a, and the drain of the driving element T _dr (such as the third drain in FIGS. 1 to 4 The terminal D3) is electrically connected to the third node c and the voltage V _DD , and the source of the driving element T _dr (such as the third source S3 in FIGS. 1 to 4 ) is electrically connected to the second node b. Since the gate of the driving element T _dr is electrically connected to the storage capacitor Cst, even if the switching element T _sw is turned off, the driving element T _dr can still be turned on for a short period of time. In some embodiments, the driving element T _dr is a double-gate thin film transistor, and one of the gates of the driving element T _dr (for example, the third bottom gate BG3 in FIGS. 1 to 4 ) is electrically connected to the driving The source of the element T _dr (for example, the third source S3 in FIGS. 1 to 4 ).

The first electrode of the light emitting element EL (such as the first electrode E1 in FIGS. 1 to 4 ) is electrically connected to the second node b, and the second electrode of the light emitting element EL (such as the second electrode E2 in FIGS. 1 to 4 ) is electrically connected to the voltage V _SS . The brightness of the light emitting element EL will vary due to the magnitude of the driving current passing through the driving element T _dr . The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting elements.

The gate of the photosensitive element T _ph (such as the first gate TG1 in FIGS. 1 to 4 ) is electrically connected to the voltage V _S3 , and the drain of the photosensitive element T _ph (such as the first drain in FIGS. 1 to 4 D1) is electrically connected to the voltage V _DD and the drain of the driving element T _dr at the third node c. In some embodiments, the photosensitive element T _ph is a double-gate TFT, and one of the gates of the photosensitive element T _ph (for example, the first bottom gate BG1 in FIGS. 1 to 4 ) is electrically connected to the photosensitive element. The source of T _ph (for example, the first source S1 in FIG. 1 to FIG. 4 ).

The gate of the sensing element T _se (eg, the second gate TG2 in FIGS. 1 to 4 ) is electrically connected to the voltage V _S2 . The drain of the sensing element T _se (such as the second drain D2 in FIGS. 1 to 4 ) is electrically connected to the source of the photosensitive element T _ph . The source of the sensing element T _se (eg, the second source S2 in FIGS. 1 to 4 ) is electrically connected to the voltage V _ses . In some embodiments, the sensing element T _se is a double-gate thin film transistor, and the two gates of the sensing element T _se (such as the second gate TG2 and the second bottom gate in FIGS. 1 to 4 poles BG2) are electrically connected to the voltage V _S2 .

FIG. 6 is a schematic diagram of an equivalent circuit of a photosensitive element substrate according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 6 follows the component numbers and part of the content of the embodiment in FIG. 3 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 6. In this embodiment, the photosensitive element T _ph is a double-gate thin film transistor, and the two gates of the photosensitive element T _ph (for example, the first gate TG1 and the first gate TG1 in FIGS. 1 to 4 A bottom gate BG1) is electrically connected to the voltage V _S3 .

10A, 10B, 10C: photosensitive element substrate 100: substrate 110: first gate dielectric layer 120: second gate dielectric layer 130: interlayer dielectric layer 140: passivation layer 210: first metal oxide layer 212, 212' : second metal oxide layer 214, 214': third metal oxide layer 216, 216': fourth metal oxide layer a: first node b: second node c: third node BG1: first bottom gate Pole BG2: second bottom gate BG3: third bottom gate ch1, ch2, ch3: channel area Cst: storage capacitor D1: first drain D2: second drain D3: third drain dr1, dr2, dr3 : drain region E1: first electrode E2: second electrode EL: light-emitting diode EM: light-emitting layer ND: normal direction NP: metal nanoparticles O, OP: opening P: doping process SL, SL': Photosensitive layer S1: first source S2: second source S3: third source sr1, sr2, sr3: source region TG1: first gate TG2: second gate TG3: third gate T _dr : Driving element T _ph : photosensitive element T _se : sensing element T _sw : switching element t1, t2: thickness V1: first contact hole V2: second contact hole V3: third contact hole V4: fourth contact hole V5: second contact hole Five contact holes V6: sixth contact holes V _S1 , V _data , V _S2 , V _S3 , V _SS , V _DD , V _ses : voltage

FIG. 1 is a schematic cross-sectional view of a photosensitive element substrate according to an embodiment of the present invention. 2A to 2G are schematic cross-sectional views of the manufacturing method of the photosensitive element substrate of FIG. 1 . FIG. 3 is a schematic cross-sectional view of a photosensitive element substrate according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a photosensitive element substrate according to an embodiment of the present invention. FIG. 5 is a schematic diagram of an equivalent circuit of a photosensitive element substrate according to an embodiment of the present invention. FIG. 6 is a schematic diagram of an equivalent circuit of a photosensitive element substrate according to an embodiment of the present invention.

10A: Photosensitive element substrate

100: Substrate

110: first gate dielectric layer

120: second gate dielectric layer

130: interlayer dielectric layer

140: passivation layer

210: first metal oxide layer

212: second metal oxide layer

214: the third metal oxide layer

216: the fourth metal oxide layer

BG1: the first bottom gate

BG2: The second bottom gate

BG3: third bottom gate

ch1, ch2, ch3: channel area

D1: the first drain

D2: the second drain

D3: The third drain

dr1, dr2, dr3: drain area

E1: first electrode

E2: second electrode

EL: light emitting diode

EM: luminous layer

ND: normal direction

O, OP: open

SL: photosensitive layer

S1: first source

S2: second source

S3: The third source

sr1, sr2, sr3: source region

TG1: first gate

TG2: the second gate

TG3: The third gate

T _dr : drive element

T _ph : photosensitive element

T _se : sensing element

t1, t2: thickness

Claims (13)

A photosensitive element substrate, comprising: a substrate; A photosensitive element is located on the substrate and includes: A photosensitive layer, including a first metal oxide layer and a second metal oxide layer stacked on each other; a first gate overlapping the photosensitive layer, wherein the second metal oxide layer is located between the first gate and the first metal oxide layer; and a first source and a first drain, electrically connected to the photosensitive layer; A sensing element is located on the substrate and electrically connected to the photosensitive element, wherein the sensing element includes: a third metal oxide layer; a second gate overlapping the third metal oxide layer; and a second source and a second drain electrically connected to the third metal oxide layer; a passivation layer covering the photosensitive element and the sensing element; and A light-emitting diode includes a first electrode, a light-emitting layer and a second electrode stacked on each other, wherein the second electrode is located on the passivation layer, and the second electrode has an opening overlapping the photosensitive element. The photosensitive element substrate as claimed in claim 1, wherein the energy gap of the first metal oxide layer is smaller than the energy gap of the second metal oxide layer. The photosensitive element substrate as claimed in claim 1, wherein the oxygen concentration of the first metal oxide layer is lower than the oxygen concentration of a channel region of the second metal oxide layer, and the oxygen concentration of the first metal oxide layer is 10 at% to 50 at%, and the oxygen concentration in the channel region of the second metal oxide layer is 30 at% to 70 at%. The photosensitive element substrate as claimed in claim 1, wherein the thickness of the first metal oxide layer is 10 nm to 30 nm, and the thickness of the second metal oxide layer is 5 nm to 50 nm. The photosensitive element substrate as claimed in claim 1, wherein the photosensitive element further comprises a plurality of metal nanoparticles located on the first metal oxide layer. The photosensitive element substrate as claimed in claim 5, wherein the particle diameter of the metal nanoparticles is 10 nm to 60 nm. The photosensitive element substrate as claimed in claim 5, wherein the metal nanoparticles are located between the first metal oxide layer and the second metal oxide layer or between the first metal oxide layer and the substrate. The photosensitive element substrate as claimed in claim 1, wherein the material of the first metal oxide layer includes indium tin oxide, indium zinc oxide or tin oxide. The photosensitive element substrate as described in claim 1, further comprising: a switching element: and A driving element, wherein the gate of the driving element is electrically connected to the source of the switching element, the source of the driving element is electrically connected to the first electrode of the light-emitting diode, and the drain of the driving element is electrically connected to the source of the switching element. Sexually connected to the first drain of the photosensitive element. The photosensitive element substrate as claimed in claim 9, wherein the driving element comprises a fourth metal oxide layer. The photosensitive element substrate according to claim 1, wherein the photosensitive element further includes a first bottom gate, the photosensitive layer is located between the first bottom gate and the first gate, and the first bottom gate Electrically connected to the first gate or the first source. A method for manufacturing a photosensitive element substrate, comprising: forming a first metal oxide layer, a second metal oxide layer and a third metal oxide layer on a substrate, wherein a photosensitive layer includes the first metal oxide layer and the second metal oxide layer stacked on each other oxide layer; forming a gate dielectric layer on the second metal oxide layer and the third metal layer; forming a first gate and a second gate on the gate dielectric layer, wherein the first gate and the second gate respectively overlap the photosensitive layer and the third metal oxide layer, and the first gate The second metal oxide layer is located between the first gate and the first metal oxide layer; forming a first source and a first drain electrically connected to the photosensitive layer; forming a second source and a second drain electrically connected to the third metal oxide layer; and forming a light-emitting diode and a passivation layer, wherein the passivation layer is located on the first source, the first drain, the second source and the second drain, the light-emitting diodes include stacked A first electrode, a light-emitting layer and a second electrode, wherein the second electrode is located on the passivation layer, and the second electrode has an opening overlapping the photosensitive layer. The method for manufacturing a photosensitive element substrate as described in claim 12, further comprising: forming a fourth metal oxide layer on the substrate; forming a third gate on the gate dielectric layer, wherein the third gate overlaps the fourth metal oxide layer; and A third source and a third drain electrically connected to the fourth metal oxide layer are formed, and the first electrode is electrically connected to the third source.

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