TW202230798A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate, a first oxide semiconductor layer, a second oxide semiconductor layer, a third oxide semiconductor layer, a top gate insulator, a top gate, an interlayer dielectric and a source/drain structure. The first oxide semiconductor layer is disposed on the substrate. The second oxide semiconductor layer is disposed on the first oxide semiconductor layer. The third oxide semiconductor layer is disposed on the second oxide semiconductor layer. The top gate insulator is disposed on the substrate and covers the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer. The top gate is disposed on the top gate insulator. The interlayer dielectric covers the top gate insulator and the top gate. The source/drain structure passes through the interlayer dielectric, the top gate insulator, and the third oxide semiconductor layer, and contacts the second oxide semiconductor layer.

Description

semiconductor element

The present disclosure relates to a semiconductor device.

Thin-film-transistor (TFT) has been widely used in many types of flat panel displays in recent years. In order to make the panel react faster, more reliable, and higher resolution, the use of low temperature polysilicon (LTPS) thin film transistors and indium gallium zinc oxide (IGZO) thin film transistors rate also increased. However, the manufacturing process of LTPS thin film transistors is complicated and yields are low, resulting in increased manufacturing costs. Although IGZO thin film transistors can improve panel performance and reduce costs, they are quite sensitive to process parameters. In addition, the reliability of long-term use needs to be strengthened.

Accordingly, there exists a need in the art to address the above-mentioned deficiencies and deficiencies.

In view of this, one objective of the present disclosure is to provide a semiconductor device that solves the above problems.

In order to achieve the above objective, according to an embodiment of the present disclosure, a semiconductor device includes a substrate, a first oxide semiconductor layer, a second oxide semiconductor layer, a third oxide semiconductor layer, a top gate insulating layer, a top gate, and an interlayer dielectric. Electricity and source/drain structure. The first oxide semiconductor layer is on the substrate. The second oxide semiconductor layer is located on the first oxide semiconductor layer. The third oxide semiconductor layer is on the second oxide semiconductor layer. The top gate insulating layer is located on the substrate and covers the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer. The top gate is on the top gate insulating layer. The interlayer dielectric covers the top gate insulating layer and the top gate. The source/drain structure passes through the interlayer dielectric, the top gate insulating layer and the third oxide semiconductor layer, and contacts the second oxide semiconductor layer.

In one or more embodiments of the present disclosure, the first oxide semiconductor layer includes indium gallium oxide or gallium oxide.

In one or more embodiments of the present disclosure, the second oxide semiconductor layer includes indium gallium zinc oxide, indium tungsten zinc oxide, or indium tin zinc oxide.

In one or more embodiments of the present disclosure, the third oxide semiconductor layer includes indium gallium oxide or gallium oxide.

In one or more embodiments of the present disclosure, the thickness of the first oxide semiconductor layer is greater than the thickness of the top portion of the third oxide semiconductor layer.

In one or more embodiments of the present disclosure, the third oxide semiconductor layer covers the second oxide semiconductor layer and contacts the first oxide semiconductor layer.

In one or more embodiments of the present disclosure, the source/drain structures contact the sidewalls and the top surface of the second oxide semiconductor layer.

In one or more embodiments of the present disclosure, the third oxide semiconductor layer covers the second oxide semiconductor layer and is separated from the first oxide semiconductor layer.

In one or more embodiments of the present disclosure, the source/drain structures contact the sidewalls of the second oxide semiconductor layer.

In one or more embodiments of the present disclosure, a bottom gate on the substrate and a bottom gate insulating layer covering the bottom gate and the substrate are further included between the substrate and the first oxide semiconductor layer.

To sum up, the present disclosure discloses an indium gallium zinc oxide thin film transistor device of three different embodiments that can be synchronously completed at different positions in an organic light emitting diode circuit through one process.

The above descriptions are only used to describe the problems to be solved by the present disclosure, the technical means for solving the problems and their effects, etc. The specific details of the present disclosure will be described in detail in the following embodiments in conjunction with the relevant drawings, although Variations and modifications may be made therein without departing from the spirit and scope of the novel concepts of the present disclosure.

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are depicted. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those of ordinary skill in the art. The same reference numerals refer to the same elements throughout.

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "a first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the content clearly dictates otherwise. Furthermore, it is to be understood that, when used in this specification, the terms "comprising" or "having" designate the stated feature, region, integer, step, operation, presence of an element and/or part, but not excluding one or more other The presence or addition of a feature, an entirety of a region, a step, an operation, an element, a component, and/or a combination thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as understood by one of ordinary skill in the art. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having meanings consistent with their meanings in the context of the related art and the present disclosure, and are not to be construed as idealized or excessive Formal meaning, unless expressly defined as such herein.

Embodiments of the present disclosure will be described with reference to the drawings. For purposes of the present disclosure, as embodied and broadly described herein, the present disclosure relates to a semiconductor device.

As mentioned above, in order to make the panel more responsive, reliable and high-resolution, low temperature polysilicon (LTPS) thin film transistors and indium gallium zinc oxide (IGZO) thin films The use of transistors has also increased. However, the manufacturing process of LTPS thin film transistors is complicated and yields are low, resulting in increased manufacturing costs. Although IGZO thin film transistors can improve panel performance and reduce costs, they are quite sensitive to process parameters. In addition, the reliability of long-term use needs to be strengthened.

In view of such defects, one object of the present disclosure is to provide a semiconductor device that solves the above problems.

FIG. 1 is a top view of a semiconductor element according to some embodiments. The semiconductor element shown in FIG. 1 is simplified, therefore, it should be understood that one or more features of the complete semiconductor element may not be shown in FIG. 1 . For example, the via, top gate insulating layer, and interlayer dielectric are not shown in FIG. 1 .

As shown in FIG. 1, the semiconductor device includes a first oxide semiconductor layer 104 on a substrate 102 and a second oxide semiconductor layer 106 on the first oxide semiconductor layer 104, wherein the second oxide semiconductor layer 106 is used as a thin film electrical conductor The channel of the crystal. The first oxide semiconductor layer 104 and the third oxide semiconductor layer 108 together serve as a protective layer covering the second oxide semiconductor layer 106 . The top gate 110 is disposed on the top gate insulating layer (see FIG. 2 ) on the third oxide semiconductor layer 108 . The source/drain structure 112 extends through the layers along vias (see FIG. 2) and contacts the second oxide semiconductor layer 106 which acts as a channel.

Figure 1 further illustrates a reference cross-section used in subsequent figures. The reference section AA' is cut along the longitudinal direction of the semiconductor element and passes through the top gate 110, the second oxide semiconductor layer 106, the first oxide semiconductor layer 104, the third oxide semiconductor layer 108, the substrate 102, and the source/drain Pole structure 112 . The reference section B-B' is perpendicular to the reference section A-A' and passes through the top gate 110 , the second oxide semiconductor layer 106 , the first oxide semiconductor layer 104 , the third oxide semiconductor layer 108 , and the substrate 102 . For the sake of clarity, subsequent drawings refer to these reference sections.

FIGS. 2 to 5 are cross-sectional views of examples of semiconductor devices according to various embodiments. Figures 2, 4 and 5 show the reference section A-A' shown in Figure 1. Figure 3 shows the reference section B-B' shown in Figure 1.

In FIG. 2, semiconductor device 100 provides substrate 102 and a first oxide semiconductor layer 104 is deposited over substrate 102, according to some embodiments. In some embodiments, the first oxide semiconductor layer 104 includes indium gallium oxide (IGaO) or gallium oxide (GaO). Such materials have relatively high sheet resistance and density, and can prevent the effects of moisture, oxygen, and ions from the underlying substrate 102 .

Further in Figure 2, a second oxide semiconductor layer 106 is deposited. In some embodiments, the second oxide semiconductor layer 106 may include indium gallium zinc oxide (IGZO), indium tungsten zinc oxide (IWZO), or indium tin zinc oxide (IWZO) ITZO). In addition, the second oxide semiconductor layer 106 will be etched. The etching can be performed by a wet lithography process. In some embodiments, the taper of the second oxide semiconductor layer 106 can be made gentler by the etching selectivity ratio. In some embodiments, the second oxide semiconductor layer 106 may be etched inward by 1 micron or wet photoresist may be undercut inward.

Further in FIG. 2 , a third oxide semiconductor layer 108 is deposited on the second oxide semiconductor layer 106 and covers the second oxide semiconductor layer 106 and contacts the first oxide semiconductor layer 104 . The thickness of the top portion of the third oxide semiconductor layer 108 is thinner than that of the first oxide semiconductor layer 104 . Next, the third oxide semiconductor layer 108 will be etched. Etching can be performed by wet or dry photolithography processes. After the etching process, the feature size of a single side of the third oxide semiconductor layer 108 is larger than that of the second oxide semiconductor layer 106 by 1 to 2 microns.

In some embodiments, the third oxide semiconductor layer 108 may include IGaO or GaO. These materials have relatively high sheet resistance and density, and are resistant to the effects of moisture, oxygen, and ions. Therefore, the first oxide semiconductor layer 104 and the third oxide semiconductor layer 108 together serve as a protective layer that completely covers the second oxide semiconductor layer 106 (refer to FIG. 2 and FIG. 3 ) to block moisture, oxygen and hydrogen atoms influence on the second oxide semiconductor layer 106, thereby increasing reliability. In addition, since the sheet resistances of the first oxide semiconductor layer 104 and the third oxide semiconductor layer 108 are high, the conduction paths of carriers can be concentrated in the second oxide semiconductor layer 106 as a channel.

Further in FIG. 2 , a top gate insulating layer 114 is deposited on the substrate 102 and covers the first oxide semiconductor layer 104 , the second oxide semiconductor layer 106 and the third oxide semiconductor layer 108 . Next, the top gate 110 is disposed on the top gate insulating layer 114 . Next, an interlayer dielectric 116 is deposited to cover the top gate insulating layer 114 and the top gate 110 .

Further in FIG. 2 , through holes 118 are formed, and self-aligned doping is performed with the top gate 110 as a mask. Next, a source/drain structure 112 is formed in the through hole 118 , and the source/drain structure 112 is in contact with the second oxide semiconductor layer 106 along the sidewall of the through hole 118 . Since self-aligned doping provides vacancy, the resistance is reduced, which can improve reliability under high current density operation.

FIG. 4 illustrates a cross-sectional view of a semiconductor device 100' according to other embodiments. As shown in FIG. 4, a semiconductor device 100' provides a substrate 102 and a bottom gate 402 is provided on the substrate 102 prior to deposition of the first oxide semiconductor layer 104. As shown in FIG. Next, a bottom gate insulating layer 404 is deposited to cover the bottom gate 402 and the substrate 102 .

Further in FIG. 4, the first oxide semiconductor layer 104 is deposited on the bottom gate insulating layer 404, and the subsequent steps of the semiconductor device 100 are repeated. In this way, the formed semiconductor device 100' is a dual-gate IGZO thin film transistor, which has better device characteristics, and can achieve higher carrier mobility, thereby reducing power consumption.

FIG. 5 illustrates a cross-sectional view of a semiconductor device 100 ″ according to other embodiments. As shown in FIG. 5 , the third oxide semiconductor layer 108 of the semiconductor device 100 ″ covers the second oxide semiconductor layer 106 and is connected to the first oxide semiconductor layer 106 . The oxide semiconductor layer 104 is separated. The first oxide semiconductor layer 104 and the third oxide semiconductor layer 108 are used as protective layers to cover the second oxide semiconductor layer 106 up and down to block the influence of water vapor, oxygen and hydrogen atoms on the second oxide semiconductor layer 106 .

It can be seen from the different embodiments in FIGS. 2 , 4 and 5 that since there are a lot of the same operations among the different embodiments, the three different embodiments of the present disclosure can be processed in the organic light emitting diode (OLED) through one process. The organic light-emitting diode, OLED) circuit is synchronized at different positions in the circuit.

FIG. 6 illustrates a circuit design diagram of a semiconductor device placed in an OLED circuit according to some embodiments. The circuit portion of the OLED circuit includes switch thin film transistors (eg, transistor T1, transistor T2), driving (driving) thin film transistors (eg, transistor T3), capacitors, and OLED. Specifically, the gate and/or source/drain of each thin film transistor and the capacitor are electrically connected to each other or connected to various power supply voltages, such as the data line power supply voltage V _data , the reference power supply voltage V _ref1 and the reference power supply voltage V _ref2 , the drain power supply voltage VDD or the source power supply voltage VSS, etc. In addition, the driving timing part of the OLED circuit includes switches (eg, switch S1, switch S2) and light-emitting control lines. Specifically, the gate of each thin film transistor can also be connected to a switch or a light-emitting control line. In some embodiments, the transistor T1 may be implemented by the semiconductor element 100 , the transistor T2 may be implemented by the semiconductor element 100 ″, and the transistor T3 may be implemented by the semiconductor element 100 ′.

FIG. 7 illustrates a circuit design diagram of a semiconductor device placed in an OLED circuit according to some embodiments. Similar to FIG. 6 , the circuit portion of the OLED circuit also includes switching thin film transistors (eg transistor T4 ), driving thin film transistors (eg transistor T5 ), capacitors (eg storage capacitor C _st ) and OLED. Specifically, the gates and/or the source/drain electrodes of the transistors T4 and T5 and the storage capacitor _Cst are electrically connected to each other or connected to various power supply voltages. The driving timing part of the OLED circuit includes scan lines and data lines. Specifically, the gate electrode of the transistor T4 is connected to the scan line, and the source electrode is connected to the data line. In some embodiments, the transistor T4 may be implemented by the semiconductor element 100 or the semiconductor element 100 ″, and the transistor T5 may be implemented by the semiconductor element 100 ′.

The foregoing outlines the features of several implementations or examples so that those of ordinary skill in the art may better understand the various aspects of the present disclosure. The foregoing description of exemplary embodiments of the present disclosure has been presented for purposes of illustration and description only, and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Those with ordinary knowledge in the art, without departing from the spirit and scope of the present disclosure, can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the implementations or embodiments described herein. To achieve the same purpose or achieve the same advantages, the protection scope of the present disclosure should be determined by the scope of the appended patent application.

100, 100', 100": semiconductor element 102: substrate 104: first oxide semiconductor layer 106: second oxide semiconductor layer 108: third oxide semiconductor layer 110: top gate 112: source/drain structure 114: top gate pole insulating layer 116: interlayer dielectric 118: through hole 402: bottom gate 404: bottom gate insulating layer A-A', BB': reference profile C _st : storage capacitor S1, S2: switch T1, T2 , T3, T4, T5: Transistor VDD: Drain power supply voltage VSS: Source power supply voltage V _data : Data line power supply voltage V _ref1 , V _ref2 : Reference power supply voltage

The present disclosure is best understood from the following detailed description when read in conjunction with the drawings. It is emphasized that, in accordance with standard practice in the art, the various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a top view of one example of a semiconductor device according to some embodiments. FIG. 2 illustrates a cross-sectional view of one example of a semiconductor device according to some embodiments. FIG. 3 illustrates a cross-sectional view of one example of a semiconductor device according to some embodiments. FIG. 4 illustrates a cross-sectional view of one example of a semiconductor device according to some embodiments. 5 illustrates a cross-sectional view of one example of a semiconductor device according to some embodiments. FIG. 6 is a circuit design diagram of a semiconductor device placed in an organic light emitting diode circuit according to some embodiments. FIG. 7 is a circuit design diagram of a semiconductor device placed in an organic light emitting diode circuit according to some embodiments.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: Semiconductor Components

102: Substrate

104: the first oxide semiconductor layer

106: the second oxide semiconductor layer

108: the third oxide semiconductor layer

110: top gate

112: source/drain structure

114: Top gate insulating layer

116: Interlayer dielectric

118: Through hole

A-A’: Reference section

Claims (10)

A semiconductor element, comprising: a substrate; a first oxide semiconductor layer on the substrate; a second oxide semiconductor layer on the first oxide semiconductor layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a top gate insulating layer on the substrate and covering the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer; a top gate on the top gate insulating layer; an interlayer dielectric covering the top gate insulating layer and the top gate; and A source/drain structure passes through the interlayer dielectric, the top gate insulating layer and the third oxide semiconductor layer, and contacts the second oxide semiconductor layer. The semiconductor device of claim 1, wherein the first oxide semiconductor layer comprises indium gallium oxide or gallium oxide. The semiconductor device of claim 1, wherein the second oxide semiconductor layer comprises indium gallium zinc oxide, indium tungsten zinc oxide or indium tin zinc oxide. The semiconductor device of claim 1, wherein the third oxide semiconductor layer comprises indium gallium oxide or gallium oxide. The semiconductor device of claim 1, wherein a thickness of the first oxide semiconductor layer is greater than a thickness of a top portion of the third oxide semiconductor layer. The semiconductor device of claim 1, wherein the third oxide semiconductor layer covers the second oxide semiconductor layer and contacts the first oxide semiconductor layer. The semiconductor device of claim 1, wherein the source/drain structure contacts sidewalls and a top surface of the second oxide semiconductor layer. The semiconductor device of claim 1, wherein the third oxide semiconductor layer covers the second oxide semiconductor layer and is separated from the first oxide semiconductor layer. The semiconductor device of claim 1, wherein the source/drain structure contacts a sidewall of the second oxide semiconductor layer. The semiconductor device as claimed in claim 1, wherein between the substrate and the first oxide semiconductor layer further comprises: a bottom gate on the substrate; and A bottom gate insulating layer covers the bottom gate and the substrate.

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