TWI822129B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a semiconductor structure, a gate dielectric layer, a first gate, a source and a drain. The semiconductor structure is disposed above the substrate. The semiconductor structure includes a first thick portion, a second thick portion, and a thin portion between the first thick portion and the second thick portion. The gate dielectric layer is disposed on the semiconductor structure. The first gate is disposed on the gate dielectric layer. The first gate overlaps a portion of the first thick portion and a portion of the thin portion. The first gate does not overlap with another portion of the thin portion and the second thick portion. The source is electrically connected to the first thick portion. The drain is electrically connected to the second thick portion.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

Generally speaking, the semiconductor layer of a thin film transistor can be divided into a channel region and a doped region. If the carrier concentration in the doped region is high and there is a sudden drop in carrier concentration between the doped region and the channel region, a high lateral electric field will appear near the drain of the thin film transistor during high current operation. , and cause the semiconductor device to deteriorate. However, if the carrier concentration of the doped region is reduced in order to avoid degradation of the semiconductor device, the operating current of the semiconductor device will be insufficient. Therefore, how to reduce the lateral electric field near the drain while maintaining sufficient operating current performance of the semiconductor device is currently a problem that needs to be improved.

The present invention provides a semiconductor device and a manufacturing method thereof, which have sufficient operating current and can reduce the lateral electric field near the drain.

At least one embodiment of the present invention provides a semiconductor device. Semiconductor packaging The device includes a substrate, a semiconductor structure, a gate dielectric layer, a first gate, a source and a drain. The semiconductor structure is disposed on the substrate. The semiconductor structure includes a first thick portion, a second thick portion, and a thin portion between the first thick portion and the second thick portion. The thickness of the first thick part and the second thick part is greater than the thickness of the thin part. The gate dielectric layer is disposed on the semiconductor structure. The first gate is disposed on the gate dielectric layer. The first gate overlaps part of the first thick part and part of the thin part in a normal direction of the top surface of the substrate. The first gate does not overlap another thin part and the second thick part in the normal direction of the top surface of the substrate. The source electrode is electrically connected to the first thick portion. The drain electrode is electrically connected to the second thick part.

At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a semiconductor structure on a substrate. The semiconductor structure includes a first thick portion, a second thick portion, and a semiconductor device located between the first thick portion and the second thick portion. a thin part, wherein the thickness of the first thick part and the second thick part is greater than the thickness of the thin part; forming a gate dielectric layer on the semiconductor structure; forming a first gate electrode on the gate dielectric layer, wherein the first gate electrode is on The normal direction of the top surface of the substrate overlaps with part of the first thick part and part of the thin part, and the first gate does not overlap with another part of the thin part and the second thick part in the normal direction of the top surface of the substrate; forming The source electrode of the first thick part is electrically connected and the drain electrode of the second thick part is electrically connected.

100:Substrate

110: Buffer layer

120,120’: Semiconductor structure

122,122’: first metal oxide layer

122a, 122a’: first island structure

122b, 122b’: second island structure

124,124’: Second metal oxide layer

130: Gate dielectric layer

140: first gate

142: Second gate

150: Interlayer dielectric layer

160: Conductive layer

C: capacitor

ch: channel area

D: drain

dr: drain area

GND: ground voltage

LED: light emitting diode

l1,l2,l3,l4: length

ND: normal direction

P: doping process

p1A: The first thick part

p1B: The second thick part

p2: thin part

OVDD: voltage

S: Source

sr: source region

T1: driving element

T1A, T1B, T1C: semiconductor device

T2: switching element

t1,t2:Thickness

V1, V2: through hole

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

2A to 2D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 .

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

4A to 4D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 3 .

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a pixel circuit according to another embodiment of the present invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , the semiconductor device T1A includes a substrate 100 , a semiconductor structure 120 , a gate dielectric layer 130 , a first gate 140 , a source S and a drain D. In this embodiment, the semiconductor device T1A further includes a buffer layer 110 and an interlayer dielectric layer 150 .

The material of the substrate 100 may be glass, quartz, organic polymer, opaque/reflective material (such as conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene dicarboxylate. (polyethylene naphthalate, PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal soft plate ( Metal Foil) or other flexible materials. The buffer layer 110 is located on the substrate 100. The material of the buffer layer 110 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the invention is not limited thereto.

The semiconductor structure 120 is disposed on the substrate 100 and the buffer layer 110 . The semiconductor structure 120 includes a first thick portion p1A, a second thick portion p1B, and a thin portion p2 located between the first thick portion p1A and the second thick portion p1B. The thickness of the first thick portion p1A and the second thick portion p1B is greater than that of the thin portion p1A. The thickness of part p2. In some embodiments, the outer sides of the first thick part p1A and the second thick part p1B away from the thin part p2 also include other thin parts, so that the first thick part p1A and the second thick part p1B are respectively sandwiched between the two corresponding thin parts. between.

The semiconductor structure 120 may include a first metal oxide layer 122 and a second metal oxide layer 124 . The stacked portions of the first metal oxide layer 122 and the second metal oxide layer 124 may constitute two thick portions of the semiconductor structure 120 . For example, in this embodiment, the first metal oxide layer 122 includes a first island-like structure 122a and a second island-like structure 122b that are separated from each other. The second metal oxide layer 124 and the first island-like structure 122a are stacked on each other to form the first thick portion p1A, and the second metal oxide layer 124 and the second island-like structure 122b are stacked on each other to form the second thick portion p1B. In this embodiment, the length l3 of the first island-shaped structure 122a is different from the length l4 of the second island-shaped structure 122b, but the invention is not limited thereto. In other embodiments, the length l3 of the first island structure 122a is equal to the length l4 of the second island structure 122b.

The portion of the second metal oxide layer 124 located between the first thick portion p1A and the second thick portion p1B may constitute the thin portion p2. In other words, the thickness of the first thick portion p1A and the second thick portion p1B is substantially the sum of the thickness t1 of the first metal oxide layer 122 and the thickness t2 of the second metal oxide layer 124 , while the thickness of the thin portion p2 is substantially equal to the thickness t2 of the second metal oxide layer 124 . In some embodiments, the portion of the second metal oxide layer 124 located outside the first thick portion p1A and the second thick portion p1B away from the thin portion p2 may also constitute other thin portions.

The materials of the semiconductor structure 120 include indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), etc. Metal compounds or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W) or lanthanide rare earths Doped metal oxides (such as Ln-IZO). In some embodiments, the first metal oxide layer 122 and the second metal oxide layer 124 may include the same metal element, but the invention is not limited thereto. In some embodiments, the thicknesses of the first metal oxide layer 122 and the second metal oxide layer 124 may be the same, for example, between 2 nm and 60 nm, but the invention is not limited thereto.

The gate dielectric layer 130 is disposed on the semiconductor structure 120 and the buffer layer 110 . The first gate 140 is disposed on the gate dielectric layer 130 . The first gate 140 overlaps with part of the first thick part p1A and part of the thin part p2 in the normal direction ND of the top surface of the substrate 100, and the first gate 140 does not overlap with another part of the first part in the normal direction ND. The thick part p1A, another thin part p2 and the second thick part p1B. In some embodiments, the length l1 of the first gate 140 and the length l2 of the thin portion p2 are equal to or different from each other.

In this embodiment, the semiconductor structure includes a source region sr, a drain region dr, and a channel region ch located between the source region sr and the drain region dr. The source region sr and the drain region dr are doped to have a lower resistivity than the channel region ch.

In this embodiment, the range of the channel region ch is defined by the first gate 140 , where the channel region ch includes a portion of the first thick portion p1A that overlaps the first gate 140 in the normal direction ND and a thin portion p2 A portion overlapping the first gate 140 in the normal direction ND. Therefore, in this embodiment, the channel region ch includes part of the first island structure 122a and part of the second metal oxide layer 124.

The first gate 140 does not overlap a portion of the first thick portion p1A in the normal direction ND, and the source region sr includes a portion of the first thick portion p1A that does not overlap the first gate 140 in the normal direction ND. The first gate 140 does not overlap the thin portion p2 and the second thick portion p1B in the normal direction ND, and the drain region dr includes a portion of the thin portion p2 that does not overlap the first gate 140 in the normal direction ND. and the second thick part p1B. In some embodiments, the source region sr also includes other thin portions located outside the first thick portion p1A away from the thin portion p2, and the drain region dr also includes other thin portions located outside the second thick portion p1B away from the thin portion p2. Thin part.

In this embodiment, since the thickness of the portion of the drain region dr close to the channel region ch is thinner, the resistivity of the portion of the drain region dr connected to the channel region ch can be reduced, thereby reducing the risk of the drain region dr due to the lateral electric field. The hot carrier effect produced. In addition, since the thickness of the portion of the source region sr close to the channel region ch is thicker, it is possible to avoid an increase in the resistivity of the source region sr due to a reduction in thickness.

In addition, although there are portions with different thicknesses in the channel region ch, due to the Most of the current in the channel region ch is conducted on the surface of the channel region ch, so the thickness change of the channel region ch has little impact on the resistivity of the channel region ch. In this embodiment, by disposing the first thick portion p1A below the first gate 140 , the connection portion between the first thick portion p1A and the thin portion p2 is located in the channel region ch. In some embodiments, by partially overlapping the first gate 140 in the normal direction ND, the first island-shaped structure 122a is used to prevent process deviation from causing the connection portion of the first thick portion p1A and the thin portion p2 to deviate from the channel. District ch.

The interlayer dielectric layer 150 is disposed on the gate dielectric layer 130 and covers the first gate electrode 140 . The materials of the interlayer dielectric layer 150 and the gate dielectric layer 130 are, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. The through holes V1 and V2 penetrate the interlayer dielectric layer 150 and the gate dielectric layer 130 , and the through holes V1 and V2 overlap the first thick portion p1A and the second thickness p1B respectively. The conductive layer 160 is located on the interlayer dielectric layer 150 and fills the through holes V1 and V2 respectively to be electrically connected to the first thick portion p1A and the second thickness p1B of the semiconductor structure 120 . The conductive layer 160 can form a source S and a drain D. The source S is electrically connected to the source region sr through the through hole V1, and the drain D is electrically connected to the drain region dr through the through hole V2. In this embodiment, the source S and the drain D are connected to the second metal oxide layer 124 . In some embodiments, the projected areas of the first thick portion p1A and the second thickness p1B on the substrate 100 are respectively larger than the contact area between the source S and the first thick portion p1A and the contact area between the drain D and the second thickness p1B, whereby This reduces the probability that the source S and the drain D are not in contact with the thick part due to process deviation.

Based on the above, in addition to improving the hot carrier effect of the semiconductor device T1A, it can also avoid an increase in the resistivity of the source region sr of the semiconductor device T1A, thereby improving The operating current of the semiconductor device T1A is increased, thereby improving the overall performance and reliability of the semiconductor device T1A.

2A to 2D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 .

Referring to Figures 2A and 2B, a semiconductor structure 120' is formed on the substrate 100. For example, the buffer layer 110 can be formed on the substrate 100 first, and then the semiconductor structure 120' can be formed on the buffer layer 110. The semiconductor structure 120' includes a first thick portion p1A, a second thick portion p1B, and a thin portion p2 located between the first thick portion p1A and the second thick portion p1B.

In this embodiment, the semiconductor structure 120' may be formed by, for example, as shown in FIG. 2A. The first metal oxide layer 122' is first formed on the buffer layer 110 and the substrate 100. The first metal oxide semiconductor layer 122' 'Includes a first island-shaped structure 122a' and a second island-shaped structure 122b' that are separated from each other. Then, as shown in FIG. 2B, a second metal oxide layer 124' is formed on the first metal oxide layer 122'. In some embodiments, the second metal oxide layer 124' completely covers the first metal oxide layer 122' to avoid damaging the first metal oxide layer during the patterning process when patterning the second metal oxide layer 124'. 122' causes damage.

In some embodiments, the oxygen concentration of the first metal oxide layer 122' is less than or equal to the oxygen concentration of the second metal oxide layer 124', thereby reducing the resistivity of the first thick portion p1A and the second thick portion p1B.

Referring to FIG. 2C, a gate dielectric layer 130 is formed on the semiconductor structure 120'. The first gate 140 is formed on the gate dielectric layer 130 . In some embodiments, forming the The manufacturing process of a gate 140 includes dry etching or wet etching. The first gate 140 overlaps part of the first thick part p1A and part of the thin part p2 in the normal direction ND of the top surface of the substrate 100, and the first gate 140 does not overlap another part of the first part in the normal direction ND. The thick part p1A, another thin part p2 and the second thick part p1B.

Next, using the first gate 140 as a mask, a doping process P is performed on the semiconductor structure 120' to form the semiconductor structure 120 including the channel region ch, the source region sr and the drain region dr. The doping concentration of the source region sr and the drain region dr is greater than the doping concentration of the channel region ch. The doping process P may be, for example, a hydrogen plasma process or an ion implantation process, but the invention is not limited thereto.

Referring to FIG. 2D , an interlayer dielectric layer 150 is formed on the gate dielectric layer 130 and covers the first gate electrode 140 . Afterwards, through holes V1 and V2 are formed penetrating the interlayer dielectric layer 150 and the gate dielectric layer 130 , and the through holes V1 and V2 respectively overlap the first thick portion p1A and the third thick portion p1A in the normal direction ND of the top surface of the substrate 100 . Part 2 p1B.

Then, please refer to FIG. 1 to form a source S and a drain D that are electrically connected to the first thick portion p1A and the second thick portion p1B respectively. For example, the conductive layer 160 can be formed on the interlayer dielectric layer 150 and filled in the through holes V1 and V2 to be electrically connected to the semiconductor structure 120 . The conductive layer 160 may include a source S and a drain D, which are electrically connected to the first thick portion p1A and the second thick portion p1B through the through holes V1 and V2 respectively.

After the above process, the production of the semiconductor device T1A can be substantially completed.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. It must be noted here that the embodiment of FIG. 3 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same. or similar components, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

The main difference between the semiconductor device T1B of FIG. 3 and the semiconductor device T1A of FIG. 1 is that the second metal oxide layer 124 of the semiconductor device T1B is located between the first metal oxide layer 122 and the substrate 100 . In addition, in this embodiment, the source S and the drain D are connected to the first metal oxide layer 122 .

Referring to FIG. 3 , the stacked portions of the first metal oxide layer 122 and the second metal oxide layer 124 may constitute two thick portions of the semiconductor structure 120 . For example, in this embodiment, the first metal oxide layer 122 includes a first island-like structure 122a and a second island-like structure 122b that are separated from each other. In this embodiment, the length l3 of the first island-shaped structure 122a is different from the length l4 of the second island-shaped structure 122b, but the invention is not limited thereto. In other embodiments, the length l3 of the first island structure 122a is equal to the length l4 of the second island structure 122b.

The second metal oxide layer 124 and the first island-like structure 122a are stacked on each other to form the first thick portion p1A, and the second metal oxide layer 124 and the second island-like structure 122b are stacked on each other to form the second thick portion p1B. The portion of the second metal oxide layer 124 located between the first thick portion p1A and the second thick portion p1B may constitute the thin portion p2. In other words, the thickness of the first thick portion p1A and the second thick portion p1B is substantially the sum of the thickness t1 of the first metal oxide layer 122 and the thickness t2 of the second metal oxide layer 124 , and the thickness of the thin portion p2 is substantially is equal to the thickness t2 of the second metal oxide layer 124 . In some embodiments, the portion of the second metal oxide layer 124 located outside the first thick portion p1A and the second thick portion p1B away from the thin portion p2 may also form other thin portions.

In this embodiment, since the thickness of the portion of the drain region dr close to the channel region ch is thinner, the resistivity of the portion of the drain region dr connected to the channel region ch can be reduced, thereby reducing the risk of the drain region dr due to the lateral electric field. The hot carrier effect produced. In addition, since the thickness of the portion of the source region sr close to the channel region ch is thicker, it is possible to avoid an increase in the resistivity of the source region sr due to a reduction in thickness.

In addition, although there are parts with different thicknesses in the channel region ch, since most of the current in the channel region ch is conducted on the surface of the channel region ch, changes in the thickness of the channel region ch have a relatively small impact on the resistivity of the channel region ch. Small. In this embodiment, by disposing the first thick portion p1A below the first gate 140 , the connection portion between the first thick portion p1A and the thin portion p2 is located in the channel region ch. In some embodiments, the first island structure 122a is overlapped with the first gate 140 in the normal direction ND to avoid process deviation causing the connection portion of the first thick portion p1A and the thin portion p2 to deviate from the channel area. ch.

4A to 4D are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 3 .

Referring to Figures 4A and 4B, a semiconductor structure 120' is formed on the substrate 100. For example, the buffer layer 110 can be formed on the substrate 100 first, and then the semiconductor structure 120' can be formed on the buffer layer 110. The semiconductor structure 120' includes a first thick portion p1A, a second thick portion p1B, and a thin portion p2 located between the first thick portion p1A and the second thick portion p1B.

In this embodiment, the semiconductor structure 120' may be formed by, for example, as shown in FIG. 4A. The second metal oxide layer 124' is first formed on the buffer layer 110 and the substrate 100. above. Then, as shown in FIG. 4B , a first metal oxide layer 122 ′ is formed on the second metal oxide layer 124 ′, wherein the first metal oxide semiconductor layer 122 ′ includes mutually separated first island structures 122 a ′ and The second island structure 122b'.

In some embodiments, the oxygen concentration of the first metal oxide layer 122' is less than or equal to the oxygen concentration of the second metal oxide layer 124', thereby reducing the resistivity of the first thick portion p1A and the second thick portion p1B.

Referring to FIG. 4C, a gate dielectric layer 130 is formed on the semiconductor structure 120'. The first gate 140 is formed on the gate dielectric layer 130 . In some embodiments, the process of forming the first gate 140 includes dry etching or wet etching. The first gate 140 overlaps part of the first thick part p1A and part of the thin part p2 in the normal direction ND of the top surface of the substrate 100, and the first gate 140 does not overlap another part of the first part in the normal direction ND. The thick part p1A, another thin part p2 and the second thick part p1B.

Using the first gate 140 as a mask, a doping process P is performed on the semiconductor structure 120' to form the semiconductor structure 120 including the channel region ch, the source region sr and the drain region dr. The doping concentration of the source region sr and the drain region dr is greater than the doping concentration of the channel region ch. The doping process P may be, for example, a hydrogen plasma process or an ion implantation process, but the invention is not limited thereto.

Referring to FIG. 4D , an interlayer dielectric layer 150 is formed on the gate dielectric layer 130 and covers the first gate electrode 140 . Afterwards, through holes V1 and V2 are formed penetrating the interlayer dielectric layer 150 and the gate dielectric layer 130 , and the through holes V1 and V2 respectively overlap the first thick portion p1A and the third thick portion p1A in the normal direction ND of the top surface of the substrate 100 . Part 2 p1B.

Then, please refer to Figure 3 to form electrical connections to the first thick portion p1A respectively. and the source S and drain D of the second thick portion p1B. For example, the conductive layer 160 can be formed on the interlayer dielectric layer 150 and filled in the through holes V1 and V2 to be electrically connected to the semiconductor structure 120 . The conductive layer 160 may include a source S and a drain D, which are electrically connected to the first thick portion p1A and the second thick portion p1B through the through holes V1 and V2 respectively.

After the above process, the production of the semiconductor device T1B can be substantially completed.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. It must be noted here that the embodiment of FIG. 5 follows the component numbers and part of the content of the embodiment of FIG. 1 , where the same or similar numbers are used to represent the same or similar elements, and descriptions of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the foregoing embodiments and will not be described again here.

Please refer to FIG. 5 . The main difference between the semiconductor device T1C in FIG. 5 and the semiconductor device T1A in FIG. 1 is that the semiconductor device T1C is a dual-gate transistor, which also includes a second gate 142 .

Referring to FIG. 5 , the second gate 142 overlaps part of the first thick part p1A, part of the second thick part p1B and the thin part p2 in the normal direction ND of the top surface of the substrate 100 . In some embodiments, the area of the second gate 142 overlapping the first thick portion p1A is larger than the area of the second gate 142 overlapping the second thick portion p1B, but the invention is not limited thereto. In some embodiments, part of the first island structure 122a is located between the first gate 140 and the second gate 142 .

In this embodiment, the provision of the second gate 142 can increase the turn-on current of the semiconductor device T1C.

FIG. 6 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

Please refer to FIG. 6 . In this embodiment, the pixel circuit includes a driving element T1 , a switching element T2 , a capacitor C and a light-emitting diode LED. In some embodiments, the light emitting diode LED is an organic light emitting diode or an inorganic light emitting diode. The semiconductor device T1A of FIG. 1 , the semiconductor device T1B of FIG. 3 , or the semiconductor device T1C of FIG. 5 can all be used as the driving element T1 of the pixel circuit of FIG. 6 . Regarding the specific structure of the driving element T1, reference may be made to the relevant contents of FIG. 1, FIG. 3, and FIG. 5, and will not be described again here.

The first gate 140 of the driving element T1 is electrically connected to the source or drain of the switching element T2 and one end of the capacitor C. The drain D of the driving element T1 is electrically connected to the voltage OVDD. The source S of the driving element T1 is electrically connected to one end of the light-emitting diode LED and the other end of the capacitor C. The other end of the light-emitting diode LED is electrically connected to the ground voltage GND.

In this embodiment, the voltage OVDD is greater than the ground voltage GND. Therefore, when the driving element T1 is turned on, the current flows from the drain D to the source S, and the light-emitting diode LED is lit.

FIG. 7 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

Please refer to FIG. 7 . In this embodiment, the pixel circuit includes a driving element T1 , a switching element T2 , a capacitor C and a light-emitting diode LED. In some embodiments, the light emitting diode LED is an organic light emitting diode or an inorganic light emitting diode. The semiconductor device T1A of FIG. 1 , the semiconductor device T1B of FIG. 3 , or the semiconductor device T1C of FIG. 5 can all be used as the driving element T1 of the pixel circuit of FIG. 7 . Regarding the specific structure of the driving element T1, reference may be made to the relevant contents of FIG. 1, FIG. 3, and FIG. 5, and will not be described again here.

The first gate 140 of the driving element T1 is electrically connected to the switching element T2 The source or drain and one end of the capacitor C. The drain D of the driving element T1 is electrically connected to one end of the light-emitting diode LED. The source S of the driving element T1 is electrically connected to the other end of the capacitor C and the ground voltage GND. The other end of the light-emitting diode LED is electrically connected to the voltage OVDD.

In this embodiment, the voltage OVDD is greater than the ground voltage GND. Therefore, when the driving element T1 is turned on, the current flows from the drain D to the source S after passing through the light-emitting diode LED.

100:Substrate

110: Buffer layer

120:Semiconductor Structure

122: First metal oxide layer

122a: First island structure

122b: Second island structure

124: Second metal oxide layer

130: Gate dielectric layer

140: first gate

150: Interlayer dielectric layer

160: Conductive layer

ch: channel area

D: drain

dr: drain area

11,12,13,14: length

ND: normal direction

p1A: The first thick part

p1B: The second thick part

p2: thin part

S: source

sr: source region

T1A: Semiconductor device

t1,t2:Thickness

V1, V2: through hole

Claims (10)

A semiconductor device including: a substrate; A semiconductor structure is provided on the substrate. The semiconductor structure includes a first thick part, a second thick part and a thin part between the first thick part and the second thick part, wherein the first thick part The thickness of the thick part and the second thick part is greater than the thickness of the thin part; a gate dielectric layer disposed on the semiconductor structure; A first gate is disposed on the gate dielectric layer, wherein the first gate overlaps part of the first thick part and part of the thin part in a normal direction of a top surface of the substrate, and the The first gate does not overlap another part of the thin part and the second thick part in the normal direction of the top surface of the substrate; a source electrically connected to the first thick portion; and A drain electrode is electrically connected to the second thick portion. The semiconductor device according to claim 1, wherein the semiconductor structure includes: a first metal oxide layer including a first island-like structure and a second island-like structure separated from each other; and a second metal oxide layer overlapping the first island-like structure and the second island-like structure, wherein the second metal oxide layer and the first island-like structure are stacked on each other to form the first thick portion, and The second metal oxide layer and the second island structure are stacked on each other to form the second thick portion. The semiconductor device of claim 2, wherein the length of the first island structure is different from the length of the second island structure. The semiconductor device of claim 2, wherein the first island structure partially overlaps the first gate in the normal direction. The semiconductor device of claim 1, wherein the semiconductor structure includes a source region, a drain region and a channel region between the source region and the drain region, wherein the channel region includes the first The thick portion overlaps a portion of the first gate in the normal direction and the thin portion overlaps a portion of the first gate in the normal direction. The semiconductor device of claim 5, wherein the drain region includes a portion of the thin portion that does not overlap the first gate in the normal direction and the second thick portion. The semiconductor device of claim 5, wherein the source region includes a portion of the first thick portion that does not overlap the first gate in the normal direction. The semiconductor device as claimed in claim 5 further includes: A second gate overlaps part of the first thick part, part of the second thick part and the thin part in the normal direction. A method of manufacturing a semiconductor device, including: A semiconductor structure is formed on a substrate. The semiconductor structure includes a first thick portion, a second thick portion and a thin portion between the first thick portion and the second thick portion, wherein the first thick portion The thickness of the second thick part and the second thick part is greater than the thickness of the thin part; forming a gate dielectric layer on the semiconductor structure; A first gate is formed on the gate dielectric layer, wherein the first gate overlaps part of the first thick part and part of the thin part in a normal direction of a top surface of the substrate, and the third gate A gate does not overlap another part of the thin part and the second thick part in the normal direction of the top surface of the substrate; A source electrode electrically connected to the first thick part and a drain electrode electrically connected to the second thick part are formed. The method for manufacturing a semiconductor device as claimed in claim 9 further includes: Using the first gate as a mask, a doping process is performed on the semiconductor structure to form a source region, a drain region and a region between the source region and the drain region in the semiconductor structure. a channel region, wherein the channel region includes a portion of the first thick portion overlapping the first gate in the normal direction and a portion of the thin portion overlapping the first gate in the normal direction, the drain The pole region includes a portion of the thin portion that does not overlap the first gate in the normal direction and the second thick portion, and the source region includes the first thick portion that does not overlap the first gate in the normal direction. part of the first gate.

Images