TWI799253B - Semiconductor device and manufactoring method thereof - Google Patents

Semiconductor device and manufactoring method thereof Download PDF

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TWI799253B
TWI799253B TW111116869A TW111116869A TWI799253B TW I799253 B TWI799253 B TW I799253B TW 111116869 A TW111116869 A TW 111116869A TW 111116869 A TW111116869 A TW 111116869A TW I799253 B TWI799253 B TW I799253B
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metal oxide
oxide layer
electrode
gate
stack structure
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TW202324761A (en
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范揚順
李奎佑
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友達光電股份有限公司
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Abstract

A semiconductor device includes a substrate, a first thin film transistor and a resistive random-access memory. The first thin film transistor includes a first gate, a first stack structure, a second gate, a source and a drain. The first stacked structure includes a first metal oxide layer and a second metal oxide layer overlapping each other. The first stack structure is located between the first gate and the second gate. The resistive random-access memory includes a first electrode, a second stack structure and a second electrode. The first electrode is electrically connected to the first gate. The second stacked structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other. The second stack structure is located between the first electrode and the second electrode, and connected with the first electrode and the second electrode.

Description

半導體裝置及其製造方法Semiconductor device and manufacturing method thereof

本發明是有關於一種半導體裝置及其製造方法。The present invention relates to a semiconductor device and its manufacturing method.

由於包含金屬氧化物半導體的薄膜電晶體易受到環境中的氧氣、氫氣和水的影響，使其在長時間使用之後，容易出現性能衰退，影響薄膜電晶體的電性。舉例來說，在包含薄膜電晶體陣列的顯示裝置中，若部分的薄膜電晶體的金屬氧化物半導體出現性能衰退，容易使顯示裝置所顯示的畫面產生不均勻(Mura)的問題。一般來説，為了減少這種不均勻的問題，會將畫素電路連接至外部晶片，並透過外部補償記憶體儲存大量的電流資訊。前述電流資訊經演算法演算以得到補償電流或電壓，再將補償電流或電壓回饋至回畫素電路中。然而，外部晶片的電路設計複雜，且成本高。Since thin film transistors containing metal oxide semiconductors are easily affected by oxygen, hydrogen and water in the environment, they are prone to performance degradation after long-term use, which affects the electrical properties of thin film transistors. For example, in a display device including a thin film transistor array, if the performance of a part of the metal oxide semiconductor of the thin film transistor is degraded, it is easy to cause the problem of non-uniformity (Mura) in the picture displayed by the display device. Generally speaking, in order to reduce this uneven problem, the pixel circuit is connected to an external chip, and a large amount of current information is stored through an external compensation memory. The aforementioned current information is calculated by an algorithm to obtain a compensation current or voltage, and then the compensation current or voltage is fed back to the pixel circuit. However, the circuit design of the external chip is complicated and costly.

本發明提供一種半導體裝置，其可變電阻式記憶體具有優異的電阻切換性能。The invention provides a semiconductor device whose variable resistance memory has excellent resistance switching performance.

本發明提供一種半導體裝置的製造方法，其可變電阻式記憶體具有優異的電阻切換性能。The invention provides a manufacturing method of a semiconductor device, the variable resistance memory of which has excellent resistance switching performance.

本發明的至少一實施例提供一種半導體裝置。半導體裝置包括基板、第一薄膜電晶體以及可變電阻式記憶體。第一薄膜電晶體設置於基板之上，且包括第一閘極、第一堆疊結構、第二閘極、源極以及汲極。第一堆疊結構包括互相重疊的第一金屬氧化物層以及第二金屬氧化物層。第一堆疊結構位於第一閘極與第二閘極之間。源極以及汲極電性連接第一堆疊結構。可變電阻式記憶體設置於基板之上，且包括第一電極、第二堆疊結構以及第二電極。第一電極電性連接第一閘極。第二堆疊結構包括互相重疊的第三金屬氧化物層以及第四金屬氧化物層。第二堆疊結構位於第一電極與第二電極之間，且連接第一電極與第二電極。At least one embodiment of the invention provides a semiconductor device. The semiconductor device includes a substrate, a first thin film transistor and a variable resistance memory. The first thin film transistor is disposed on the substrate and includes a first gate, a first stack structure, a second gate, a source and a drain. The first stack structure includes a first metal oxide layer and a second metal oxide layer overlapping each other. The first stack structure is located between the first gate and the second gate. The source and the drain are electrically connected to the first stack structure. The variable resistance memory is disposed on the substrate and includes a first electrode, a second stack structure and a second electrode. The first electrode is electrically connected to the first gate. The second stack structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other. The second stack structure is located between the first electrode and the second electrode, and is connected to the first electrode and the second electrode.

本發明的至少一實施例提供一種半導體裝置的製造方法，包括：形成第一閘極以及第一電極於基板之上；形成第一閘介電層於第一閘極以及第一電極之上，第一閘介電層具有暴露出第一電極的第一開口；形成第一堆疊結構以及第二堆疊結構於第一閘介電層之上，其中第一堆疊結構包括互相重疊的第一金屬氧化物層以及第二金屬氧化物層，且第二堆疊結構包括互相重疊的第三金屬氧化物層以及第四金屬氧化物層，第三金屬氧化物層填入第一開口中；形成第二閘介電層於第一堆疊結構以及第二堆疊結構之上，第二閘介電層具有暴露出第四金屬氧化物層的第二開口；形成第二閘極以及第二電極於第二閘介電層上，其中第一堆疊結構位於第一閘極與第二閘極之間，且第二電極填入第二開口中；形成電性連接第一堆疊結構的源極以及汲極。At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first gate and a first electrode on a substrate; forming a first gate dielectric layer on the first gate and the first electrode, The first gate dielectric layer has a first opening exposing the first electrode; forming a first stacked structure and a second stacked structure on the first gate dielectric layer, wherein the first stacked structure includes overlapping first metal oxides layer and a second metal oxide layer, and the second stack structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other, and the third metal oxide layer is filled in the first opening; forming a second gate The dielectric layer is on the first stack structure and the second stack structure, the second gate dielectric layer has a second opening exposing the fourth metal oxide layer; forming a second gate electrode and a second electrode on the second gate dielectric layer On the electrical layer, wherein the first stack structure is located between the first gate and the second gate, and the second electrode is filled in the second opening; forming a source and a drain electrically connected to the first stack structure.

圖1是依照本發明的一實施例的一種半導體裝置的剖面示意圖。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.

請參考圖1，半導體裝置10A包括基板100、第一薄膜電晶體T1以及可變電阻式記憶體R1。Please refer to FIG. 1 , the semiconductor device 10A includes a substrate 100 , a first thin film transistor T1 and a variable resistance memory R1 .

基板100之材質可為玻璃、石英、有機聚合物或是不透光/反射材料（例如：導電材料、金屬、晶圓、陶瓷或其他可適用的材料）或是其他可適用的材料。若使用導電材料或金屬時，則在基板100上覆蓋一層絕緣層（未繪示），以避免短路問題。在一些實施例中，基板100為軟性基板，且基板100的材料例如為聚乙烯對苯二甲酸酯（polyethylene terephthalate, PET）、聚二甲酸乙二醇酯（polyethylene naphthalate, PEN）、聚酯（polyester, PES）、聚甲基丙烯酸甲酯（polymethylmethacrylate, PMMA）、聚碳酸酯（polycarbonate, PC）、聚醯亞胺(polyimide, PI）或金屬軟板（Metal Foil）或其他可撓性材質。The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials .

第一薄膜電晶體T1以及可變電阻式記憶體R1設置於基板100之上。在一些實施例中，第一薄膜電晶體T1與基板100之間以及可變電阻式記憶體R1與基板100之間還設置有一層或多層緩衝層（未繪示），但本發明不以此為限。第一薄膜電晶體T1包括第一閘極202、第一堆疊結構ST1、第二閘極232、源極242以及汲極244。可變電阻式記憶體R1包括第一電極204、第二堆疊結構ST2以及第二電極234。The first thin film transistor T1 and the variable resistance memory R1 are disposed on the substrate 100 . In some embodiments, one or more buffer layers (not shown) are arranged between the first thin film transistor T1 and the substrate 100 and between the variable resistance memory R1 and the substrate 100, but the present invention does not limit. The first thin film transistor T1 includes a first gate 202 , a first stack structure ST1 , a second gate 232 , a source 242 and a drain 244 . The variable resistance memory R1 includes a first electrode 204 , a second stack structure ST2 and a second electrode 234 .

第一閘極202以及第一電極204設置於基板100之上。在一實施例中，第一閘極202以及第一電極204可以為不易氧化且具有較高功函數(work function)的非活性金屬，例如包括鎢、鉬、鉑、鈀、金、鉬/鋁/鉬或其組合。在一些實施例中，第一閘極202以及第一電極204包括成分相同或不同的材料。在一些實施例中，第一閘極202以及第一電極204包括相同或不同的厚度。在一些實施例中，第一閘極202以及第一電極204屬於同一圖案化層，且第一閘極202以及第一電極204連成一體。The first gate 202 and the first electrode 204 are disposed on the substrate 100 . In one embodiment, the first gate 202 and the first electrode 204 may be inactive metals that are not easily oxidized and have a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum /molybdenum or combinations thereof. In some embodiments, the first gate 202 and the first electrode 204 include the same or different materials. In some embodiments, the first gate 202 and the first electrode 204 include the same or different thicknesses. In some embodiments, the first gate 202 and the first electrode 204 belong to the same patterned layer, and the first gate 202 and the first electrode 204 are integrated.

第一閘介電層110位於第一閘極202以及第一電極204上。第一閘介電層110覆蓋第一閘極202以及第一電極204，且第一閘介電層110具有重疊於第一電極204的第一開口。第一閘介電層110的材料例如為氧化矽、氮化矽、氮氧化矽、氧化鉿或其他合適的材料。The first gate dielectric layer 110 is located on the first gate 202 and the first electrode 204 . The first gate dielectric layer 110 covers the first gate 202 and the first electrode 204 , and the first gate dielectric layer 110 has a first opening overlapping the first electrode 204 . The material of the first gate dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other suitable materials.

第一堆疊結構ST1以及第二堆疊結構ST2位於第一閘介電層110上。第一堆疊結構ST1包括互相重疊的第一金屬氧化物層212以及第二金屬氧化物層222。第二堆疊結構ST2包括互相重疊的第三金屬氧化物層214以及第四金屬氧化物層224。The first stack structure ST1 and the second stack structure ST2 are located on the first gate dielectric layer 110 . The first stack structure ST1 includes a first metal oxide layer 212 and a second metal oxide layer 222 overlapping each other. The second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 overlapping each other.

第一金屬氧化物層212在基板100的頂面的法線方向ND上重疊於第一閘極202，且第三金屬氧化物層214在基板100的頂面的法線方向ND上重疊於第一電極204。第三金屬氧化物層214填入第一閘介電層110的第一開口並連接至第一電極204。在一些實施例中，第三金屬氧化物層214與第一電極204之間具有肖特基接觸。在一些實施例中，第一金屬氧化物層212以及第三金屬氧化物層214屬於同一圖案化層。The first metal oxide layer 212 overlaps the first gate electrode 202 in the normal direction ND of the top surface of the substrate 100, and the third metal oxide layer 214 overlaps the first gate electrode 214 in the normal direction ND of the top surface of the substrate 100. An electrode 204 . The third metal oxide layer 214 fills the first opening of the first gate dielectric layer 110 and is connected to the first electrode 204 . In some embodiments, there is a Schottky contact between the third metal oxide layer 214 and the first electrode 204 . In some embodiments, the first metal oxide layer 212 and the third metal oxide layer 214 belong to the same patterned layer.

第二金屬氧化物層222與第四金屬氧化物層224在基板100的頂面的法線方向ND上分別重疊於第一金屬氧化物層212以及第三金屬氧化物層214。第二金屬氧化物層222包括源極區222a、汲極區222c及位於源極區222a與汲極區222c之間的通道區222b，其中通道區222b在法線方向ND上重疊於第一閘極202。在一些實施例中，源極區222a與汲極區222c經摻雜而具有低於通道區222b的電阻率。在一些實施例中，第四金屬氧化物層224與第二金屬氧化物層222的通道區222b具有實質上相同的電阻率。在一些實施例中，第二金屬氧化物層222與第四金屬氧化物層224屬於同一圖案化層。The second metal oxide layer 222 and the fourth metal oxide layer 224 respectively overlap the first metal oxide layer 212 and the third metal oxide layer 214 in the normal direction ND of the top surface of the substrate 100 . The second metal oxide layer 222 includes a source region 222a, a drain region 222c, and a channel region 222b between the source region 222a and the drain region 222c, wherein the channel region 222b overlaps the first gate in the normal direction ND Pole 202. In some embodiments, the source region 222a and the drain region 222c are doped to have lower resistivity than the channel region 222b. In some embodiments, the fourth metal oxide layer 224 has substantially the same resistivity as the channel region 222 b of the second metal oxide layer 222 . In some embodiments, the second metal oxide layer 222 and the fourth metal oxide layer 224 belong to the same patterned layer.

第一金屬氧化物層212的載子濃度大於第二金屬氧化物層222的通道區222b的載子濃度。第一金屬氧化物層212的氧濃度小於第二金屬氧化物層222的通道區222b的氧濃度。在一些實施例中，第一金屬氧化物層212的氧濃度為10at%至50at%，且第二金屬氧化物層222的通道區222b的氧濃度為30at%至70at%。在一些實施例中，藉由調整氧濃度，使第一金屬氧化物層212的能隙（Band Gap）小於第二金屬氧化物層222的能隙，藉此於第一金屬氧化物層212以及第二金屬氧化物層222之間的界面形成二維電子氣2DEG。第二金屬氧化物層222的厚度t2小於或等於第一金屬氧化物層212的厚度t1，藉此使二維電子氣2DEG更容易的形成於前述界面。在一些實施例中，第一金屬氧化物層212的厚度t1為10奈米至50奈米，第二金屬氧化物層222的厚度t2為5奈米至50奈米。在一些實施例中，第一金屬氧化物層212以及第二金屬氧化物層222的材料包括銦鎵鋅氧化物、銦錫鋅氧化物、鋁鋅錫氧化物、銦鎢鋅氧化物等四元化合物或包含前述四元化合物中的其中兩種金屬元素以及氧元素的三元化合物。The carrier concentration of the first metal oxide layer 212 is greater than the carrier concentration of the channel region 222 b of the second metal oxide layer 222 . The oxygen concentration of the first metal oxide layer 212 is smaller than the oxygen concentration of the channel region 222 b of the second metal oxide layer 222 . In some embodiments, the oxygen concentration of the first metal oxide layer 212 is 10 at % to 50 at %, and the oxygen concentration of the channel region 222 b of the second metal oxide layer 222 is 30 at % to 70 at %. In some embodiments, by adjusting the oxygen concentration, the energy gap (Band Gap) of the first metal oxide layer 212 is smaller than the energy gap of the second metal oxide layer 222, whereby the first metal oxide layer 212 and the The interface between the second metal oxide layers 222 forms a two-dimensional electron gas 2DEG. The thickness t2 of the second metal oxide layer 222 is smaller than or equal to the thickness t1 of the first metal oxide layer 212 , so that the two-dimensional electron gas 2DEG can be formed at the aforementioned interface more easily. In some embodiments, the thickness t1 of the first metal oxide layer 212 is 10 nm to 50 nm, and the thickness t2 of the second metal oxide layer 222 is 5 nm to 50 nm. In some embodiments, the materials of the first metal oxide layer 212 and the second metal oxide layer 222 include quaternary elements such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, etc. compound or a ternary compound containing two metal elements and oxygen in the aforementioned quaternary compounds.

第三金屬氧化物層214的載子濃度大於第四金屬氧化物層224的載子濃度。第三金屬氧化物層214的氧濃度小於第四金屬氧化物層224的氧濃度。在一些實施例中，第三金屬氧化物層214的氧濃度為10at%至50at%，且第四金屬氧化物層224的氧濃度為30at%至70at%。在一些實施例中，對第二堆疊結構ST2施加電壓可以使第二堆疊結構ST2在不同電阻率的狀態之間進行切換，換句話說，第二堆疊結構ST2具有多個不同電阻率的狀態。由於第三金屬氧化物層214的載子濃度不同於第四金屬氧化物層224的載子濃度，第二堆疊結構ST2的不同狀態的電阻率為漸變的，換句話說，可變電阻式記憶體R1可以儲存單級單元、多級單元、三級單元、四級單元甚至為類比資訊。第四金屬氧化物層224的厚度t2小於或等於第三金屬氧化物層214的厚度t1。在一些實施例中，第三金屬氧化物層214的厚度t1為10奈米至50奈米，第四金屬氧化物層224的厚度t2為5奈米至50奈米。在一些實施例中，第三金屬氧化物層214以及第四金屬氧化物層224的材料包括銦鎵鋅氧化物、銦錫鋅氧化物、鋁鋅錫氧化物、銦鎢鋅氧化物等四元化合物或包含前述四元化合物中的其中兩種金屬元素以及氧元素的三元化合物。The carrier concentration of the third metal oxide layer 214 is greater than the carrier concentration of the fourth metal oxide layer 224 . The oxygen concentration of the third metal oxide layer 214 is smaller than the oxygen concentration of the fourth metal oxide layer 224 . In some embodiments, the oxygen concentration of the third metal oxide layer 214 is 10 at % to 50 at %, and the oxygen concentration of the fourth metal oxide layer 224 is 30 at % to 70 at %. In some embodiments, applying a voltage to the second stack structure ST2 can switch the second stack structure ST2 between states with different resistivities. In other words, the second stack structure ST2 has a plurality of states with different resistivities. Since the carrier concentration of the third metal oxide layer 214 is different from that of the fourth metal oxide layer 224, the resistivity of the different states of the second stack structure ST2 changes gradually, in other words, the variable resistance memory The volume R1 can store single-level units, multi-level units, three-level units, four-level units and even analog information. The thickness t2 of the fourth metal oxide layer 224 is less than or equal to the thickness t1 of the third metal oxide layer 214 . In some embodiments, the thickness t1 of the third metal oxide layer 214 is 10 nm to 50 nm, and the thickness t2 of the fourth metal oxide layer 224 is 5 nm to 50 nm. In some embodiments, the materials of the third metal oxide layer 214 and the fourth metal oxide layer 224 include quaternary elements such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, etc. compound or a ternary compound containing two metal elements and oxygen in the aforementioned quaternary compounds.

第二閘介電層120覆蓋第一堆疊結構ST1以及第二堆疊結構ST2，且第二閘介電層120具有重疊於第二堆疊結構ST2的第二開口。第二閘介電層120的材料例如為氧化矽、氮化矽、氮氧化矽、氧化鉿或其他合適的材料。The second gate dielectric layer 120 covers the first stack structure ST1 and the second stack structure ST2, and the second gate dielectric layer 120 has a second opening overlapping the second stack structure ST2. The material of the second gate dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide or other suitable materials.

第二閘極232以及第二電極234設置於第二閘介電層120之上。第二閘極232在基板100的頂面的法線方向ND上重疊於第三金屬氧化物層222的通道區222b。第一堆疊結構ST1位於第一閘極202與第二閘極232之間。第二電極234在基板100的頂面的法線方向ND上重疊於第四金屬氧化物層224。第二電極234填入第二閘介電層120的第二開口並連接至第四金屬氧化物層224。在一些實施例中，第二電極234與第四金屬氧化物層224之間具有肖特基接觸。第二堆疊結構ST2位於第一電極204與第二電極234之間，且連接第一電極204與第二電極234。The second gate 232 and the second electrode 234 are disposed on the second gate dielectric layer 120 . The second gate 232 overlaps the channel region 222 b of the third metal oxide layer 222 in the normal direction ND of the top surface of the substrate 100 . The first stack structure ST1 is located between the first gate 202 and the second gate 232 . The second electrode 234 overlaps the fourth metal oxide layer 224 in the normal direction ND of the top surface of the substrate 100 . The second electrode 234 fills the second opening of the second gate dielectric layer 120 and is connected to the fourth metal oxide layer 224 . In some embodiments, there is a Schottky contact between the second electrode 234 and the fourth metal oxide layer 224 . The second stack structure ST2 is located between the first electrode 204 and the second electrode 234 and is connected to the first electrode 204 and the second electrode 234 .

在一實施例中，第二閘極232以及第二電極234可以為不易氧化且具有較高功函數(work function)的非活性金屬，例如包括鎢、鉬、鉑、鈀、金、鉬/鋁/鉬或其組合。在一些實施例中，第二閘極232以及第二電極234包括成分相同或不同的材料。在一些實施例中，第二閘極232以及第二電極234包括相同或不同的厚度。在一些實施例中，第二閘極232以及第二電極234屬於同一圖案化層，第二閘極232以及第二電極234彼此分離。In one embodiment, the second gate 232 and the second electrode 234 may be inactive metals that are not easily oxidized and have a relatively high work function, such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum /molybdenum or combinations thereof. In some embodiments, the second gate 232 and the second electrode 234 include the same or different materials. In some embodiments, the second gate 232 and the second electrode 234 include the same or different thicknesses. In some embodiments, the second gate 232 and the second electrode 234 belong to the same patterned layer, and the second gate 232 and the second electrode 234 are separated from each other.

層間介電層130設置於第二閘極232以及第二電極234之上，且覆蓋第二閘極232以及第二電極234。層間介電層130的材料例如為氧化矽、氮化矽、氮氧化矽或其他合適的材料。The interlayer dielectric layer 130 is disposed on the second gate 232 and the second electrode 234 and covers the second gate 232 and the second electrode 234 . The material of the interlayer dielectric layer 130 is, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

源極242以及汲極244位於層間介電層130上，且分別填入貫穿層間介電層130以及第二閘介電層120的開口而電性連接至第一堆疊結構ST1。在一些實施例中，源極242以及汲極244分別電性連接至第二金屬氧化物層222的源極區222a及汲極區222c。另外，源極242還填入貫穿層間介電層130的開口而電性連接至第二電極234。The source electrode 242 and the drain electrode 244 are located on the interlayer dielectric layer 130 , and respectively fill the openings penetrating the interlayer dielectric layer 130 and the second gate dielectric layer 120 to be electrically connected to the first stack structure ST1 . In some embodiments, the source 242 and the drain 244 are electrically connected to the source region 222 a and the drain region 222 c of the second metal oxide layer 222 , respectively. In addition, the source electrode 242 also fills the opening penetrating through the interlayer dielectric layer 130 and is electrically connected to the second electrode 234 .

基於上述，半導體裝置10A的第一薄膜電晶體T1中具有二維電子氣2DEG，因此可以提升第一薄膜電晶體T1的輸出電流大小。另外，可變電阻式記憶體R1中的第二堆疊結構ST2包括載子濃度不同的第三金屬氧化物層214以及第四金屬氧化物層224，因此可變電阻式記憶體R1可以儲存類比資訊。此外，可變電阻式記憶體R1的第一電極204電性連接第一薄膜電晶體T1的第一閘極202，因此，第一閘極202可以作為屏蔽電極，用於阻擋外界電場對第一薄膜電晶體T1造成的不良影響。Based on the above, the first thin film transistor T1 of the semiconductor device 10A has a two-dimensional electron gas 2DEG, so the output current of the first thin film transistor T1 can be increased. In addition, the second stack structure ST2 in the variable resistance memory R1 includes the third metal oxide layer 214 and the fourth metal oxide layer 224 with different carrier concentrations, so the variable resistance memory R1 can store analog information . In addition, the first electrode 204 of the variable resistance memory R1 is electrically connected to the first gate 202 of the first thin film transistor T1, therefore, the first gate 202 can be used as a shielding electrode for blocking the external electric field from affecting the first Adverse effects caused by thin film transistor T1.

圖2A至圖2H是圖1的半導體裝置的製造方法的剖面示意圖。2A to 2H are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 .

請參考圖2A，形成第一閘極202以及第一電極204於基板100之上。在一些實施例中，形成第一閘極202以及第一電極204的方法包括以下步驟：首先，在基板100上形成毯覆的導電材料層（未繪示）；接著，利用微影製程，在導電材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對導電材料層進行濕式或乾式蝕刻製程，以形成第一閘極202以及第一電極204；之後，移除圖案化光阻。換句話說，第一閘極202以及第一電極204例如為同時形成。Referring to FIG. 2A , a first gate 202 and a first electrode 204 are formed on the substrate 100 . In some embodiments, the method for forming the first gate 202 and the first electrode 204 includes the following steps: firstly, forming a blanket conductive material layer (not shown) on the substrate 100; Forming a patterned photoresist (not shown) on the conductive material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the conductive material layer to form the first gate 202 and the first electrode 204; after that, remove the patterned photoresist. In other words, for example, the first gate 202 and the first electrode 204 are formed simultaneously.

請參考圖2B，形成第一閘介電層110於第一閘極202以及第一電極204之上。第一閘介電層110具有暴露出第一電極204的第一開口O1。Referring to FIG. 2B , a first gate dielectric layer 110 is formed on the first gate 202 and the first electrode 204 . The first gate dielectric layer 110 has a first opening O1 exposing the first electrode 204 .

請參考圖2C與圖2D，形成第一堆疊結構ST1’以及第二堆疊結構ST2於第一閘介電層110之上。第一堆疊結構ST1’包括互相重疊的第一金屬氧化物層212以及第二金屬氧化物層222’，且第二堆疊結構ST2包括互相重疊的第三金屬氧化物層214以及第四金屬氧化物層224。Referring to FIG. 2C and FIG. 2D , a first stack structure ST1' and a second stack structure ST2 are formed on the first gate dielectric layer 110. Referring to FIG. The first stack structure ST1' includes a first metal oxide layer 212 and a second metal oxide layer 222' overlapping each other, and the second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer overlapping each other. Layer 224.

形成第一堆疊結構ST1’以及第二堆疊結構ST2的方法包括：如圖2C所示，形成第一金屬氧化物層212以及第三金屬氧化物層214於第一閘介電層110之上，其中第三金屬氧化物層214填入第一閘介電層110的第一開口O1中，以接觸第一電極204。接著如圖2D所示，形成第二金屬氧化物層222’以及第四金屬氧化物層224於第一金屬氧化物層212以及第三金屬氧化物層214上。The method for forming the first stack structure ST1' and the second stack structure ST2 includes: as shown in FIG. 2C , forming a first metal oxide layer 212 and a third metal oxide layer 214 on the first gate dielectric layer 110, The third metal oxide layer 214 is filled into the first opening O1 of the first gate dielectric layer 110 to contact the first electrode 204 . Next, as shown in FIG. 2D , a second metal oxide layer 222 ′ and a fourth metal oxide layer 224 are formed on the first metal oxide layer 212 and the third metal oxide layer 214 .

在一些實施例中，形成第一金屬氧化物層212以及第三金屬氧化物層214的方法包括以下步驟：首先，在第一閘介電層110上形成毯覆的半導體材料層（未繪示）；接著，利用微影製程，在半導體材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對半導體材料層進行濕式或乾式蝕刻製程，以形成第一金屬氧化物層212以及第三金屬氧化物層214；之後，移除圖案化光阻。換句話說，第一金屬氧化物層212以及第三金屬氧化物層214例如為同時形成。In some embodiments, the method for forming the first metal oxide layer 212 and the third metal oxide layer 214 includes the following steps: first, forming a blanket semiconductor material layer (not shown) on the first gate dielectric layer 110 ); then, using a lithography process to form a patterned photoresist (not shown) on the semiconductor material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the semiconductor material layer, to form the first metal oxide layer 212 and the third metal oxide layer 214; after that, the patterned photoresist is removed. In other words, the first metal oxide layer 212 and the third metal oxide layer 214 are formed simultaneously, for example.

在一些實施例中，形成第二金屬氧化物層222’以及第四金屬氧化物層224的方法包括以下步驟：首先，在第一閘介電層110、第一金屬氧化物層212以及第三金屬氧化物層214上形成毯覆的半導體材料層（未繪示）；接著，利用微影製程，在半導體材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對半導體材料層進行濕式或乾式蝕刻製程，以形成第二金屬氧化物層222’以及第四金屬氧化物層224；之後，移除圖案化光阻。換句話說，第二金屬氧化物層222’以及第四金屬氧化物層224例如為同時形成。In some embodiments, the method for forming the second metal oxide layer 222 ′ and the fourth metal oxide layer 224 includes the following steps: first, on the first gate dielectric layer 110 , the first metal oxide layer 212 and the third A blanket semiconductor material layer (not shown) is formed on the metal oxide layer 214; then, a patterned photoresist (not shown) is formed on the semiconductor material layer by using a lithography process; As a mask, a wet or dry etching process is performed on the semiconductor material layer to form the second metal oxide layer 222 ′ and the fourth metal oxide layer 224 ; after that, the patterned photoresist is removed. In other words, the second metal oxide layer 222' and the fourth metal oxide layer 224 are formed simultaneously, for example.

在其他實施例中，形成第一堆疊結構ST1’以及第二堆疊結構ST2的方法包括一次的微影蝕刻製程。舉例來說，在第一閘介電層110上形成兩層毯覆的半導體材料層；接著，利用微影製程，在半導體材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對半導體材料層進行濕式或乾式蝕刻製程，以形成第一堆疊結構ST1’以及第二堆疊結構ST2；之後，移除圖案化光阻。In other embodiments, the method for forming the first stack structure ST1' and the second stack structure ST2 includes a lithography etching process once. For example, two blanket semiconductor material layers are formed on the first gate dielectric layer 110; then, a patterned photoresist (not shown) is formed on the semiconductor material layer by using a lithography process; The patterned photoresist is used as a mask to perform wet or dry etching process on the semiconductor material layer to form the first stack structure ST1 ′ and the second stack structure ST2; after that, the patterned photoresist is removed.

請參考圖2E，形成第二閘介電層120於第一堆疊結構ST1’以及第二堆疊結構ST2之上，第二閘介電層120具有暴露出第四金屬氧化物層224的第二開口O2。2E, a second gate dielectric layer 120 is formed on the first stack structure ST1' and the second stack structure ST2, the second gate dielectric layer 120 has a second opening exposing the fourth metal oxide layer 224 O2.

請參考圖2F，形成第二閘極232以及第二電極234於第二閘介電層120上。第二電極234填入第二閘介電層120的第二開口O2中，以接觸第四金屬氧化物層224。Referring to FIG. 2F , a second gate 232 and a second electrode 234 are formed on the second gate dielectric layer 120 . The second electrode 234 is filled into the second opening O2 of the second gate dielectric layer 120 to contact the fourth metal oxide layer 224 .

接著，以第二閘極232以及第二電極234為遮罩，對第二金屬氧化物層222’進行摻雜製程P，以形成包括源極區222a、通道區222b與汲極區222c的第二金屬氧化物層222。在一些實施例中，摻雜製程P包括氫電漿製程或離子植入製程。在本實施例中，由於第四金屬氧化物層224被第二電極234所覆蓋，摻雜製程P不會對第四金屬氧化物層224進行摻雜。Next, using the second gate 232 and the second electrode 234 as a mask, the doping process P is performed on the second metal oxide layer 222 ′ to form a first region including the source region 222 a , the channel region 222 b and the drain region 222 c. Two metal oxide layers 222 . In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process. In this embodiment, since the fourth metal oxide layer 224 is covered by the second electrode 234 , the doping process P does not dope the fourth metal oxide layer 224 .

請參考圖2G，形成層間介電層130於第二閘介電層120、第二閘極232以及第二電極234之上。在一些實施例中，層間介電層130為不含氫的絕緣層，藉此避免層間介電層130中的氫原子擴散至第一堆疊結構ST1以及第二堆疊結構ST2，但本發明不以此為限。在一些實施例中，層間介電層130中含有氫原子，因此，可以藉由熱處理使氫原子擴散至第一堆疊結構ST1中，以調整第一堆疊結構ST1的電阻率。在一些實施例中，當使用層間介電層130中的氫原子進行第一堆疊結構ST1的摻雜時，可以省略圖2F的摻雜製程P。Referring to FIG. 2G , an interlayer dielectric layer 130 is formed on the second gate dielectric layer 120 , the second gate electrode 232 and the second electrode 234 . In some embodiments, the interlayer dielectric layer 130 is an insulating layer that does not contain hydrogen, thereby preventing the hydrogen atoms in the interlayer dielectric layer 130 from diffusing into the first stack structure ST1 and the second stack structure ST2, but the present invention does not rely on This is the limit. In some embodiments, the interlayer dielectric layer 130 contains hydrogen atoms, so the hydrogen atoms can be diffused into the first stack structure ST1 by heat treatment, so as to adjust the resistivity of the first stack structure ST1. In some embodiments, when hydrogen atoms in the interlayer dielectric layer 130 are used for doping the first stacked structure ST1, the doping process P of FIG. 2F may be omitted.

請參考圖2H，形成開口V1、V2、V3，方法包括以下步驟：首先，利用微影製程，在層間介電層130上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來進行濕式或乾式蝕刻製程，以於層間介電層130以及第二閘介電層120中形成開口V1、V2，同時於層間介電層130中形成開口V3；之後，移除圖案化光阻。開口V1、V2分別暴露出第二金屬氧化物層222的汲極區222c以及源極區222a，開口V3暴露出第二電極234。Please refer to FIG. 2H , forming the openings V1, V2, V3, the method includes the following steps: first, using a lithography process, forming a patterned photoresist (not shown) on the interlayer dielectric layer 130; The resist is used as a mask to perform a wet or dry etching process to form openings V1, V2 in the interlayer dielectric layer 130 and the second gate dielectric layer 120, and simultaneously form an opening V3 in the interlayer dielectric layer 130; after that, Remove the patterned photoresist. The openings V1 and V2 respectively expose the drain region 222 c and the source region 222 a of the second metal oxide layer 222 , and the opening V3 exposes the second electrode 234 .

最後請回到圖1，形成汲極244以及源極242於層間介電層130上。汲極244以及源極242分別填入開口V1、V2以電性連接汲極區222c以及源極區222a。此外，源極242還填入開口V3中以電性連接第二電極234。在一些實施例中，形成汲極244以及源極242的方法包括以下步驟：首先，在層間介電層130上形成毯覆的導電材料層（未繪示）；接著，利用微影製程，在導電材料層上形成圖案化光阻（未繪示）；繼之，利用圖案化光阻作為罩幕，來對導電材料層進行濕式或乾式蝕刻製程，以形成汲極244以及源極242；之後，移除圖案化光阻。換句話說，汲極244以及源極242例如為同時形成。Finally, please return to FIG. 1 , forming the drain 244 and the source 242 on the interlayer dielectric layer 130 . The drain 244 and the source 242 respectively fill the openings V1 and V2 to electrically connect the drain region 222c and the source region 222a. In addition, the source electrode 242 is also filled into the opening V3 to be electrically connected to the second electrode 234 . In some embodiments, the method for forming the drain electrode 244 and the source electrode 242 includes the following steps: first, forming a blanket conductive material layer (not shown) on the interlayer dielectric layer 130; forming a patterned photoresist (not shown) on the conductive material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the conductive material layer to form the drain 244 and the source 242; Afterwards, the patterned photoresist is removed. In other words, the drain 244 and the source 242 are formed simultaneously, for example.

經過上述製程後可大致上完成主動元件基板10A的製作。After the above process, the fabrication of the active device substrate 10A can be substantially completed.

圖3是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It must be noted here that the embodiment in FIG. 3 uses the component numbers and parts of the content in the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖3的半導體裝置10B與圖1的半導體裝置10A的主要差異在於：半導體裝置10B的汲極244與源極242延伸穿過第二金屬氧化物層222。The main difference between the semiconductor device 10B of FIG. 3 and the semiconductor device 10A of FIG. 1 is that the drain 244 and the source 242 of the semiconductor device 10B extend through the second metal oxide layer 222 .

請參考圖3，汲極244與源極242延伸穿過第二金屬氧化物層222，並接觸第一金屬氧化物層212以及第二金屬氧化物層222的界面。換句話說，汲極244與源極242直接接觸二維電子氣2DEG，藉此提升第一薄膜電晶體T1的輸出電流大小。Referring to FIG. 3 , the drain 244 and the source 242 extend through the second metal oxide layer 222 and contact the interface of the first metal oxide layer 212 and the second metal oxide layer 222 . In other words, the drain 244 and the source 242 directly contact the two-dimensional electron gas 2DEG, thereby increasing the output current of the first thin film transistor T1.

圖4是依照本發明的一實施例的一種半導體裝置的剖面示意圖。在此必須說明的是，圖4的實施例沿用圖1的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 4 follows the component numbers and partial content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

圖4的半導體裝置10C與圖1的半導體裝置10A的主要差異在於：半導體裝置10C的第一金屬氧化物層212包括第一摻雜區212a以及第二摻雜區212c。The main difference between the semiconductor device 10C of FIG. 4 and the semiconductor device 10A of FIG. 1 is that the first metal oxide layer 212 of the semiconductor device 10C includes a first doped region 212 a and a second doped region 212 c.

在本實施例中，執行摻雜製程以於第二金屬氧化物層222中形成源極區222a以及汲極區222c，且摻雜製程於第一金屬氧化物層212中形成第一摻雜區212a以及第二摻雜區212c。換句話說，摻雜製程中的摻子（例如氫原子）穿過第二金屬氧化物層222後抵達第一金屬氧化物層212，並於第一金屬氧化物層212中形成第一摻雜區212a以及第二摻雜區212c。第一摻雜區212a以及第二摻雜區212c分別接觸源極區222c以及汲極區222a的底部。In this embodiment, the doping process is performed to form the source region 222a and the drain region 222c in the second metal oxide layer 222, and the doping process forms the first doped region in the first metal oxide layer 212 212a and the second doped region 212c. In other words, the dopant (such as hydrogen atom) in the doping process reaches the first metal oxide layer 212 after passing through the second metal oxide layer 222, and forms the first dopant in the first metal oxide layer 212. region 212a and the second doped region 212c. The first doped region 212a and the second doped region 212c are in contact with bottoms of the source region 222c and the drain region 222a respectively.

在一些實施例中，第一摻雜區212a的厚度以及第二摻雜區212c的厚度小於第一金屬氧化物層212的厚度。In some embodiments, the thickness of the first doped region 212 a and the thickness of the second doped region 212 c are smaller than the thickness of the first metal oxide layer 212 .

在一些實施例中，源極區222a、汲極區222c、第一摻雜區212a以及第二摻雜區212c的寬度隨著靠近基板100而逐漸縮小。源極區222a以及汲極區222c朝向通道區222b的面為弧面。In some embodiments, the widths of the source region 222 a , the drain region 222 c , the first doped region 212 a and the second doped region 212 c gradually shrink as they approach the substrate 100 . The surfaces of the source region 222a and the drain region 222c facing the channel region 222b are arc surfaces.

圖5是依照本發明的一實施例的一種畫素電路PX的等效電路示意圖。圖5的畫素電路PX例如包括前述任一實施例中的半導體裝置。FIG. 5 is a schematic diagram of an equivalent circuit of a pixel circuit PX according to an embodiment of the present invention. The pixel circuit PX in FIG. 5 includes, for example, the semiconductor device in any of the aforementioned embodiments.

請參考圖5，畫素電路PX包括第一薄膜電晶體T1、可變電阻式記憶體R1、第二薄膜電晶體T2、第三薄膜電晶體T3、儲存電容Cst及發光元件EL。Please refer to FIG. 5 , the pixel circuit PX includes a first thin film transistor T1 , a variable resistance memory R1 , a second thin film transistor T2 , a third thin film transistor T3 , a storage capacitor Cst and a light emitting element EL.

第二薄膜電晶體T2可作為開關電晶體使用。第二薄膜電晶體T2的閘極電性連接於電壓V S1(例如為掃描線電壓)，第二薄膜電晶體T2的汲極（或源極）電性連接於電壓V data(例如為資料線電壓)，第二薄膜電晶體T2的源極（或汲極）電性連接於第一節點a。 The second thin film transistor T2 can be used as a switching transistor. The gate of the second thin film transistor T2 is electrically connected to the voltage V S1 (for example, the scan line voltage), and the drain (or source) of the second thin film transistor T2 is electrically connected to the voltage V data (for example, the data line Voltage), the source (or drain) of the second TFT T2 is electrically connected to the first node a.

第一薄膜電晶體T1可作為驅動電晶體使用。第一薄膜電晶體T1的第二閘極電性連接於第一節點a。第一薄膜電晶體T1的汲極電性連接於電壓V DD，第一薄膜電晶體T1的源極電性連接於可變電阻式記憶體R1的一端（第二電極）。第一薄膜電晶體T1的第一閘極以及可變電阻式記憶體R1的另一端（第一電極）電性連接至第二節點b。 The first thin film transistor T1 can be used as a driving transistor. The second gate of the first TFT T1 is electrically connected to the first node a. The drain of the first thin film transistor T1 is electrically connected to the voltage V DD , and the source of the first thin film transistor T1 is electrically connected to one terminal (the second electrode) of the variable resistance memory R1 . The first gate of the first thin film transistor T1 and the other end (first electrode) of the variable resistance memory R1 are electrically connected to the second node b.

第三薄膜電晶體T3例如可作為感測電晶體使用。第三薄膜電晶體T3的閘極電性連接於電壓V S2，第三薄膜電晶體T3的汲極電性連接於第三節點c，第三薄膜電晶體T3的源極電性連接於電壓V sus。電壓V S2用於控制第三薄膜電晶體T3的開關，以透過第三薄膜電晶體T3將驅動電流的資訊傳送給外部晶片。 The third thin film transistor T3 can be used as a sensing transistor, for example. The gate of the third thin film transistor T3 is electrically connected to the voltage V S2 , the drain of the third thin film transistor T3 is electrically connected to the third node c, and the source of the third thin film transistor T3 is electrically connected to the voltage V sus . The voltage V S2 is used to control the switch of the third thin film transistor T3 so as to transmit the driving current information to the external chip through the third thin film transistor T3 .

儲存電容Cst的一端電性連接於第一節點a，儲存電容Cst的另一端電性連接於第三節點c。第二節點b與第三節點c電性相連。由於第一薄膜電晶體T1的第二閘極電性連接至儲存電容Cst，即使關閉第二薄膜電晶體T2，第一薄膜電晶體T1仍可持續導通一小段時間。One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the third node c. The second node b is electrically connected to the third node c. Since the second gate of the first thin film transistor T1 is electrically connected to the storage capacitor Cst, even if the second thin film transistor T2 is turned off, the first thin film transistor T1 can still be turned on for a short period of time.

發光元件EL的一端電性連接於第二節點b，發光元件EL的另一端電性連接於電壓V SS。發光元件EL的亮度會因為通過第一薄膜電晶體T1之驅動電流的大小不同而改變。發光元件EL例如是微型發光二極體、有機發光二極體或其他發光元件。 One end of the light emitting element EL is electrically connected to the second node b, and the other end of the light emitting element EL is electrically connected to the voltage V SS . The brightness of the light emitting element EL will vary due to the magnitude of the driving current passing through the first thin film transistor T1. The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting elements.

在本實施例中，在第一節點a處，第二薄膜電晶體T2的源極（或汲極）、第一薄膜電晶體T1的第二閘極以及儲存電容Cst的一端彼此電性連接。在第二節點b處，第一薄膜電晶體T1的第一閘極以及可變電阻式記憶體R1的另一端彼此電性連接。在第三節點c處，第三薄膜電晶體T3的汲極以及儲存電容Cst的另一端彼此電性連接。第三薄膜電晶體T3的汲極透過第三節點c以及第二節點b而電性連接至可變電阻式記憶體R1的另一端以及第一薄膜電晶體T1的第一閘極。In this embodiment, at the first node a, the source (or drain) of the second TFT T2 , the second gate of the first TFT T1 and one end of the storage capacitor Cst are electrically connected to each other. At the second node b, the first gate of the first thin film transistor T1 and the other end of the variable resistance memory R1 are electrically connected to each other. At the third node c, the drain of the third TFT T3 and the other end of the storage capacitor Cst are electrically connected to each other. The drain of the third thin film transistor T3 is electrically connected to the other end of the variable resistance memory R1 and the first gate of the first thin film transistor T1 through the third node c and the second node b.

圖6是依照本發明的一實施例的一種顯示裝置在圖5的畫素電路設置下的畫素補償操作流程圖。FIG. 6 is a flowchart of a pixel compensation operation of a display device under the setting of the pixel circuit in FIG. 5 according to an embodiment of the present invention.

以下簡述顯示裝置在畫素電路PX的設置下，畫素補償的操作方式，請同時參考圖5及圖6。首先，顯示裝置為關閉狀態，使畫素電路PX在背景執行灰階(grey level)感測。灰階感測的方式例如是將第一薄膜電晶體T1、第二薄膜電晶體T2及第三薄膜電晶體T3開啟，以使通過第一薄膜電晶體T1的驅動電流可以透過第三半導體元件T3傳送給外部晶片。The following briefly describes the operation mode of the pixel compensation of the display device under the setting of the pixel circuit PX, please refer to FIG. 5 and FIG. 6 at the same time. First, the display device is turned off, so that the pixel circuit PX performs gray level sensing in the background. The way of grayscale sensing is, for example, to turn on the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3, so that the driving current passing through the first thin film transistor T1 can pass through the third semiconductor element T3 sent to the external chip.

接著，外部晶片透過訊號處理及演算，建立出對應模型，進而計算出對應的補償資訊。之後，再將補償資訊寫入畫素電路PX中。舉例來說，開啟第一薄膜電晶體T1、第二薄膜電晶體T2及第三薄膜電晶體T3，以將外部晶片計算出的補償資訊寫入可變電阻式記憶體R1中。具體地說，透過可變電阻式記憶體R1的第一電極與第二電極之間的電壓差來改變可變電阻式記憶體R1的電阻值。Then, the external chip establishes a corresponding model through signal processing and calculation, and then calculates the corresponding compensation information. Afterwards, the compensation information is written into the pixel circuit PX. For example, the first thin film transistor T1 , the second thin film transistor T2 and the third thin film transistor T3 are turned on to write the compensation information calculated by the external chip into the variable resistance memory R1 . Specifically, the resistance value of the variable resistance memory R1 is changed through the voltage difference between the first electrode and the second electrode of the variable resistance memory R1.

接著，開啟顯示裝置。由於補償資訊已經寫入可變電阻式記憶體R1，通過第一薄膜電晶體T1以及可變電阻式記憶體R1的驅動電流的大小可以被調整，進而達成畫素補償的功能。在一些實施例中，在開啟顯示裝置時，第三薄膜電晶體T3為關斷狀態。Next, turn on the display device. Since the compensation information has been written into the variable resistance memory R1, the magnitude of the driving current passing through the first thin film transistor T1 and the variable resistance memory R1 can be adjusted, thereby achieving the function of pixel compensation. In some embodiments, when the display device is turned on, the third thin film transistor T3 is in an off state.

綜上所述，本發明的可變電阻式記憶體R1具有記憶體的功能，因而不需要在外部晶片中設置補償記憶體，使整體系統簡化、成本降低。此外，由於可變電阻式記憶體R1可以儲存類比資訊，可以更精細的調整不同位置處的畫素的驅動電流，以改善畫面不均勻的問題。To sum up, the variable resistance memory R1 of the present invention has the function of a memory, so there is no need to install a compensation memory in an external chip, which simplifies the overall system and reduces the cost. In addition, since the variable resistive memory R1 can store analog information, the driving current of pixels at different positions can be finely adjusted to improve the unevenness of the picture.

10A,10B,10C:半導體裝置 100:基板 110:第一閘介電層 120:第二閘介電層 130:層間介電層 2DEG:二維電子氣 202:第一閘極 204:第一電極 212:第一金屬氧化物層 212a:第一摻雜區 212c:第二摻雜區 214:第三金屬氧化物層 222,222’:第二金屬氧化物層 222a:源極區 222b:通道區 222c:汲極區 224:第四金屬氧化物層 232:第二閘極 234:第二電極 242:源極 244:汲極 a:第一節點 b:第二節點 c:第三節點 Cst:儲存電容 EL:發光元件 ND:法線方向 P:摻雜製程 PX:畫素電路 O1:第一開口 O2:第二開口 R1:可變電阻式記憶體 ST1,ST1’:第一堆疊結構 ST2:第二堆疊結構 T1:第一薄膜電晶體 T2:第二薄膜電晶體 T3:第三薄膜電晶體 t1,t2:厚度 V1,V2,V3:開口 V S1,V data,V DD,V S2,V sus,V SS:電壓10A, 10B, 10C: semiconductor device 100: substrate 110: first gate dielectric layer 120: second gate dielectric layer 130: interlayer dielectric layer 2DEG: two-dimensional electron gas 202: first gate electrode 204: first electrode 212: first metal oxide layer 212a: first doped region 212c: second doped region 214: third metal oxide layer 222, 222': second metal oxide layer 222a: source region 222b: channel region 222c: Drain region 224: fourth metal oxide layer 232: second gate 234: second electrode 242: source 244: drain a: first node b: second node c: third node Cst: storage capacitor EL : light-emitting element ND: normal direction P: doping process PX: pixel circuit O1: first opening O2: second opening R1: variable resistance memory ST1, ST1': first stack structure ST2: second stack Structure T1: first thin film transistor T2: second thin film transistor T3: third thin film transistor t1, t2: thickness V1, V2, V3: opening V S1 , V data , V DD , V S2 , V sus , V SS : Voltage

圖1是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 圖2A至圖2H是圖1的半導體裝置的製造方法的剖面示意圖。 圖3是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 圖4是依照本發明的一實施例的一種半導體裝置的剖面示意圖。 圖5是依照本發明的一實施例的一種畫素電路的等效電路示意圖。 圖6是依照本發明的一實施例的一種顯示裝置在圖5的畫素電路設置下的畫素補償操作流程圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. 2A to 2H are schematic cross-sectional views of the manufacturing method of the semiconductor device of FIG. 1 . FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention. FIG. 6 is a flowchart of a pixel compensation operation of a display device under the setting of the pixel circuit in FIG. 5 according to an embodiment of the present invention.

a:第一節點 a: the first node

b:第二節點 b: the second node

c:第三節點 c: the third node

Cst:儲存電容 Cst: storage capacitor

EL:發光元件 EL: light emitting element

PX:畫素電路 PX: pixel circuit

R1:可變電阻式記憶體 R1: variable resistance memory

T1:第一薄膜電晶體 T1: The first thin film transistor

T2:第二薄膜電晶體 T2: Second thin film transistor

T3:第三薄膜電晶體 T3: The third thin film transistor

VS1,Vdata,VDD,VS2,Vsus,VSS:電壓 V S1 , V data , V DD , V S2 , V sus , V SS : Voltage

Claims (15)

一種半導體裝置，包括： 一基板； 一第一薄膜電晶體，設置於該基板之上，且包括： 一第一閘極； 一第一堆疊結構，包括互相重疊的一第一金屬氧化物層以及一第二金屬氧化物層； 一第二閘極，其中該第一堆疊結構位於該第一閘極與該第二閘極之間；以及 一源極以及一汲極，電性連接該第一堆疊結構；以及 一可變電阻式記憶體，設置於該基板之上，且包括： 一第一電極，電性連接該第一閘極； 一第二堆疊結構，包括互相重疊的一第三金屬氧化物層以及一第四金屬氧化物層；以及 一第二電極，其中該第二堆疊結構位於該第一電極與該第二電極之間，且該第二堆疊結構連接該第一電極與該第二電極。 A semiconductor device comprising: a substrate; A first thin film transistor is arranged on the substrate and includes: a first gate; A first stack structure, including a first metal oxide layer and a second metal oxide layer overlapping each other; a second gate, wherein the first stack structure is located between the first gate and the second gate; and a source and a drain electrically connected to the first stack structure; and A variable resistance memory is arranged on the substrate and includes: a first electrode electrically connected to the first gate; a second stack structure including a third metal oxide layer and a fourth metal oxide layer overlapping each other; and A second electrode, wherein the second stack structure is located between the first electrode and the second electrode, and the second stack structure connects the first electrode and the second electrode. 如請求項1所述的半導體裝置，其中該第一電極與該第一閘極連成一體，且該第一電極、該第二電極、該第一閘極與該第二閘極的材料包括鎢、鉬、鉑、鈀、金、鉬/鋁/鉬或其組合。The semiconductor device according to claim 1, wherein the first electrode and the first gate are integrally connected, and the materials of the first electrode, the second electrode, the first gate and the second gate include Tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum or combinations thereof. 如請求項1所述的半導體裝置，其中該第二電極與該第四金屬氧化物層之間具有肖特基接觸。The semiconductor device according to claim 1, wherein there is a Schottky contact between the second electrode and the fourth metal oxide layer. 如請求項1所述的半導體裝置，其中該第一金屬氧化物層的載子濃度大於該第二金屬氧化物層的一通道區的載子濃度。The semiconductor device as claimed in claim 1, wherein the carrier concentration of the first metal oxide layer is greater than the carrier concentration of a channel region of the second metal oxide layer. 如請求項4所述的半導體裝置，其中一二維電子氣位於該第一金屬氧化物層以及該第二金屬氧化物層之間的界面。The semiconductor device as claimed in claim 4, wherein a two-dimensional electron gas is located at the interface between the first metal oxide layer and the second metal oxide layer. 如請求項4所述的半導體裝置，其中該第一金屬氧化物層的氧濃度小於該第二金屬氧化物層的一通道區的氧濃度，該第二金屬氧化物層的厚度小於或等於該第一金屬氧化物層的厚度。The semiconductor device as claimed in item 4, wherein the oxygen concentration of the first metal oxide layer is less than the oxygen concentration of a channel region of the second metal oxide layer, and the thickness of the second metal oxide layer is less than or equal to the The thickness of the first metal oxide layer. 如請求項1所述的半導體裝置，其中該第三金屬氧化物層的載子濃度大於該第四金屬氧化物層的載子濃度。The semiconductor device as claimed in claim 1, wherein the carrier concentration of the third metal oxide layer is greater than the carrier concentration of the fourth metal oxide layer. 如請求項7所述的半導體裝置，其中該第三金屬氧化物層的氧濃度小於該第四金屬氧化物層的氧濃度，該第四金屬氧化物層的厚度小於或等於該第三金屬氧化物層的厚度。The semiconductor device according to claim 7, wherein the oxygen concentration of the third metal oxide layer is less than the oxygen concentration of the fourth metal oxide layer, and the thickness of the fourth metal oxide layer is less than or equal to that of the third metal oxide layer. layer thickness. 如請求項1所述的半導體裝置，其中該第一金屬氧化物層與該第三金屬氧化物層屬於同一圖案化層，且該第二金屬氧化物層與該第四金屬氧化物層屬於另外同一圖案化層。The semiconductor device according to claim 1, wherein the first metal oxide layer and the third metal oxide layer belong to the same patterned layer, and the second metal oxide layer and the fourth metal oxide layer belong to another same patterned layer. 如請求項1所述的半導體裝置，更包括： 一發光元件，電性連接該第一電極；以及 一第二薄膜電晶體，電性連接該發光元件以及該第一電極。 The semiconductor device as described in Claim 1, further comprising: a light emitting element electrically connected to the first electrode; and A second thin film transistor is electrically connected to the light emitting element and the first electrode. 如請求項1所述的半導體裝置，其中該第一金屬氧化物層以及該第三金屬氧化物層的厚度為10奈米至50奈米，且該第二金屬氧化物層以及該第四金屬氧化物層的厚度為5奈米至50奈米。The semiconductor device as claimed in claim 1, wherein the thickness of the first metal oxide layer and the third metal oxide layer is 10 nm to 50 nm, and the second metal oxide layer and the fourth metal oxide layer The oxide layer has a thickness of 5 nm to 50 nm. 如請求項1所述的半導體裝置，其中該第一金屬氧化物層以及該第三金屬氧化物層的氧濃度為10at%至50at %，且該第二金屬氧化物層的一通道區以及該第四金屬氧化物層的氧濃度為30at%至70at%。The semiconductor device according to claim 1, wherein the oxygen concentration of the first metal oxide layer and the third metal oxide layer is 10 at % to 50 at %, and a channel region of the second metal oxide layer and the The oxygen concentration of the fourth metal oxide layer is 30 at % to 70 at %. 如請求項1所述的半導體裝置，其中該第一源極電性連接該第二電極。The semiconductor device as claimed in claim 1, wherein the first source is electrically connected to the second electrode. 一種半導體裝置的製造方法，包括： 形成一第一閘極以及一第一電極於一基板之上； 形成一第一閘介電層於該第一閘極以及該第一電極之上，該第一閘介電層具有暴露出該第一電極的一第一開口； 形成一第一堆疊結構以及一第二堆疊結構於該第一閘介電層之上，其中該第一堆疊結構包括互相重疊的一第一金屬氧化物層以及一第二金屬氧化物層，且該第二堆疊結構包括互相重疊的一第三金屬氧化物層以及一第四金屬氧化物層，該第三金屬氧化物層填入該第一開口中； 形成一第二閘介電層於該第一堆疊結構以及該第二堆疊結構之上，該第二閘介電層具有暴露出該第四金屬氧化物層的一第二開口； 形成一第二閘極以及一第二電極於該第二閘介電層上，其中該第一堆疊結構位於該第一閘極與該第二閘極之間，且該第二電極填入該第二開口中；以及 形成電性連接該第一堆疊結構的一源極以及一汲極。 A method of manufacturing a semiconductor device, comprising: forming a first gate and a first electrode on a substrate; forming a first gate dielectric layer on the first gate and the first electrode, the first gate dielectric layer having a first opening exposing the first electrode; forming a first stack structure and a second stack structure on the first gate dielectric layer, wherein the first stack structure includes a first metal oxide layer and a second metal oxide layer overlapping each other, and The second stack structure includes a third metal oxide layer and a fourth metal oxide layer overlapping with each other, and the third metal oxide layer is filled into the first opening; forming a second gate dielectric layer on the first stack structure and the second stack structure, the second gate dielectric layer having a second opening exposing the fourth metal oxide layer; forming a second gate and a second electrode on the second gate dielectric layer, wherein the first stack structure is located between the first gate and the second gate, and the second electrode fills the in the second opening; and A source and a drain electrically connected to the first stack structure are formed. 如請求項14所述的半導體裝置的製造方法，其中該第一金屬氧化物層以及該第三金屬氧化物層同時形成，且該第二金屬氧化物層以及該第四金屬氧化物層同時形成。The method for manufacturing a semiconductor device according to claim 14, wherein the first metal oxide layer and the third metal oxide layer are formed simultaneously, and the second metal oxide layer and the fourth metal oxide layer are formed simultaneously .
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