TW202324705A - Memory device, memory circuit and manufacturing method of memory circuit - Google Patents

Abstract

A memory device includes a substrate, an oxide insulation layer, a first metal oxide layer, a first gate dielectric layer, a second metal oxide layer, a second gate dielectric layer, a first gate, a source and a drain. The oxide insulation layer is located above the substrate. The first metal oxide layer is located above the oxide insulation layer. The first gate dielectric layer is located above the first metal oxide layer. The second metal oxide layer is located above the first gate dielectric layer. The second gate dielectric layer is located above the second metal oxide layer. The first gate is located above the second gate dielectric layer. The second metal oxide layer is located between the first gate and the first metal oxide layer. The source and the drain are electrically connected to the first metal oxide layer.

Description

Memory device, memory circuit and method for manufacturing memory circuit

The invention relates to a memory device, a memory circuit and a manufacturing method of the memory circuit.

Electronic Erasable Programmable Read-Only Memory (hereinafter referred to as EEPROM) is a memory device that can save data without power supply. It has the advantages of fast access speed, large capacity and small size. Therefore, EEPROM is currently Has been widely used in various electronic products.

In a general EEPROM, by applying different control gate voltages (Vg) to the gate, whether electrons tunnel into the floating gate is controlled. When electrons enter the floating gate, the memory cell of EEPROM will store "1". Conversely, when electrons escape from the floating gate, the memory cell of EEPROM will store "0".

The invention provides a memory device, a memory circuit and a manufacturing method of the memory circuit, wherein the memory device has the advantage of fast access speed.

At least one embodiment of the invention provides a memory device. The memory device includes a substrate, an oxide insulating layer, a first metal oxide layer, a first gate dielectric layer, a second metal oxide layer, a second gate dielectric layer, a first gate, a source and a drain. An oxide insulating layer is on the substrate. The first metal oxide layer is located on the oxide insulating layer. The first gate dielectric layer is located on the first metal oxide layer. The second metal oxide layer is on the first gate dielectric layer. The second gate dielectric layer is located on the second metal oxide layer. The first gate is located on the second gate dielectric layer. The second metal oxide layer is located between the first gate and the first metal oxide layer. The source and the drain are electrically connected to the first metal oxide layer.

At least one embodiment of the invention provides a memory circuit. The memory circuit includes a substrate, an oxide insulating layer, a first gate dielectric layer, a second gate dielectric layer, a memory device and a thin film transistor. The oxide insulating layer is located on the substrate and includes a first oxygen-containing structure and a second oxygen-containing structure. The first gate dielectric layer is located on the oxide insulating layer and includes a first dielectric structure and a second dielectric structure. The second oxygen-containing structure and the second dielectric structure are stacked to form a protruding structure. The second gate dielectric layer is located on the first gate dielectric layer. The memory device includes a first metal oxide layer, a second metal oxide layer, a first gate, a first source and a first drain. A first metal oxide layer overlies the first oxygen-containing structure. The first dielectric structure is located between the first metal oxide layer and the second metal oxide layer. The second gate dielectric layer is located between the second metal oxide layer and the first gate. The second metal oxide layer is located between the first gate and the first metal oxide layer. The first source and the first drain are electrically connected to the first metal oxide layer. The TFT includes a third metal oxide layer, a second gate, a second source and a second drain. The third metal oxide layer covers the top surface and side surfaces of the protruding structures. The second gate overlaps the third metal oxide layer. The second gate dielectric layer is located between the second gate electrode and the third metal oxide layer. The second source and the second drain are electrically connected to the third metal oxide layer.

At least one embodiment of the present invention provides a method for manufacturing a memory circuit, comprising: forming an oxide insulating layer on a substrate; forming a first metal oxide layer on the oxide insulating layer; forming a first gate dielectric layer On the first metal oxide layer; forming a second metal oxide layer on the first gate dielectric layer; forming a second gate dielectric layer on the second metal oxide layer; forming the first gate on the On the second gate dielectric layer, wherein the second metal oxide layer is located between the first gate electrode and the first metal oxide layer; a source electrode and a drain electrode electrically connected to the first metal oxide layer are formed.

FIG. 1 is a schematic cross-sectional view of a memory circuit according to an embodiment of the present invention.

Referring to FIG. 1 , the memory circuit 10 includes a substrate 100 , an oxide insulating layer 120 , a first gate dielectric layer 130 , a second gate dielectric layer 140 , a memory device ROM and a thin film transistor TFT. In this embodiment, the memory circuit 10 further includes a buffer layer 110 and an interlayer dielectric layer 150 .

The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive materials or metals are used, an insulating layer (not shown) is covered on the substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene glycol ester (polyethylene naphthalate, PEN), polyester (polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft board (Metal Foil) or other flexible materials .

In some embodiments, the buffer layer 110 is located on the substrate 100 , and the buffer layer 110 contains hydrogen. For example, the material of the buffer layer 110 includes hydrogen-containing silicon nitride (or hydrogenated silicon nitride) or other suitable materials. In some embodiments, the buffer layer 110 is blanketed on the substrate 100 . In some embodiments, the buffer layer 110 has a thickness of 100 angstroms to 6000 angstroms.

The oxide insulating layer 120 is located on the substrate 100 . In this embodiment, the oxide insulating layer 120 is located on the buffer layer 110 . In some embodiments, the oxide insulating layer 120 is patterned without covering part of the buffer layer 110 . In other words, the oxide insulating layer 120 covers part of the top surface of the buffer layer 110 and does not cover another part of the top surface of the buffer layer 110 . In some embodiments, the oxide insulating layer 120 includes a first oxygen-containing structure 122 and a second oxygen-containing structure 124 . In some embodiments, the first oxygen-containing structure 122 and the second oxygen-containing structure 124 are separated from each other. In some embodiments, the material of the oxide insulating layer 120 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials. In some embodiments, the oxide insulating layer 120 has a thickness of 300 angstroms to 5000 angstroms.

The memory device ROM and the thin film transistor TFT are located on the substrate 100 . In some embodiments, the memory device ROM and the thin film transistor TFT are located on the oxide insulating layer 120 . The memory device ROM includes a first metal oxide layer OS1, a second metal oxide layer OS2, a first gate G1, a first source S1, and a first drain D1. The thin film transistor TFT includes a third metal oxide layer OS3 , a second gate G2 , a second source S2 and a second drain D2 .

The first metal oxide layer OS1 is located on the first oxygen-containing structure 122 of the oxide insulating layer 120 , and the first metal oxide layer OS1 contacts the top surface of the first oxygen-containing structure 122 . The first oxygen-containing structure 122 is located between the first metal oxide layer OS1 and the buffer layer 110 . The buffer layer 110 and the first oxygen-containing structure 122 are located between the first metal oxide layer OS1 and the substrate 100 .

The first metal oxide layer OS1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 between the first source region sr1 and the first drain region dr1, wherein the first source The resistivity of the region sr1 and the first drain region dr1 is lower than the resistivity of the first channel region ch1. In some embodiments, the distance between the first channel region ch1 and the substrate 100 is substantially equal to the distance between the first source region sr1 and the substrate 100 and the distance between the first drain region dr1 and the substrate 100 .

In some embodiments, the first oxygen-containing structure 122 under the first metal oxide layer OS1 supplies oxygen to the first metal oxide layer OS1 to increase the resistivity of the first metal oxide layer OS1 . In this embodiment, the first source region sr1 and the first drain region dr1 and the first oxygen-containing structure 122 under the first channel region ch1 have substantially uniform thickness.

The first gate dielectric layer 130 is located on the oxide insulating layer 120 and includes a first dielectric structure 132 and a second dielectric structure 134 . The first dielectric structure 132 of the first gate dielectric layer 130 is located on the first metal oxide layer OS1 and covers the first metal oxide layer OS1 . In some embodiments, the first source region sr1 , the first drain region dr1 and the first channel region ch1 are located at the first oxygen-containing structure 122 of the oxide insulating layer 120 and the first layer of the first gate dielectric layer 130 . between the dielectric structures 132 .

The second dielectric structure 134 is located on the second oxygen-containing structure 124 , and the second oxygen-containing structure 124 is located between the second dielectric structure 134 and the buffer layer 110 . The second oxygen-containing structure 124 and the second dielectric structure 134 are stacked to form the protruding structure P. Referring to FIG. In some embodiments, the material of the first gate dielectric layer 130 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials. In some embodiments, the thickness of the first gate dielectric layer 130 is 100 angstroms to 1000 angstroms.

The second metal oxide layer OS2 is located on the first dielectric structure 132 of the first gate dielectric layer 130 and overlaps the first channel region ch1 of the first metal oxide layer OS1 . The first dielectric structure 132 is located between the first metal oxide layer OS1 and the second metal oxide layer OS2.

The third metal oxide layer OS3 is located on the protruding structure P, covers the top and side surfaces of the protruding structure P, and extends to the top surface of the buffer layer 110 . The third metal oxide layer OS3 contacts the top surface of the second dielectric structure 134 , the side surfaces of the second dielectric structure 134 , the side surfaces of the second oxygen-containing structure 124 and the top surface of the buffer layer 110 .

The third metal oxide layer OS3 includes a second drain region dr2, a second source region sr2, a second channel region ch2, a resistance gradient region g2a connected between the second drain region dr2 and the second channel region ch2, and The resistance gradient region g2b is connected between the second source region sr2 and the second channel region ch2. The second channel region ch2 covers the top surface of the second dielectric structure 134 , and the protruding structure P is located between the buffer layer 110 and the second channel region ch2 . The resistance gradient region g2 a and the resistance gradient region g2 b contact the side surfaces of the protruding structure P (including the side surfaces of the second dielectric structure 134 and the second oxygen-containing structure 124 ). The second drain region dr2 and the second source region sr2 extend from the side of the protruding structure P to a direction away from the protruding structure P, and the second drain region dr2 and the second source region sr2 contact the top of the buffer layer 110 noodle. The distance between the second channel region ch2 and the substrate 100 is greater than the distance between the second drain region dr2 and the substrate 100 and the distance between the second source region sr2 and the substrate 100 .

In some embodiments, the protruding structure P under the third metal oxide layer OS3 will supply oxygen to the third metal oxide layer OS3, so that the resistivity of the third metal oxide layer OS3 will increase, thereby avoiding the thin film electrical resistance. The crystal TFT is short-circuited because the resistivity of the second channel region ch2 is too low. In addition, in some embodiments, the first dielectric structure 132 under the second metal oxide layer OS2 also supplies oxygen to the second metal oxide layer OS2, thereby adjusting the resistivity of the second metal oxide layer OS2. .

The overall thickness of the protruding structure P will affect its ability to supply oxygen to the third metal oxide layer OS3, thereby affecting the resistivity of the third metal oxide layer OS3 in different regions. Specifically, under the second channel region ch2, the overall thickness of the raised structure P is relatively large, so the resistivity of the second channel region ch2 is relatively large; under the resistance gradient region g2a and the resistance gradient region g2b, the protrusion structure P The overall thickness gradually decreases, so the resistivity of the resistance gradient region g2a and the resistance gradient region g2b also gradually decreases accordingly. In other words, the resistivity of the resistance gradient region g2a and the resistance gradient region g2b decreases with distance from the second channel region ch2; there is no protruding structure P under the second drain region dr2 and the second source region sr2, and the first The second drain region dr2 and the second source region sr2 have lower resistivity than the second channel region ch2 , resistance gradient region g2a and resistance gradient region g2b. In some embodiments, the oxygen concentration of the second channel region ch2 is greater than the oxygen concentration of the resistance gradient region g2a and the resistance gradient region g2b, and the oxygen concentration of the resistance gradient region g2a and the resistance gradient region g2b is greater than that of the second drain region dr2 and the second drain region dr2. Oxygen concentration in the second source region sr2.

In some embodiments, the materials of the first metal oxide layer OS1, the second metal oxide layer OS2 and the third metal oxide layer OS3 include indium gallium tin zinc oxide (IGTZO) or indium gallium zinc oxide (IGZO), Indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO) and other metal compounds or containing gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum ( An oxide of any three of Al), tungsten (W), or a lanthanide rare earth-doped metal oxide (such as Ln-IZO). In some embodiments, the first metal oxide layer OS1, the second metal oxide layer OS2, and the third metal oxide layer OS3 include the same material. In other embodiments, the material of the first metal oxide layer OS1 is different from that of the second metal oxide layer OS2 and the third metal oxide layer OS3 . In some embodiments, the second metal oxide layer OS2 and the third metal oxide layer OS3 belong to the same patterned layer. In some embodiments, the carrier mobility of the second metal oxide layer OS2 and the carrier mobility of the second channel region ch2 of the third metal oxide layer OS3 are greater than the first channel region of the first metal oxide layer OS1 The carrier mobility of ch1 is used to increase the switching speed of the thin film transistor TFT.

The second gate dielectric layer 140 is located on the buffer layer 110 , the first dielectric structure 132 of the first gate dielectric layer 130 , the second metal oxide layer OS2 and the third metal oxide layer OS3 . The second metal oxide layer OS2 is located between the first dielectric structure 132 of the first gate dielectric layer 130 and the second gate dielectric layer 140 . The third metal oxide layer OS3 is located between the second dielectric structure 134 of the first gate dielectric layer 130 and the second gate dielectric layer 140 and between the buffer layer 110 and the second gate dielectric layer 140 . In some embodiments, the material of the second gate dielectric layer 140 includes silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide or other suitable materials. In some embodiments, the second gate dielectric layer 140 has a thickness of 500 angstroms to 2000 angstroms. In some embodiments, the thickness of the first gate dielectric layer 140 is smaller than the thickness of the second gate dielectric layer 130, thereby making it easier for electrons to tunnel from the first channel region ch1 to the second metal oxide layer OS2. , to increase the switching speed of the memory device ROM.

The first gate G1 and the second gate G2 are located on the second gate dielectric layer 140 and overlap the first channel region ch1 of the first metal oxide layer OS1 and the second channel of the third metal oxide layer OS3 respectively. District ch2. The second gate dielectric layer 140 is located between the first gate G1 and the second metal oxide layer OS2 and between the second gate G2 and the third metal oxide layer OS3 . The second metal oxide layer OS2 is located between the first gate G1 and the first channel region ch1 of the first metal oxide layer OS1.

In some embodiments, the materials of the first gate G1 and the second gate G2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or any combination of the above metals Alloys or stacks of the aforementioned metals and/or alloys, but the present invention is not limited thereto. The first gate G1 and the second gate G2 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other conductive materials. The material.

The interlayer dielectric layer 150 is located on the second gate dielectric layer 140 and covers the first gate G1 and the second gate G2 . In some embodiments, the material of the interlayer dielectric layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials.

The first contact hole V1 and the second contact hole V2 pass through the interlayer dielectric layer 150 , the second gate dielectric layer 140 and the first dielectric structure 132 . The first drain D1 and the first source S1 are located on the interlayer dielectric layer 150 and respectively fill the first contact hole V1 and the second contact hole V2 to electrically connect the first metal oxide layer OS1 . The first drain D1 and the first source S1 are respectively connected to the first drain region dr1 and the first source region sr1 of the first metal oxide layer OS1 .

The third contact hole V3 and the fourth contact hole V4 pass through the interlayer dielectric layer 150 and the second gate dielectric layer 140 . The second drain D2 and the second source S2 are located on the interlayer dielectric layer 150 and respectively fill the third contact hole V3 and the fourth contact hole V4 to electrically connect the third metal oxide layer OS3. The second drain D2 and the second source S2 are connected to the second drain region dr2 and the second source region sr2 of the third metal oxide layer OS3 respectively.

The materials of the first drain D1, the first source S1, the second drain D2 and the second source S2 may include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, Titanium, tantalum, aluminum, zinc (or an alloy of any combination of the above metals or a stack of the above metals and/or alloys, but the present invention is not limited thereto. The first drain D1, the first source S1, the second The drain D2 and the second source S2 can also use other conductive materials, such as: metal nitride, metal oxide, metal oxynitride, stacked layers of metal and other conductive materials, or other materials with conductive properties .

FIG. 2A is a circuit diagram of the memory circuit of FIG. 1 . FIG. 2B is a signal diagram of the memory circuit in FIG. 2A . In FIG. 2B , the vertical axis is voltage, and the horizontal axis is time.

Please refer to FIG. 1 and FIG. 2A at the same time, the memory circuit 10 further includes word lines WL, bit lines BL, data lines DL and source lines SL. The word line WL is electrically connected to the second gate G2 of the thin film transistor TFT. The bit line BL is electrically connected to the second drain D2 of the thin film transistor TFT. The second source S2 of the thin film transistor TFT is electrically connected to the first gate G1 of the memory device ROM. The data line DL is electrically connected to the first drain D1 of the memory device ROM. The source line SL is electrically connected to the first source S1 of the memory device ROM.

Please refer to FIG. 1, FIG. 2A and FIG. 2B. When executing a write command of the memory device ROM, a voltage is applied to the second gate G2 of the thin film transistor TFT through the word line WL to turn on the thin film transistor TFT, and At the same time, a first voltage (for example, 15 V to 30 V) is applied to the second drain D2 of the thin film transistor TFT through the bit line BL. The signal on the bit line BL is transmitted to the first gate electrode G1 of the memory device ROM, and electrons are passed from the first metal oxide layer OS1 through the first dielectric structure 132 of the first gate dielectric layer 130 by the electric field. tunnel into the second metal oxide layer OS2. Since electrons are stored in the second metal oxide layer OS2, the threshold voltage (threshold voltage, V _th ) of the memory device ROM is changed.

When executing the read command of the memory device ROM, apply a voltage to the second gate G2 of the thin film transistor TFT through the word line WL to turn on the thin film transistor TFT, and at the same time, apply a voltage to the thin film transistor TFT through the bit line BL A second voltage (for example, 5 V to 15 V) is applied to the second drain D2 of the TFT. The signal on the bit line BL is transmitted to the first gate G1 of the memory device ROM to turn on the memory device ROM, and at the same time, a voltage is applied to the first drain D1 of the memory device ROM through the data line DL to enable the memory device A voltage difference is generated between the first drain D1 and the first source S1 of the ROM, so that signals can pass through the memory device ROM. By reading the signal passing through the memory device ROM, it can be known that the memory device ROM is currently in state "1" or state "0". The second voltage used when executing the read command is lower than the first voltage used when executing the write command. Therefore, it is not easy to change the threshold voltage of the memory device ROM due to electron tunneling when executing the write command.

When executing the erase command of the memory device ROM, a voltage is applied to the second gate G2 of the thin film transistor TFT through the word line WL to turn on the thin film transistor TFT, and at the same time, the voltage is applied to the thin film transistor TFT through the bit line BL A third voltage (eg -15 V to -30 V) is applied to the second drain D2 of the TFT. The signal on the bit line BL is transmitted to the first gate electrode G1 of the memory device ROM, and electrons are passed from the second metal oxide layer OS2 through the first dielectric structure 132 of the first gate dielectric layer 130 by the electric field. Tunneling into the first metal oxide layer OS1, so that the threshold voltage of the memory device ROM can return to the original value.

Based on the above, using the memory device ROM has the advantage of fast access speed.

3A to 3F are schematic cross-sectional views of the manufacturing method of the memory circuit shown in FIG. 1 .

Referring to FIG. 3A , a buffer layer 110 and an oxide insulating layer 120 are formed on the substrate 100 . In some embodiments, the buffer layer 110 blankets the substrate 100 , and the oxide insulating layer 120 blankets the buffer layer 110 .

Next, a first metal oxide layer OS1' is formed on the oxide insulating layer 120. In some embodiments, the method for forming the first metal oxide layer OS1' includes: forming a first semiconductor material layer (not shown) on the oxide insulating layer 120; forming a patterned Photoresist (not shown); using the patterned photoresist as a mask to etch the first semiconductor material layer to form the first metal oxide layer OS1 ′; finally, remove the patterned photoresist.

Referring to FIG. 3B , a first gate dielectric layer 130 is formed on the first metal oxide layer OS1' and the oxide insulating layer 120. Referring to FIG. In some embodiments, the first gate dielectric layer 130 blankets the first metal oxide layer OS1' and the oxide insulating layer 120.

Referring to FIG. 3C , a patterning process is performed on the oxide insulating layer 120 and the first gate dielectric layer 130, so that the oxide insulating layer 120 includes a first oxygen-containing structure 122 and a second oxygen-containing structure 124, and the first The gate dielectric layer 130 includes a first dielectric structure 132 and a second dielectric structure 134 . The first metal oxide layer OS1' is located between the first oxygen-containing structure 122 and the first dielectric structure 132. The second oxygen-containing structure 124 and the second dielectric structure 134 are stacked to form the protruding structure P. Referring to FIG. In some embodiments, the aforementioned patterning process includes wet etching or dry etching, and the aforementioned patterning process etch stops at the buffer layer 110 .

In some embodiments, the oxide insulating layer 120 and the first gate dielectric layer 130 are patterned by the same photomask, so the sides of the first oxygen-containing structure 122 are aligned with the first dielectric structure 132, and the second The sides of the oxygen-containing structure 124 are aligned with the second dielectric structure 134 .

Next, referring to FIG. 3D , a second metal oxide layer OS2 and a third metal oxide layer OS3' are formed on the first gate dielectric layer 130 . In this embodiment, the second metal oxide layer OS2 is formed on the first dielectric structure 132 of the first gate dielectric layer 130, and the third metal oxide layer OS3' is formed on the top surface of the protruding structure P, On the side of the protruding structure P and the buffer layer 110 . In some embodiments, the method for forming the second metal oxide layer OS2 and the third metal oxide layer OS3 ′ includes: forming a second semiconductor layer on the buffer layer 110 , the oxide insulating layer 120 and the first gate dielectric layer 130 material layer (not shown); forming a patterned photoresist (not shown) on the aforementioned second semiconductor material layer; using the patterned photoresist as a mask, etching the second semiconductor material layer to form a second metal oxide layer OS2 and the third metal oxide layer OS3'; finally, remove the patterned photoresist. In this embodiment, since the first metal oxide layer OS1' is covered by the first oxygen-containing structure 122 and the first dielectric structure 132, the aforementioned etching process will not cause damage to the first metal oxide layer OS1' .

Referring to FIG. 3E , a second gate dielectric layer 140 is formed on the second metal oxide layer OS2 and the third metal oxide layer OS3'. In this embodiment, the second gate dielectric layer 140 is located on the second metal oxide layer OS2, the first dielectric structure 132, the buffer layer 110 and the third metal oxide layer OS3'.

A first gate G1 and a second gate G2 are formed on the second gate dielectric layer 140 . The second metal oxide layer OS2 is located between the first gate G1 and the first metal oxide layer OS1', and the second gate G2 overlaps the third metal oxide layer OS3'.

In some embodiments, before forming the first gate G1 and the second gate G2, a heat treatment process is performed to diffuse the oxygen element in the protruding structure P into the third metal oxide layer OS3 ′, thereby improving the The resistivity of the third metal oxide layer OS3' on the protruding structure P. In some embodiments, the heat treatment process also diffuses the oxygen element in the first dielectric structure 132 into the second metal oxide layer OS2, thereby increasing the resistivity of the second metal oxide layer OS2. In some embodiments, the aforementioned heat treatment process is, for example, a heating process when depositing the second gate dielectric layer 140 , but the invention is not limited thereto.

Next, using the first gate G1 and the second gate G2 as masks, a doping process DP is performed on the first metal oxide layer OS1' and the third metal oxide layer OS3'. To form the first metal oxide layer OS1 including the first source region sr1, the first drain region dr1 and the first channel region ch1 and the second source region sr2, the second drain region dr2, the resistance gradient region g2a , the resistance gradient region g2b and the third metal oxide layer OS3 in the second channel region ch2. In some embodiments, the doping process DP is, for example, a hydrogen plasma process or other suitable processes. In some embodiments, in the normal direction ND of the top surface of the substrate 100 , the first gate G1 completely covers the second metal oxide layer OS2 . Therefore, the first source region sr1 and the first drain region dr1 are not shielded by the second metal oxide layer OS2 in the doping process DP.

In some embodiments, the buffer layer 110 provides hydrogen elements to the third metal oxide layer OS3 during the manufacturing process, thereby reducing the resistivity of the second source region sr2 and the second drain region dr2 .

In this embodiment, the first gate G1 and the second gate G2 belong to the same patterned layer, and the first metal oxide layer OS1 and the second metal oxide layer OS2 can be doped through the same doping process DP. Therefore, the manufacturing cost of memory devices and thin film transistors can be saved.

Referring to FIG. 3F , an interlayer dielectric layer 150 is formed on the second gate dielectric layer 140 . Next, an etching process is performed to form a first contact hole V1 , a second contact hole V2 , a third contact hole V3 and a fourth contact hole V4 .

Finally, please return to FIG. 1, form the first drain D1, the first source S1, the second drain D2 and the second source S2 on the interlayer dielectric layer 150, and respectively fill the first contact holes V1, In the second contact hole V2 , the third contact hole V3 and the fourth contact hole V4 . So far, the memory circuit 10 is roughly completed. In some embodiments, the method for forming the first source S1, the first drain D1, the second source S2, and the second drain D2 includes: forming a conductive material layer (not shown) on the interlayer dielectric layer 150 ; Forming a patterned photoresist (not shown) on the aforementioned conductive material layer; using the patterned photoresist as a mask, etching the conductive material layer to form the first source S1, the first drain D1, the second The source S2 and the second drain D2; finally, remove the patterned photoresist. In other words, the first source S1 , the first drain D1 , the second source S2 and the second drain D2 belong to the same patterned layer.

FIG. 4 is a schematic cross-sectional view of a memory circuit according to an embodiment of the invention. It must be noted here that the embodiment in FIG. 4 follows the component numbers and part of the content of the embodiment in FIG. 1 , where the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the memory circuit 20 in FIG. 4 and the memory circuit 10 in FIG. 1 is that: the thin film transistor TFT of the memory circuit 20 further includes a bottom gate BG.

Referring to FIG. 4 , the bottom gate BG is located on the substrate 100 . The buffer layer 110 is located on the bottom gate BG. The third metal oxide layer OS3 is located between the bottom gate BG and the second gate G2, and the protruding structure P is located between the bottom gate BG and the third metal oxide layer OS3. In some embodiments, the length L2 of the bottom gate BG is greater than the length L1 of the second gate G2.

FIG. 5 is a schematic cross-sectional view of a memory circuit according to an embodiment of the invention. It must be noted here that the embodiment in FIG. 5 follows the component numbers and part of the content of the embodiment in FIG. 1 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The main difference between the memory circuit 30 of FIG. 5 and the memory circuit 10 of FIG. 1 is that the first metal oxide layer OS1 of the memory device ROM of the memory circuit 30 includes a resistance gradient region g1a and a resistance gradient region g1b. The resistance gradient region g1a is connected between the first drain region dr1 and the first channel region ch1, and the resistance gradient region g1b is also connected between the first source region sr1 and the first channel region ch1.

Referring to FIG. 5 , the first channel region ch1 of the first metal oxide layer OS1 is located on the first oxygen-containing structure 122 , and the first oxygen-containing structure 122 is located between the first channel region ch1 and the buffer layer 110 . The resistance gradient region g1 a and the second resistance gradient region g1 b of the first metal oxide layer OS1 contact the side surface of the first oxygen-containing structure 122 . The first drain region dr1 and the first source region sr1 extend from the side of the first oxygen-containing structure 122 to a direction away from the first oxygen-containing structure 122, and the first drain region dr1 and the first source region sr1 are in contact with the buffer top surface of layer 110. The distance between the first channel region ch1 and the substrate 100 is greater than the distance between the first drain region dr1 and the substrate 100 and the distance between the first source region sr1 and the substrate 100 .

In some embodiments, the first oxygen-containing structure 122 under the first metal oxide layer OS1 supplies oxygen to the first metal oxide layer OS1 to increase the resistivity of the first metal oxide layer OS1, thereby avoiding The memory device ROM is short-circuited because the resistivity of the first channel region ch1 is too low.

The thickness of the first oxygen-containing structure 122 affects its ability to supply oxygen to the first metal oxide layer OS1 , thereby affecting the resistivity of the first metal oxide layer OS1 in different regions. Specifically, under the first channel region ch1, the thickness of the first oxygen-containing structure 122 is relatively large, so the resistivity of the first channel region ch1 is relatively large; under the resistance gradient region g1a and resistance gradient region g1b, the first oxygen-containing structure The thickness of the oxygen structure 122 decreases gradually, so the resistivity of the resistance gradient region g1a and the resistance gradient region g1b also gradually decreases accordingly. In other words, the resistivity of the resistance gradient region g1a and the resistance gradient region g1b decreases with distance from the first channel region ch1. There is no first oxygen-containing structure 122 under the first drain region dr1 and the first source region sr1 , and the first drain region dr1 and the first source region sr1 have a larger structure than the first channel region ch1 , the resistance gradient region g1a and the first channel region ch1 . The resistance gradient region g1b has a low resistivity. In some embodiments, the oxygen concentration of the first channel region ch1 is greater than the oxygen concentration of the resistance gradient region g1a and the resistance gradient region g1b, and the oxygen concentration of the resistance gradient region g1a and the resistance gradient region g1b is greater than that of the first drain region dr1 and the first drain region dr1. Oxygen concentration in the source region sr1.

In some embodiments, the buffer layer 110 provides hydrogen elements to the first metal oxide layer OS1 during the manufacturing process, thereby reducing the resistivity of the first source region sr1 and the first drain region dr1 .

To sum up, the second metal oxide layer OS2 of the memory device ROM of the present invention is located between the first gate G1 and the first metal oxide layer OS1, and the electrons can be released by applying a voltage to the first gate G1. Tunneling between the first metal oxide layer OS1 and the second metal oxide layer OS2 enables fast switching of the memory device ROM.

10, 20, 30: memory circuits 100: Substrate 110: buffer layer 120: Oxide insulating layer 122: The first oxygen-containing structure 124: Second oxygen-containing structure 130: The first gate dielectric layer 132: first dielectric structure 134: Second dielectric structure 140: second gate dielectric layer 150: interlayer dielectric layer BG: bottom gate BL: bit line ch1: the first channel area ch2: the second channel area DL: data line dr1: the first drain region dr2: the second drain area D1: the first drain D2: the second drain DP: doping process G1: the first gate G2: the second gate g1a, g1b, g2a, g2b: resistance gradient area L1, L2: Length ND: normal direction OS1, OS1’: first metal oxide layer OS2: second metal oxide layer OS3, OS3’: the third metal oxide layer P: raised structure ROM: memory device SL: source line S1: first source S2: second source sr1: the first source region sr2: second source region TFT: thin film transistor V1: first contact hole V2: Second contact hole V3: The third contact hole V4: Fourth contact hole WL: character line

FIG. 1 is a schematic cross-sectional view of a memory circuit according to an embodiment of the present invention. FIG. 2A is a circuit diagram of the memory circuit of FIG. 1 . FIG. 2B is a signal diagram of the memory circuit in FIG. 2A . 3A to 3F are schematic cross-sectional views of the manufacturing method of the memory circuit shown in FIG. 1 . FIG. 4 is a schematic cross-sectional view of a memory circuit according to an embodiment of the invention. FIG. 5 is a schematic cross-sectional view of a memory circuit according to an embodiment of the invention.

10: Memory circuit

100: Substrate

110: buffer layer

120: Oxide insulating layer

122: The first oxygen-containing structure

124: Second oxygen-containing structure

130: The first gate dielectric layer

132: first dielectric structure

134: Second dielectric structure

140: second gate dielectric layer

150: interlayer dielectric layer

ch1: the first channel area

ch2: the second channel area

dr1: the first drain region

dr2: the second drain region

D1: the first drain

D2: the second drain

G1: the first gate

G2: the second gate

g2a, g2b: resistance gradient area

OS1: first metal oxide layer

OS2: second metal oxide layer

OS3: third metal oxide layer

P: raised structure

ROM: memory device

S1: first source

S2: second source

sr1: the first source region

sr2: second source region

TFT: thin film transistor

V1: first contact hole

V2: Second contact hole

V3: The third contact hole

V4: Fourth contact hole

Claims (17)

A memory device comprising: a substrate; an oxide insulating layer located on the substrate; a first metal oxide layer located on the oxide insulating layer; a first gate dielectric layer located on the first metal oxide layer; a second metal oxide layer located on the first gate dielectric layer; a second gate dielectric layer located on the second metal oxide layer; a first gate on the second gate dielectric layer, wherein the second metal oxide layer is between the first gate and the first metal oxide layer; and A source and a drain are electrically connected to the first metal oxide layer. The memory device according to claim 1, wherein the first metal oxide layer includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source The resistivity of the electrode region and the drain region is lower than that of the channel region, and the second metal oxide layer is located between the channel region and the first gate. The memory device as described in claim 2, further comprising: A buffer layer is located on the substrate, and the buffer layer contains hydrogen elements, wherein a first oxygen-containing structure of the oxide insulating layer is located between the channel region and the buffer layer, and the source region and the buffer layer The drain region contacts the buffer layer. The memory device according to claim 3, wherein the first metal oxide layer further comprises: a first resistance gradient region and a second resistance gradient region contacting a side surface of the first oxygen-containing structure, wherein the resistivity of the first resistance gradient region and the second resistance gradient region decreases with distance from the channel region , wherein the first resistance gradient region is connected between the channel region and the source region, and the second resistance gradient region is connected between the channel region and the drain region. The memory device as claimed in claim 1, wherein the thickness of the first gate dielectric layer is smaller than the thickness of the second gate dielectric layer. The memory device as claimed in claim 1, wherein in the direction normal to the top surface of the substrate, the first gate completely shields the second metal oxide layer. A memory circuit comprising: a substrate; An oxide insulating layer is located on the substrate and includes a first oxygen-containing structure and a second oxygen-containing structure; A first gate dielectric layer is located on the oxide insulating layer and includes a first dielectric structure and a second dielectric structure, wherein the second oxygen-containing structure and the second dielectric structure are stacked on each other so as to forming a raised structure; a second gate dielectric layer located on the first gate dielectric layer; A memory device, comprising: a first metal oxide layer overlying the first oxygen-containing structure; a second metal oxide layer, wherein the first dielectric structure is located between the first metal oxide layer and the second metal oxide layer; A first gate, wherein the second gate dielectric layer is located between the second metal oxide layer and the first gate, and the second metal oxide layer is located between the first gate and the first metal oxide layer between oxide layers; and a first source and a first drain electrically connected to the first metal oxide layer; and A thin film transistor, comprising: a third metal oxide layer covering a top surface and a side surface of the raised structure; a second gate overlapping the third metal oxide layer, and the second gate dielectric layer is located between the second gate and the third metal oxide layer; and A second source and a second drain are electrically connected to the third metal oxide layer. The memory circuit as claimed in item 7, wherein the third metal oxide layer comprises: a channel area covering the top surface of the raised structure; a first resistance gradient region and a second resistance gradient region contacting the side surface of the raised structure, wherein the resistivity of the first resistance gradient region and the second resistance gradient region decreases away from the channel region; and A source region and a drain region extend from the side of the raised structure to a direction away from the raised structure, wherein the first resistance gradient region is connected between the channel region and the source region, and the The second resistance gradient area is connected between the channel area and the drain area. The memory circuit as described in claim item 8, further comprising: A buffer layer is located on the substrate, and the buffer layer contains hydrogen, wherein the raised structure is located between the channel region and the buffer layer, and the source region and the drain region are in contact with the buffer layer. The memory circuit as described in claim item 7, further comprising: a word line electrically connected to the second gate; a bit line electrically connected to the second drain, and the second source electrically connected to the first gate; a data line electrically connected to the first drain; A source line is electrically connected to the first source. The memory circuit as claimed in item 7, wherein the thin film transistor further comprises: A bottom gate, wherein the third metal oxide layer is located between the bottom gate and the second gate, and the raised structure is located between the bottom gate and the third metal oxide layer. The memory circuit according to claim 11, wherein the length of the bottom gate is greater than the length of the second gate. The memory circuit as claimed in claim 7, wherein the second metal oxide layer and the third metal oxide layer belong to the same patterned layer. A method of manufacturing a memory circuit, comprising: forming an oxide insulating layer on a substrate; forming a first metal oxide layer on the oxide insulating layer; forming a first gate dielectric layer on the first metal oxide layer; forming a second metal oxide layer on the first gate dielectric layer; forming a second gate dielectric layer on the second metal oxide layer; forming a first gate over the second gate dielectric layer, wherein the second metal oxide layer is between the first gate and the first metal oxide layer; and A source and a drain electrically connected to the first metal oxide layer are formed. The method for manufacturing a memory circuit as described in claim 14, further comprising: performing a patterning process on the oxide insulating layer and the first gate dielectric layer, so that the oxide insulating layer includes a first oxygen-containing structure and a second oxygen-containing structure, and makes the first gate dielectric The layer includes a first dielectric structure and a second dielectric structure, wherein the second oxygen-containing structure and the second dielectric structure are stacked to form a raised structure; forming the second metal oxide layer on the first dielectric structure of the first gate dielectric layer, and forming a third metal oxide layer on a top surface and a side surface of the raised structure; forming the second gate dielectric layer on the second metal oxide layer and the third metal oxide layer; forming the first gate and a second gate on the second gate dielectric layer, wherein the second gate overlaps the third metal oxide layer; A second source and a second drain electrically connected to the third metal oxide layer are formed. The manufacturing method of the memory circuit as described in claim item 15, further comprising: A doping process is performed on the first metal oxide layer and the third metal oxide layer by using the first gate electrode and the second gate electrode as masks. The manufacturing method of the memory circuit as described in claim item 15, further comprising: Before forming the first gate and the second gate, a heat treatment process is performed to diffuse the oxygen element in the raised structure into the third metal oxide layer.

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