JP6005391B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a logic circuit or a semiconductor device including a transistor including an oxide semiconductor.

  A central processing unit (CPU) has a variety of configurations depending on its application. A nonvolatile memory or a volatile memory can be used as the storage means of the CPU. As the volatile memory, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) can be used.

  The circuit configuration of the DRAM includes a switching element and a storage element that are electrically connected to a bit line and a wort line. A transistor including silicon is used for the switching element, and a capacitor element is used for the memory element.

  Such a DRAM has a simple configuration as compared with an SRAM, but the charge accumulated in the capacitor element decreases to zero with time, so that a refresh operation for newly applying a charge every certain period is performed. Necessary. The refresh operation is normally performed once every 15 to 60 microseconds for each row address.

  Such a volatile memory does not supply an erase signal because data is erased when the power is turned off.

  By the way, in recent years, studies have been made on using an oxide semiconductor instead of silicon as a material for forming a transistor. An oxide semiconductor includes an oxide material (IGZO-based material) containing In, Ga, and Zn. An oxide semiconductor is composed of ionic bonds and is different from silicon composed of covalent bonds. Research has been conducted on a nonvolatile latch circuit that holds data in a latch portion using such an oxide semiconductor for a latch holding portion (see Patent Document 1). It is described that a nonvolatile latch circuit is used as a register of a CPU.

JP 2011-142621 A

  Patent Document 1 describes that since a transistor using an oxide semiconductor is used as a switching element of a data holding portion, a logic state can be stored even when the power is turned off. Further, it is described that the system can be started at high speed and with low power when the power is turned on.

  When such a logic circuit is mounted on a CPU register, a state in which the data is not deleted continues for a certain period. This may raise security issues. That is, depending on the user, a situation occurs in which the data is forcibly deleted after a certain time.

  Therefore, the present invention provides a semiconductor device including a logic circuit capable of forcibly deleting data that causes a problem in terms of security.

  The present invention is a semiconductor device provided with means for forcibly deleting data stored in a logic circuit. The logic circuit includes a circuit that can record data and can hold the recorded data for a certain period. A circuit that can be held for a certain period includes an oxide semiconductor transistor (hereinafter referred to as an OS transistor). Since the current when Vg = 0 of the OS transistor, that is, the off-state current is very small, when the OS transistor is turned off, a terminal (node) electrically connected to the source or the drain is connected to the power source or It can be in a state where it is not connected to a grant or the like, that is, in a floating state, and data can be held for the period.

  The means for forcibly deleting the data stored in the logic circuit has means for inputting an erase signal to the gate of the OS transistor, for example. By the transistor being turned on by the means, accumulated charge can be released and data can be deleted. That is, the charge is released with the node in a floating state being electrically connected to a power source or the like.

  The means for forcibly deleting the data stored in the logic circuit includes means capable of irradiating light to the OS transistor, for example. When the OS transistor is irradiated with light, the current when Vg = 0, that is, the off-current may increase. By increasing the off-state current, accumulated charges can be released and data can be deleted. That is, the charge is released with the node in a floating state being electrically connected to a power source or the like.

  A register or cache which is a storage means of the CPU can have such a logic circuit. Registers and caches composed of Si transistors have been volatile memories, but become non-volatile memories by using the logic circuits described above.

  According to one embodiment of the present invention, a memory cell including a transistor including an oxide semiconductor, a first gate over the oxide semiconductor, and a memory element electrically connected to a source or a drain of the transistor is provided. When the transistor is off, the node of one electrode of the memory element electrically connected to the transistor can be in a floating state, and is accumulated in the memory element through the node after a certain period of time. This is a semiconductor device having means for removing charges.

  According to one embodiment of the present invention, a memory cell including a transistor including an oxide semiconductor, a first gate over the oxide semiconductor, and a memory element electrically connected to a source or a drain of the transistor is provided. When the transistor is off, the node of one electrode of the memory element electrically connected to the transistor can be in a floating state, and an erase signal is input to the first gate, In this case, the semiconductor device has means for removing charges accumulated in the storage element.

  According to one embodiment of the present invention, a transistor including an oxide semiconductor, a first gate over the oxide semiconductor, and a second gate under the oxide semiconductor, and a source or a drain of the transistor electrically And a node of one electrode of the memory element electrically connected to the transistor can be in a floating state when the memory cell includes a memory cell having a memory element connected thereto and the transistor is in an off state. 2 is a semiconductor device having means for inputting an erase signal to the gate of No. 2 and deleting charges accumulated in the memory element via the node.

  According to one embodiment of the present invention, a memory cell including a transistor including an oxide semiconductor, a first gate over the oxide semiconductor, and a memory element electrically connected to a source or a drain of the transistor is provided. And when the transistor is off, the node of one electrode of the memory element electrically connected to the transistor can be in a floating state, and the oxide semiconductor is irradiated with light to be stored through the node. This is a semiconductor device having means for removing charges accumulated in the element.

  In the structure according to one embodiment of the present invention, when a CPU including a memory cell is provided and charge accumulated in the memory element is deleted, power supply to the CPU may be stopped.

  According to the present invention as described above, even when data that is a security problem remains in the logic circuit, the data can be forcibly deleted.

It is a figure which shows the logic circuit (semiconductor device) of this invention. It is a circuit diagram showing a logic circuit (semiconductor device) of the present invention. It is a circuit diagram showing a logic circuit (semiconductor device) of the present invention. 3 is a flowchart showing an operation procedure of the logic circuit (semiconductor device) of the present invention. 3 is a flowchart showing an operation procedure of the logic circuit (semiconductor device) of the present invention. It is a figure which shows the logic circuit (semiconductor device) of this invention. It is a circuit diagram showing a logic circuit (semiconductor device) of the present invention. It is a circuit diagram showing a logic circuit (semiconductor device) of the present invention. It is a circuit diagram showing a logic circuit (semiconductor device) of the present invention. It is a circuit diagram showing a logic circuit (semiconductor device) of the present invention. It is a figure which shows CPU including the logic circuit (semiconductor device) of this invention. 1 is a diagram showing a personal computer including a logic circuit (semiconductor device) of the present invention. It is a figure which shows the structure of the logic circuit (semiconductor device) of this invention. It is a figure which shows the structure of the logic circuit (semiconductor device) of this invention. It is a figure which shows the structure of the logic circuit (semiconductor device) of this invention. It is a figure which shows the structure of the logic circuit (semiconductor device) of this invention. It is a figure which shows the usage example of IC card containing the logic circuit (semiconductor device) of this invention. It is a figure which shows the experimental result of this invention. It is a figure which shows the structure of the logic circuit (semiconductor device) of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

(Embodiment 1)
In this embodiment, a logic circuit having a storage function such as a cache, a register, and a main memory will be described as an example. FIG. 1A shows a logic circuit including a memory cell 102 having the above storage function and data erasing means 103. Since the logic circuit uses a semiconductor element, the logic circuit is also referred to as a semiconductor device. The data erasing unit 103 can output an erasing signal (Erasing Signal) to the memory cell 102 and can erase data in the memory cell 102.

  The data erasing means 103 is preferably arranged in the vicinity of the memory cell 102. For this reason, part and all of the data erasing means 103 are preferably provided in the CPU.

  FIG. 1B illustrates a mode different from that in FIG. The power supply system of the data erasing unit 103 and the power supply system of the entire logic circuit 101 are preferably different. For example, the logic circuit including the memory cell 102 is supplied with power from a first power supply 108a including an AC / DC converter, a DC / DC converter, and the like. On the other hand, the data erasing unit 103 is supplied with power from a second power source 108b including an AC / DC converter, a DC / DC converter, and the like. When supplying an erasing signal for erasing data, only the second power source 108b needs to be activated. Of course, the erase signal can be supplied even when the first and second power supplies are activated.

  By separating the power supply system in this way, accumulated data can be forcibly deleted even when power supply to a CPU having a logic circuit is stopped. For example, even if the processor having the CPU is shut down, data can be forcibly deleted. Further, data can be forcibly deleted when the processor having the CPU is in a sleep state. Further, the processor having the CPU can forcibly delete data when the display is in the screen saver state.

  FIG. 1C shows a mode in which the logic circuit further includes a control circuit 104 for controlling the data erasing means 103. The control circuit 104 can instruct the timing for executing the data erasing means 103. For example, a control circuit 104 having a timer function is arranged. By the timer function, the data erasing means 103 is controlled to output an erasing signal after a predetermined time, and the data in the memory cell 102 is erased.

  Further, the control circuit 104 has a circuit capable of instructing a situation where data should be erased by a signal. For example, a circuit that can receive a signal for erasing data after an unauthorized access to the memory cell 102 is confirmed. The control circuit 104 controls the data erasing unit 103 and outputs an erasing signal from the data erasing unit 103 to erase the data in the memory cell 102.

  The control circuit 104 does not need to be as close to the data erasing means 103 and the memory cell 102 as judged from its functional aspect. Therefore, the control circuit 104 can be provided outside the CPU. Of course, part and all of the control circuit 104 may be provided in the CPU.

  As shown in FIG. 1C, the power supply system of the data erasing means 103, the power supply system of the entire logic circuit 101, and the power supply system of the control circuit 104 can be different. The power supply system to the logic circuit including the memory cell 102 and the power supply system to the data erasing means 103 can be the same as in FIG. The control circuit 104 may be supplied with electric power from another power source including an AC / DC converter, a DC / DC converter, or the like. For example, the power may be supplied from the battery 109.

  1A to 1C, the memory cell 102 can include an OS transistor as a switching element. For example, FIG. 2 shows a circuit diagram in the case where the memory cell 102 is composed of one OS transistor and one capacitor as in a DRAM.

  As shown in FIG. 2A, a bit line 111 and a word line 112 are provided, and a memory unit 110 is provided in an intersecting region between them. A plurality of bit lines 111 are provided according to the number of memory units 110. The memory unit 110 includes an OS transistor 113 and a storage element 114. As the memory element 114, a capacitor element or a gate capacitor of a semiconductor element can be used. A source or a drain of the OS transistor 113 is electrically connected to one electrode of the memory element 114. Let the connected terminal be a node (N).

  An oxide semiconductor including In, Ga, and Zn is used for a channel formation region of the OS transistor 113. Such an oxide semiconductor can be described as an In-M-Zn-O-based material, and the metal element M only needs to be an element that has higher binding energy with oxygen than In and Zn. Specifically, the metal element M includes Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga, Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta or W may be used, and Al, Ti, Ga, Y, Zr, Ce or Hf is preferable. The metal element M can be selected from one or more of the aforementioned elements. Further, Si or Ge can be used in place of the metal element M.

  Another oxide semiconductor may be used for a channel formation region of the OS transistor 113. There are an M—Zn—O-based material or an M—O-based material (the metal element M can be selected from the preceding metal elements), a Zn—O-based material, and the like.

  Such an OS transistor 113 has a very small off-state current when the gate potential is 0 V (Vg = 0) as compared with the Si transistor. In addition, in an N-type oxide semiconductor, a leakage current when the gate potential is negative (Vg <0) is much smaller than that of a Si transistor. That is, in the memory unit in which the OS transistor 113 functions as a switching element, charge leakage from the memory element 114 becomes very small. In addition, the terminal (node: N) of one electrode of the memory element 114 which is electrically connected to the source or drain of the OS transistor 113 can be set in a floating state. Therefore, a logic circuit having an OS transistor can be regarded as non-volatile.

  Note that even if the logic circuit is not an OS transistor, a transistor with lower off-state current and leakage current than a Si transistor can be used.

  When such a logic circuit is used for a CPU register, cache, or main memory, the data in the storage element 114 remains without being erased for a certain period, so that it is necessary to delete it for security. At this time, data is forcibly deleted by an erasing signal (Erasing Signal) input from the word line 112. The erase signal input to the word line 112 may be a pulse signal having a value of Vg> 0 or more as long as the OS transistor is N-type. Further, since there is no restriction on the clock of the CPU, the potential of the erase signal can be made lower than the potential supplied to the word line 112 at the time of writing or reading. Such an erasing signal can be supplied from the data erasing means 103. Further, since neither writing nor reading is performed at the time of erasing, it is not necessary to supply a signal to the bit line 111.

  FIG. 2B shows a preferable mode when inputting the erase signal. As described above, when the erase signal is supplied from the word line 112, the data “1” is set to “0” when the potential (Vb) of the bit line 111 is lower than the potential (Va) of the memory element 114. Suitable for erasing data. For example, Vb may be 0V. In this case, when writing or reading is performed, if the bit line 111 is electrically connected to Vb, the writing or reading may not be performed well. Therefore, the transistor 119 is electrically connected to the bit line 111 as a switching element. The transistor 119 may be a Si transistor or an OS transistor. The transistor 119 only needs to be on when the OS transistor 113 is turned on by the erase signal. A signal for turning on can be supplied from the wiring 118. Thus, instead of supplying a signal to the bit line 111, the potential of the bit line 111 may be set to a low potential of Vb and an erase signal may be input to the word line 112.

  FIG. 3A shows a circuit diagram of a DRAM different from that in FIG. The OS transistor 113 in FIG. 3A includes a so-called back gate, and includes a wiring 115 for supplying a signal thereto.

  When the logic circuit is operating, the signal applied to the back gate has a signal for controlling the threshold voltage. For example, if the threshold voltage is controlled when the OS transistor is normally on, the signal can be supplied with a fixed negative value. That is, the wiring 115 can have a fixed potential.

  When the logic circuit information is deleted, an erase signal can be input using the wiring 115. That is, an erasing signal can be supplied from the data erasing means 103 to the wiring 115. When the OS transistor is N-type, the erase signal only needs to have a positive value.

  Also in the logic circuit shown in FIG. 3A, an erase signal may be input to the gate (control gate) of the OS transistor 113 via the word line 112 to forcibly erase data.

  When the logic circuit shown in FIG. 3A is used for a register, cache, or main memory of a CPU, when it is necessary to delete data for security, an erasure signal is input to the wiring 115 to forcibly You can delete data.

  FIG. 3B shows a preferable mode when inputting the erase signal. As described above, when the erase signal is supplied from the word line 112, when the potential (Vb) of the bit line 111 is lower than the potential (Va) of the memory element 114, the data “1” is set to “0”. Suitable for erasing data. For example, Vb may be 0V. In this case, when writing or reading is performed, if the bit line 111 is electrically connected to Vb, the writing or reading may not be performed well. Therefore, the transistor 119 is electrically connected to the bit line 111 as a switching element. The transistor 119 may be a Si transistor or an OS transistor. The transistor 119 only needs to be on when the OS transistor 113 is turned on by the erase signal. The signal that is turned on may be supplied from the wiring 118. Thus, instead of supplying a signal to the bit line 111, the potential of the bit line 111 may be set to a low potential of Vb and an erase signal may be input to the word line 112.

  In this way, the logic circuit of the present invention can forcibly delete data that is a problem in terms of security.

(Embodiment 2)
In this embodiment mode, another logic circuit including an OS transistor is shown, and a mode in which an erase signal is input to the circuit will be described.

  As shown in FIG. 7, six Si transistors 701 to 706 are provided, the Si transistors 702 and 704 are P-type, and the other transistors are N-type. A word line (WL) is electrically connected to the gates of the Si transistors 701 and 706. The first bit line (BT1) is electrically connected to the source or drain of the Si transistor 701. A second bit line (BT2) is electrically connected to the source or drain of the Si transistor 706. The potential of the first bit line and the potential of the second bit line can have an inversion relationship. The sources or drains of the Si transistors 702 and 704 are electrically connected to the first power supply line (Vdd). The sources or drains of the Si transistors 703 and 705 are electrically connected to the second power supply line (Vss). The potential of the first power supply line can be higher than the potential of the second power supply line. From the above, it can be seen that the logic circuit has a so-called SRAM circuit.

  In FIG. 7, two OS transistors 711 and 712, and a first capacitor element C1 and a second capacitor element C2 electrically connected to the OS transistors are further provided. One of the source and the drain of the OS transistor 711 is electrically connected to the source or drain of the Si transistor 701, and is electrically connected to an input terminal portion to which the Si transistors 702 and 703 are electrically connected. The transistors 704 and 705 are electrically connected to an output terminal portion to which the transistors 704 and 705 are electrically connected. The other of the source and the drain of the OS transistor 711 is electrically connected to the first electrode of the first capacitor C1. The second electrode of the first capacitor C1 has a constant potential Vc1. Vc1 can be a ground potential.

  One of the source and the drain of the OS transistor 712 is electrically connected to the source or drain of the Si transistor 706, and is electrically connected to the input terminal portion to which the Si transistors 704 and 705 are electrically connected. The Si transistors 702 and 703 are electrically connected to the output terminal portion to which the Si transistors 702 and 703 are electrically connected. The other of the source and the drain of the OS transistor 712 is electrically connected to the first electrode of the second capacitor C2. The second electrode of the second capacitor C2 has a constant potential Vc2. Vc2 can be a ground potential.

  Writing to and reading from such a logic circuit can be performed like an SRAM. At that time, for example, when the Si transistor 702 is turned on and the potential of Vdd is supplied to the output terminal, the OS transistor 711 is also turned on, and Vdd can be stored in the first capacitor C1. Similarly, when the Si transistor 703 is turned on and the potential of Vss is supplied to the output terminal, the OS transistor 711 is also turned on, so that Vss can be stored in the first capacitor C1. In order to hold the accumulated Vdd and Vss, the OS transistor 711 is turned off.

  As described above, the first capacitor C <b> 1 can hold the potential of Vdd or Vss output via the OS transistor 711. When the OS transistor 711 is turned off, the off-state current and the leakage current are much smaller than those of the Si transistor, so that the potential of Vdd or Vss can be held for a certain period. The terminal N1 of the first capacitor element C1 can be in a floating state.

  Similarly, when the Si transistor 704 is turned on and Vdd is supplied to the output terminal, the OS transistor 712 is turned on, Vdd is supplied to the second capacitor C2, and the OS transistor 712 is turned on when Vss is supplied to the output terminal. As described above, Vss can be stored in the second capacitor element. The OS transistor 712 is turned off in order to hold the accumulated Vdd and Vss.

  As described above, the second capacitor C <b> 2 can hold the output potential of Vdd or Vss through the OS transistor 712. When the OS transistor 712 is turned off, the off-state current and the leakage current are very small as compared with the Si transistor, so that the potential of Vdd or Vss can be held for a certain period. The terminal N2 of the second capacitor element C2 can be in a floating state.

  In this way, even when the power is turned off in a state where charges are held in the first capacitor element C1 or the second capacitor element C2, the charges can be held. That is, such a logic circuit can be provided with non-volatility as compared with a circuit including Si transistors 701 to 706.

  After that, when the power supply is turned on, the logic circuit shown in FIG. 7 can read the charge accumulated in the first capacitor element C1 or the second capacitor element C2 by turning on the OS transistor 711 or 712. . For example, when the OS transistor 711 is turned on, the potential of the output terminal of the CMOS circuit formed by the Si transistors 702 and 703 can be set to a potential corresponding to the first capacitor C1. This operation can be executed without turning on the Si transistor 701, that is, without writing. When the OS transistor 712 is turned on, the potential of the output terminal of the CMOS circuit formed by the Si transistors 702 and 703 can be set to a potential corresponding to the second capacitor element C2. This operation can be performed without turning on the Si transistor 706, that is, without performing writing.

  In view of the above operation, the first capacitor element C1 and the second capacitor element C2 are more preferable as the capacitance value is larger.

  Note that in the above logic circuit, transistors other than the OS transistors 711 and 712 can have transistors with lower off-state current and leakage current than Si transistors.

  When such a logic circuit is used for a register, cache, or main memory of a CPU, data stored in the first capacitor element C1 and the second capacitor element C2 remains without being erased for a certain period. In addition, it is necessary to delete. At that time, an erase signal (Erasing Signal) is input to the gates (Vg1, Vg2) of the OS transistors 711, 712 to forcibly delete the data. The erase signal may be a pulse signal having a value of Vg> 0 or more as long as the OS transistor is N-type. The erasing signal can be supplied from the data erasing means 103. The erase signal can be input to one or both of the OS transistors 711 and 712 that are electrically connected to the capacitor in which electric charge is stored. All you have to do is erase the data.

  When the erase signal is input to the gate of the OS transistor 711, the Si transistor 701 is turned on. Then, charges are discharged from the first capacitor element C1 to the bit line (BT1).

  When the erase signal is input, a switching element electrically connected to the bit line (BT1) may be provided as illustrated in FIG. A transistor can be used as the switching element. When an erase signal is input to the gate of the OS transistor 711, the transistor is turned on at the same time, so that the charge accumulated in the first capacitor element C1 can be easily discharged. . This is suitable for erasing data when “1” data is set to “0”.

  When an erase signal is input to the gate of the OS transistor 712, the Si transistor 706 is turned on. Then, charges are discharged from the second capacitor element C2 to the bit line (BT2).

  When the erase signal is input, a switching element electrically connected to the bit line (BT2) may be provided as illustrated in FIG. A transistor can be used as the switching element. When an erase signal is input to the gate of the OS transistor 712, the transistor is turned on at the same time, so that the charge accumulated in the second capacitor element C2 can be easily discharged. . This is suitable for erasing data when “1” data is set to “0”.

  FIG. 8 shows a circuit diagram different from FIG. The OS transistors 711 and 712 in FIG. 8 have so-called back gates. Although not shown in FIG. 8, a wiring for supplying a signal to the back gate is also provided.

  When the logic circuit is operating, the signal applied to the back gate has a signal for controlling the threshold voltage. For example, when the threshold voltage is controlled when the OS transistors 711 and 712 are normally on, the signal can be supplied with a fixed negative value.

  When deleting information on the logic circuit, an erasing signal can be input. In the case where the OS transistors 711 and 712 are N-type, the erase signal only needs to have a positive value.

  When the logic circuit shown in FIG. 8 is used for a CPU register, cache, or main memory, when it is necessary to delete data for security reasons, an erase signal is input to the back gate to force data to be deleted. Can be deleted.

  Also in the logic circuit shown in FIG. 8, an erase signal may be input to the gate (control gate) of the OS transistor 711 or 712 to forcibly erase data.

  When an erase signal is input, a switching element electrically connected to the bit line (BT1) may be provided as illustrated in FIG. A transistor can be used as the switching element. When the erase signal is input to the back gate of the OS transistor 711, the transistor is turned on at the same time, so that the charge accumulated in the first capacitor element C1 can be easily discharged. To do. This is suitable for erasing data when “1” data is set to “0”.

  Similarly, when an erase signal is input, a switching element electrically connected to the bit line (BT2) may be provided as shown in FIG. A transistor can be used as the switching element. When an erase signal is input to the back gate of the OS transistor 712, the transistor is turned on at the same time, so that the charge accumulated in the second capacitor element C2 can be easily discharged. To do. This is suitable for erasing data when “1” data is set to “0”.

  In this way, the logic circuit of the present invention can forcibly delete data that is a problem in terms of security.

(Embodiment 3)
In this embodiment mode, another logic circuit including an OS transistor is shown, and a mode in which an erase signal is input to the circuit will be described.

  As shown in FIG. 9A, a case will be described in which one Si transistor 901, one OS transistor 911, and a capacitor C1 are included, and each transistor is N-type. The first electrode of the capacitor C <b> 1 is electrically connected to one of the source and the drain of the OS transistor 911 and the gate of the Si transistor 901.

  FIG. 9B shows the relationship between the potential (Vc) of the second electrode of the capacitor C1 and the current (Id) flowing through the Si transistor 901. When the node of the first electrode of the capacitor C1 becomes High, the current Id1 flowing through the Si transistor 901 becomes Id1 shown in FIG. 9B, and when the node becomes Low, the current flowing through the Si transistor 902 Id is Id2 shown in FIG. 9B, and the current Id shows two states when viewed from the terminal Vc. By utilizing this, a binary memory element can be obtained.

  When the OS transistor 911 is turned off at the time of Id1, the node N is in a floating state, and the current Id1 flowing through the Si transistor 901 can be held for a certain period or more. At the time of Id2, when the OS transistor 911 is turned off, the node N is in a floating state, and the current Id2 flowing through the Si transistor 901 can be held for a certain period or more.

  If such a logic circuit is used for a register, cache or main memory of a CPU, the data accumulated as the current Id1 or Id2 flowing through the Si transistor 901 remains without being erased for a certain period. Need to do. At that time, an erase signal (Erasing Signal) is input to the gate (S2) of the OS transistor 911 to forcibly delete the data. The erase signal may be a pulse signal having a value of Vg> 0 or more as long as the OS transistor is N-type. The erasing signal can be supplied from the data erasing means 103. When the erase signal is input to the OS transistor 911, the node (N) becomes LOW, so that the current Id1 becomes Id2, and the data is erased.

  FIG. 10 shows a circuit diagram different from FIG. The OS transistor 911 in FIG. 10 has a so-called back gate. Although not shown in FIG. 10, wiring for supplying a signal to the back gate is also provided.

  When the logic circuit is operating, the signal applied to the back gate has a signal for controlling the threshold voltage. For example, when the threshold voltage is controlled when the OS transistor 911 is a normally-on type, the signal can be supplied with a fixed negative value.

  When deleting information on the logic circuit, an erasing signal can be input. In the case where the OS transistor 911 is N-type, the erase signal only needs to have a positive value. When the erase signal is input to the back gate side of the OS transistor 911, the node (N) becomes LOW, so that the current Id1 becomes Id2, thereby erasing data.

  Also in the logic circuit shown in FIG. 10, an erase signal may be input to the gate (control gate) of the OS transistor 911 to forcibly erase data.

  When the logic circuit shown in FIG. 10 is used for a CPU register, cache, or main memory, when it is necessary to delete data for security reasons, an erase signal is input to the back gate to force the data to be deleted. Can be deleted.

  In this way, the logic circuit of the present invention can forcibly delete data that is a problem in terms of security.

(Embodiment 4)
In the present embodiment, an example of the configuration of the data erasing unit is illustrated with reference to FIG.

  The data erasing unit 103 illustrated in FIG. 6A includes a detection unit 201, a determination unit 202, and an erasure signal generation unit 203. The detection unit 201 detects whether data is stored in the memory cell 102 and whether the data needs to be erased. For example, the detection unit 201 includes a counter circuit and can count the number of accesses to the memory cell 102, that is, the number of times a signal is input to the word line 112 or the bit line 111. The detection unit 201 includes a reset circuit that resets the count number of the counter circuit. When the number of times reaches a certain value, the data in the memory cell 102 can be erased. In erasing, there is no problem even if an external input device such as a touch panel, keyboard, mouse, or voice input device is accessed, but it is preferable for the CPU that the access is not performed.

  Accordingly, the determination unit 202 can determine that there is no access from an external input device such as a touch panel, a keyboard, a mouse, or a voice input device. If the detection unit 201 detects that the number of times is equal to or greater than a certain number and there is no access to the external input device, the erase signal generation unit 203 generates a data erase signal, Can be output.

  Such a detection unit 201 and an erasure signal generation unit 203 can be provided in the CPU, and the determination unit 202 can be provided outside the CPU. Thus, a part of the data erasing means can be provided inside the CPU. Of course, all of the data erasing means may be provided inside the CPU.

  The data erasure signal may have a potential at which the OS transistor is turned on. For example, if the OS transistor is an N-type transistor, it is turned on when a gate potential Vg> 0 is applied, and the charge of the memory element 114 electrically connected to the turned-on OS transistor is discharged. Data is erased. That is, the node (N) that has been in a floating state is electrically connected to a power source or the like.

  Note that the data erasure unit 103 does not have a detection unit such as a counter circuit, and may erase the data based on an instruction that the data is to be erased for security reasons. Allocate the command. When erasing data, it is preferable that there is no access to the external input device.

  A data erasing unit 103 illustrated in FIG. 6B includes a light irradiation unit 213 instead of the erasing signal generation unit 203 illustrated in FIG. The light irradiation means 213 includes a light source 213a and a drive circuit 213b that controls the light source.

  First, as in FIG. 6A, the detection unit 201 detects whether data is stored in the memory cell 102 and whether the data needs to be erased. For example, it can be detected by a counter circuit.

  Next, the determination unit 202 determines that there is no access to the external input device. When it is detected by the detection unit 201 that the number of times has reached a certain number or more and there is no access to the external input device, a signal is output to the drive circuit 213b included in the light irradiation unit 213, and the light source 213a is operated. The memory cell 102 is irradiated with light.

  A halogen lamp can be used as the light source 213a. A self-luminous element can be used instead of the halogen lamp. The wavelength of the light source 213a can be determined from the band gap of the oxide semiconductor included in the OS transistor.

  Since the off-state current of the OS transistor exposed to the light increases, the charge of the memory element 114 that is electrically connected to the OS transistor can be discharged.

  Such a detection part 201 and the light irradiation means 213 can be provided in CPU. It is preferable to provide the light irradiation unit 213 in the CPU because it can be made into one chip. The determination unit 202 can be provided outside the CPU. Thus, a part of the data erasing unit 103 can be provided inside the CPU. Of course, all of the data erasing means 103 may be provided inside the CPU.

  Note that the data erasure unit 103 does not have a detection unit such as a counter circuit, and may erase the data based on an instruction that the data is to be erased for security reasons. Allocate the command. When erasing data, it is preferable that there is no access to the external input device.

  In this way, the data in the memory cell can be erased by the data erasing means.

(Embodiment 5)
In the present embodiment, a procedure until data erasure is performed will be described using the flowchart shown in FIG.

  First, it is confirmed whether or not data is held (S1). If it is held, as the next procedure, it is confirmed whether or not the data is to be deleted (S2). The state in which data is deleted is a state in which the logic circuit is not operating or a state in which writing and reading to the memory cell are not performed. Thereafter, an access status to an external input device such as a touch panel, a keyboard, a mouse, and a voice input device is confirmed (S3). If there is an access to the external input device, there is a possibility that data writing or reading to other than the memory cell continues. At this time, the data in the memory cell may be erased, but this is not preferable for the CPU. Furthermore, if access to the external device is confirmed, the user continues to use it, and the necessity of erasing data is low for security. Therefore, data erasure should be performed when there is no access to the external input device for a certain period or longer (S4).

  The user can set a period when there is no access to the external input device in advance. The access frequency can also be taken into account. For example, when the statistics of the most recent usage time are created and the time is an outlier from the value derived from the statistics, it can be determined that the access is not longer than a certain period.

  FIG. 5 shows a procedure in a case different from the flowchart shown in FIG. The difference is that a step (S3 ') for stopping the power supply to the CPU is provided after the step (S3) for checking the access status to the external input device. Low power consumption can be achieved. Stopping power supply includes stopping a start pulse, a clock signal, and the like, and the power of the CPU system can be turned off.

  In such a case, the sleep state can be entered. Even in the sleep state, data can be deleted by the data erasure signal means (S4).

  Even when the power supply of the CPU system is turned off, the OS transistor has a very small off-current compared to the Si transistor, so that data can be held for a certain period. If the data is a security problem, the data is erased by the data erasing means, but a power supply different from the power supply of the CPU system may be required.

  According to such a procedure, the data in the memory cell can be erased.

(Embodiment 6)
In this embodiment, an example of an internal circuit of a CPU and an external circuit of the CPU will be described.

  FIG. 11 shows an interrupt controller 11, an instruction register / decoder 12, a program counter 13, an arithmetic logic unit (ALU) 14, a plurality of registers 15, a data input / output register 16, and an address output register 17, which are internal circuits of the CPU. Show.

  The CPU fetches the instruction at the instruction address set in the program counter 13 into the instruction register, and decodes the fetched instruction with the instruction decoder. These are performed via the bus 20a.

  The instruction decoder generates an internal control signal for executing the instruction according to the result. By these control signals, the operation of an arithmetic circuit such as the ALU 14 and the like, and the read / write of the operand with respect to the register 15 are controlled, and the instruction is executed. The executed result can be output to the register 15. These are performed via the bus 20c.

  Since the primary cache memory 31 has the same speed as the program counter 13 and the like, it exchanges with the program counter 13 and the instruction register / decoder 12 and the like via the bus 20a. The one cache memory 31 is provided to improve transfer efficiency by shielding the transfer delay as much as possible when there is a transfer delay between the other memory and the program counter.

  As other memories, there are a secondary cache memory 32 and a main memory 33. These can be exchanged via each controller via the bus 20b. When the primary cache memory 31 communicates with the secondary cache memory 32 and the main memory 33, information is transferred using the bus 20b through the controller.

  These memory areas having a storage function are arbitrarily accessible by the CPU. The OS transistor can be used as a switching element of the register 15, the primary cache 31, the secondary cache 32, and the main memory 33.

  The interrupt controller 11 has logic for controlling instruction execution procedures such as interrupt and exception processing.

  The bus 20a is a bus having a higher transfer speed than the bus 20b and the bus 20c.

  The CPU outputs the address of the instruction address to the address bus 21 via the address output register 17 and inputs / outputs data to / from the data bus 22 via the data input / output register 16.

  As an internal circuit of the CPU, a part 35a of data erasing means can be provided. Via the bus 20b and the primary cache memory 31, it is possible to communicate with the program counter 13, the ALU 14, the register 15, and the like. A part 35a of the data erasing means can communicate with the secondary cache 32 and the main memory 33 via the data bus 21b. A part 35 a of the data erasing means can obtain an address from the address bus 22.

  The control register 41 can communicate with the primary cache memory 31, the secondary cache memory 32, the main memory 33 and the like via the data bus 21 and the data input / output register 16. The control register 41 can obtain an address from the address bus 22. The control register 41 can communicate with an external controller (including a display controller) 42 and an external memory (including a nonvolatile memory such as an HDD) 43. The other part 35b of the data erasing means can communicate with the external controller 42, and can grasp the access status to the external controller 42. The information is output to the control register 41, and is output to the part 35a of the data erasing means via the data bus 21. It is possible to specify whether the situation is forcibly deleted.

  FIG. 12 shows an overall view of a personal computer equipped with a CPU. The CPU 50 based on FIG. 11 and the main memory 51 provided outside are mainly shown. The external controller 42 includes a power controller 52, a clock controller 53, a sound controller 54, an I / O controller 55, and a display controller 56. The sound controller 54 can control the speaker 62. The I / O controller 55 is controlled by a switch 64. The display controller 56 can control the display 63.

  A ROM (Read Only Memory) 61 serving as an HDD is provided as an external memory. A RAM (Random Access Memory) 60 may be included.

  In such a personal computer, an OS transistor can be used for any one or all of a register in the CUP, a primary cache, a secondary cache, and a main memory. Since the OS transistor has an extremely small off-state current or leakage current as compared with the Si transistor, power consumption can be suppressed. In addition, information in the memory element electrically connected to the OS transistor can be held for a certain period. That is, any one or all of the register, the primary cache, the secondary cache, and the main memory can function as a nonvolatile memory.

  The information held for a certain period can be forcibly deleted if it is deleted for security reasons.

(Embodiment 7)
In this embodiment, a structure of a logic circuit is described.

  As illustrated in FIG. 13, the OS transistor 131 and the capacitor 132 are provided over the insulating surface 130. Such a structure can be applied to, for example, the logic circuit described with reference to FIG. 2, and the memory element 114 in FIG. 2 corresponds to the capacitor 132 in FIG.

  The OS transistor 131 includes an oxide semiconductor layer 134. An oxide semiconductor including In, Ga, and Zn is used for a channel formation region of the transistor in the oxide semiconductor layer 134. Such an oxide semiconductor can be described as an In-M-Zn-O-based material, and the metal element M only needs to be an element that has higher binding energy with oxygen than In and Zn. Specifically, the metal element M includes Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga, Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta or W may be used, and Al, Ti, Ga, Y, Zr, Ce or Hf is preferable. The metal element M can be selected from one or more of the aforementioned elements. Further, Si or Ge can be used in place of the metal element M.

  Another oxide semiconductor may be used for the channel formation region. There are an M—Zn—O-based material or an M—O-based material (the metal element M can be selected from the preceding metal elements), a Zn—O-based material, and the like.

  The oxide semiconductor layer 134 may be amorphous or crystalline, or may have a mixed state of amorphous and crystals. That is, the oxide semiconductor layer can have a crystal region. The crystal region included in the oxide semiconductor layer includes two or more types of crystal parts having different a-axis or b-axis orientations on the ab plane (or the upper surface or the formation surface). The boundary between one crystal part and another crystal part cannot be clearly discriminated by an observation image obtained by a transmission electron microscope (TEM). At least one of the crystals is c-axis oriented and has an atomic arrangement of at least a triangular shape or a hexagonal shape when viewed from a direction perpendicular to the ab plane, the top surface, or the formation surface. The c-axis has a region where metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. This is also called CAAC oxide: C Axis Aligned Crystalline Oxide. In other words, the CAAC oxide is a non-single crystal in a broad sense and is not formed only from an amorphous material.

  Next, an example of a method for forming a CAAC oxide film is described.

First, an oxide film is formed over a flat insulating surface by a sputtering method, an evaporation method, a PCVD method, a PLD method, an ALD method, an MBE method, or the like. In order for the formed oxide film to be a CAAC oxide film, one or more of the following heat treatments are performed.
(1) An oxide film is formed while heating the insulating surface.
(2) After the oxide film is formed, the oxide film is heated.

<When forming an oxide film while heating the insulating surface>
The insulating surface will be described as a substrate. By forming the oxide film while heating the substrate, an oxide film in which the proportion of the crystal portion is larger than that of the amorphous portion can be obtained. For example, heating is performed so that the substrate temperature is 150 ° C to 450 ° C, preferably 200 ° C to 350 ° C.

<When heating the oxide film after forming the oxide film>
For example, heat treatment is performed on the formed oxide film at 200 ° C. or higher and lower than the strain point of the substrate, preferably 250 ° C. or higher and 450 ° C. or lower. The oxide film may be radiantly heated by heating the substrate at the heating temperature. The heating atmosphere may be an oxidizing atmosphere, an inert atmosphere, or a reduced pressure atmosphere (10 Pa or less). The oxidizing gas is oxygen, ozone, nitrous oxide, or the like, and preferably does not contain water, hydrogen, or the like. The inert atmosphere is an atmosphere mainly containing an inert gas such as nitrogen or a rare gas (helium, neon, argon, krypton, xenon). The heat treatment time is 3 minutes to 24 hours. As the treatment time is increased, an oxide film having a higher ratio of crystal parts to amorphous parts can be formed.

  When the heat treatment time is short, an RTA (Rapid Thermal Anneal) apparatus can be used.

  Note that as described above, this heat treatment may be performed after the treatment (1).

  With the above method, a CAAC oxide film can be formed.

  The oxide semiconductor layer 134 may form an oxide stack obtained by forming a second oxide film over the first oxide film. The composition ratio of the first oxide film and the second oxide film may be different. Not only two layers but also a multilayer structure may be used.

  Next, a conductive film functioning as the source 135 and the drain 136 electrically connected to the oxide semiconductor layer 134 is formed. Cu having low resistance can be used for the source and drain. W may be used instead of Cu. In addition to Cu and W, Al, Ti, Mo, Ta, or the like can be used. The nitrides of the listed materials can be used. The listed materials may be laminated.

  The capacitor 132 includes a conductive film 137 having the same material as the source and drain. The conductive film 137 can function as one electrode of the capacitor 132. One of the source and the drain can be electrically connected to one electrode 137 of the capacitor 132.

  An insulating film 138 functioning as a gate insulating film is formed so as to cover them. The capacitor 132 can also include part of the insulating film 138 and can function as a dielectric. By reducing the thickness of the insulating film 138, the capacitance value of the capacitor 132 can be increased.

  For the insulating film 138, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, or the like can be used.

In the OS transistor 131, a conductive film 139 which functions as a gate electrode overlapping with the oxide semiconductor layer 134 is formed with the insulating film 138 interposed therebetween. For the conductive film 139, a light-transmitting material is used. As one of the erasing means, in the case where light having a wavelength corresponding to the band gap of the oxide semiconductor included in the oxide semiconductor layer 134 is irradiated, it is preferable that the light has a light-transmitting property. In the case where the light-transmitting property is low, the thickness of the gate electrode is preferably smaller than that of the oxide semiconductor layer 134. As the light-transmitting material, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like may be used.

  In the case where data is not erased by irradiating light, choices of materials for the conductive film 139 are widened. For example, W can be used. Instead of W, Cu having low resistance can be used. In addition to W and Cu, Al, Ti, Mo, Ta and the like can be used. The nitrides of the listed materials can be used. The listed materials may be laminated. For example, there is a laminated structure of tantalum nitride and tungsten, which can be selected from various combinations.

  A region where the gate electrode 139 overlaps with the oxide semiconductor layer 134 serves as a channel formation region. The gate electrode 139 is disposed so as not to overlap the source 135 and the drain 136. Impurities can be implanted into the non-overlapping regions 141 and 142 in the oxide semiconductor layer 134 using the gate electrode 139 as a mask. For example, phosphorus is injected. Then, the resistance of the regions 141 and 142 can be lowered.

  In the case where light irradiation for forcibly erasing data is performed on the oxide semiconductor layer 134, the oxide semiconductor layer can be irradiated with the light from the regions 141 and 142.

  The capacitor 132 also includes a conductive film 140 that has the same material as the gate electrode. When the conductive film 137 is a first electrode, the conductive film 140 functions as a second electrode. The capacitor 132 has an insulating film 138 between them.

  A passivation film 145 is formed over the OS transistor 131 and the capacitor 132. As the passivation film, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, or the like can be used. The passivation film may be formed by stacking the listed materials.

  In this manner, the OS transistor 131 and the capacitor 132 can be formed over the same insulating surface.

  An erase signal can be input to the gate electrode 139 of the OS transistor 131. As a result, data stored in the capacitor 132 can be forcibly erased.

(Embodiment 8)
In this embodiment, a structure of another logic circuit, in which an OS transistor has a so-called bottom gate, is described.

  As illustrated in FIG. 14, the conductive film 151 is provided below the oxide semiconductor layer 134. It can function as a so-called back gate of the OS transistor 131. The conductive film 151 can be formed over the insulating surface 130. For the conductive film 151, W can be used. Instead of W, Cu having low resistance can be used. In addition to W and Cu, Al, Ti, Mo, Ta and the like can be used. The nitrides of the listed materials can be used. The listed materials may be laminated. For example, there is a laminated structure of tantalum nitride and tungsten, which can be selected from various combinations.

  The conductive film 151 functioning as a back gate preferably has more regions overlapping with the oxide semiconductor layer 134. This is because the threshold value of the OS transistor 131 can be reliably controlled. The conductive film 151 preferably does not have a region provided beyond the oxide semiconductor layer 134. This is because when the conductive film 151 is provided so as to exceed the oxide semiconductor layer 134, the source 135 and the drain 136 overlap with the conductive film 151, which may cause unnecessary capacitance. That is, in FIG. 14, the width d1 of the conductive film 151 is preferably smaller than the width d3 of the oxide semiconductor layer 134, and this relationship can be expressed as d1 <d3.

  When the width of the gate electrode 139 is d2, d1> d2. This is because the threshold value of the OS transistor 131 can be reliably controlled.

  In the case where light irradiation is performed forcibly erasing data from above the oxide semiconductor layer 134, the light travels from the regions 141 and 142 and is irradiated to the oxide semiconductor layer 134. Further, the light can be emitted from the back of the oxide semiconductor layer 134 by being reflected by the conductive film 151.

  An insulating film 152 is formed so as to cover the conductive film 151. For the insulating film 152, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, or the like can be used. The insulating film 152 is planarized so that the surface thereof is the same as the surface of the conductive film 151.

  An insulating film 153 is formed over the insulating film 152. The insulating film 153 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, or the like. Since it is preferable to use aluminum oxide as the oxide semiconductor 134 is approached, silicon oxide is preferably used for the insulating film 152 and aluminum oxide is used for the insulating film 153.

  A signal for controlling a threshold value can be input to the conductive film 151 functioning as a back gate, and an erase signal can be input. When a signal for controlling the threshold value is input, for example, a normally-on type OS transistor can be changed to a normally-off type OS transistor. When an erase signal is input, data stored in the capacitor 132 can be forcibly erased.

(Embodiment 9)
In this embodiment, a structure of another logic circuit, which includes both an OS transistor and a Si transistor, will be described.

  As shown in FIG. 15A, an OS transistor 131 and a capacitor 132 are provided over an Si transistor 160 with an insulator that forms an insulating surface 130 interposed therebetween. Such a configuration can be applied to the logic circuit described with reference to FIG. The Si transistor 160 of FIG. 15 can be applied to the Si transistors 701 to 706 of FIG. The OS transistor 131 in FIG. 15 can be applied to the OS transistors 711 and 712 in FIG. Further, the capacitor 132 in FIG. 15 can be applied to the first capacitor C1 and the second capacitor C2 in FIG. As shown in FIG. 15A, the capacitor 132 can be provided in a layer different from that of the Si transistor, and since there is not much restriction on the area, the capacitance value can be increased. That is, the capacitance values of the first capacitor element C1 and the second capacitor element C2 in FIG. 7 can be increased.

  A semiconductor substrate 161 is prepared. An insulator for element isolation is formed on the semiconductor substrate 161. So-called insulation isolation is performed. After that, the surface of the semiconductor substrate 161 is thermally oxidized to form an insulating film 163 that functions as a gate insulating film. A conductive film 164 functioning as a gate electrode is formed over the insulating film 163. Polycrystalline silicon can be used for the conductive film 164. In addition to polycrystalline silicon, materials having high heat resistance such as W and Mo can be used. These listed materials may be laminated.

  The insulating film 163 is etched using the gate electrode so as to be a selective gate insulating film. Then, the edge part of a gate electrode and the edge part of a gate insulating film can correspond.

  An impurity is added to the semiconductor substrate 161 using the gate electrode, so that a first impurity region 165 is formed. N-type impurities or P-type impurities can be used. Since the impurity is added using the gate electrode, the end portion of the first impurity region 165 and the end portion of the gate electrode can coincide with each other. The first impurity region 165 can be provided so that the depth gradually increases from a location that matches the end portion of the gate electrode as the distance from the location is increased.

  An insulator 166 functioning as a sidewall is formed on the side surface of the gate electrode. An insulator 166 functioning as a sidewall can be obtained by forming an insulating film so as to cover the gate electrode and performing etching. After that, a second impurity region 167 is formed by adding an impurity to the semiconductor substrate 161 using a sidewall. N-type impurities or P-type impurities can be used. The end portion of the second impurity region 167 substantially coincides with the end portion of the sidewall. However, since the impurity diffuses, the combination of the end portion of the first impurity region 165 and the end portion of the gate electrode is increased. The parts do not match.

  Silicide treatment may be performed to reduce the resistance of the gate electrode. In the case where the gate electrode is formed of polycrystalline silicon, silicide treatment is performed using nickel or titanium. Platinum or the like may be added to these to improve the silicidation process efficiency. When the silicide treatment is performed, a silicide region can be formed at least on the upper surface of the gate electrode.

  Thereafter, a passivation film 170 is formed. As the passivation film 170, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film can be used. Such a material is a film containing an inorganic material, and the surface remains uneven. In order to maintain the flatness of the unevenness, an insulating film 171 can be further formed. The insulating film 171 can be formed using a silicon oxide film, a silicon oxynitride film, or a silicon nitride film, and may be formed thicker than the passivation film 170.

  A wiring 172 electrically connected to the second impurity region 167 is formed. For the wiring 172, a material having high heat resistance such as W or Mo can be used. In order to form the wiring 172, contact holes are formed in the passivation film 170 and the insulating film 171.

  Thereafter, planarization is performed to align the surfaces of the wiring 172 and the insulating film 171. A first connection wiring 173 is formed on the planarized surface. It becomes easier to form the first connection wiring 173. The first connection wiring 173 may be formed using a low resistance material such as Cu. Cu is easily thermally diffused. In the case of thermal diffusion, a barrier film such as tantalum or tantalum nitride is preferably provided surrounding the first connection wiring 173.

  Thereafter, as described with reference to FIG. 13 or FIG. 14, an insulating film constituting the insulating surface 130 is formed. After that, the OS transistor 131 and the capacitor 132 are formed over the insulating surface. A second connection wiring 174 is formed to electrically connect the OS transistor 131 and the like to the Si transistor 160. In order to form the second connection wiring 174, a contact hole is formed in the insulating film constituting the insulating surface 130. The contact hole has a bottom surface width (W) larger than a height (h). That is, a sufficiently wide bottom surface can be formed, and the second connection wiring 174 can be formed on the bottom surface. On the bottom surface, the contact area with the first connection wiring 173 can be increased, and the connection can be ensured.

  The second connection wiring 174 can be formed using the same material as the source 135 and the drain 136. A material having low resistance such as Cu may be used for the second connection wiring 174. In the case of thermal diffusion, a barrier film such as tantalum or tantalum nitride may be provided. In the case of providing a barrier film, the insulating film 138 which covers the second connection wiring 174 and partially functions as a gate insulating film may be formed of tantalum, tantalum nitride, or the like. If a function as a gate insulating film is added, a barrier film such as tantalum or tantalum nitride may be stacked with the above-described material such as silicon oxide, silicon nitride, or gallium oxide.

  In this way, a configuration having both an OS transistor and a Si transistor can be obtained.

  As in the above embodiment, an erase signal can be input to the gate electrode 139 of the OS transistor 131. As a result, data stored in the capacitor 132 can be forcibly erased.

  FIG. 15B is different from FIG. 15A in that it includes a light-blocking film 180. The light-shielding film 180 can prevent the Si transistor 160 from being irradiated with light when the oxide semiconductor layer 134 is irradiated with light.

  When the light shielding film 180 has conductivity such as Ti, the light shielding film 180 is formed on the insulating film 181. In the case where the light shielding film 180 has low conductivity such as black resin, the insulating film 181 can be omitted. Note that the insulating film 181 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, or the like.

  The passivation film 170 may have a function of a light shielding film for preventing light irradiation to the Si transistor 160.

FIG. 15B further differs from FIG. 15A in that the sidewall has a two-layer structure. The second impurity region has two regions having different concentrations.
As described above, the Si transistor 160 can have various configurations.

  In FIG. 15B as well, an erase signal can be input to the gate electrode 139 of the OS transistor 131. As a result, data stored in the capacitor 132 can be forcibly erased.

(Embodiment 10)
In this embodiment, another structure of a logic circuit, which includes an OS transistor and an Si transistor, and the OS transistor includes a so-called back gate will be described.

  The back gate included in the OS transistor 131 illustrated in FIG. 16A may be provided with reference to FIG.

  A signal for controlling a threshold value can be input to the conductive film 151 functioning as a back gate, and an erase signal can be input. When a signal for controlling the threshold value is input, for example, a normally-on type OS transistor can be changed to a normally-off type OS transistor. When an erase signal is input, data stored in the capacitor 132 can be forcibly erased.

  The structure illustrated in FIG. 16A is different from the structure illustrated in FIG. 15A in the shape of a contact hole for forming the second connection wiring 174. The width (W) of the bottom surface of the contact hole is made smaller than the depth (h). Then, the contact hole can be formed inside the first connection wiring 173. Even if the second connection wiring 174 is formed in such a contact hole, electrical connection can be established. Such contact holes can increase the degree of integration. The shape of the contact hole can be applied to the contact hole of the second connection wiring 174 illustrated in FIGS. 15A and 15B can be applied to the contact hole shown in FIG. 16A.

  FIG. 16B has a light-blocking film 180 unlike FIG. The light-shielding film 180 can prevent the Si transistor 160 from being irradiated with light when the oxide semiconductor layer 134 is irradiated with light. In the case where the light shielding film 180 has conductivity, the light shielding film 180 is formed over the insulating film 181.

The passivation film 170 can also have the function of a light shielding film.
The conductive film 151 functioning as a back gate can have the function of a light-blocking film. In that case, the source 135 and the drain 136 may be used together as a light-shielding film. Since the conductive film 151, the source 135, and the drain 136 can be arranged so as to overlap with each other, a path through which light passes can be blocked.
In this way, if the existing film can function as a light shielding film, the light shielding film 180 and the insulating film 181 can be omitted.

FIG. 16B is different from FIG. 16A in that the sidewall has a two-layer structure. The second impurity region has two regions having different concentrations.
As described above, the Si transistor 160 can have various configurations.

  In FIG. 16B as well, an erase signal can be input to the gate electrode 139 of the OS transistor 131. As a result, data stored in the capacitor 132 can be forcibly erased.

(Embodiment 11)
In this embodiment mode, a configuration in which a self-luminous element is used as a light source of a light irradiation unit, which is a configuration of a logic circuit, will be described.

  As illustrated in FIG. 19, an OS transistor 131 having a back gate is provided over a Si transistor 160, and a light-emitting element 190 is provided over the OS transistor 131. The light emitting element 190 is provided over the insulating film 191. The insulating film 191 preferably has flatness and is preferably formed using a film containing an organic material. For example, the film | membrane containing an acryl and a polyimide is mentioned.

A conductive film 193 to be a first electrode of the light-emitting element 190 is formed over the insulating film 191. The first electrode can function as an anode or a cathode. In order to extract light from the first electrode side, the conductive film 193 has a light-transmitting property. For example, the transparent conductive film 193 can be formed using ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like.

  An insulator 192 functioning selectively as a bank is formed over the first electrode. The side surface of the insulator 192 may have a reverse taper. The insulator 192 can be formed of a layer containing an inorganic material such as silicon oxide or silicon oxynitride.

  An organic compound layer 194 is formed over the first electrode. The organic compound layer 194 may have a light emitting layer of a light emitting element. The organic compound layer 194 may have a hole injection layer or a hole transport layer. The organic compound layer 194 may have an electron injection layer or an electron transport layer. The organic compound layer 194 is divided by an insulator 192 having a reverse taper.

  A conductive film 195 that serves as the second electrode of the light-emitting element 190 is formed over the organic compound layer 194. The second electrode can function as a cathode or an anode. The second electrode is preferably highly reflective, and can be formed from a film containing Al or Ag, for example. For example, an Mg—Ag film having Mg and Al may be used.

In this state, packaging is performed. Using the sealing substrate 198, the Si transistor, the OS transistor, and the light emitting element can be formed into one chip.
In order to prevent deterioration of the light-emitting element, an atmosphere surrounded by the sealing substrate 198 is preferably filled with an inert gas.

  In this manner, data stored in the capacitor can be forcibly deleted by irradiating the OS transistor with light.

(Embodiment 12)
In this embodiment, a usage example of an IC card on which a logic circuit is mounted will be described.

  A chip is mounted on the IC card 350 and can have a memory function. The structure of the logic circuit of the present invention can be applied to the memory function.

  As shown in FIG. 17A, data such as personal information of the owner and shopping history is recorded in the IC card 350 equipped with a memory function. Since the data is accumulated by a logic circuit having an OS transistor, the data can be held for a certain period.

  If the IC card 350 is lost or stolen, there is a possibility of unauthorized use by a third party. At that time, when the owner makes an offer lost or stolen to the card company, the information is sent from the card company to the reading terminal. When a third party passes the IC card through the reading device 351 in this state, the information transmitted to the reading device is recognized as shown in FIG. 17B (S11), and the above data is held in the IC card. If the data image is confirmed (S12), the data is erased (S13). When the urgency is high, the data may be erased without solving the step (S12) for confirming whether the data is held in the IC card.

  As data is erased, the IC card 350 becomes unusable.

  As described above, an IC card equipped with the logic circuit of the present invention can hold information for a certain period, and forcibly delete the information when used illegally by a third party.

In this example, the photoconductivity of an IGZO-based oxide semiconductor used for an OS transistor was measured. The result is shown in FIG. The X axis in FIG. 18 represents the photon energy of light, and the Y axis represents the conductivity. As conditions 1 to 4 below, an IGZO-based oxide semiconductor was manufactured using a sputtering method. As a common condition, a target having an In: Ga: Zn ratio of 1: 1: 1 was used. The film thickness was 50 nm.
Condition 1: Substrate temperature: room temperature, oxygen in film formation atmosphere: 33%
Condition 2: substrate temperature: 400 ° C., oxygen in film forming atmosphere: 33%
Condition 3: substrate temperature: room temperature, oxygen in film formation atmosphere: 100%
Condition 4: substrate temperature: 400 ° C., oxygen in film formation atmosphere: 100%

  Since the band gap of the IGZO-based oxide semiconductor is 3.1 [eV], light with a photon energy of 3 [eV] or more was irradiated. This is shown on the X axis in FIG. 3.1 [eV] corresponds to 400 nm in terms of the wavelength of light, and is irradiated with light having a wavelength of 400 nm or less.

It can be seen that the conductivity [Ω ⁻¹ cm ⁻¹ ] is increased in the IGZO-based oxide semiconductor film formed under any conditions. That is, it can be seen that the conductivity of a transistor including an IGZO-based oxide semiconductor is increased when irradiated with light. If the conductivity is increased, the charge accumulated in the capacitor electrically connected to the transistor can be discharged. Such light may be irradiated for 1 second or longer. Light can pass through the gate and irradiate the oxide semiconductor. The light can be emitted to the oxide semiconductor from the gate and the source or between the gate and the drain.

  FIG. 18 shows experimental results on the IGZO-based oxide semiconductor. It is known that the oxide semiconductor is a wide gap semiconductor. That is, it can be understood that the above photoconductivity characteristics are provided in the case of an oxide semiconductor, and light having a band gap greater than that of the oxide semiconductor may be irradiated. For example, in the case of a transistor having ZnO, the band gap of ZnO is 3.3 [eV];

  Thus, by using such an oxide semiconductor transistor for a memory cell, stored charge can be held even when power supplied to the CPU is stopped. Furthermore, even when the power is turned off, the accumulated charge can be released and information can be deleted by performing light irradiation as necessary.

C1 first capacitive element C2 second capacitive element 101 logic circuit 102 memory cell 103 data erasing means 104 control circuit 108a first power supply 108b second power supply 109 battery 110 memory unit 111 bit line 112 word line 113 OS transistor 114 Memory element 115 Wiring 118 Wiring 119 Transistor 130 Insulating surface 131 OS transistor 132 Capacitance element 134 Oxide semiconductor 135 Source (or drain)
136 Drain (or source)
137 conductive film 138 insulating film 139 conductive film 140 conductive film 141 region 142 region 145 passivation film 151 conductive film 152 insulating film 153 insulating film 160 Si transistor 161 semiconductor substrate 163 insulating film 164 conductive film 165 first impurity region 166 insulating Material 167 Second impurity region 170 Passivation film 171 Insulating film 172 Wiring 173 First connecting wiring 174 Second connecting wiring 180 Light shielding film 181 Insulating film 190 Light emitting element 191 Insulating film 192 Insulator 193 Conductive film 194 Organic compound Layer 195 Conductive film 198 Sealing substrate 201 Detection unit 202 Determination unit 203 Erase signal generation unit 213 Light irradiation means 213a Light source 213b Drive circuit 701 Si transistor 702 Si transistor 703 Si transistor 704 Si transistor 705 Si Njisuta 706 Si transistor 711 OS transistor 712 OS transistor 901 Si transistor 902 Si transistor 911 OS transistor

Claims (4)

Having a central processing unit register, cache or main memory,
The register of the central processing unit, the cache, or the main memory includes first to eighth transistors, a first capacitor element, and a second capacitor element.
Each of the first to sixth transistors has a channel formation region formed in silicon,
The seventh transistor and the eighth transistor each have a channel formation region formed in an oxide semiconductor,
A gate of the first transistor is electrically connected to a first wiring;
One of a source and a drain of the first transistor is electrically connected to a second wiring;
The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor;
A gate of the second transistor is electrically connected to a gate of the third transistor;
One of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor;
The other of the source and the drain of the third transistor is electrically connected to a fifth wiring;
A gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor;
A gate of the fourth transistor is electrically connected to a gate of the fifth transistor;
The one is the fourth of the source and the drain of the transistor, the fourth wiring electrically connected,
The other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor;
Wherein the other of the source and the drain of the fifth transistor is the fifth wiring and electrically connected,
A gate of the sixth transistor is electrically connected to the first wiring;
One of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fourth transistor;
The other of the source and the drain of the sixth transistor is electrically connected to a third wiring;
One of a source and a drain of the seventh transistor is electrically connected to the other of the source and the drain of the first transistor;
A gate of the seventh transistor is electrically connected to a sixth wiring;
The other of the source and the drain of the seventh transistor is electrically connected to the electrode of the first capacitor,
One of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the sixth transistor;
A gate of the eighth transistor is electrically connected to a seventh wiring;
The other of the source and the drain of the eighth transistor is electrically connected to the electrode of the second capacitor,
When the second transistor is turned on and the first potential of the fourth wiring is output, the seventh transistor is turned on, and the first capacitor is turned on in accordance with the first potential. And then the seventh transistor is turned off, the first node of the electrode of the first capacitor electrically connected to the seventh transistor is in a floating state. Can be
When the fourth transistor is turned on and the second potential of the fourth wiring is output, the eighth transistor is turned on and the second capacitor element is turned on according to the second potential. When the eighth transistor is turned off after that, the second node of the electrode of the second capacitor element electrically connected to the eighth transistor is in a floating state. Can be
After a certain period of time, the charge accumulated in the first capacitor element is deleted via the first node, or the charge accumulated in the second capacitor element is deleted via the second node. A semiconductor device comprising means for performing In claim 1,
The means for deleting the charge accumulated in the first capacitor element through the first node after the lapse of the predetermined period has means for supplying an erase signal to the gate of the seventh transistor,
The means for deleting the charge accumulated in the second capacitor element through the second node after the lapse of the predetermined period has means for supplying an erase signal to the gate of the eighth transistor. A semiconductor device. In claim 1,
The seventh transistor includes the gate and a back gate;
Transistor of the eighth has said gate, and back gate, and
The means for deleting the charge accumulated in the first capacitor element through the first node after the lapse of the predetermined period has means for supplying an erase signal to the back gate of the seventh transistor,
The means for deleting the charge accumulated in the second capacitor element through the second node after the fixed period has elapsed includes means for supplying an erase signal to the back gate of the eighth transistor. A featured semiconductor device. In claim 1,
The means for removing the charge accumulated in the first capacitor element through the first node after the fixed period has elapsed includes means for irradiating light to the oxide semiconductor included in the seventh transistor. ,
The means for removing the charge accumulated in the second capacitor element through the second node after the fixed period has elapsed includes means for irradiating light to the oxide semiconductor included in the eighth transistor. A semiconductor device characterized by the above.

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