WO2011129037A1 - Thin film transistor substrate, method for producing same, and display device - Google Patents
Thin film transistor substrate, method for producing same, and display device Download PDFInfo
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- WO2011129037A1 WO2011129037A1 PCT/JP2011/000103 JP2011000103W WO2011129037A1 WO 2011129037 A1 WO2011129037 A1 WO 2011129037A1 JP 2011000103 W JP2011000103 W JP 2011000103W WO 2011129037 A1 WO2011129037 A1 WO 2011129037A1
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- thin film
- semiconductor layer
- film transistor
- substrate
- channel region
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Definitions
- the present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate using an oxide semiconductor layer, a method for manufacturing the same, and a display device.
- a thin film transistor (hereinafter also referred to as “TFT”) is provided as a switching element for each pixel which is the minimum unit of an image.
- a typical bottom gate type TFT has, for example, a gate electrode provided on an insulating substrate, a gate insulating film provided so as to cover the gate electrode, and an island shape so as to overlap the gate electrode on the gate insulating film. And a source electrode and a drain electrode provided to face each other on the semiconductor layer.
- a thin film transistor with a low leakage current used for a switching element of a pixel and a thin film transistor that has a low threshold voltage and can be driven at a high speed are used.
- the threshold voltage of the CMOS inverter that requires both the n-type channel and the p-type channel or the two thin film transistors that constitute the inverter from the viewpoint of high-speed driving.
- Enhancement-depletion (E / D) inverters with large differences are widely used.
- an IGZO In—Ga—Zn—
- a conventional thin film transistor using an amorphous silicon semiconductor layer as a switching element of each pixel that is the minimum unit of an image is used instead of a conventional thin film transistor using an amorphous silicon semiconductor layer as a switching element of each pixel that is the minimum unit of an image.
- a TFT using an oxide semiconductor layer (hereinafter also referred to as “oxide semiconductor layer”) formed of an O) -based oxide semiconductor film has been proposed.
- CMOS inverter circuit cannot be used in a circuit using a high-speed moving oxide semiconductor, and an E / D inverter circuit capable of independently controlling the threshold voltage of each thin film transistor and capable of high-speed operation. The production of is needed.
- an E / D inverter composed of a thin film transistor having an oxide semiconductor as a channel layer. More specifically, an E / D including a first thin film transistor and a second thin film transistor having different channel layer thicknesses, and at least one of the channel layers of the first and second thin film transistors is heat-treated.
- An inverter is disclosed. With such a configuration, a difference occurs in the threshold voltage due to a difference in channel layer thickness between the first and second thin film transistors constituting the E / D inverter or due to a difference in heat treatment conditions of the channel layer. Therefore, it is described that the difference between the threshold voltages of two thin film transistors constituting the E / D inverter can be sufficiently increased (see, for example, Patent Document 1).
- the channel layer is heated by contact heating or electromagnetic wave irradiation (high frequency irradiation). Or the ultraviolet light irradiation), the threshold voltage of the first and second thin film transistors is changed.
- the selective heat treatment in such a local region complicates the process and has high definition and fineness. It can be said that application to a thin film transistor is difficult. As a result, there is a problem that the yield decreases.
- the present invention has been made in view of the above problems, and a thin film transistor substrate capable of forming a plurality of thin film transistors having different threshold voltages with a simple configuration and suppressing a decrease in yield, and the thin film transistor substrate therefor
- An object is to provide a manufacturing method and a display device.
- a thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and the insulating substrate.
- a second insulating film formed of a material different from that of the first insulating film is provided between the layer and the first insulating film and in the second channel region of the second semiconductor layer; It is characterized by.
- the insulating film structure in the channel region of the first semiconductor layer in the first thin film transistor can be different from the insulating film structure in the channel region of the second semiconductor layer in the second thin film transistor.
- the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large.
- a thin film transistor substrate including a thin film transistor that is, an E / D inverter
- a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
- the second insulating film may be a channel protective film that protects the second channel region.
- the second semiconductor layer is formed. It becomes possible to protect the channel region from being etched.
- the first insulating film is a silicon oxide film made of TEOS (Tetra Ethyl Ortho Silicate), and the second insulating film is made of N 2 O and SiH 4 as materials. It may be a silicon oxide film.
- TEOS Tetra Ethyl Ortho Silicate
- the thin film transistor substrate of the present invention may further include a source electrode and a drain electrode provided on the second insulating film so as to face each other with the second channel region interposed therebetween.
- the thin film transistor substrate of the present invention further includes a source electrode and a drain electrode provided to face each other with the second channel region interposed between the second semiconductor layer and the second insulating film. It may be.
- the thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and a second channel region provided on the insulating substrate.
- a second thin film transistor having a second semiconductor layer having a first semiconductor layer, and an insulating film covering the second semiconductor layer, wherein the insulating film in the first channel region of the first semiconductor layer The thickness is different from the thickness of the insulating film in the second channel region of the second semiconductor layer.
- the thickness of the insulating film in the channel region of the first semiconductor layer in the first thin film transistor can be different from the thickness of the insulating film in the channel region of the second semiconductor layer in the second thin film transistor.
- the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large.
- a thin film transistor substrate including a thin film transistor that is, an E / D inverter
- a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
- the semiconductor layer may be an oxide semiconductor layer.
- the oxide semiconductor layer includes at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). It is good also as a structure which consists of a metal oxide containing.
- the oxide semiconductor layer made of these materials has high mobility even if it is amorphous, so that the on-resistance of the switching element can be increased.
- the oxide semiconductor layer may be formed of an In—Ga—Zn—O-based metal oxide.
- the semiconductor layer may be a silicon-based semiconductor layer.
- the thin film transistor substrate of the present invention has a simple structure and includes a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor having different threshold voltages, without reducing the yield. It has excellent characteristics that it can be manufactured. Therefore, the thin film transistor substrate of the present invention can be suitably used for a display device including a thin film transistor substrate, a counter substrate disposed to face the thin film transistor substrate, and a display medium layer provided between the thin film transistor substrate and the counter substrate. .
- the display device of the present invention can be suitably used for a display device in which the display medium layer is a liquid crystal layer.
- the thin film transistor substrate manufacturing method of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, an insulating substrate, A method for manufacturing a thin film transistor substrate, comprising: a second thin film transistor including a second semiconductor layer having a channel region; a first semiconductor layer; and a first insulating film covering the second semiconductor layer.
- an insulating film formation step of forming a first insulating film so as to cover the first semiconductor layer, the second semiconductor layer, and the second insulating film.
- a thin film transistor substrate in which the insulating film structure in the channel region of the first semiconductor layer in the first thin film transistor is different from the insulating film structure in the channel region of the second semiconductor layer in the second thin film transistor is manufactured. be able to. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
- a thin film transistor substrate including a thin film transistor that is, an E / D inverter
- the method for manufacturing a thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and a second thin film transistor provided on the insulating substrate.
- a method of manufacturing a thin film transistor substrate comprising: a second thin film transistor comprising a second semiconductor layer having a channel region; a first semiconductor layer; and an insulating film covering the second semiconductor layer, the method comprising:
- a semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer, and a thickness in the first channel region and a thickness in the second channel region are formed in the first channel region and the second channel region.
- the thickness of the insulating film in the channel region of the first semiconductor layer in the first thin film transistor can be different from the thickness of the insulating film in the channel region of the second semiconductor layer in the second thin film transistor.
- the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large.
- a thin film transistor substrate including a thin film transistor that is, an E / D inverter
- a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
- a plurality of thin film transistors having different threshold voltages can be formed with a simple configuration, and a reduction in yield of the thin film transistor substrate can be suppressed.
- FIG. 1 is a plan view of an active matrix substrate including a thin film transistor according to a first embodiment of the present invention.
- 1 is a plan view of an active matrix substrate including a thin film transistor according to a first embodiment of the present invention.
- 1 is a cross-sectional view of an active matrix substrate according to a first embodiment of the present invention. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section.
- Ids-Vg characteristic diagram showing the relationship between drain-source current (Ids) and gate voltage (Vg). It is an Ids-Vg characteristic diagram showing the relationship between drain-source current (Ids) and gate voltage (Vg).
- Ids-Vg characteristic diagram showing the relationship between drain-source current (Ids) and gate voltage (Vg).
- FIG. 1 is a sectional view of a liquid crystal display device having an active matrix substrate (thin film transistor substrate) including a thin film transistor according to the first embodiment of the present invention
- FIG. 2 is a thin film transistor according to the first embodiment of the present invention. It is a top view of an active matrix substrate provided with.
- FIG. 3 is a plan view of an active matrix substrate including the thin film transistor according to the first embodiment of the present invention
- FIG. 4 is a cross-sectional view of the active matrix substrate according to the first embodiment of the present invention. .
- the liquid crystal display device 50 includes an active matrix substrate 20a and a counter substrate 30, which are thin film transistor substrates provided so as to face each other, and a display provided between the active matrix substrate 20a and the counter substrate 30. And a liquid crystal layer 40 which is a medium layer.
- the liquid crystal display device 50 adheres the active matrix substrate 20a and the counter substrate 30 to each other, and seals 35 provided in a frame shape to enclose the liquid crystal layer 40 between the active matrix substrate 20a and the counter substrate 30. And.
- a display region D that is composed of a plurality of pixels and the like and that displays an image in an inner portion of the sealing material 35 is defined.
- a drive circuit region (terminal region) T is defined in a portion protruding from the counter substrate 30 of 20a. The drive circuit region T is provided around the display region D as shown in FIGS.
- a gate driver region Tg and a source driver region Ts are provided in the drive circuit region T.
- the gate driver region Tg is provided with a gate driver 26 for driving the scanning wiring (gate wiring) 11a of the display region D, and the signal wiring (source wiring) 16a of the display region D is provided in the source driver region Ts.
- a source driver 27 for driving is provided.
- the active matrix substrate 20a includes an insulating substrate 10a, a plurality of scanning wirings 11a provided in the display region D so as to extend parallel to each other, and each scanning wiring.
- the active matrix substrate 20a includes a thin film transistor 5.
- the thin film transistor 5 is an active element of a drive circuit (that is, a gate driver 26) as shown in FIG. 4, and is formed on the insulating substrate 10a.
- the first thin film transistor 5a and the second thin film transistor 5b and a third thin film transistor 5c which is a pixel switching element and is formed on the insulating substrate 10a.
- the active matrix substrate 20a is an interlayer insulating film that is a first insulating film provided so as to cover the first thin film transistor 5a, the second thin film transistor 5b, and the third thin film transistor 5c. 17, a planarizing film 18 provided so as to cover the interlayer insulating film 17, a plurality of pixel electrodes 19 a provided in a matrix on the planarizing film 18 and connected to the third thin film transistor 5 c, and each pixel And an alignment film (not shown) provided so as to cover the electrode 19a.
- the scanning wiring 11a is led out to the gate driver region Tg of the driving circuit region T, and is connected to the gate terminal 19b in the gate driver region Tg.
- the signal wiring 16a is led out as a relay wiring to the source driver region Ts in the driving circuit region T, and is connected to the source terminal 19c in the source driver region Ts.
- the first thin film transistor 5a has a bottom gate structure. As shown in FIG. 4, the gate electrode 11aa provided on the insulating substrate 10a and the gate insulating layer 12 provided so as to cover the gate electrode 11aa. And.
- the first thin film transistor 5a includes a first oxide semiconductor layer 13a having a first channel region Ca provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a first oxide semiconductor layer 13a.
- a source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13a so as to overlap the gate electrode 11aa and to face each other across the first channel region Ca.
- the second thin film transistor 5b has a bottom gate structure, and is provided so as to cover the gate electrode 11aa provided on the insulating substrate 10a and the gate electrode 11aa as shown in FIG. And a gate insulating layer 12.
- the second thin film transistor 5b includes a second oxide semiconductor layer 13b having a second channel region Cb provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a second oxide semiconductor layer 13b.
- a source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13b so as to overlap the gate electrode 11aa and to face each other across the second channel region Cb.
- the third thin film transistor 5c has a bottom gate structure, and as shown in FIG. 4, a gate electrode 11aa provided on the insulating substrate 10a and a gate insulation provided so as to cover the gate electrode 11aa.
- Layer 12 The third thin film transistor 5c includes a third oxide semiconductor layer 13c having a third channel region Cc provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a third oxide semiconductor layer 13c.
- a source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13c so as to overlap the gate electrode 11aa and to face each other across the third channel region Cc.
- the first to third oxide semiconductor layers 13a, 13b, and 13c are formed of, for example, an IGZO (In—Ga—Zn—O) -based oxide semiconductor film.
- the gate electrode 11aa is a portion where the scanning wiring 11a protrudes to the side.
- the source electrode 16aa is a portion from which the signal wiring 16a protrudes to the side, and is constituted by a laminated film of the first conductive layer 14a and the second conductive layer 15a as shown in FIG.
- the drain electrode 16b is composed of a laminated film of a first conductive layer 14b and a second conductive layer 15b.
- the drain electrode 16b constituting the third thin film transistor 5c is connected to the pixel electrode 19a through a contact hole C formed in the laminated film of the interlayer insulating film 17 and the planarizing film 18.
- the drain electrode 16b constituting the third thin film transistor 5c forms an auxiliary capacitance by overlapping with the auxiliary capacitance wiring 11b via the gate insulating layer 12.
- the counter substrate 30 includes an insulating substrate 10b, a black matrix 21 provided in a lattice shape on the insulating substrate 10b, and a red color provided between each lattice of the black matrix 21. And a color filter layer having a colored layer 22 such as a green layer and a blue layer.
- the counter substrate 30 includes a common electrode 23 provided so as to cover the color filter layer, a photo spacer 24 provided on the common electrode 23, and an alignment film (non-coated) provided so as to cover the common electrode 23. As shown).
- the liquid crystal layer 40 is made of, for example, a nematic liquid crystal material having electro-optical characteristics.
- the source driver 27 a source signal is sent to the source electrode 16aa through the signal wiring 16a, and a predetermined charge is written into the pixel electrode 19a through the oxide semiconductor layer 13c and the drain electrode 16b.
- a predetermined voltage is applied to the auxiliary capacitor.
- liquid crystal display device 50 in each pixel, an image is displayed by adjusting the light transmittance of the liquid crystal layer 40 by changing the alignment state of the liquid crystal layer 40 according to the magnitude of the voltage applied to the liquid crystal layer 40. .
- the second channel of the second oxide semiconductor layer 13b in the second thin film transistor 5b functioning as an active element of the drive circuit that is, the gate driver 26.
- the region Cb is characterized in that a channel protective film 25 which is a second insulating film for protecting the channel region Cb is provided.
- the first oxide semiconductor layer 13a of the first thin film transistor 5a is first.
- the interlayer insulating film 17 is provided, the above-described channel protective film 25 is not provided, and the second channel region of the second oxide semiconductor layer 13b in the second thin film transistor 5b is provided.
- the channel protective film 25 is provided only on Cb.
- the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second oxide semiconductor layer 13b in the second thin film transistor 5b It is possible to vary the insulating film structure in the channel region Cb. Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. As a result, a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
- the second thin film transistor is also provided in the third channel region Cc of the third oxide semiconductor layer 13c in the third thin film transistor 5c functioning as a pixel switching element. Similar to 5b, a channel protective film 25 which is a second insulating film for protecting the channel region Cc is provided.
- the first thin film transistor 5a is used as a depletion type thin film transistor having a low threshold voltage
- the second thin film transistor 5b is used as an enhancement type thin film transistor having a high threshold voltage.
- These first and second thin film transistors 5a and 5b constitute an enhancement-depletion (E / D) inverter having a large difference in threshold voltage.
- the third thin film transistor 5c is used as a switching element for a pixel as an enhancement type thin film transistor having a high threshold voltage and a low leakage current.
- FIGS. 5 to 11 are explanatory views showing the manufacturing process of the first to third thin film transistors and the active matrix substrate in cross section
- FIG. 12 is an explanatory view showing the manufacturing process of the counter substrate in cross section.
- the manufacturing method of this embodiment includes a thin film transistor and active matrix substrate manufacturing step, a counter substrate manufacturing step, and a liquid crystal injection step.
- a molybdenum film (thickness of about 150 nm) or the like is formed on the entire substrate of the insulating substrate 10a such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate by a sputtering method. Then, by performing photolithography, wet etching, and resist removal cleaning, the gate electrode 11aa and the auxiliary capacitor wiring 11b are formed on the insulating substrate 10a as shown in FIG. Note that the scanning wiring 11a and the signal wiring 16a are formed simultaneously with the formation of the gate electrode 11aa and the auxiliary capacitance wiring 11b.
- the molybdenum film having a single-layer structure is exemplified as the metal film constituting the gate electrode 11aa.
- a metal such as an aluminum film, a tungsten film, a tantalum film, a chromium film, a titanium film, or a copper film is used.
- the gate electrode 11aa may be formed with a thickness of 50 nm to 300 nm using a film or a film made of such an alloy film or metal nitride.
- polyethylene terephthalate resin polyethylene naphthalate resin
- polyether sulfone resin acrylic resin
- polyimide resin polyimide resin
- a silicon nitride film (with a thickness of about 200 nm to 500 nm) is formed by CVD on the entire substrate on which the gate electrode 11aa and the auxiliary capacitance wiring 11b are formed, and as shown in FIG.
- a gate insulating layer 12 is formed so as to cover the gate electrode 11aa and the auxiliary capacitance line 11b.
- the gate insulating layer 12 may have a two-layer structure.
- a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy, x> y), a silicon nitride oxide film (SiNxOy, x> y), or the like is used in addition to the above-described silicon nitride film (SiNx). be able to.
- a silicon nitride film or a silicon nitride oxide film is used as a lower gate insulating film, and a silicon oxide film, as an upper gate insulating film, Alternatively, a structure using a silicon oxynitride film is preferable.
- a silicon nitride film having a thickness of 100 nm to 200 nm is formed as a lower gate insulating film using SiH 4 and NH 3 as reaction gases, and N 2 O and SiH 4 are reacted as an upper gate insulating film.
- a silicon oxide film with a thickness of 50 nm to 100 nm can be formed as the gas.
- a rare gas such as argon gas in the reaction gas and mix it in the insulating film.
- an IGZO-based oxide semiconductor film (with a thickness of about 30 nm to 100 nm) is formed by sputtering, and then the photolithography, wet etching, and resist removal cleaning are performed on the oxide semiconductor film.
- first to third oxide semiconductor layers 13a, 13b, and 13c are formed as shown in FIG.
- ⁇ Channel protective film forming step (second insulating film forming step)>
- a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, and 13c are formed by a plasma CVD method.
- photolithography, etching, and resist peeling cleaning are performed using the resist as a mask, thereby protecting the channel region Cb in the second channel region Cb of the second oxide semiconductor layer 13b as shown in FIG.
- a channel protective film 25 is formed to a thickness of about 50 to 100 nm.
- a channel protective film 25 for protecting the channel region Cc is formed to a thickness of about 50 to 100 nm in the third channel region Cc of the third oxide semiconductor layer 13c.
- a silicon oxide film with a thickness of 100 nm to 200 nm can be formed using SiH 4 and N 2 O as reaction gases.
- a titanium film (thickness 30 nm to 150 nm) and a copper film (thickness 30 nm to 150 nm) are formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, 13c and the channel protective film 25 are formed by sputtering.
- a film having a thickness of about 50 nm to 400 nm) is sequentially formed.
- the copper film is subjected to photolithography and wet etching, and the titanium film is dry-etched and resist is peeled and washed, so that the signal wiring 16a (see FIG. 3) is obtained. ),
- the source electrode 16aa and the drain electrode 16b are formed.
- the first channel region Ca of the first oxide semiconductor layer 13a, the second channel region Cb of the second oxide semiconductor layer 13b covered with the channel protective film 25, and the channel protective film 25 are covered.
- the third channel region Cc of the third oxide semiconductor layer 13c thus formed is exposed.
- the source electrode 16aa and the drain electrode 16b are provided on the channel protective film 25 so as to face each other with the second channel region Cb interposed therebetween.
- the source electrode 16aa and the drain electrode 16b are provided on the channel protective film 25 so as to face each other across the third channel region Cc. It is done.
- the metal film constituting the source electrode 16aa and the drain electrode 16b a titanium film and a copper film having a laminated structure are exemplified.
- a metal such as an aluminum film, a tungsten film, a tantalum film, or a chromium film is used.
- the source electrode 16aa and the drain electrode 16b may be formed by a film, or a film of an alloy film or metal nitride thereof.
- ITO indium tin oxide
- IZO indium zinc oxide
- ITSO indium tin oxide containing silicon oxide
- I 2 O 3 indium oxide
- SnO 2 tin oxide
- Zinc oxide Zinc oxide
- TiN titanium nitride
- etching process either dry etching or wet etching described above may be used. However, when processing a large area substrate, it is preferable to use dry etching.
- a fluorine-based gas such as CF 4 , NF 3 , SF 6 , or CHF 3
- a chlorine-based gas such as Cl 2 , BCl 3 , SiCl 4 , or CCl 4
- an oxygen gas or the like
- an inert gas such as argon may be added.
- a silicon nitride film, an oxide film, or the like is formed by plasma CVD.
- a silicon film, a silicon nitride oxide film, or the like is formed, and covers the first to third thin film transistors 5a, 5b, and 5c as shown in FIG. 9 (that is, the first to third oxide semiconductor layers 13a and 13b).
- 13c, covering the source electrode 16aa, the drain electrode 16b, and the channel protective film 25) the interlayer insulating film 17 is formed to a thickness of about 200 to 300 nm.
- a silicon oxide film having a thickness of 200 nm to 300 nm is formed by, for example, plasma CVD using TEOS (TetraTeEthyl Ortho Silicate) as a source gas. be able to.
- TEOS TetraTeEthyl Ortho Silicate
- a resist mask is formed on the interlayer insulating film 17 by a photolithography process, and as shown in FIG. 9, the contact hole C is etched, and the entire surface of the substrate is heat-treated.
- the semiconductor characteristics of a thin film transistor including an oxide semiconductor layer are extremely sensitively influenced by the oxygen vacancy concentration in the oxide semiconductor layer. Even after the oxide semiconductor layer is formed, the oxygen vacancy concentration in the oxide semiconductor layer increases or decreases due to the influence of surrounding moisture and oxygen.
- the film quality of the protective insulating film greatly affects the characteristics of the thin film transistor.
- the ratio (flow rate) of N 2 O is large. Since the oxygen concentration increases, the oxidation effect on the second oxide semiconductor layer 13b increases, and the proportion of SiH 4 decreases, so that the hydrogen concentration decreases and the second oxide semiconductor layer 13b is formed. The reduction effect of becomes smaller.
- the threshold voltage Vth is increased (i.e., shifted in the direction of arrow Y 1 in the figure) will be.
- the second thin film transistor 5b including the second oxide semiconductor layer 13b in which the channel protective film 25 is provided in the second channel region Cb can be used as an enhancement type thin film transistor having a high threshold voltage Vth. Become.
- the third thin film transistor 5c including the third oxide semiconductor layer 13c in which the channel protective film 25 is provided in the third channel region Cc is enhanced with a high threshold voltage Vth and a low leakage current. It can be used as a thin film transistor.
- the current value is increased (i.e., the direction of the arrow X 2 in FIG. while shifting), the threshold voltage Vth is lowered (i.e., shifted in the direction of the arrow Y 2 in the figure) will be.
- a photosensitive organic insulating film made of photosensitive acrylic resin or the like is formed to a thickness of about 1.0 ⁇ m to 3.0 ⁇ m on the entire substrate on which the interlayer insulating film 17 is formed by spin coating or slit coating.
- a planarizing film 18 is formed on the surface of the interlayer insulating film 17 as shown in FIG.
- a transparent conductive film such as, for example, an ITO film (thickness of about 50 nm to 200 nm) made of indium tin oxide is formed on the entire substrate on which the interlayer insulating film 17 and the planarizing film 18 are formed by sputtering. . Thereafter, the transparent conductive film is subjected to photolithography, wet etching, and resist peeling and cleaning, so that the pixel electrode 19a, the gate terminal 19b (see FIG. 3), and the source terminal 19c (see FIG. 3), as shown in FIG. (See FIG. 3).
- ITO film thickness of about 50 nm to 200 nm
- the transparent conductive film is subjected to photolithography, wet etching, and resist peeling and cleaning, so that the pixel electrode 19a, the gate terminal 19b (see FIG. 3), and the source terminal 19c (see FIG. 3), as shown in FIG. (See FIG. 3).
- the pixel electrode 19a is formed on the surface of the planarizing film 18 and the interlayer insulating film 17 so as to cover the surface of the contact hole C.
- the pixel electrode 19a is made of indium oxide or indium zinc oxide (IZO) containing tungsten oxide, indium oxide or indium tin oxide (ITO) containing titanium oxide. ) Etc. can be used. In addition to the above-mentioned indium zinc oxide and indium tin oxide, indium tin oxide containing silicon oxide (ITSO) can also be used.
- IZO indium oxide or indium zinc oxide
- ITO indium tin oxide
- Etc. Etc.
- indium zinc oxide and indium tin oxide indium tin oxide containing silicon oxide (ITSO) can also be used.
- the conductive thin film is made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, or an alloy thereof. A film can be used, and this metal thin film can be used as the pixel electrode 19a.
- the active matrix substrate 20a shown in FIG. 4 can be manufactured.
- ⁇ Opposite substrate manufacturing process First, by applying, for example, a photosensitive resin colored in black to the entire substrate of the insulating substrate 10b such as a glass substrate by spin coating or slit coating, the coating film is exposed and developed. As shown in FIG. 12A, the black matrix 21 is formed to a thickness of about 1.0 ⁇ m.
- a photosensitive resin colored in red, green, or blue is applied to the entire substrate on which the black matrix 21 is formed by spin coating or slit coating. Thereafter, the coating film is exposed and developed to form a colored layer 22 (for example, a red layer) of a selected color with a thickness of about 2.0 ⁇ m as shown in FIG. The same process is repeated for the other two colors to form the other two colored layers 22 (for example, a green layer and a blue layer) with a thickness of about 2.0 ⁇ m.
- the common electrode 23 has a thickness as shown in FIG. It is formed to have a thickness of about 50 nm to 200 nm.
- the photo spacer 24 is formed to a thickness of about 4 ⁇ m.
- the counter substrate 30 can be manufactured as described above.
- a polyimide resin film is applied to each surface of the active matrix substrate 20a manufactured in the active matrix substrate manufacturing process and the counter substrate 30 manufactured in the counter substrate manufacturing process by a printing method, and then the coating film is applied.
- an alignment film is formed by performing baking and rubbing treatment.
- a sealing material 35 made of UV (ultraviolet) curing and thermosetting resin is printed on the surface of the counter substrate 30 on which the alignment film is formed in a frame shape, a liquid crystal material is formed inside the sealing material. Is dripped.
- the bonded bonded body is released to atmospheric pressure. The surface and the back surface of the bonded body are pressurized.
- the sealing material 35 is hardened by heating the bonding body.
- the unnecessary part is removed by dividing the bonded body in which the sealing material 35 is cured, for example, by dicing.
- the liquid crystal display device 50 of the present embodiment can be manufactured.
- the second channel region of the second oxide semiconductor layer 13b is between the second oxide semiconductor layer 13b and the interlayer insulating film 17 that is the first insulating film.
- a channel protective film 25 that is a second insulating film formed of a material different from that of the interlayer insulating film 17 is provided on Cb. Therefore, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second channel region Cb of the second oxide semiconductor layer 13b in the second thin film transistor 5b. It is possible to vary the insulating film structure in.
- the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large.
- an active matrix substrate 20a including a thin film transistor (that is, an E / D inverter) including a first thin film transistor 5a and a second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
- a high-quality device capable of high current driving and low voltage driving can be realized, and for example, high-functional circuits such as a pixel memory circuit, a photosensor circuit, and an OLED driving circuit can be realized.
- the channel protective film 25 that protects the channel region Cb is provided in the second channel region Cb of the second oxide semiconductor layer 13b. Therefore, in the step of forming the source electrode 16aa and the drain electrode 16b, when the source electrode 16aa and the drain electrode 16b are formed by patterning by etching, the second channel region Cb of the second oxide semiconductor layer 13b is formed. Can be protected from being etched.
- the first and second oxide semiconductor layers 13a and 13b are used as the semiconductor layers. Accordingly, it is possible to form a thin film transistor that has a higher electron mobility and can be processed at a lower temperature than a thin film transistor using amorphous silicon as a semiconductor layer.
- FIG. 15 is a cross-sectional view of an active matrix substrate including a thin film transistor according to the second embodiment of the present invention.
- the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.
- the overall configuration and the manufacturing method of the liquid crystal display device are the same as those described in the first embodiment, and thus detailed description thereof is omitted here.
- interlayer insulating film 28 is provided as the second insulating film instead of the channel protective film 25 described above. There is a feature in that.
- an interlayer insulating film 17 is formed in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a that functions as an active element of the drive circuit.
- the interlayer insulating film 28 is provided, but the interlayer insulating film 28 is not provided, and the interlayer insulating film 28 is provided in the second channel region Cb of the second oxide semiconductor layer 13b in the second thin film transistor 5b.
- the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second thin film transistor as in the case of the first embodiment described above.
- the insulating film structure in the second channel region Cb of the second oxide semiconductor layer 13b in 5b can be made different.
- the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. Therefore, an active matrix substrate including a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
- a thin film transistor that is, an E / D inverter
- the second thin film transistor is also provided in the third channel region Cc of the third oxide semiconductor layer 13c in the third thin film transistor 5c functioning as a switching element of the pixel. Similar to 5b, an interlayer insulating film 28 which is a second insulating film for protecting the channel region Cc is provided.
- FIG. 16 is an explanatory view showing the manufacturing process of the thin film transistor and the active matrix substrate in cross section.
- the gate electrode forming process and the semiconductor layer forming process are performed as in FIGS. 5 and 6 described in the first embodiment.
- a titanium film (thickness of 30 nm to 150 nm) and a copper film (thickness of about 50 nm to 400 nm) are formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, and 13c are formed by sputtering. ) Etc. in order. Thereafter, the copper film is subjected to photolithography and wet etching, and the titanium film is dry-etched and the resist is peeled and washed, so that the signal wiring 16a (see FIG. 3) is obtained. ), The source electrode 16aa and the drain electrode 16b are formed. At this time, the first channel region Ca of the first oxide semiconductor layer 13a, the second channel region Cb of the second oxide semiconductor layer 13b, and the third channel region of the third oxide semiconductor layer 13c. Cc is exposed.
- the source electrode 16aa and the drain electrode 16b are opposed to each other on the second oxide semiconductor layer 13b with the second channel region Cb interposed therebetween. Provided.
- the source electrode 16aa and the drain electrode 16b are opposed to each other on the third oxide semiconductor layer 13c with the third channel region Cc interposed therebetween. To be provided.
- a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the second and third thin film transistors 5b and 5c are formed by plasma CVD, and is selectively etched.
- the second and third thin film transistors 5b and 5c are covered by patterning (that is, the second and third oxide semiconductor layers 13b and 13c, the source electrode 16aa, and the drain electrode 16b are covered).
- a cover) interlayer insulating film 28 is formed to a thickness of about 200 to 300 nm.
- the source is arranged so as to face each other with the second channel region Cb interposed between the second oxide semiconductor layer 13b and the interlayer insulating film 28.
- An electrode 16aa and a drain electrode 16b are provided.
- a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed on the entire substrate on which the first to third thin film transistors 5a, 5b, and 5c are formed by plasma CVD.
- Etc. to cover the first to third thin film transistors 5a, 5b, 5c that is, the first to third oxide semiconductor layers 13a, 13b, 13c, the source electrode 16aa, the drain electrode 16b, and the interlayer insulation
- An interlayer insulating film 17 (covering the film 28) is formed to a thickness of about 200 to 300 nm.
- a resist mask is formed on the interlayer insulating film 17 by a photolithography process, etching for the contact hole C is performed, and heat treatment is performed on the entire surface of the substrate.
- a silicon oxide film having a thickness of 200 nm to 300 nm can be formed using N 2 O and SiH 4 .
- the planarization film forming step, the opening forming step, and the pixel electrode forming step are performed, whereby the active matrix substrate 20a shown in FIG. Can be produced.
- liquid crystal display device 50 of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.
- an oxide semiconductor layer is used as the semiconductor layer.
- the semiconductor layer is not limited to this.
- a silicon-based semiconductor layer made of amorphous silicon or polysilicon is used as a thin film transistor instead of the oxide semiconductor layer.
- the semiconductor layer may be used as a semiconductor layer.
- an oxide semiconductor layer made of an In—Ga—Zn—O-based metal oxide is used as the oxide semiconductor layer.
- the oxide semiconductor layer is not limited to this, and indium (In ), Gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn), magnesium (Mg), and cadmium (Cd), a material made of a metal oxide containing at least one kind may be used.
- the oxide semiconductor layer 13a made of these materials has high mobility even if it is amorphous, the on-resistance of the switching element can be increased. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved.
- oxide semiconductor films such as InGaO 3 (ZnO) 5 , Mg x Zn 1-x O, Cd x Zn 1-x O, and CdO can be given. it can.
- an amorphous state, a polycrystalline state, or a non-crystalline state of ZnO to which one or more kinds of impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element, or Group 17 element are added is also possible to use a microcrystalline state in which a crystalline state and a polycrystalline state are mixed, or a material to which the above impurities are not added.
- the thickness of the interlayer insulating film 17 may be different without providing the channel protective film 25 and the interlayer insulating film 28 described above. More specifically, as shown in FIG. 17, the thickness T 1 of the interlayer insulating film 17 in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a, and the second thin film transistor 5b. in (in FIG. 17, T 2> T 1) of the second thickness T 2 of the interlayer insulating film 17 in the channel region Cb is different of the second oxide semiconductor layer 13b may be configured.
- the threshold voltage of the thin film transistor varies.
- the thickness T 1 of the interlayer insulating film 17 a second for the thickness T 2 of the interlayer insulating film 17 in the channel region Cb are different, the first channel region Ca and the second channel region of the second oxide semiconductor layer 13b In Cb, the charges generated at the interface between the interlayer insulating film 17 and the planarizing film 18 are different.
- the amount of variation in the threshold voltage of the first thin film transistor 5a is different from the amount of variation in the threshold voltage of the second thin film transistor 5b, the same as in the case where the channel protective film 25 and the interlayer insulating film 28 are provided.
- the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different.
- the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large.
- an active matrix substrate 20a having a thin film transistor that is, an E / D inverter
- the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
- a high-quality device capable of high current drive and low voltage drive can be realized, and for example, high-functional circuits such as a pixel memory circuit, a photo sensor circuit, and an OLED drive circuit can be realized.
- the gate electrode forming process, the semiconductor layer forming process, and the source / drain forming process are performed as in the second embodiment.
- a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the first to third thin film transistors 5a, 5b, and 5c are formed by plasma CVD, and is etched.
- the first to third thin film transistors 5a, 5b and 5c are covered (that is, the first to third oxide semiconductor layers 13a, 13b and 13c, the source electrode).
- An interlayer insulating film 17 is formed to cover 16aa and the drain electrode 16b.
- the thickness of the interlayer insulating film 17 in the third channel region Cc of the third oxide semiconductor layer 13c included in the third thin film transistor 5c functioning as a pixel switching element is The thickness is set to be the same as the thickness of the interlayer insulating film 17 in the second channel region Cb of the second oxide semiconductor layer 13b (that is, T 2 ).
- a resist mask is formed on the interlayer insulating film 17 by a photolithography process, etching for the contact hole C is performed, and heat treatment is performed on the entire surface of the substrate.
- the planarization film forming step, the opening portion forming step, and the pixel electrode forming step are performed, whereby the active matrix substrate 20a shown in FIG. Can be produced.
- liquid crystal display device 50 of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.
- Examples of utilization of the present invention include a thin film transistor substrate using an oxide semiconductor layer, a method for manufacturing the same, and a display device.
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Abstract
Disclosed is an active matrix substrate (20a) which comprises: an insulating substrate (10a); a first thin film transistor (5a) that is formed on the insulating substrate (10a) and comprises a first oxide semiconductor layer (13a) having a first channel region (Ca); a second thin film transistor (5b) that is formed on the insulating substrate (10a) and comprises a second oxide semiconductor layer (13b) having a second channel region (Cb); and an interlayer insulating film (17) that covers the first oxide semiconductor layer (13a) and the second oxide semiconductor layer (13b). A channel protection film (25), which is formed from a material different from that of the interlayer insulating film (17), is provided between the second oxide semiconductor layer (13b) and the interlayer insulating film (17) in the second channel region (Cb) of the second oxide semiconductor layer (13b).
Description
本発明は、薄膜トランジスタ基板に関し、特に、酸化物半導体の半導体層を用いた薄膜トランジスタ基板及びその製造方法、表示装置に関する。
The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate using an oxide semiconductor layer, a method for manufacturing the same, and a display device.
アクティブマトリクス基板では、画像の最小単位である各画素毎に、スイッチング素子として、例えば、薄膜トランジスタ（Thin Film Transistor、以下、「ＴＦＴ」とも称する）が設けられている。
In the active matrix substrate, for example, a thin film transistor (hereinafter also referred to as “TFT”) is provided as a switching element for each pixel which is the minimum unit of an image.
一般的なボトムゲート型のＴＦＴは、例えば、絶縁基板上に設けられたゲート電極と、ゲート電極を覆うように設けられたゲート絶縁膜と、ゲート絶縁膜上にゲート電極に重なるように島状に設けられた半導体層と、半導体層上に互いに対峙するように設けられたソース電極及びドレイン電極とを備えている。
A typical bottom gate type TFT has, for example, a gate electrode provided on an insulating substrate, a gate insulating film provided so as to cover the gate electrode, and an island shape so as to overlap the gate electrode on the gate insulating film. And a source electrode and a drain electrode provided to face each other on the semiconductor layer.
また、一般的な周辺回路一体型の表示装置においては、例えば、画素のスイッチング素子に用いられるリーク電流の低い薄膜トランジスタと、周辺回路に用いられる閾値電圧が低く、高速駆動が可能な薄膜トランジスタが要求される。
Further, in a general peripheral circuit integrated display device, for example, a thin film transistor with a low leakage current used for a switching element of a pixel and a thin film transistor that has a low threshold voltage and can be driven at a high speed are used. The
また、複数の薄膜トランジスタを使用して周辺回路を作製する場合、高速駆動の観点から、ｎ型チャネルとｐ型チャネルとの両方が必要なＣＭＯＳインバータや、インバータを構成する２つの薄膜トランジスタの閾値電圧の差が大きいエンハンスメント－ディプリーション（Ｅ／Ｄ）インバータが広く使用されている。
Further, when a peripheral circuit is manufactured using a plurality of thin film transistors, the threshold voltage of the CMOS inverter that requires both the n-type channel and the p-type channel or the two thin film transistors that constitute the inverter from the viewpoint of high-speed driving. Enhancement-depletion (E / D) inverters with large differences are widely used.
また、近年、アクティブマトリクス基板では、画像の最小単位である各画素のスイッチング素子として、アモルファスシリコンの半導体層を用いた従来の薄膜トランジスタに代わって、高速移動が可能なＩＧＺＯ（Ｉｎ-Ｇａ-Ｚｎ-Ｏ）系の酸化物半導体膜により形成された酸化物半導体の半導体層（以下、「酸化物半導体層」とも称する）を用いたＴＦＴが提案されている。
In recent years, in an active matrix substrate, an IGZO (In—Ga—Zn—) that can move at high speed is used instead of a conventional thin film transistor using an amorphous silicon semiconductor layer as a switching element of each pixel that is the minimum unit of an image. A TFT using an oxide semiconductor layer (hereinafter also referred to as “oxide semiconductor layer”) formed of an O) -based oxide semiconductor film has been proposed.
ここで、アモルファスＩＧＺＯ等の高速移動酸化物半導体は、その多くがｎ型（電子）伝導であり、ドーピングによってもｐ型（ホール）伝導化しないため、ＣＭＯＳ回路構成が使用できない。従って、高速移動酸化物半導体を使用した回路においては、ＣＭＯＳインバータ回路を利用することができないという課題があり、各薄膜トランジスタの閾値電圧を独立に制御し、かつ高速動作が可能なＥ／Ｄインバータ回路の作製が必要とされている。
Here, many high-speed moving oxide semiconductors such as amorphous IGZO have n-type (electron) conduction, and do not become p-type (hole) conduction even by doping, so that a CMOS circuit configuration cannot be used. Therefore, there is a problem that a CMOS inverter circuit cannot be used in a circuit using a high-speed moving oxide semiconductor, and an E / D inverter circuit capable of independently controlling the threshold voltage of each thin film transistor and capable of high-speed operation. The production of is needed.
そこで、酸化物半導体をチャネル層とする薄膜トランジスタからなるＥ／Ｄインバータが開示されている。より具体的には、チャネル層の膜厚が互いに異なる第１の薄膜トランジスタと第２の薄膜トランジスタとを備え、第１及び第２の薄膜トランジスタのチャネル層のうち、少なくとも１つが熱処理されているＥ／Ｄインバータが開示されている。そして、このような構成により、Ｅ／Ｄインバータを構成する第１及び第２の薄膜トランジスタのチャネル層の膜厚の差によって、または、チャネル層の加熱処理条件の差によって、閾値電圧に差が生じるため、Ｅ／Ｄインバータを構成する２つの薄膜トランジスタの閾値電圧の差を十分に大きくすることができると記載されている（例えば、特許文献１参照）。
Therefore, an E / D inverter composed of a thin film transistor having an oxide semiconductor as a channel layer is disclosed. More specifically, an E / D including a first thin film transistor and a second thin film transistor having different channel layer thicknesses, and at least one of the channel layers of the first and second thin film transistors is heat-treated. An inverter is disclosed. With such a configuration, a difference occurs in the threshold voltage due to a difference in channel layer thickness between the first and second thin film transistors constituting the E / D inverter or due to a difference in heat treatment conditions of the channel layer. Therefore, it is described that the difference between the threshold voltages of two thin film transistors constituting the E / D inverter can be sufficiently increased (see, for example, Patent Document 1).
しかし、上記特許文献１に記載のＥ／Ｄインバータにおいては、チャネル層となるアモルファスＩＧＺＯ膜を基板上に成膜した後、アモルファスＩＧＺＯ膜に対してエッチング（ドライエッチングまたはウェットエッチング）を行うことにより、チャネル層の膜厚が互いに異なる第１及び第２の薄膜トランジスタを形成するため、基板のサイズが大きくなると、チャネル層の膜厚の制御が困難になり、膜厚の均一性が低下するという問題があった。
However, in the E / D inverter described in Patent Document 1, after an amorphous IGZO film serving as a channel layer is formed on a substrate, etching (dry etching or wet etching) is performed on the amorphous IGZO film. Since the first and second thin film transistors having different channel layer thicknesses are formed, if the substrate size is increased, it becomes difficult to control the channel layer thickness, resulting in a decrease in film thickness uniformity. was there.
より具体的には、上記特許文献１に記載のＥ／Ｄインバータにおいては、第１及び第２の薄膜トランジスタの各チャネル層に相当する部分において６０ｎｍの膜厚でアモルファスＩＧＺＯ膜を成膜した後、ドライエッチングにより、第２の薄膜トランジスタのチャネル層となるアモルファスＩＧＺＯ膜の膜厚を成膜時の半分の厚み（即ち、３０ｎｍ）になるようにエッチングを行うが、基板サイズが大きくなると、基板全体に渡って、均一に、成膜時の半分の厚みにエッチングすることは、相当高度な技術の確立と高価な装置導入の両方が要求される。そのため、薄膜トランジスタの製造が困難になり、結果として、歩留まりが低下するという問題があった。
More specifically, in the E / D inverter described in Patent Document 1, after forming an amorphous IGZO film with a thickness of 60 nm in a portion corresponding to each channel layer of the first and second thin film transistors, Etching is performed so that the film thickness of the amorphous IGZO film serving as the channel layer of the second thin film transistor is reduced to half the thickness (ie, 30 nm) at the time of film formation by dry etching. In order to etch uniformly to half the thickness at the time of film formation, both establishment of a highly advanced technique and introduction of an expensive apparatus are required. Therefore, it is difficult to manufacture the thin film transistor, and as a result, there is a problem that the yield is lowered.
また、上記特許文献１に記載のＥ／Ｄインバータにおいては、チャネル層となるアモルファスＩＧＺＯ膜を基板上に成膜した後、例えば、チャネル層に対して接触加熱や電磁波の照射による加熱（高周波照射や紫外光照射）を行うことにより、第１及び第２の薄膜トランジスタの閾値電圧を変化させるが、このような局所領域での選択的な加熱処理は、工程が複雑化するとともに、高精細かつ微細な薄膜トランジスタへの適用は困難であると言える。その結果、歩留まりが低下するという問題があった。
In the E / D inverter described in Patent Document 1, after an amorphous IGZO film serving as a channel layer is formed on a substrate, for example, the channel layer is heated by contact heating or electromagnetic wave irradiation (high frequency irradiation). Or the ultraviolet light irradiation), the threshold voltage of the first and second thin film transistors is changed. However, the selective heat treatment in such a local region complicates the process and has high definition and fineness. It can be said that application to a thin film transistor is difficult. As a result, there is a problem that the yield decreases.
そこで、本発明は、上述の問題に鑑みてなされたものであり、簡単な構成で、閾値電圧の異なる複数の薄膜トランジスタを形成することができ、歩留まりの低下を抑制することができる薄膜トランジスタ基板及びその製造方法、表示装置を提供することを目的とする。
Therefore, the present invention has been made in view of the above problems, and a thin film transistor substrate capable of forming a plurality of thin film transistors having different threshold voltages with a simple configuration and suppressing a decrease in yield, and the thin film transistor substrate therefor An object is to provide a manufacturing method and a display device.
上記目的を達成するために、本発明の薄膜トランジスタ基板は、絶縁基板と、絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、第１の半導体層、及び第２の半導体層を覆う第１の絶縁膜とを備え、第２の半導体層と第１の絶縁膜との間であって、第２の半導体層の第２のチャネル領域に、第１の絶縁膜と異なる材料により形成された第２の絶縁膜が設けられていることを特徴とする。
To achieve the above object, a thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and the insulating substrate. A second semiconductor film including a second thin film transistor provided with a second semiconductor layer having a second channel region, a first semiconductor layer, and a first insulating film covering the second semiconductor layer; A second insulating film formed of a material different from that of the first insulating film is provided between the layer and the first insulating film and in the second channel region of the second semiconductor layer; It is characterized by.
同構成によれば、第１の薄膜トランジスタにおける第１の半導体層のチャネル領域における絶縁膜構造と、第２の薄膜トランジスタにおける第２の半導体層のチャネル領域における絶縁膜構造を異ならせることが可能になる。従って、第１の薄膜トランジスタと第２の薄膜トランジスタの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタの閾値電圧の差を十分に大きくすることが可能になる。その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタと第２の薄膜トランジスタからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備える薄膜トランジスタ基板を、歩留まりを低下させることなく作製することができる。
According to this configuration, the insulating film structure in the channel region of the first semiconductor layer in the first thin film transistor can be different from the insulating film structure in the channel region of the second semiconductor layer in the second thin film transistor. . Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
また、本発明の薄膜トランジスタ基板においては、第２の絶縁膜が、第２のチャネル領域を保護するチャネル保護膜であってもよい。
In the thin film transistor substrate of the present invention, the second insulating film may be a channel protective film that protects the second channel region.
同構成によれば、例えば、第２の半導体層上にソース電極及びドレイン電極を形成する工程において、エッチングによりパターンニングして、ソース電極、ドレイン電極を形成する際に、第２の半導体層のチャネル領域をエッチングしないように保護することが可能になる。
According to this configuration, for example, in the step of forming the source electrode and the drain electrode on the second semiconductor layer, when the source electrode and the drain electrode are formed by patterning by etching, the second semiconductor layer is formed. It becomes possible to protect the channel region from being etched.
また、本発明の薄膜トランジスタ基板においては、第１の絶縁膜が、ＴＥＯＳ（Tetra Ethyl Ortho Silicate）を材料とする酸化シリコン膜であり、第２の絶縁膜が、Ｎ２ＯとＳｉＨ４を材料とする酸化シリコン膜であってもよい。
In the thin film transistor substrate of the present invention, the first insulating film is a silicon oxide film made of TEOS (Tetra Ethyl Ortho Silicate), and the second insulating film is made of N 2 O and SiH 4 as materials. It may be a silicon oxide film.
また、本発明の薄膜トランジスタ基板においては、第２の絶縁膜上に、第２のチャネル領域を挟んで互いに対峙するように設けられたソース電極及びドレイン電極を更に備えていてもよい。
In addition, the thin film transistor substrate of the present invention may further include a source electrode and a drain electrode provided on the second insulating film so as to face each other with the second channel region interposed therebetween.
また、本発明の薄膜トランジスタ基板においては、第２の半導体層と第２の絶縁膜との間に、第２のチャネル領域を挟んで互いに対峙するように設けられたソース電極及びドレイン電極を更に備えていてもよい。
In addition, the thin film transistor substrate of the present invention further includes a source electrode and a drain electrode provided to face each other with the second channel region interposed between the second semiconductor layer and the second insulating film. It may be.
本発明の薄膜トランジスタ基板は、絶縁基板と、絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、第１の半導体層、及び第２の半導体層を覆う絶縁膜とを備え、第１の半導体層の第１のチャネル領域における絶縁膜の厚みと、第２の半導体層の第２のチャネル領域における絶縁膜の厚みが異なることを特徴とする。
The thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and a second channel region provided on the insulating substrate. A second thin film transistor having a second semiconductor layer having a first semiconductor layer, and an insulating film covering the second semiconductor layer, wherein the insulating film in the first channel region of the first semiconductor layer The thickness is different from the thickness of the insulating film in the second channel region of the second semiconductor layer.
同構成によれば、第１の薄膜トランジスタにおける第１の半導体層のチャネル領域における絶縁膜の厚みと、第２の薄膜トランジスタにおける第２の半導体層のチャネル領域における絶縁膜の厚みを異ならせることが可能になる。従って、第１の薄膜トランジスタと第２の薄膜トランジスタの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタの閾値電圧の差を十分に大きくすることが可能になる。その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタと第２の薄膜トランジスタからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備える薄膜トランジスタ基板を、歩留まりを低下させることなく作製することができる。
According to the configuration, the thickness of the insulating film in the channel region of the first semiconductor layer in the first thin film transistor can be different from the thickness of the insulating film in the channel region of the second semiconductor layer in the second thin film transistor. become. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
また、本発明の薄膜トランジスタ基板においては、半導体層が、酸化物半導体層であってもよい。
In the thin film transistor substrate of the present invention, the semiconductor layer may be an oxide semiconductor layer.
同構成によれば、アモルファスシリコンを半導体層に使用した薄膜トランジスタに比し、電子移動度が大きく、かつ低温プロセスが可能である薄膜トランジスタを形成することができる。
According to this configuration, it is possible to form a thin film transistor that has a higher electron mobility and can be processed at a lower temperature than a thin film transistor using amorphous silicon as a semiconductor layer.
また、本発明の薄膜トランジスタ基板においては、酸化物半導体層が、インジウム(Ｉｎ)、ガリウム(Ｇａ)、アルミニウム（Ａｌ）、銅（Ｃｕ）及び亜鉛(Ｚｎ)からなる群より選ばれる少なくとも１種を含む金属酸化物からなる構成としても良い。
In the thin film transistor substrate of the present invention, the oxide semiconductor layer includes at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). It is good also as a structure which consists of a metal oxide containing.
同構成によれば、これらの材料からなる酸化物半導体層は、アモルファスであっても移動度が高いため、スイッチング素子のオン抵抗を大きくすることができる。
According to the same configuration, the oxide semiconductor layer made of these materials has high mobility even if it is amorphous, so that the on-resistance of the switching element can be increased.
また、本発明の薄膜トランジスタ基板においては、酸化物半導体層が、Ｉｎ-Ｇａ-Ｚｎ-Ｏ系の金属酸化物からなる構成としてもよい。
In the thin film transistor substrate of the present invention, the oxide semiconductor layer may be formed of an In—Ga—Zn—O-based metal oxide.
同構成によれば、薄膜トランジスタにおいて、高移動度、低オフ電流という良好な特性を得ることができる。
According to the same configuration, good characteristics such as high mobility and low off-state current can be obtained in the thin film transistor.
また、本発明の薄膜トランジスタ基板においては、半導体層がシリコン系半導体層であってもよい。
In the thin film transistor substrate of the present invention, the semiconductor layer may be a silicon-based semiconductor layer.
また、本発明の薄膜トランジスタ基板は、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタと第２の薄膜トランジスタからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備える薄膜トランジスタ基板を、歩留まりを低下させることなく作製することができるという優れた特性を備えている。従って、本発明の薄膜トランジスタ基板は、薄膜トランジスタ基板と、薄膜トランジスタ基板に対向して配置された対向基板と、薄膜トランジスタ基板及び対向基板の間に設けられた表示媒体層とを備える表示装置に好適に使用できる。また、本発明の表示装置は、表示媒体層が液晶層である表示装置に好適に使用できる。
In addition, the thin film transistor substrate of the present invention has a simple structure and includes a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor having different threshold voltages, without reducing the yield. It has excellent characteristics that it can be manufactured. Therefore, the thin film transistor substrate of the present invention can be suitably used for a display device including a thin film transistor substrate, a counter substrate disposed to face the thin film transistor substrate, and a display medium layer provided between the thin film transistor substrate and the counter substrate. . The display device of the present invention can be suitably used for a display device in which the display medium layer is a liquid crystal layer.
本発明の薄膜トランジスタ基板の製造方法は、絶縁基板と絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、第１の半導体層、及び第２の半導体層を覆う第１の絶縁膜とを備えた薄膜トランジスタ基板の製造方法であって、絶縁基板上に、第１の半導体層及び第２の半導体層を形成する半導体層形成工程と、第２の半導体層の第２のチャネル領域に第１の絶縁膜と異なる材料からなる第２の絶縁膜を形成し、第１の半導体層、第２の半導体層、及び第２の絶縁膜を覆うように第１の絶縁膜を形成する絶縁膜形成工程とを少なくとも備えることを特徴とする。
The thin film transistor substrate manufacturing method of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, an insulating substrate, A method for manufacturing a thin film transistor substrate, comprising: a second thin film transistor including a second semiconductor layer having a channel region; a first semiconductor layer; and a first insulating film covering the second semiconductor layer. A semiconductor layer forming step of forming a first semiconductor layer and a second semiconductor layer on the substrate; and a second insulating layer made of a material different from that of the first insulating film in the second channel region of the second semiconductor layer. And an insulating film formation step of forming a first insulating film so as to cover the first semiconductor layer, the second semiconductor layer, and the second insulating film.
同構成によれば、第１の薄膜トランジスタにおける第１の半導体層のチャネル領域における絶縁膜構造と、第２の薄膜トランジスタにおける第２の半導体層のチャネル領域における絶縁膜構造とが異なる薄膜トランジスタ基板を製造することができる。従って、第１の薄膜トランジスタと第２の薄膜トランジスタの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタの閾値電圧の差を十分に大きくすることが可能になる。その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタと第２の薄膜トランジスタからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備える薄膜トランジスタ基板を、歩留まりを低下させることなく作製することができる。
According to this configuration, a thin film transistor substrate in which the insulating film structure in the channel region of the first semiconductor layer in the first thin film transistor is different from the insulating film structure in the channel region of the second semiconductor layer in the second thin film transistor is manufactured. be able to. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
本発明の薄膜トランジスタ基板の製造方法は、絶縁基板と、絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、第１の半導体層、及び第２の半導体層を覆う絶縁膜とを備えた薄膜トランジスタ基板の製造方法であって、絶縁基板上に、第１の半導体層及び第２の半導体層を形成する半導体層形成工程と、第１のチャネル領域及び第２のチャネル領域に、第１のチャネル領域における厚みと第２のチャネル領域における厚みとが異なる絶縁膜を形成する絶縁膜形成工程とを少なくとも備えることを特徴とする。
The method for manufacturing a thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and a second thin film transistor provided on the insulating substrate. A method of manufacturing a thin film transistor substrate comprising: a second thin film transistor comprising a second semiconductor layer having a channel region; a first semiconductor layer; and an insulating film covering the second semiconductor layer, the method comprising: In addition, a semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer, and a thickness in the first channel region and a thickness in the second channel region are formed in the first channel region and the second channel region. And an insulating film forming step of forming an insulating film different from the above.
同構成によれば、第１の薄膜トランジスタにおける第１の半導体層のチャネル領域における絶縁膜の厚みと、第２の薄膜トランジスタにおける第２の半導体層のチャネル領域における絶縁膜の厚みを異ならせることが可能になる。従って、第１の薄膜トランジスタと第２の薄膜トランジスタの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタの閾値電圧の差を十分に大きくすることが可能になる。その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタと第２の薄膜トランジスタからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備える薄膜トランジスタ基板を、歩留まりを低下させることなく作製することができる。
According to the configuration, the thickness of the insulating film in the channel region of the first semiconductor layer in the first thin film transistor can be different from the thickness of the insulating film in the channel region of the second semiconductor layer in the second thin film transistor. become. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.
本発明によれば、簡単な構成で、閾値電圧の異なる複数の薄膜トランジスタを形成することができ、薄膜トランジスタ基板の歩留まりの低下を抑制することができる。
According to the present invention, a plurality of thin film transistors having different threshold voltages can be formed with a simple configuration, and a reduction in yield of the thin film transistor substrate can be suppressed.
（第１の実施形態）
以下、本発明の実施形態について、図面を参照しながら詳細に説明する。尚、本発明は以下の実施形態に限定されるものではない。 (First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.
以下、本発明の実施形態について、図面を参照しながら詳細に説明する。尚、本発明は以下の実施形態に限定されるものではない。 (First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.
図１は、本発明の第１の実施形態に係る薄膜トランジスタを備えるアクティブマトリクス基板（薄膜トランジスタ基板）を有する液晶表示装置の断面図であり、図２は、本発明の第１の実施形態に係る薄膜トランジスタを備えるアクティブマトリクス基板の平面図である。また、図３は、本発明の第１の実施形態に係る薄膜トランジスタを備えるアクティブマトリクス基板の平面図であり、図４は、本発明の第１の実施形態に係るアクティブマトリクス基板の断面図である。
FIG. 1 is a sectional view of a liquid crystal display device having an active matrix substrate (thin film transistor substrate) including a thin film transistor according to the first embodiment of the present invention, and FIG. 2 is a thin film transistor according to the first embodiment of the present invention. It is a top view of an active matrix substrate provided with. FIG. 3 is a plan view of an active matrix substrate including the thin film transistor according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional view of the active matrix substrate according to the first embodiment of the present invention. .
液晶表示装置５０は、図１に示すように、互いに対向するように設けられた薄膜トランジスタ基板であるアクティブマトリクス基板２０ａと対向基板３０と、アクティブマトリクス基板２０ａ及び対向基板３０の間に設けられた表示媒体層である液晶層４０とを備えている。また、液晶表示装置５０は、アクティブマトリクス基板２０ａ及び対向基板３０を互いに接着するとともに、アクティブマトリクス基板２０ａ及び対向基板３０の間に液晶層４０を封入するために枠状に設けられたシール材３５とを備えている。
As shown in FIG. 1, the liquid crystal display device 50 includes an active matrix substrate 20a and a counter substrate 30, which are thin film transistor substrates provided so as to face each other, and a display provided between the active matrix substrate 20a and the counter substrate 30. And a liquid crystal layer 40 which is a medium layer. In addition, the liquid crystal display device 50 adheres the active matrix substrate 20a and the counter substrate 30 to each other, and seals 35 provided in a frame shape to enclose the liquid crystal layer 40 between the active matrix substrate 20a and the counter substrate 30. And.
また、液晶表示装置５０では、図１～図３に示すように、複数の画素等で構成され、シール材３５の内側の部分に画像表示を行う表示領域Ｄが規定され、また、アクティブマトリクス基板２０ａの対向基板３０から突出する部分に駆動回路領域（端子領域）Ｔが規定されている。この駆動回路領域Ｔは、図２、図３に示すように、表示領域Ｄの周辺に設けられている。
Further, in the liquid crystal display device 50, as shown in FIG. 1 to FIG. 3, a display region D that is composed of a plurality of pixels and the like and that displays an image in an inner portion of the sealing material 35 is defined. A drive circuit region (terminal region) T is defined in a portion protruding from the counter substrate 30 of 20a. The drive circuit region T is provided around the display region D as shown in FIGS.
また、駆動回路領域Ｔには、ゲートドライバ領域Ｔｇとソースドライバ領域Ｔｓとが設けられている。そして、ゲートドライバ領域Ｔｇには、表示領域Ｄの走査配線（ゲート配線）１１ａを駆動するゲートドライバ２６が設けられており、ソースドライバ領域Ｔｓには、表示領域Ｄの信号配線（ソース配線）１６ａを駆動するソースドライバ２７が設けられている。
In the drive circuit region T, a gate driver region Tg and a source driver region Ts are provided. The gate driver region Tg is provided with a gate driver 26 for driving the scanning wiring (gate wiring) 11a of the display region D, and the signal wiring (source wiring) 16a of the display region D is provided in the source driver region Ts. A source driver 27 for driving is provided.
アクティブマトリクス基板２０ａは、図３、図４に示すように、絶縁基板１０ａと、表示領域Ｄにおいて、絶縁基板１０ａ上に互いに平行に延びるように設けられた複数の走査配線１１ａと、各走査配線１１ａの間にそれぞれ設けられた複数の補助容量配線１１ｂと、絶縁基板１０ａ上に互いに平行に延びるように設けられた複数の信号配線１６ａとを備えている。
As shown in FIGS. 3 and 4, the active matrix substrate 20a includes an insulating substrate 10a, a plurality of scanning wirings 11a provided in the display region D so as to extend parallel to each other, and each scanning wiring. A plurality of auxiliary capacitance wirings 11b provided between 11a and a plurality of signal wirings 16a provided on the insulating substrate 10a so as to extend in parallel with each other.
また、アクティブマトリクス基板２０ａは、薄膜トランジスタ５を備えており、この薄膜トランジスタ５は、図４に示すように、駆動回路（即ち、ゲートドライバ２６）の能動素子であって、絶縁基板１０ａ上に形成された第１の薄膜トランジスタ５ａ及び第２の薄膜トランジスタ５ｂと、画素のスイッチング素子であって、絶縁基板１０ａ上に形成された第３の薄膜トランジスタ５ｃとにより構成されている。
The active matrix substrate 20a includes a thin film transistor 5. The thin film transistor 5 is an active element of a drive circuit (that is, a gate driver 26) as shown in FIG. 4, and is formed on the insulating substrate 10a. The first thin film transistor 5a and the second thin film transistor 5b and a third thin film transistor 5c which is a pixel switching element and is formed on the insulating substrate 10a.
また、アクティブマトリクス基板２０ａは、図４に示すように、第１の薄膜トランジスタ５ａ、第２の薄膜トランジスタ５ｂ、及び第３の薄膜トランジスタ５ｃを覆うように設けられた第１の絶縁膜である層間絶縁膜１７と、層間絶縁膜１７を覆うように設けられた平坦化膜１８と、平坦化膜１８上にマトリクス状に設けられ、第３の薄膜トランジスタ５ｃに接続された複数の画素電極１９ａと、各画素電極１９ａを覆うように設けられた配向膜（不図示）とを備えている。
Further, as shown in FIG. 4, the active matrix substrate 20a is an interlayer insulating film that is a first insulating film provided so as to cover the first thin film transistor 5a, the second thin film transistor 5b, and the third thin film transistor 5c. 17, a planarizing film 18 provided so as to cover the interlayer insulating film 17, a plurality of pixel electrodes 19 a provided in a matrix on the planarizing film 18 and connected to the third thin film transistor 5 c, and each pixel And an alignment film (not shown) provided so as to cover the electrode 19a.
走査配線１１ａは、図３に示すように、駆動回路領域Ｔのゲートドライバ領域Ｔｇに引き出され、そのゲートドライバ領域Ｔｇにおいて、ゲート端子１９ｂに接続されている。
As shown in FIG. 3, the scanning wiring 11a is led out to the gate driver region Tg of the driving circuit region T, and is connected to the gate terminal 19b in the gate driver region Tg.
また、信号配線１６ａは、図３に示すように、駆動回路領域Ｔのソースドライバ領域Ｔｓに中継用の配線として引き出され、そのソースドライバ領域Ｔｓにおいて、ソース端子１９ｃに接続されている。
Further, as shown in FIG. 3, the signal wiring 16a is led out as a relay wiring to the source driver region Ts in the driving circuit region T, and is connected to the source terminal 19c in the source driver region Ts.
第１の薄膜トランジスタ５ａは、ボトムゲート構造を有しており、図４に示すように、絶縁基板１０ａ上に設けられたゲート電極１１ａａと、ゲート電極１１ａａを覆うように設けられたゲート絶縁層１２とを備えている。また、第１の薄膜トランジスタ５ａは、ゲート絶縁層１２上でゲート電極１１ａａに重なるように島状に設けられた第１のチャネル領域Ｃａを有する第１の酸化物半導体層１３ａと、第１の酸化物半導体層１３ａ上にゲート電極１１ａａに重なるとともに第１のチャネル領域Ｃａを挟んで互いに対峙するように設けられたソース電極１６ａａ及びドレイン電極１６ｂとを備えている。
The first thin film transistor 5a has a bottom gate structure. As shown in FIG. 4, the gate electrode 11aa provided on the insulating substrate 10a and the gate insulating layer 12 provided so as to cover the gate electrode 11aa. And. The first thin film transistor 5a includes a first oxide semiconductor layer 13a having a first channel region Ca provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a first oxide semiconductor layer 13a. A source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13a so as to overlap the gate electrode 11aa and to face each other across the first channel region Ca.
また、同様に、第２の薄膜トランジスタ５ｂは、ボトムゲート構造を有しており、図４に示すように、絶縁基板１０ａ上に設けられたゲート電極１１ａａと、ゲート電極１１ａａを覆うように設けられたゲート絶縁層１２とを備えている。また、第２の薄膜トランジスタ５ｂは、ゲート絶縁層１２上でゲート電極１１ａａに重なるように島状に設けられた第２のチャネル領域Ｃｂを有する第２の酸化物半導体層１３ｂと、第２の酸化物半導体層１３ｂ上にゲート電極１１ａａに重なるとともに第２のチャネル領域Ｃｂを挟んで互いに対峙するように設けられたソース電極１６ａａ及びドレイン電極１６ｂとを備えている。
Similarly, the second thin film transistor 5b has a bottom gate structure, and is provided so as to cover the gate electrode 11aa provided on the insulating substrate 10a and the gate electrode 11aa as shown in FIG. And a gate insulating layer 12. The second thin film transistor 5b includes a second oxide semiconductor layer 13b having a second channel region Cb provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a second oxide semiconductor layer 13b. A source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13b so as to overlap the gate electrode 11aa and to face each other across the second channel region Cb.
また、第３の薄膜トランジスタ５ｃは、ボトムゲート構造を有しており、図４に示すように、絶縁基板１０ａ上に設けられたゲート電極１１ａａと、ゲート電極１１ａａを覆うように設けられたゲート絶縁層１２とを備えている。また、第３の薄膜トランジスタ５ｃは、ゲート絶縁層１２上でゲート電極１１ａａに重なるように島状に設けられた第３のチャネル領域Ｃｃを有する第３の酸化物半導体層１３ｃと、第３の酸化物半導体層１３ｃ上にゲート電極１１ａａに重なるとともに第３のチャネル領域Ｃｃを挟んで互いに対峙するように設けられたソース電極１６ａａ及びドレイン電極１６ｂとを備えている。
Further, the third thin film transistor 5c has a bottom gate structure, and as shown in FIG. 4, a gate electrode 11aa provided on the insulating substrate 10a and a gate insulation provided so as to cover the gate electrode 11aa. Layer 12. The third thin film transistor 5c includes a third oxide semiconductor layer 13c having a third channel region Cc provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a third oxide semiconductor layer 13c. A source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13c so as to overlap the gate electrode 11aa and to face each other across the third channel region Cc.
第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃは、例えば、ＩＧＺＯ（Ｉｎ-Ｇａ-Ｚｎ-Ｏ）系の酸化物半導体膜により形成されている。
The first to third oxide semiconductor layers 13a, 13b, and 13c are formed of, for example, an IGZO (In—Ga—Zn—O) -based oxide semiconductor film.
なお、ゲート電極１１ａａは、走査配線１１ａが側方への突出した部分である。また、ソース電極１６ａａは、信号配線１６ａが側方への突出した部分であり、図４に示すように、第１導電層１４ａ及び第２導電層１５ａの積層膜により構成されている。
Note that the gate electrode 11aa is a portion where the scanning wiring 11a protrudes to the side. Further, the source electrode 16aa is a portion from which the signal wiring 16a protrudes to the side, and is constituted by a laminated film of the first conductive layer 14a and the second conductive layer 15a as shown in FIG.
さらに、ドレイン電極１６ｂは、図４に示すように、第１導電層１４ｂ及び第２導電層１５ｂの積層膜により構成されている。
Furthermore, as shown in FIG. 4, the drain electrode 16b is composed of a laminated film of a first conductive layer 14b and a second conductive layer 15b.
そして、第３の薄膜トランジスタ５ｃを構成するドレイン電極１６ｂは、層間絶縁膜１７及び平坦化膜１８の積層膜に形成されたコンタクトホールＣを介して画素電極１９ａに接続されている。また、第３の薄膜トランジスタ５ｃを構成するドレイン電極１６ｂは、ゲート絶縁層１２を介して補助容量配線１１ｂと重なることにより補助容量を構成している。
The drain electrode 16b constituting the third thin film transistor 5c is connected to the pixel electrode 19a through a contact hole C formed in the laminated film of the interlayer insulating film 17 and the planarizing film 18. The drain electrode 16b constituting the third thin film transistor 5c forms an auxiliary capacitance by overlapping with the auxiliary capacitance wiring 11b via the gate insulating layer 12.
対向基板３０は、後述する図１２（ｃ）に示すように、絶縁基板１０ｂと、絶縁基板１０ｂ上に格子状に設けられたブラックマトリクス２１並びにブラックマトリクス２１の各格子間にそれぞれ設けられた赤色層、緑色層及び青色層などの着色層２２を有するカラーフィルター層とを備えている。また、対向基板３０は、そのカラーフィルター層を覆うように設けられた共通電極２３と、共通電極２３上に設けられたフォトスペーサ２４と、共通電極２３を覆うように設けられた配向膜（不図示）とを備えている。
As shown in FIG. 12C, which will be described later, the counter substrate 30 includes an insulating substrate 10b, a black matrix 21 provided in a lattice shape on the insulating substrate 10b, and a red color provided between each lattice of the black matrix 21. And a color filter layer having a colored layer 22 such as a green layer and a blue layer. The counter substrate 30 includes a common electrode 23 provided so as to cover the color filter layer, a photo spacer 24 provided on the common electrode 23, and an alignment film (non-coated) provided so as to cover the common electrode 23. As shown).
液晶層４０は、例えば、電気光学特性を有するネマチックの液晶材料などにより構成されている。
The liquid crystal layer 40 is made of, for example, a nematic liquid crystal material having electro-optical characteristics.
上記構成の液晶表示装置５０では、各画素において、ゲートドライバ２６からゲート信号が走査配線１１ａを介してゲート電極１１ａａに送られて、第３の薄膜トランジスタ５ｃがオン状態になったときに、ソースドライバ２７からソース信号が信号配線１６ａを介してソース電極１６ａａに送られて、酸化物半導体層１３ｃ及びドレイン電極１６ｂを介して、画素電極１９ａに所定の電荷が書き込まれる。
In the liquid crystal display device 50 configured as described above, in each pixel, when the gate signal is sent from the gate driver 26 to the gate electrode 11aa via the scanning wiring 11a and the third thin film transistor 5c is turned on, the source driver 27, a source signal is sent to the source electrode 16aa through the signal wiring 16a, and a predetermined charge is written into the pixel electrode 19a through the oxide semiconductor layer 13c and the drain electrode 16b.
この際、アクティブマトリクス基板２０ａの各画素電極１９ａと対向基板３０の共通電極２３との間において電位差が生じ、液晶層４０、すなわち、各画素の液晶容量、及びその液晶容量に並列に接続された補助容量に所定の電圧が印加される。
At this time, a potential difference is generated between each pixel electrode 19a of the active matrix substrate 20a and the common electrode 23 of the counter substrate 30, and the liquid crystal layer 40, that is, the liquid crystal capacitance of each pixel, and the liquid crystal capacitance connected to the liquid crystal layer in parallel. A predetermined voltage is applied to the auxiliary capacitor.
そして、液晶表示装置５０では、各画素において、液晶層４０に印加する電圧の大きさによって液晶層４０の配向状態を変えることにより、液晶層４０の光透過率を調整して画像が表示される。
In the liquid crystal display device 50, in each pixel, an image is displayed by adjusting the light transmittance of the liquid crystal layer 40 by changing the alignment state of the liquid crystal layer 40 according to the magnitude of the voltage applied to the liquid crystal layer 40. .
ここで、本実施形態においては、図４に示すように、駆動回路（即ち、ゲートドライバ２６）の能動素子として機能する第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂに、当該チャネル領域Ｃｂを保護するための第２の絶縁膜であるチャネル保護膜２５が設けられている点に特徴がある。
Here, in this embodiment, as shown in FIG. 4, the second channel of the second oxide semiconductor layer 13b in the second thin film transistor 5b functioning as an active element of the drive circuit (that is, the gate driver 26). The region Cb is characterized in that a channel protective film 25 which is a second insulating film for protecting the channel region Cb is provided.
より具体的には、図４に示すように、駆動回路の能動素子を構成する第１及び第２の薄膜トランジスタ５ａ，５ｂにおいて、第１の薄膜トランジスタ５ａにおける第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａには、層間絶縁膜１７が設けられており、上述のチャネル保護膜２５が設けられておらず、第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにのみチャネル保護膜２５が設けられている点に特徴がある。
More specifically, as shown in FIG. 4, in the first and second thin film transistors 5a and 5b constituting the active element of the drive circuit, the first oxide semiconductor layer 13a of the first thin film transistor 5a is first. In the channel region Ca, the interlayer insulating film 17 is provided, the above-described channel protective film 25 is not provided, and the second channel region of the second oxide semiconductor layer 13b in the second thin film transistor 5b is provided. The channel protective film 25 is provided only on Cb.
このような構成により、第１の薄膜トランジスタ５ａにおける第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａにおける絶縁膜構造と、第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにおける絶縁膜構造を異ならせることが可能になる。従って、第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタ５ａ，５ｂの閾値電圧の差を十分に大きくすることが可能になる。その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を作製することができる。
With such a configuration, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second oxide semiconductor layer 13b in the second thin film transistor 5b. It is possible to vary the insulating film structure in the channel region Cb. Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. As a result, a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
なお、本実施形態においては、図４に示すように、画素のスイッチング素子として機能する第３の薄膜トランジスタ５ｃにおける第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃにも、第２の薄膜トランジスタ５ｂと同様に、当該チャネル領域Ｃｃを保護するための第２の絶縁膜であるチャネル保護膜２５が設けられている。
In the present embodiment, as shown in FIG. 4, the second thin film transistor is also provided in the third channel region Cc of the third oxide semiconductor layer 13c in the third thin film transistor 5c functioning as a pixel switching element. Similar to 5b, a channel protective film 25 which is a second insulating film for protecting the channel region Cc is provided.
そして、本実施形態においては、第１の薄膜トランジスタ５ａが、閾値電圧が低いディプリーション型の薄膜トランジスタとして使用されるとともに、第２の薄膜トランジスタ５ｂが、閾値電圧が高いエンハンスメント型の薄膜トランジスタとして使用され、これらの第１及び第２の薄膜トランジスタ５ａ，５ｂにより、閾値電圧の差が大きいエンハンスメント－ディプリーション（Ｅ／Ｄ）インバータが構成されている。
In the present embodiment, the first thin film transistor 5a is used as a depletion type thin film transistor having a low threshold voltage, and the second thin film transistor 5b is used as an enhancement type thin film transistor having a high threshold voltage. These first and second thin film transistors 5a and 5b constitute an enhancement-depletion (E / D) inverter having a large difference in threshold voltage.
また、第３の薄膜トランジスタ５ｃが、閾値電圧が高く、リーク電流の低いエンハンスメント型の薄膜トランジスタとして画素のスイッチング素子に使用される。
The third thin film transistor 5c is used as a switching element for a pixel as an enhancement type thin film transistor having a high threshold voltage and a low leakage current.
次に、本実施形態の液晶表示装置５０の製造方法の一例について図５～図１２を用いて説明する。図５～図１１は、第１～第３の薄膜トランジスタ、及びアクティブマトリクス基板の製造工程を断面で示す説明図であり、図１２は、対向基板の製造工程を断面で示す説明図である。なお、本実施形態の製造方法は、薄膜トランジスタ及びアクティブマトリクス基板作製工程、対向基板作製工程及び液晶注入工程を備える。
Next, an example of a method for manufacturing the liquid crystal display device 50 of the present embodiment will be described with reference to FIGS. 5 to 11 are explanatory views showing the manufacturing process of the first to third thin film transistors and the active matrix substrate in cross section, and FIG. 12 is an explanatory view showing the manufacturing process of the counter substrate in cross section. The manufacturing method of this embodiment includes a thin film transistor and active matrix substrate manufacturing step, a counter substrate manufacturing step, and a liquid crystal injection step.
まず、薄膜トランジスタ及びアクティブマトリクス基板作製工程について説明する。
First, a manufacturing process of a thin film transistor and an active matrix substrate will be described.
＜ゲート電極形成工程＞
まず、ガラス基板、シリコン基板、耐熱性を有するプラスチック基板などの絶縁基板１０ａの基板全体に、スパッタリング法により、例えば、モリブテン膜（厚さ１５０ｎｍ程度）などを成膜した後に、そのモリブテン膜に対して、フォトリソグラフィ、ウエットエッチング及びレジストの剥離洗浄を行うことにより、図５に示すように、絶縁基板１０ａ上にゲート電極１１ａａ、及び補助容量配線１１ｂを形成する。なお、ゲート電極１１ａａ、補助容量配線１１ｂの形成と同時に、走査配線１１ａ及び信号配線１６ａを形成する。 <Gate electrode formation process>
First, for example, a molybdenum film (thickness of about 150 nm) or the like is formed on the entire substrate of the insulatingsubstrate 10a such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate by a sputtering method. Then, by performing photolithography, wet etching, and resist removal cleaning, the gate electrode 11aa and the auxiliary capacitor wiring 11b are formed on the insulating substrate 10a as shown in FIG. Note that the scanning wiring 11a and the signal wiring 16a are formed simultaneously with the formation of the gate electrode 11aa and the auxiliary capacitance wiring 11b.
まず、ガラス基板、シリコン基板、耐熱性を有するプラスチック基板などの絶縁基板１０ａの基板全体に、スパッタリング法により、例えば、モリブテン膜（厚さ１５０ｎｍ程度）などを成膜した後に、そのモリブテン膜に対して、フォトリソグラフィ、ウエットエッチング及びレジストの剥離洗浄を行うことにより、図５に示すように、絶縁基板１０ａ上にゲート電極１１ａａ、及び補助容量配線１１ｂを形成する。なお、ゲート電極１１ａａ、補助容量配線１１ｂの形成と同時に、走査配線１１ａ及び信号配線１６ａを形成する。 <Gate electrode formation process>
First, for example, a molybdenum film (thickness of about 150 nm) or the like is formed on the entire substrate of the insulating
また、本実施形態では、ゲート電極１１ａａを構成する金属膜として、単層構造のモリブテン膜を例示したが、例えば、アルミニウム膜、タングステン膜、タンタル膜、クロム膜、チタン膜、銅膜等の金属膜、または、これらの合金膜や金属窒化物による膜によりゲート電極１１ａａを、５０ｎｍ～３００ｎｍの厚さで形成する構成としても良い。
In the present embodiment, the molybdenum film having a single-layer structure is exemplified as the metal film constituting the gate electrode 11aa. For example, a metal such as an aluminum film, a tungsten film, a tantalum film, a chromium film, a titanium film, or a copper film is used. The gate electrode 11aa may be formed with a thickness of 50 nm to 300 nm using a film or a film made of such an alloy film or metal nitride.
また、上記プラスチック基板を形成する材料としては、例えば、ポリエチレンテレフタレート樹脂、ポリエチレンナフタレート樹脂、ポリエーテルサルフォン樹脂、アクリル樹脂、及びポリイミド樹脂を使用することができる。
Also, as a material for forming the plastic substrate, for example, polyethylene terephthalate resin, polyethylene naphthalate resin, polyether sulfone resin, acrylic resin, and polyimide resin can be used.
＜半導体層形成工程＞
続いて、ゲート電極１１ａａ、及び補助容量配線１１ｂが形成された基板全体に、ＣＶＤ法により、例えば、窒化シリコン膜（厚さ２００ｎｍ～５００ｎｍ程度）を成膜して、図６に示すように、ゲート電極１１ａａ、及び補助容量配線１１ｂを覆うようにゲート絶縁層１２を形成する。 <Semiconductor layer formation process>
Subsequently, for example, a silicon nitride film (with a thickness of about 200 nm to 500 nm) is formed by CVD on the entire substrate on which the gate electrode 11aa and theauxiliary capacitance wiring 11b are formed, and as shown in FIG. A gate insulating layer 12 is formed so as to cover the gate electrode 11aa and the auxiliary capacitance line 11b.
続いて、ゲート電極１１ａａ、及び補助容量配線１１ｂが形成された基板全体に、ＣＶＤ法により、例えば、窒化シリコン膜（厚さ２００ｎｍ～５００ｎｍ程度）を成膜して、図６に示すように、ゲート電極１１ａａ、及び補助容量配線１１ｂを覆うようにゲート絶縁層１２を形成する。 <Semiconductor layer formation process>
Subsequently, for example, a silicon nitride film (with a thickness of about 200 nm to 500 nm) is formed by CVD on the entire substrate on which the gate electrode 11aa and the
なお、ゲート絶縁層１２を２層の積層構造で形成する構成としても良い。この場合、上述の窒化シリコン膜（ＳｉＮｘ）以外に、例えば、酸化シリコン膜（ＳｉＯｘ）、酸化窒化シリコン膜（ＳｉＯｘＮｙ、ｘ＞ｙ）、窒化酸化シリコン膜（ＳｉＮｘＯｙ、ｘ＞ｙ）等を使用することができる。
Note that the gate insulating layer 12 may have a two-layer structure. In this case, for example, a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy, x> y), a silicon nitride oxide film (SiNxOy, x> y), or the like is used in addition to the above-described silicon nitride film (SiNx). be able to.
また、絶縁基板１０ａからの不純物等の拡散防止の観点から、下層側のゲート絶縁膜として、窒化シリコン膜、または窒化酸化シリコン膜を使用するとともに、上層側のゲート絶縁膜として、酸化シリコン膜、または酸化窒化シリコン膜を使用する構成とすることが好ましい。
Further, from the viewpoint of preventing diffusion of impurities and the like from the insulating substrate 10a, a silicon nitride film or a silicon nitride oxide film is used as a lower gate insulating film, and a silicon oxide film, as an upper gate insulating film, Alternatively, a structure using a silicon oxynitride film is preferable.
例えば、下層側のゲート絶縁膜として、ＳｉＨ４とＮＨ３とを反応ガスとして膜厚１００ｎｍから２００ｎｍの窒化シリコン膜を形成するとともに、上層側のゲート絶縁膜として、Ｎ２Ｏ、ＳｉＨ４を反応ガスとして膜厚５０ｎｍから１００ｎｍの酸化シリコン膜を形成することができる。
For example, a silicon nitride film having a thickness of 100 nm to 200 nm is formed as a lower gate insulating film using SiH 4 and NH 3 as reaction gases, and N 2 O and SiH 4 are reacted as an upper gate insulating film. A silicon oxide film with a thickness of 50 nm to 100 nm can be formed as the gas.
また、低い成膜温度により、ゲートリーク電流の少ない緻密なゲート絶縁層１２を形成するとの観点から、アルゴンガス等の希ガスを反応ガス中に含有させて絶縁膜中に混入させることが好ましい。
Further, from the viewpoint of forming a dense gate insulating layer 12 with a low gate leakage current at a low film formation temperature, it is preferable to include a rare gas such as argon gas in the reaction gas and mix it in the insulating film.
その後、スパッタリング法により、例えば、ＩＧＺＯ系の酸化物半導体膜（厚さ３０ｎｍ～１００ｎｍ程度）を成膜し、その後、その酸化物半導体膜に対して、フォトリソグラフィ、ウエットエッチング及びレジストの剥離洗浄を行うことにより、図６に示すように、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃを形成する。
Thereafter, for example, an IGZO-based oxide semiconductor film (with a thickness of about 30 nm to 100 nm) is formed by sputtering, and then the photolithography, wet etching, and resist removal cleaning are performed on the oxide semiconductor film. As a result, first to third oxide semiconductor layers 13a, 13b, and 13c are formed as shown in FIG.
＜チャネル保護膜形成工程（第２の絶縁膜形成工程）＞
次いで、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃが形成された基板全体に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜する。その後、レジストをマスクとしてフォトリソグラフィ、エッチング及びレジストの剥離洗浄を行うことにより、図７に示すように、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂに当該チャネル領域Ｃｂを保護するためのチャネル保護膜２５を厚さ５０～１００ｎｍ程度に形成する。また、同様に、第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃに当該チャネル領域Ｃｃを保護するためのチャネル保護膜２５を厚さ５０～１００ｎｍ程度に形成する。 <Channel protective film forming step (second insulating film forming step)>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, and 13c are formed by a plasma CVD method. Thereafter, photolithography, etching, and resist peeling cleaning are performed using the resist as a mask, thereby protecting the channel region Cb in the second channel region Cb of the second oxide semiconductor layer 13b as shown in FIG. A channel protective film 25 is formed to a thickness of about 50 to 100 nm. Similarly, a channel protective film 25 for protecting the channel region Cc is formed to a thickness of about 50 to 100 nm in the third channel region Cc of the third oxide semiconductor layer 13c.
次いで、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃが形成された基板全体に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜する。その後、レジストをマスクとしてフォトリソグラフィ、エッチング及びレジストの剥離洗浄を行うことにより、図７に示すように、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂに当該チャネル領域Ｃｂを保護するためのチャネル保護膜２５を厚さ５０～１００ｎｍ程度に形成する。また、同様に、第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃに当該チャネル領域Ｃｃを保護するためのチャネル保護膜２５を厚さ５０～１００ｎｍ程度に形成する。 <Channel protective film forming step (second insulating film forming step)>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the entire substrate on which the first to third
例えば、チャネル保護膜２５として、ＳｉＨ４とＮ２Ｏとを反応ガスとして、膜厚１００ｎｍ～２００ｎｍの酸化シリコン膜を形成することができる。
For example, as the channel protective film 25, a silicon oxide film with a thickness of 100 nm to 200 nm can be formed using SiH 4 and N 2 O as reaction gases.
＜ソースドレイン形成工程＞
さらに、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、及びチャネル保護膜２５が形成された基板全体に、スパッタリング法により、例えば、チタン膜（厚さ３０ｎｍ～１５０ｎｍ）及び銅膜（厚さ５０ｎｍ～４００ｎｍ程度）などを順に成膜する。その後、その銅膜に対してフォトリソグラフィ及びウエットエッチングを行うとともに、そのチタン膜に対してドライエッチング、並びにレジストの剥離洗浄を行うことにより、図８に示すように、信号配線１６ａ（図３参照）、ソース電極１６ａａ、及びドレイン電極１６ｂを形成する。 <Source drain formation process>
Further, for example, a titanium film (thickness 30 nm to 150 nm) and a copper film (thickness 30 nm to 150 nm) are formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, 13c and the channel protective film 25 are formed by sputtering. A film having a thickness of about 50 nm to 400 nm) is sequentially formed. Thereafter, the copper film is subjected to photolithography and wet etching, and the titanium film is dry-etched and resist is peeled and washed, so that the signal wiring 16a (see FIG. 3) is obtained. ), The source electrode 16aa and the drain electrode 16b are formed.
さらに、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、及びチャネル保護膜２５が形成された基板全体に、スパッタリング法により、例えば、チタン膜（厚さ３０ｎｍ～１５０ｎｍ）及び銅膜（厚さ５０ｎｍ～４００ｎｍ程度）などを順に成膜する。その後、その銅膜に対してフォトリソグラフィ及びウエットエッチングを行うとともに、そのチタン膜に対してドライエッチング、並びにレジストの剥離洗浄を行うことにより、図８に示すように、信号配線１６ａ（図３参照）、ソース電極１６ａａ、及びドレイン電極１６ｂを形成する。 <Source drain formation process>
Further, for example, a titanium film (
この際、第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａ、チャネル保護膜２５により被覆された第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂ、及びチャネル保護膜２５により被覆された第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃを露出させる。
At this time, the first channel region Ca of the first oxide semiconductor layer 13a, the second channel region Cb of the second oxide semiconductor layer 13b covered with the channel protective film 25, and the channel protective film 25 are covered. The third channel region Cc of the third oxide semiconductor layer 13c thus formed is exposed.
また、図８に示すように、第２の薄膜トランジスタ５ｂにおいて、ソース電極１６ａａ及びドレイン電極１６ｂは、チャネル保護膜２５上に、第２のチャネル領域Ｃｂを挟んで互いに対峙するように設けられる。
Also, as shown in FIG. 8, in the second thin film transistor 5b, the source electrode 16aa and the drain electrode 16b are provided on the channel protective film 25 so as to face each other with the second channel region Cb interposed therebetween.
また、同様に、図８に示すように、第３の薄膜トランジスタ５ｃにおいて、ソース電極１６ａａ及びドレイン電極１６ｂは、チャネル保護膜２５上に、第３のチャネル領域Ｃｃを挟んで互いに対峙するように設けられる。
Similarly, as shown in FIG. 8, in the third thin film transistor 5c, the source electrode 16aa and the drain electrode 16b are provided on the channel protective film 25 so as to face each other across the third channel region Cc. It is done.
なお、本実施形態では、ソース電極１６ａａ及びドレイン電極１６ｂを構成する金属膜として、積層構造のチタン膜及び銅膜を例示したが、例えば、アルミニウム膜、タングステン膜、タンタル膜、クロム膜等の金属膜、または、これらの合金膜や金属窒化物による膜によりソース電極１６ａａ及びドレイン電極１６ｂを形成する構成としても良い。
In this embodiment, as the metal film constituting the source electrode 16aa and the drain electrode 16b, a titanium film and a copper film having a laminated structure are exemplified. However, for example, a metal such as an aluminum film, a tungsten film, a tantalum film, or a chromium film is used. The source electrode 16aa and the drain electrode 16b may be formed by a film, or a film of an alloy film or metal nitride thereof.
また、導電性材料として、インジウム錫酸化物（ＩＴＯ）、インジウム亜鉛酸化物（ＩＺＯ）、酸化ケイ素を含有するインジウム錫酸化物（ＩＴＳＯ）、酸化インジウム（Ｉｎ２Ｏ３）、酸化錫（ＳｎＯ２）、酸化亜鉛（ＺｎＯ）、窒化チタン（ＴｉＮ）等の透光性を有する材料を使用する構成としても良い。
In addition, as a conductive material, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), indium oxide (In 2 O 3 ), tin oxide (SnO 2) ), Zinc oxide (ZnO), titanium nitride (TiN), or the like may be used.
また、エッチング加工としては、上述のドライエッチングまたはウェットエッチングのどちらを使用しても良いが、大面積基板を処理する場合は、ドライエッチングを使用する方が好ましい。エッチングガスとしては、ＣＦ４、ＮＦ３、ＳＦ６、ＣＨＦ３等のフッ素系ガス、Ｃｌ２、ＢＣｌ３、ＳｉＣｌ４、ＣＣｌ４等の塩素系ガス、酸素ガス等を使用することができ、ヘリウムやアルゴン等の不活性ガスを添加する構成としても良い。
As the etching process, either dry etching or wet etching described above may be used. However, when processing a large area substrate, it is preferable to use dry etching. As an etching gas, a fluorine-based gas such as CF 4 , NF 3 , SF 6 , or CHF 3 , a chlorine-based gas such as Cl 2 , BCl 3 , SiCl 4 , or CCl 4 , an oxygen gas, or the like can be used. Alternatively, an inert gas such as argon may be added.
＜層間絶縁膜形成工程（第１の絶縁膜形成工程）＞
次いで、ソース電極１６ａａ及びドレイン電極１６ｂが形成された（即ち、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃが形成された）基板の全体に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、図９に示すように、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃを覆う（即ち、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂ、及びチャネル保護膜２５を覆う）層間絶縁膜１７を厚さ２００～３００ｎｍ程度に形成する。 <Interlayer Insulating Film Forming Step (First Insulating Film Forming Step)>
Next, on the entire substrate on which the source electrode 16aa and thedrain electrode 16b are formed (that is, the first to third thin film transistors 5a, 5b, and 5c are formed), for example, a silicon nitride film, an oxide film, or the like is formed by plasma CVD. A silicon film, a silicon nitride oxide film, or the like is formed, and covers the first to third thin film transistors 5a, 5b, and 5c as shown in FIG. 9 (that is, the first to third oxide semiconductor layers 13a and 13b). , 13c, covering the source electrode 16aa, the drain electrode 16b, and the channel protective film 25), the interlayer insulating film 17 is formed to a thickness of about 200 to 300 nm.
次いで、ソース電極１６ａａ及びドレイン電極１６ｂが形成された（即ち、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃが形成された）基板の全体に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、図９に示すように、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃを覆う（即ち、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂ、及びチャネル保護膜２５を覆う）層間絶縁膜１７を厚さ２００～３００ｎｍ程度に形成する。 <Interlayer Insulating Film Forming Step (First Insulating Film Forming Step)>
Next, on the entire substrate on which the source electrode 16aa and the
なお、本実施形態においては、層間絶縁膜１７として、例えば、ＴＥＯＳ（Tetra Ethyl Ortho Silicate）を原料ガスとして使用して、例えば、プラズマＣＶＤ法により、膜厚２００ｎｍ～３００ｎｍの酸化シリコン膜を形成することができる。
In this embodiment, as the interlayer insulating film 17, a silicon oxide film having a thickness of 200 nm to 300 nm is formed by, for example, plasma CVD using TEOS (TetraTeEthyl Ortho Silicate) as a source gas. be able to.
次いで、層間絶縁膜１７上にフォトリソグラフィ工程でレジストマスクを形成し、図９に示すように、コンタクトホールＣ用のエッチングを行い、基板全面に対して熱処理を行う。
Next, a resist mask is formed on the interlayer insulating film 17 by a photolithography process, and as shown in FIG. 9, the contact hole C is etched, and the entire surface of the substrate is heat-treated.
ここで、酸化物半導体層と接する絶縁膜構造により、薄膜トランジスタの閾値電圧が変化するメカニズムについて説明する。
Here, the mechanism by which the threshold voltage of the thin film transistor changes due to the insulating film structure in contact with the oxide semiconductor layer will be described.
一般に、酸化物半導体層を備える薄膜トランジスタの半導体特性は、酸化物半導体層における酸素空孔濃度に極めて敏感に影響される。そして、酸化物半導体層を形成した後においても、周囲の水分や酸素の影響を受け、酸化物半導体層における酸素空孔濃度が増減する。
Generally, the semiconductor characteristics of a thin film transistor including an oxide semiconductor layer are extremely sensitively influenced by the oxygen vacancy concentration in the oxide semiconductor layer. Even after the oxide semiconductor layer is formed, the oxygen vacancy concentration in the oxide semiconductor layer increases or decreases due to the influence of surrounding moisture and oxygen.
そして、本実施形態のごとく、酸化物半導体層上に保護絶縁膜（チャネル保護膜）を設ける絶縁膜構造の場合、保護絶縁膜の膜質自体が薄膜トランジスタの特性に大きく影響を与える。
As in this embodiment, in the case of an insulating film structure in which a protective insulating film (channel protective film) is provided over an oxide semiconductor layer, the film quality of the protective insulating film greatly affects the characteristics of the thin film transistor.
例えば、本実施形態のごとく、チャネル保護膜２５として、ＳｉＨ４とＮ２Ｏとを反応ガスとして膜厚１００ｎｍ～２００ｎｍの酸化シリコン膜を形成する場合、Ｎ２Ｏの割合（流量）が多いと、酸素濃度が増加するため、第２の酸化物半導体層１３ｂへの酸化効果が大きくなるとともに、ＳｉＨ４の割合が少なくなるため、水素濃度が低下して、第２の酸化物半導体層１３ｂへの還元効果が小さくなる。
For example, as in the present embodiment, when a silicon oxide film having a film thickness of 100 nm to 200 nm is formed as a channel protective film 25 using SiH 4 and N 2 O as a reaction gas, the ratio (flow rate) of N 2 O is large. Since the oxygen concentration increases, the oxidation effect on the second oxide semiconductor layer 13b increases, and the proportion of SiH 4 decreases, so that the hydrogen concentration decreases and the second oxide semiconductor layer 13b is formed. The reduction effect of becomes smaller.
そうすると、図１３に示す、ドレイン・ソース電流（Ｉｄｓ）とゲート電圧（Ｖｇ）との関係を示すＩｄｓ－Ｖｇ特性のように、電流値が低下（即ち、図中の矢印Ｘ１の方向にシフト）して、リーク電流が低くなるとともに、閾値電圧Ｖｔｈが増加する（即ち、図中の矢印Ｙ１の方向にシフトする）ことになる。
Then, 13, as in the Ids-Vg characteristics showing the relationship between the drain-source current (Ids) and the gate voltage (Vg), lowering the current value (i.e., a shift in the direction of arrow X 1 in FIG. ) to, together with the leakage current decreases, the threshold voltage Vth is increased (i.e., shifted in the direction of arrow Y 1 in the figure) will be.
従って、第２のチャネル領域Ｃｂにチャネル保護膜２５が設けられた第２の酸化物半導体層１３ｂを備える第２の薄膜トランジスタ５ｂを、閾値電圧Ｖｔｈが高いエンハンスメント型の薄膜トランジスタとして使用することが可能になる。
Accordingly, the second thin film transistor 5b including the second oxide semiconductor layer 13b in which the channel protective film 25 is provided in the second channel region Cb can be used as an enhancement type thin film transistor having a high threshold voltage Vth. Become.
また、同様の原理により、第３のチャネル領域Ｃｃにチャネル保護膜２５が設けられた第３の酸化物半導体層１３ｃを備える第３の薄膜トランジスタ５ｃを、閾値電圧Ｖｔｈが高く、リーク電流の低いエンハンスメント型の薄膜トランジスタとして使用することが可能になる。
Further, according to the same principle, the third thin film transistor 5c including the third oxide semiconductor layer 13c in which the channel protective film 25 is provided in the third channel region Cc is enhanced with a high threshold voltage Vth and a low leakage current. It can be used as a thin film transistor.
なお、Ｎ２Ｏの割合（流量）が少ないと、酸素濃度が低下するため、第２の酸化物半導体層１３ｂへの酸化効果が小さくなるとともに、ＳｉＨ４の割合が多くなるため、水素濃度が向上して、第２の酸化物半導体層１３ｂへの還元効果が大きくなる。
Note that when the ratio (flow rate) of N 2 O is small, the oxygen concentration is decreased, so that the oxidation effect on the second oxide semiconductor layer 13b is reduced and the ratio of SiH 4 is increased, so that the hydrogen concentration is increased. As a result, the reduction effect on the second oxide semiconductor layer 13b is increased.
そうすると、図１４に示す、ドレイン・ソース電流（Ｉｄｓ）とゲート電圧（Ｖｇ）との関係を示すＩｄｓ－Ｖｇ特性に示すように、電流値が増加する（即ち、図中の矢印Ｘ２の方向にシフトする）とともに、閾値電圧Ｖｔｈが低下する（即ち、図中の矢印Ｙ２の方向にシフトする）ことになる。
Then, 14, as shown in Ids-Vg characteristics showing the relationship between the drain-source current (Ids) and the gate voltage (Vg), the current value is increased (i.e., the direction of the arrow X 2 in FIG. while shifting), the threshold voltage Vth is lowered (i.e., shifted in the direction of the arrow Y 2 in the figure) will be.
＜平坦化膜形成工程＞
次いで、層間絶縁膜１７が形成された基板の全体に、スピンコート法又はスリットコート法により、感光性のアクリル樹脂等からなる感光性の有機絶縁膜を厚さ１．０μｍ～３．０μｍ程度に塗布することにより、図１０に示すように、層間絶縁膜１７の表面上に平坦化膜１８を形成する。 <Planarization film formation process>
Next, a photosensitive organic insulating film made of photosensitive acrylic resin or the like is formed to a thickness of about 1.0 μm to 3.0 μm on the entire substrate on which theinterlayer insulating film 17 is formed by spin coating or slit coating. By applying, a planarizing film 18 is formed on the surface of the interlayer insulating film 17 as shown in FIG.
次いで、層間絶縁膜１７が形成された基板の全体に、スピンコート法又はスリットコート法により、感光性のアクリル樹脂等からなる感光性の有機絶縁膜を厚さ１．０μｍ～３．０μｍ程度に塗布することにより、図１０に示すように、層間絶縁膜１７の表面上に平坦化膜１８を形成する。 <Planarization film formation process>
Next, a photosensitive organic insulating film made of photosensitive acrylic resin or the like is formed to a thickness of about 1.0 μm to 3.0 μm on the entire substrate on which the
＜開口部形成工程＞
次いで、平坦化膜１８に対して、露光及び現像を行うことにより、図１１に示すように、平坦化膜１８に、ドレイン電極１６ｂに達するコンタクトホールＣが形成される。 <Opening step>
Next, by performing exposure and development on theplanarizing film 18, a contact hole C reaching the drain electrode 16b is formed in the planarizing film 18, as shown in FIG.
次いで、平坦化膜１８に対して、露光及び現像を行うことにより、図１１に示すように、平坦化膜１８に、ドレイン電極１６ｂに達するコンタクトホールＣが形成される。 <Opening step>
Next, by performing exposure and development on the
＜画素電極形成工程＞
次いで、層間絶縁膜１７及び平坦化膜１８が形成された基板全体に、スパッタリング法により、例えば、インジウム錫酸化物からなるＩＴＯ膜（厚さ５０ｎｍ～２００ｎｍ程度）などの透明導電膜を成膜する。その後、その透明導電膜に対して、フォトリソグラフィ、ウエットエッチング及びレジストの剥離洗浄を行うことにより、図４に示すように、画素電極１９ａ、ゲート端子１９ｂ（図３を参照）、ソース端子１９ｃ（図３を参照）を形成する。 <Pixel electrode formation process>
Next, a transparent conductive film such as, for example, an ITO film (thickness of about 50 nm to 200 nm) made of indium tin oxide is formed on the entire substrate on which theinterlayer insulating film 17 and the planarizing film 18 are formed by sputtering. . Thereafter, the transparent conductive film is subjected to photolithography, wet etching, and resist peeling and cleaning, so that the pixel electrode 19a, the gate terminal 19b (see FIG. 3), and the source terminal 19c (see FIG. 3), as shown in FIG. (See FIG. 3).
次いで、層間絶縁膜１７及び平坦化膜１８が形成された基板全体に、スパッタリング法により、例えば、インジウム錫酸化物からなるＩＴＯ膜（厚さ５０ｎｍ～２００ｎｍ程度）などの透明導電膜を成膜する。その後、その透明導電膜に対して、フォトリソグラフィ、ウエットエッチング及びレジストの剥離洗浄を行うことにより、図４に示すように、画素電極１９ａ、ゲート端子１９ｂ（図３を参照）、ソース端子１９ｃ（図３を参照）を形成する。 <Pixel electrode formation process>
Next, a transparent conductive film such as, for example, an ITO film (thickness of about 50 nm to 200 nm) made of indium tin oxide is formed on the entire substrate on which the
この際、図４に示すように、画素電極１９ａは、コンタクトホールＣの表面を覆うように、平坦化膜１８及び層間絶縁膜１７の表面上に形成される。
At this time, as shown in FIG. 4, the pixel electrode 19a is formed on the surface of the planarizing film 18 and the interlayer insulating film 17 so as to cover the surface of the contact hole C.
なお、画素電極１９ａは、透過型の液晶表示装置５０を形成する場合は、酸化タングステンを含むインジウム酸化物やインジウム亜鉛酸化物（ＩＺＯ）、酸化チタンを含むインジウム酸化物やインジウム錫酸化物（ＩＴＯ）等を使用することができる。また、上述のインジウム亜鉛酸化物、インジウム錫酸化物以外に、酸化ケイ素を含有するインジウム錫酸化物（ＩＴＳＯ）等を使用することもできる。
In the case of forming the transmissive liquid crystal display device 50, the pixel electrode 19a is made of indium oxide or indium zinc oxide (IZO) containing tungsten oxide, indium oxide or indium tin oxide (ITO) containing titanium oxide. ) Etc. can be used. In addition to the above-mentioned indium zinc oxide and indium tin oxide, indium tin oxide containing silicon oxide (ITSO) can also be used.
また、反射型の液晶表示装置５０を形成する場合は、反射性を有する金属薄膜として、チタン、タングステン、ニッケル、金、白金、銀、アルミニウム、マグネシウム、カルシウム、リチウム、及びこれらの合金からなる導電膜を使用し、この金属薄膜を画素電極１９ａとして使用する構成とすることができる。
Further, when the reflective liquid crystal display device 50 is formed, the conductive thin film is made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, or an alloy thereof. A film can be used, and this metal thin film can be used as the pixel electrode 19a.
以上のようにして、図４に示すアクティブマトリクス基板２０ａを作製することができる。
As described above, the active matrix substrate 20a shown in FIG. 4 can be manufactured.
＜対向基板作製工程＞
まず、ガラス基板などの絶縁基板１０ｂの基板全体に、スピンコート法又はスリットコート法により、例えば、黒色に着色された感光性樹脂を塗布した後に、その塗布膜を露光及び現像することにより、図１２（ａ）に示すように、ブラックマトリクス２１を厚さ１．０μｍ程度に形成する。 <Opposite substrate manufacturing process>
First, by applying, for example, a photosensitive resin colored in black to the entire substrate of the insulatingsubstrate 10b such as a glass substrate by spin coating or slit coating, the coating film is exposed and developed. As shown in FIG. 12A, the black matrix 21 is formed to a thickness of about 1.0 μm.
まず、ガラス基板などの絶縁基板１０ｂの基板全体に、スピンコート法又はスリットコート法により、例えば、黒色に着色された感光性樹脂を塗布した後に、その塗布膜を露光及び現像することにより、図１２（ａ）に示すように、ブラックマトリクス２１を厚さ１．０μｍ程度に形成する。 <Opposite substrate manufacturing process>
First, by applying, for example, a photosensitive resin colored in black to the entire substrate of the insulating
次いで、ブラックマトリクス２１が形成された基板全体に、スピンコート法又はスリットコート法により、例えば、赤色、緑色又は青色に着色された感光性樹脂を塗布する。その後、その塗布膜を露光及び現像することにより、図１２（ａ）に示すように、選択した色の着色層２２（例えば、赤色層）を厚さ２．０μｍ程度に形成する。そして、他の２色についても同様な工程を繰り返して、他の２色の着色層２２（例えば、緑色層及び青色層）を厚さ２．０μｍ程度に形成する。
Next, for example, a photosensitive resin colored in red, green, or blue is applied to the entire substrate on which the black matrix 21 is formed by spin coating or slit coating. Thereafter, the coating film is exposed and developed to form a colored layer 22 (for example, a red layer) of a selected color with a thickness of about 2.0 μm as shown in FIG. The same process is repeated for the other two colors to form the other two colored layers 22 (for example, a green layer and a blue layer) with a thickness of about 2.0 μm.
さらに、各色の着色層２２が形成された基板上に、スパッタリング法により、例えば、ＩＴＯ膜などの透明導電膜を堆積することにより、図１２（ｂ）に示すように、共通電極２３を厚さ５０ｎｍ～２００ｎｍ程度に形成する。
Further, by depositing, for example, a transparent conductive film such as an ITO film on the substrate on which the colored layer 22 of each color is formed by sputtering, the common electrode 23 has a thickness as shown in FIG. It is formed to have a thickness of about 50 nm to 200 nm.
最後に、共通電極２３が形成された基板全体に、スピンコート法又はスリットコート法により、感光性樹脂を塗布した後に、その塗布膜を露光及び現像することにより、図１２（ｃ）に示すように、フォトスペーサ２４を厚さ４μｍ程度に形成する。
Finally, after the photosensitive resin is applied to the entire substrate on which the common electrode 23 is formed by spin coating or slit coating, the coating film is exposed and developed, as shown in FIG. 12C. The photo spacer 24 is formed to a thickness of about 4 μm.
以上のようにして、対向基板３０を作製することができる。
The counter substrate 30 can be manufactured as described above.
＜液晶注入工程＞
まず、上記アクティブマトリクス基板作製工程で作製されたアクティブマトリクス基板２０ａ、及び上記対向基板作製工程で作製された対向基板３０の各表面に、印刷法によりポリイミドの樹脂膜を塗布した後に、その塗布膜に対して、焼成及びラビング処理を行うことにより、配向膜を形成する。 <Liquid crystal injection process>
First, a polyimide resin film is applied to each surface of theactive matrix substrate 20a manufactured in the active matrix substrate manufacturing process and the counter substrate 30 manufactured in the counter substrate manufacturing process by a printing method, and then the coating film is applied. On the other hand, an alignment film is formed by performing baking and rubbing treatment.
まず、上記アクティブマトリクス基板作製工程で作製されたアクティブマトリクス基板２０ａ、及び上記対向基板作製工程で作製された対向基板３０の各表面に、印刷法によりポリイミドの樹脂膜を塗布した後に、その塗布膜に対して、焼成及びラビング処理を行うことにより、配向膜を形成する。 <Liquid crystal injection process>
First, a polyimide resin film is applied to each surface of the
次いで、例えば、上記配向膜が形成された対向基板３０の表面に、ＵＶ（ultraviolet）硬化及び熱硬化併用型樹脂などからなるシール材３５を枠状に印刷した後に、シール材の内側に液晶材料を滴下する。
Next, for example, after a sealing material 35 made of UV (ultraviolet) curing and thermosetting resin is printed on the surface of the counter substrate 30 on which the alignment film is formed in a frame shape, a liquid crystal material is formed inside the sealing material. Is dripped.
さらに、上記液晶材料が滴下された対向基板３０と、上記配向膜が形成されたアクティブマトリクス基板２０ａとを、減圧下で貼り合わせた後に、その貼り合わせた貼合体を大気圧に開放することにより、その貼合体の表面及び裏面を加圧する。
Furthermore, after the counter substrate 30 onto which the liquid crystal material is dropped and the active matrix substrate 20a on which the alignment film is formed are bonded together under reduced pressure, the bonded bonded body is released to atmospheric pressure. The surface and the back surface of the bonded body are pressurized.
そして、上記貼合体に挟持されたシール材３５にＵＶ光を照射した後に、その貼合体を加熱することによりシール材３５を硬化させる。
And after irradiating UV light to the sealing material 35 pinched | interposed into the said bonding body, the sealing material 35 is hardened by heating the bonding body.
最後に、上記シール材３５を硬化させた貼合体を、例えば、ダイシングにより分断することにより、その不要な部分を除去する。
Finally, the unnecessary part is removed by dividing the bonded body in which the sealing material 35 is cured, for example, by dicing.
以上のようにして、本実施形態の液晶表示装置５０を製造することができる。
As described above, the liquid crystal display device 50 of the present embodiment can be manufactured.
以上に説明した本実施形態によれば、以下の効果を得ることができる。
According to the present embodiment described above, the following effects can be obtained.
（１）本実施形態においては、第２の酸化物半導体層１３ｂと第１の絶縁膜である層間絶縁膜１７との間であって、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂに、層間絶縁膜１７と異なる材料により形成された第２の絶縁膜であるチャネル保護膜２５を設ける構成としている。従って、第１の薄膜トランジスタ５ａにおける第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａにおける絶縁膜構造と、第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにおける絶縁膜構造を異ならせることが可能になる。従って、第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタ５ａ，５ｂの閾値電圧の差を十分に大きくすることが可能になる。その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備えたアクティブマトリクス基板２０ａを作製することができる。
(1) In the present embodiment, the second channel region of the second oxide semiconductor layer 13b is between the second oxide semiconductor layer 13b and the interlayer insulating film 17 that is the first insulating film. A channel protective film 25 that is a second insulating film formed of a material different from that of the interlayer insulating film 17 is provided on Cb. Therefore, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second channel region Cb of the second oxide semiconductor layer 13b in the second thin film transistor 5b. It is possible to vary the insulating film structure in. Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. As a result, an active matrix substrate 20a including a thin film transistor (that is, an E / D inverter) including a first thin film transistor 5a and a second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
（２）また、高電流駆動や低電圧駆動が可能な高品質デバイスが実現可能になり、例えば、画素メモリー回路や光センサー回路、ＯＬＥＤ駆動回路等の高機能回路が実現可能になる。
(2) In addition, a high-quality device capable of high current driving and low voltage driving can be realized, and for example, high-functional circuits such as a pixel memory circuit, a photosensor circuit, and an OLED driving circuit can be realized.
（３）本実施形態においては、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂに、当該チャネル領域Ｃｂを保護するチャネル保護膜２５を設ける構成としている。従って、ソース電極１６ａａ及びドレイン電極１６ｂを形成する工程において、エッチングによりパターンニングして、ソース電極１６ａａ、ドレイン電極１６ｂを形成する際に、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂをエッチングしないように保護することが可能になる。
(3) In this embodiment, the channel protective film 25 that protects the channel region Cb is provided in the second channel region Cb of the second oxide semiconductor layer 13b. Therefore, in the step of forming the source electrode 16aa and the drain electrode 16b, when the source electrode 16aa and the drain electrode 16b are formed by patterning by etching, the second channel region Cb of the second oxide semiconductor layer 13b is formed. Can be protected from being etched.
（４）本実施形態においては、半導体層として、第１及び第２の酸化物半導体層１３ａ，１３ｂを使用する構成としている。従って、アモルファスシリコンを半導体層に使用した薄膜トランジスタに比し、電子移動度が大きく、かつ低温プロセスが可能である薄膜トランジスタを形成することができる。
(4) In this embodiment, the first and second oxide semiconductor layers 13a and 13b are used as the semiconductor layers. Accordingly, it is possible to form a thin film transistor that has a higher electron mobility and can be processed at a lower temperature than a thin film transistor using amorphous silicon as a semiconductor layer.
（第２の実施形態）
次に、本発明の第２の実施形態について説明する。図１５は、本発明の第２の実施形態に係る薄膜トランジスタを備えるアクティブマトリクス基板の断面図である。なお、本実施形態においては、上記第１の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。また、液晶表示装置の全体構成及び製造方法については、上述の第１の実施形態において説明したものと同様であるため、ここでは詳しい説明を省略する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 15 is a cross-sectional view of an active matrix substrate including a thin film transistor according to the second embodiment of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The overall configuration and the manufacturing method of the liquid crystal display device are the same as those described in the first embodiment, and thus detailed description thereof is omitted here.
次に、本発明の第２の実施形態について説明する。図１５は、本発明の第２の実施形態に係る薄膜トランジスタを備えるアクティブマトリクス基板の断面図である。なお、本実施形態においては、上記第１の実施形態と同様の構成部分については同一の符号を付してその説明を省略する。また、液晶表示装置の全体構成及び製造方法については、上述の第１の実施形態において説明したものと同様であるため、ここでは詳しい説明を省略する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 15 is a cross-sectional view of an active matrix substrate including a thin film transistor according to the second embodiment of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The overall configuration and the manufacturing method of the liquid crystal display device are the same as those described in the first embodiment, and thus detailed description thereof is omitted here.
本実施形態においては、図１５に示すように、第２の絶縁膜として、上述のチャネル保護膜２５の代わりに、他の層間絶縁膜（以下、「層間絶縁膜」と言う。）２８を設けている点に特徴がある。
In the present embodiment, as shown in FIG. 15, another interlayer insulating film (hereinafter referred to as “interlayer insulating film”) 28 is provided as the second insulating film instead of the channel protective film 25 described above. There is a feature in that.
より具体的には、図１５に示すように、駆動回路の能動素子として機能する第１の薄膜トランジスタ５ａにおける第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａには、層間絶縁膜１７が設けられており、上述の層間絶縁膜２８が設けられておらず、第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂに層間絶縁膜２８が設けられている点に特徴がある。
More specifically, as shown in FIG. 15, an interlayer insulating film 17 is formed in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a that functions as an active element of the drive circuit. The interlayer insulating film 28 is provided, but the interlayer insulating film 28 is not provided, and the interlayer insulating film 28 is provided in the second channel region Cb of the second oxide semiconductor layer 13b in the second thin film transistor 5b. There is a feature.
このような構成により、上述の第１の実施形態の場合と同様に、第１の薄膜トランジスタ５ａにおける第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａにおける絶縁膜構造と、第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにおける絶縁膜構造を異ならせることが可能になる。
With such a configuration, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second thin film transistor, as in the case of the first embodiment described above. The insulating film structure in the second channel region Cb of the second oxide semiconductor layer 13b in 5b can be made different.
従って、第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂの閾値電圧を異ならせることが可能になり、２つの薄膜トランジスタ５ａ，５ｂの閾値電圧の差を十分に大きくすることが可能になる。従って、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備えるアクティブマトリクス基板を作製することができる。
Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. Therefore, an active matrix substrate including a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
なお、本実施形態においては、図１５に示すように、画素のスイッチング素子として機能する第３の薄膜トランジスタ５ｃにおける第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃにも、第２の薄膜トランジスタ５ｂと同様に、当該チャネル領域Ｃｃを保護するための第２の絶縁膜である層間絶縁膜２８が設けられている。
In the present embodiment, as shown in FIG. 15, the second thin film transistor is also provided in the third channel region Cc of the third oxide semiconductor layer 13c in the third thin film transistor 5c functioning as a switching element of the pixel. Similar to 5b, an interlayer insulating film 28 which is a second insulating film for protecting the channel region Cc is provided.
次に、本実施形態の液晶表示装置の製造方法の一例について、図１６を用いて説明する。図１６は、薄膜トランジスタ及びアクティブマトリクス基板の製造工程を断面で示す説明図である。
Next, an example of a method for manufacturing the liquid crystal display device of the present embodiment will be described with reference to FIG. FIG. 16 is an explanatory view showing the manufacturing process of the thin film transistor and the active matrix substrate in cross section.
まず、薄膜トランジスタ及びアクティブマトリクス基板作製工程において、上述の第１の実施形態において説明した図５、図６と同様に、ゲート電極形成工程、及び半導体層形成工程を行う。
First, in the thin film transistor and active matrix substrate manufacturing process, the gate electrode forming process and the semiconductor layer forming process are performed as in FIGS. 5 and 6 described in the first embodiment.
＜ソースドレイン形成工程＞
次いで、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃが形成された基板全体に、スパッタリング法により、例えば、チタン膜（厚さ３０ｎｍ～１５０ｎｍ）及び銅膜（厚さ５０ｎｍ～４００ｎｍ程度）などを順に成膜する。その後、その銅膜に対してフォトリソグラフィ及びウエットエッチングを行うとともに、そのチタン膜に対してドライエッチング、並びにレジストの剥離洗浄を行うことにより、図１６に示すように、信号配線１６ａ（図３参照）、ソース電極１６ａａ、及びドレイン電極１６ｂを形成する。この際、第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａ、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂ、及び第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃを露出させる。 <Source drain formation process>
Next, for example, a titanium film (thickness of 30 nm to 150 nm) and a copper film (thickness of about 50 nm to 400 nm) are formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, and 13c are formed by sputtering. ) Etc. in order. Thereafter, the copper film is subjected to photolithography and wet etching, and the titanium film is dry-etched and the resist is peeled and washed, so that the signal wiring 16a (see FIG. 3) is obtained. ), The source electrode 16aa and the drain electrode 16b are formed. At this time, the first channel region Ca of the first oxide semiconductor layer 13a, the second channel region Cb of the second oxide semiconductor layer 13b, and the third channel region of the third oxide semiconductor layer 13c. Cc is exposed.
次いで、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃが形成された基板全体に、スパッタリング法により、例えば、チタン膜（厚さ３０ｎｍ～１５０ｎｍ）及び銅膜（厚さ５０ｎｍ～４００ｎｍ程度）などを順に成膜する。その後、その銅膜に対してフォトリソグラフィ及びウエットエッチングを行うとともに、そのチタン膜に対してドライエッチング、並びにレジストの剥離洗浄を行うことにより、図１６に示すように、信号配線１６ａ（図３参照）、ソース電極１６ａａ、及びドレイン電極１６ｂを形成する。この際、第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａ、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂ、及び第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃを露出させる。 <Source drain formation process>
Next, for example, a titanium film (thickness of 30 nm to 150 nm) and a copper film (thickness of about 50 nm to 400 nm) are formed on the entire substrate on which the first to third
また、図１６に示すように、第２の薄膜トランジスタ５ｂにおいて、ソース電極１６ａａ及びドレイン電極１６ｂは、第２の酸化物半導体層１３ｂ上に、第２のチャネル領域Ｃｂを挟んで互いに対峙するように設けられる。
Further, as shown in FIG. 16, in the second thin film transistor 5b, the source electrode 16aa and the drain electrode 16b are opposed to each other on the second oxide semiconductor layer 13b with the second channel region Cb interposed therebetween. Provided.
また、同様に、図１６に示すように、第３の薄膜トランジスタ５ｃにおいて、ソース電極１６ａａ及びドレイン電極１６ｂは、第３の酸化物半導体層１３ｃ上に、第３のチャネル領域Ｃｃを挟んで互いに対峙するように設けられる。
Similarly, as shown in FIG. 16, in the third thin film transistor 5c, the source electrode 16aa and the drain electrode 16b are opposed to each other on the third oxide semiconductor layer 13c with the third channel region Cc interposed therebetween. To be provided.
＜層間絶縁膜形成工程（第２の絶縁膜形成工程）＞
次いで、第２及び第３の薄膜トランジスタ５ｂ，５ｃが形成された基板の表面に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、エッチングにより選択的にパターニングすることにより、図１６に示すように、第２及び第３の薄膜トランジスタ５ｂ，５ｃを覆う（即ち、第２及び第３の酸化物半導体層１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂを覆う）層間絶縁膜２８を厚さ２００～３００ｎｍ程度に形成する。 <Interlayer Insulating Film Forming Step (Second Insulating Film Forming Step)>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the second and third thin film transistors 5b and 5c are formed by plasma CVD, and is selectively etched. As shown in FIG. 16, the second and third thin film transistors 5b and 5c are covered by patterning (that is, the second and third oxide semiconductor layers 13b and 13c, the source electrode 16aa, and the drain electrode 16b are covered). A cover) interlayer insulating film 28 is formed to a thickness of about 200 to 300 nm.
次いで、第２及び第３の薄膜トランジスタ５ｂ，５ｃが形成された基板の表面に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、エッチングにより選択的にパターニングすることにより、図１６に示すように、第２及び第３の薄膜トランジスタ５ｂ，５ｃを覆う（即ち、第２及び第３の酸化物半導体層１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂを覆う）層間絶縁膜２８を厚さ２００～３００ｎｍ程度に形成する。 <Interlayer Insulating Film Forming Step (Second Insulating Film Forming Step)>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the second and third
この際、本実施形態においては、図１６に示すように、第２の酸化物半導体層１３ｂと層間絶縁膜２８との間に、第２のチャネル領域Ｃｂを挟んで互いに対峙するように、ソース電極１６ａａ及びドレイン電極１６ｂが設けられる。
At this time, in this embodiment, as shown in FIG. 16, the source is arranged so as to face each other with the second channel region Cb interposed between the second oxide semiconductor layer 13b and the interlayer insulating film 28. An electrode 16aa and a drain electrode 16b are provided.
＜層間絶縁膜形成工程（第１の絶縁膜形成工程）＞
次いで、上述の図９と同様に、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃが形成された基板の全体に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃを覆う（即ち、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂ、及び層間絶縁膜２８を覆う）層間絶縁膜１７を厚さ２００～３００ｎｍ程度に形成する。 <Interlayer Insulating Film Forming Step (First Insulating Film Forming Step)>
Next, as in FIG. 9 described above, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed on the entire substrate on which the first to third thin film transistors 5a, 5b, and 5c are formed by plasma CVD. Etc. to cover the first to third thin film transistors 5a, 5b, 5c (that is, the first to third oxide semiconductor layers 13a, 13b, 13c, the source electrode 16aa, the drain electrode 16b, and the interlayer insulation) An interlayer insulating film 17 (covering the film 28) is formed to a thickness of about 200 to 300 nm.
次いで、上述の図９と同様に、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃが形成された基板の全体に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃを覆う（即ち、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂ、及び層間絶縁膜２８を覆う）層間絶縁膜１７を厚さ２００～３００ｎｍ程度に形成する。 <Interlayer Insulating Film Forming Step (First Insulating Film Forming Step)>
Next, as in FIG. 9 described above, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed on the entire substrate on which the first to third
次いで、上述の図９と同様に、層間絶縁膜１７上にフォトリソグラフィ工程でレジストマスクを形成し、コンタクトホールＣ用のエッチングを行い、基板全面に対して熱処理を行う。
Next, similarly to FIG. 9 described above, a resist mask is formed on the interlayer insulating film 17 by a photolithography process, etching for the contact hole C is performed, and heat treatment is performed on the entire surface of the substrate.
なお、本実施形態においては、他の層間絶縁膜２８として、例えば、Ｎ２ＯとＳｉＨ４を使用して膜厚２００ｎｍ～３００ｎｍの酸化シリコン膜を形成することができる。
In the present embodiment, as the other interlayer insulating film 28, for example, a silicon oxide film having a thickness of 200 nm to 300 nm can be formed using N 2 O and SiH 4 .
次いで、上述の第１の実施形態において説明した図１０、図１１と同様に、平坦化膜形成工程、開口部形成工程、及び画素電極形成工程を行うことにより、図１５に示すアクティブマトリクス基板２０ａを作製することができる。
Next, similarly to FIGS. 10 and 11 described in the first embodiment, the planarization film forming step, the opening forming step, and the pixel electrode forming step are performed, whereby the active matrix substrate 20a shown in FIG. Can be produced.
更に、上述の第１の実施形態において説明した対向基板作製工程、及び液晶注入工程を行うことにより、本実施形態の液晶表示装置５０を製造することができる。
Further, the liquid crystal display device 50 of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.
以上に説明した本実施形態によれば、上述の（１）～（４）の効果と同様の効果を得ることができる。
According to the present embodiment described above, the same effects as the effects (1) to (4) described above can be obtained.
なお、上記実施形態は以下のように変更しても良い。
Note that the above embodiment may be modified as follows.
上記実施形態においては、半導体層として酸化物半導体層を使用したが、半導体層はこれに限定されず、酸化物半導体層の代わりに、例えば、アモルファスシリコンやポリシリコンからなるシリコン系半導体層を薄膜トランジスタの半導体層として使用する構成としても良い。
In the above embodiment, an oxide semiconductor layer is used as the semiconductor layer. However, the semiconductor layer is not limited to this. For example, a silicon-based semiconductor layer made of amorphous silicon or polysilicon is used as a thin film transistor instead of the oxide semiconductor layer. The semiconductor layer may be used as a semiconductor layer.
また、上記実施形態においては、酸化物半導体層としてＩｎ-Ｇａ-Ｚｎ-Ｏ系の金属酸化物からなる酸化物半導体層を使用したが、酸化物半導体層はこれに限定されず、インジウム(Ｉｎ)、ガリウム(Ｇａ)、アルミニウム（Ａｌ）、銅（Ｃｕ）、亜鉛(Ｚｎ)、マグネシウム（Ｍｇ）、カドミウム（Ｃｄ）のうち少なくとも１種を含む金属酸化物からなる材料を用いても良い。
In the above embodiment, an oxide semiconductor layer made of an In—Ga—Zn—O-based metal oxide is used as the oxide semiconductor layer. However, the oxide semiconductor layer is not limited to this, and indium (In ), Gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn), magnesium (Mg), and cadmium (Cd), a material made of a metal oxide containing at least one kind may be used.
これらの材料からなる酸化物半導体層１３ａは、アモルファスであっても移動度が高いため、スイッチング素子のオン抵抗を大きくすることができる。従って、データ読み出し時の出力電圧の差が大きくなり、Ｓ／Ｎ比を向上させることができる。
Since the oxide semiconductor layer 13a made of these materials has high mobility even if it is amorphous, the on-resistance of the switching element can be increased. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved.
例えば、ＩＧＺＯ（Ｉｎ-Ｇａ-Ｚｎ-Ｏ）の他に、ＩｎＧａＯ３（ＺｎＯ）５、ＭｇｘＺｎ１－ｘＯ、ＣｄｘＺｎ１－ｘＯ、ＣｄＯ等の酸化物半導体膜を挙げることができる。
For example, in addition to IGZO (In—Ga—Zn—O), oxide semiconductor films such as InGaO 3 (ZnO) 5 , Mg x Zn 1-x O, Cd x Zn 1-x O, and CdO can be given. it can.
また、１族元素、１３族元素、１４族元素、１５族元素、または１７族元素のうち１種、または複数種の不純物元素が添加されたＺｎＯの非晶質状態、多結晶状態、または非晶質状態と多結晶状態が混在する微結晶状態のもの、あるいは上記不純物が添加されていないものを使用することもできる。
In addition, an amorphous state, a polycrystalline state, or a non-crystalline state of ZnO to which one or more kinds of impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element, or Group 17 element are added. It is also possible to use a microcrystalline state in which a crystalline state and a polycrystalline state are mixed, or a material to which the above impurities are not added.
また、上述のチャネル保護膜２５や層間絶縁膜２８を設けずに、層間絶縁膜１７の厚みを異ならせる構成としても良い。より具体的には、図１７に示すように、第１の薄膜トランジスタ５ａにおける第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａにおける層間絶縁膜１７の厚みＴ１と、第２の薄膜トランジスタ５ｂにおける第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにおける層間絶縁膜１７の厚みＴ２が異なる（図１７においては、Ｔ２＞Ｔ１）構成としても良い。
Further, the thickness of the interlayer insulating film 17 may be different without providing the channel protective film 25 and the interlayer insulating film 28 described above. More specifically, as shown in FIG. 17, the thickness T 1 of the interlayer insulating film 17 in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a, and the second thin film transistor 5b. in (in FIG. 17, T 2> T 1) of the second thickness T 2 of the interlayer insulating film 17 in the channel region Cb is different of the second oxide semiconductor layer 13b may be configured.
この場合、ボトムゲート型の薄膜トランジスタが組み込まれた液晶表示装置５０においては、ゲート電極１１ａａの電位等によって、電気光学物質である液晶層４０中の水分やイオン（陽イオン）が引きつけられ、これが、平坦化膜１８とその上層の液晶層４０との界面において陽電荷として滞留する。また、この水分やイオンが平坦化膜１８中を下方拡散し、層間絶縁膜１７と平坦化膜１８の界面に電荷（陽電荷）が生じる。
In this case, in the liquid crystal display device 50 in which the bottom-gate thin film transistor is incorporated, moisture and ions (positive ions) in the liquid crystal layer 40 that is an electro-optical material are attracted by the potential of the gate electrode 11aa, It stays as a positive charge at the interface between the planarizing film 18 and the upper liquid crystal layer 40. Further, the moisture and ions diffuse downward in the planarization film 18, and charge (positive charge) is generated at the interface between the interlayer insulating film 17 and the planarization film 18.
そうすると、この電荷により、薄膜トランジスタのチャネル領域中にバックチャネルが形成されてしまい、薄膜トランジスタの閾値電圧に変動が生じるが、上述のごとく、第１の酸化物半導体層１３ａの第１のチャネル領域Ｃａにおける層間絶縁膜１７の厚みＴ１と、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにおける層間絶縁膜１７の厚みＴ２が異なるため、第１のチャネル領域Ｃａと第２のチャネル領域Ｃｂにおいて、層間絶縁膜１７と平坦化膜１８の界面に生じる電荷が異なることになる。
Then, a back channel is formed in the channel region of the thin film transistor due to this charge, and the threshold voltage of the thin film transistor varies. As described above, in the first channel region Ca of the first oxide semiconductor layer 13a. the thickness T 1 of the interlayer insulating film 17, a second for the thickness T 2 of the interlayer insulating film 17 in the channel region Cb are different, the first channel region Ca and the second channel region of the second oxide semiconductor layer 13b In Cb, the charges generated at the interface between the interlayer insulating film 17 and the planarizing film 18 are different.
従って、第１の薄膜トランジスタ５ａの閾値電圧の変動量と、第２の薄膜トランジスタ５ｂの閾値電圧の変動量が異なることになるため、上述のチャネル保護膜２５や層間絶縁膜２８を設ける場合と同様に、第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂの閾値電圧を異ならせることが可能になり、結果として、２つの薄膜トランジスタ５ａ，５ｂの閾値電圧の差を十分に大きくすることが可能になる。
Accordingly, since the amount of variation in the threshold voltage of the first thin film transistor 5a is different from the amount of variation in the threshold voltage of the second thin film transistor 5b, the same as in the case where the channel protective film 25 and the interlayer insulating film 28 are provided. The threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different. As a result, the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large.
その結果、簡単な構成で、閾値電圧の異なる第１の薄膜トランジスタ５ａと第２の薄膜トランジスタ５ｂからなる薄膜トランジスタ（即ち、Ｅ／Ｄインバータ）を備えたアクティブマトリクス基板２０ａを作製することができる。
As a result, an active matrix substrate 20a having a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.
また、高電流駆動や低電圧駆動が可能な高品質デバイスが実現可能になり、例えば、画素メモリー回路や光センサー回路、ＯＬＥＤ駆動回路等の高機能回路が実現可能になる。
Also, a high-quality device capable of high current drive and low voltage drive can be realized, and for example, high-functional circuits such as a pixel memory circuit, a photo sensor circuit, and an OLED drive circuit can be realized.
また、この場合、薄膜トランジスタ及びアクティブマトリクス基板作製工程において、まず、上述の第２の実施形態と同様に、ゲート電極形成工程、半導体層形成工程、及びソースドレイン形成工程を行う。
In this case, in the thin film transistor and active matrix substrate manufacturing process, first, the gate electrode forming process, the semiconductor layer forming process, and the source / drain forming process are performed as in the second embodiment.
次いで、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃが形成された基板の表面に、プラズマＣＶＤ法により、例えば、窒化シリコン膜、酸化シリコン膜、窒化酸化シリコン膜などを成膜し、エッチングにより選択的にパターニングすることにより、図１７に示すように、第１～第３の薄膜トランジスタ５ａ，５ｂ，５ｃを覆う（即ち、第１～第３の酸化物半導体層１３ａ，１３ｂ，１３ｃ、ソース電極１６ａａ、ドレイン電極１６ｂを覆う）層間絶縁膜１７を形成する。
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the first to third thin film transistors 5a, 5b, and 5c are formed by plasma CVD, and is etched. By selectively patterning, as shown in FIG. 17, the first to third thin film transistors 5a, 5b and 5c are covered (that is, the first to third oxide semiconductor layers 13a, 13b and 13c, the source electrode). An interlayer insulating film 17 is formed to cover 16aa and the drain electrode 16b.
この際、図１７に示すように、第１のチャネル領域Ｃａ及び第２のチャネル領域Ｃｂに、第１のチャネル領域Ｃａにおける厚みＴ１と第２のチャネル領域Ｃｂにおける厚みＴ２とが異なるように層間絶縁膜１７を形成する。
At this time, as shown in FIG. 17, the first channel region Ca and the second channel region Cb, so that the thickness T 2 between the thickness T 1 in the second channel region Cb in the first channel region Ca is different Then, an interlayer insulating film 17 is formed.
また、この場合、図１７に示すように、画素のスイッチング素子として機能する第３の薄膜トランジスタ５ｃが備える第３の酸化物半導体層１３ｃの第３のチャネル領域Ｃｃにおける層間絶縁膜１７の厚みは、第２の酸化物半導体層１３ｂの第２のチャネル領域Ｃｂにおける層間絶縁膜１７の厚みと同じ（即ち、Ｔ２）に設定される。
In this case, as shown in FIG. 17, the thickness of the interlayer insulating film 17 in the third channel region Cc of the third oxide semiconductor layer 13c included in the third thin film transistor 5c functioning as a pixel switching element is The thickness is set to be the same as the thickness of the interlayer insulating film 17 in the second channel region Cb of the second oxide semiconductor layer 13b (that is, T 2 ).
次いで、上述の図９と同様に、層間絶縁膜１７上にフォトリソグラフィ工程でレジストマスクを形成し、コンタクトホールＣ用のエッチングを行い、基板全面に対して熱処理を行う。
Next, similarly to FIG. 9 described above, a resist mask is formed on the interlayer insulating film 17 by a photolithography process, etching for the contact hole C is performed, and heat treatment is performed on the entire surface of the substrate.
次いで、上述の第１の実施形態において説明した図１０、図１１と同様に、平坦化膜形成工程、開口部形成工程、及び画素電極形成工程を行うことにより、図１７に示すアクティブマトリクス基板２０ａを作製することができる。
Next, as in FIGS. 10 and 11 described in the first embodiment, the planarization film forming step, the opening portion forming step, and the pixel electrode forming step are performed, whereby the active matrix substrate 20a shown in FIG. Can be produced.
更に、上述の第１の実施形態において説明した対向基板作製工程、及び液晶注入工程を行うことにより、本実施形態の液晶表示装置５０を製造することができる。
Further, the liquid crystal display device 50 of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.
本発明の活用例としては、酸化物半導体の半導体層を用いた薄膜トランジスタ基板及びその製造方法、表示装置が挙げられる。
Examples of utilization of the present invention include a thin film transistor substrate using an oxide semiconductor layer, a method for manufacturing the same, and a display device.
５ 薄膜トランジスタ
５ａ 第１の薄膜トランジスタ
５ｂ 第２の薄膜トランジスタ
５ｃ 第３の薄膜トランジスタ
１０ａ 絶縁基板
１１ａａ ゲート電極
１２ ゲート絶縁層
１３ａ 第１の酸化物半導体層（第１の半導体層）
１３ｂ 第２の酸化物半導体層（第２の半導体層）
１３ｃ 第３の酸化物半導体層
１６ａａ ソース電極
１６ｂ ドレイン電極
１７ 層間絶縁膜（第１の絶縁膜）
１８ 平坦化膜
１９ａ 画素電極
２０ａ アクティブマトリクス基板（薄膜トランジスタ基板）
２５ チャネル保護膜（第２の絶縁膜）
２８ 他の層間絶縁膜（第２の絶縁膜）
３０ 対向基板
４０ 液晶層（表示媒体層）
５０ 液晶表示装置
Ｃａ 第１のチャネル領域
Ｃｂ 第２のチャネル領域
Ｃｃ 第３のチャネル領域
Ｔ１ 第１のチャネル領域における層間絶縁膜の厚み
Ｔ２ 第２のチャネル領域における層間絶縁膜の厚み DESCRIPTION OFSYMBOLS 5 Thin-film transistor 5a 1st thin-film transistor 5b 2nd thin-film transistor 5c 3rd thin-film transistor 10a Insulating substrate 11aa Gate electrode 12 Gate insulating layer 13a 1st oxide semiconductor layer (1st semiconductor layer)
13b Second oxide semiconductor layer (second semiconductor layer)
13c Third oxide semiconductor layer16aa Source electrode 16b Drain electrode 17 Interlayer insulating film (first insulating film)
18Planarizing film 19a Pixel electrode 20a Active matrix substrate (thin film transistor substrate)
25 channel protective film (second insulating film)
28 Other interlayer insulating film (second insulating film)
30Counter substrate 40 Liquid crystal layer (display medium layer)
50 Liquid crystal display device Ca First channel region Cb Second channel region Cc Third channel region T 1 Thickness of interlayer insulating film in first channel region T 2 Thickness of interlayer insulating film in second channel region
５ａ 第１の薄膜トランジスタ
５ｂ 第２の薄膜トランジスタ
５ｃ 第３の薄膜トランジスタ
１０ａ 絶縁基板
１１ａａ ゲート電極
１２ ゲート絶縁層
１３ａ 第１の酸化物半導体層（第１の半導体層）
１３ｂ 第２の酸化物半導体層（第２の半導体層）
１３ｃ 第３の酸化物半導体層
１６ａａ ソース電極
１６ｂ ドレイン電極
１７ 層間絶縁膜（第１の絶縁膜）
１８ 平坦化膜
１９ａ 画素電極
２０ａ アクティブマトリクス基板（薄膜トランジスタ基板）
２５ チャネル保護膜（第２の絶縁膜）
２８ 他の層間絶縁膜（第２の絶縁膜）
３０ 対向基板
４０ 液晶層（表示媒体層）
５０ 液晶表示装置
Ｃａ 第１のチャネル領域
Ｃｂ 第２のチャネル領域
Ｃｃ 第３のチャネル領域
Ｔ１ 第１のチャネル領域における層間絶縁膜の厚み
Ｔ２ 第２のチャネル領域における層間絶縁膜の厚み DESCRIPTION OF
13b Second oxide semiconductor layer (second semiconductor layer)
13c Third oxide semiconductor layer
18
25 channel protective film (second insulating film)
28 Other interlayer insulating film (second insulating film)
30
50 Liquid crystal display device Ca First channel region Cb Second channel region Cc Third channel region T 1 Thickness of interlayer insulating film in first channel region T 2 Thickness of interlayer insulating film in second channel region
Claims (14)
- 絶縁基板と、
前記絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、
前記絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、
前記第１の半導体層、及び前記第２の半導体層を覆う第１の絶縁膜と
を備えた薄膜トランジスタ基板であって、
第２の半導体層と前記第１の絶縁膜との間であって、前記第２の半導体層の前記第２のチャネル領域に、前記第１の絶縁膜と異なる材料により形成された第２の絶縁膜が設けられていることを特徴とする薄膜トランジスタ基板。 An insulating substrate;
A first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region;
A second thin film transistor provided on the insulating substrate and including a second semiconductor layer having a second channel region;
A thin film transistor substrate comprising: the first semiconductor layer; and a first insulating film covering the second semiconductor layer,
A second semiconductor layer formed between the second semiconductor layer and the first insulating film, in the second channel region of the second semiconductor layer, using a material different from that of the first insulating film; A thin film transistor substrate provided with an insulating film. - 前記第２の絶縁膜が、前記第２のチャネル領域を保護するチャネル保護膜であることを特徴とする請求項１に記載の薄膜トランジスタ基板。 2. The thin film transistor substrate according to claim 1, wherein the second insulating film is a channel protective film for protecting the second channel region.
- 前記第１の絶縁膜が、ＴＥＯＳ（Tetra Ethyl Ortho Silicate）を材料とする酸化シリコン膜であり、前記第２の絶縁膜が、Ｎ２ＯとＳｉＨ４を材料とする酸化シリコン膜であることを特徴とする請求項２に記載の薄膜トランジスタ基板。 The first insulating film is a silicon oxide film made of TEOS (Tetra Ethyl Ortho Silicate), and the second insulating film is a silicon oxide film made of N 2 O and SiH 4. The thin film transistor substrate according to claim 2, wherein the thin film transistor substrate is a thin film transistor substrate.
- 前記第２の絶縁膜上に、前記第２のチャネル領域を挟んで互いに対峙するように設けられたソース電極及びドレイン電極を更に備えていることを特徴とする請求項１～請求項３のいずれか１項に記載の薄膜トランジスタ基板。 The source electrode and the drain electrode further provided on the second insulating film so as to face each other across the second channel region. 2. The thin film transistor substrate according to claim 1.
- 前記第２の半導体層と前記第２の絶縁膜との間に、前記第２のチャネル領域を挟んで互いに対峙するように設けられたソース電極及びドレイン電極を更に備えていることを特徴とする請求項１に記載の薄膜トランジスタ基板。 A source electrode and a drain electrode are further provided between the second semiconductor layer and the second insulating film so as to face each other with the second channel region interposed therebetween. The thin film transistor substrate according to claim 1.
- 絶縁基板と、
前記絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、
前記絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、
前記第１の半導体層、及び前記第２の半導体層を覆う絶縁膜と
を備えた薄膜トランジスタ基板であって、
前記第１の半導体層の第１のチャネル領域における前記絶縁膜の厚みと、前記第２の半導体層の第２のチャネル領域における前記絶縁膜の厚みが異なることを特徴とする薄膜トランジスタ基板。 An insulating substrate;
A first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region;
A second thin film transistor provided on the insulating substrate and including a second semiconductor layer having a second channel region;
A thin film transistor substrate comprising: an insulating film covering the first semiconductor layer and the second semiconductor layer;
A thin film transistor substrate, wherein the thickness of the insulating film in the first channel region of the first semiconductor layer is different from the thickness of the insulating film in the second channel region of the second semiconductor layer. - 前記第１の半導体層と前記第２の半導体層が、酸化物半導体層であることを特徴とする請求項１～請求項６のいずれか１項に記載の薄膜トランジスタ基板。 7. The thin film transistor substrate according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are oxide semiconductor layers.
- 前記酸化物半導体層が、インジウム(Ｉｎ)、ガリウム(Ｇａ)、アルミニウム（Ａｌ）、銅（Ｃｕ）及び亜鉛(Ｚｎ)からなる群より選ばれる少なくとも１種を含む金属酸化物からなることを特徴とする請求項７に記載の薄膜トランジスタ基板。 The oxide semiconductor layer is made of a metal oxide including at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). The thin film transistor substrate according to claim 7.
- 前記酸化物半導体層が、Ｉｎ-Ｇａ-Ｚｎ-Ｏ系の金属酸化物からなることを特徴とする請求項８に記載の薄膜トランジスタ基板。 The thin film transistor substrate according to claim 8, wherein the oxide semiconductor layer is made of an In-Ga-Zn-O-based metal oxide.
- 前記半導体層がシリコン系半導体層であることを特徴とする請求項１～請求項６のいずれか１項に記載の薄膜トランジスタ基板。 The thin film transistor substrate according to any one of claims 1 to 6, wherein the semiconductor layer is a silicon-based semiconductor layer.
- 請求項１～請求項１０のいずれか１項に記載の前記薄膜トランジスタ基板と、
前記薄膜トランジスタ基板に対向して配置された対向基板と、
前記薄膜トランジスタ基板及び前記対向基板の間に設けられた表示媒体層と
を備えることを特徴とする表示装置。 The thin film transistor substrate according to any one of claims 1 to 10,
A counter substrate disposed to face the thin film transistor substrate;
And a display medium layer provided between the thin film transistor substrate and the counter substrate. - 前記表示媒体層が液晶層であることを特徴とする請求項１１に記載の表示装置。 The display device according to claim 11, wherein the display medium layer is a liquid crystal layer.
- 絶縁基板と、該絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、前記絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、前記第１の半導体層、及び前記第２の半導体層を覆う第１の絶縁膜とを備えた薄膜トランジスタ基板の製造方法であって、
前記絶縁基板上に、前記第１の半導体層及び前記第２の半導体層を形成する半導体層形成工程と、
前記第２のチャネル領域に前記第１の絶縁膜と異なる材料からなる第２の絶縁膜を形成する第２の絶縁膜形成工程と、
前記第１の半導体層、前記第２の半導体層、及び前記第２の絶縁膜を覆うように前記第１の絶縁膜を形成する第１の絶縁膜形成工程と
を少なくとも備えることを特徴とする薄膜トランジスタ基板の製造方法。 A first thin film transistor provided with an insulating substrate, a first semiconductor layer provided on the insulating substrate and having a first channel region; and a second thin film transistor provided on the insulating substrate and having a second channel region. A method of manufacturing a thin film transistor substrate comprising: a second thin film transistor including a semiconductor layer; the first semiconductor layer; and a first insulating film covering the second semiconductor layer,
A semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer on the insulating substrate;
A second insulating film forming step of forming a second insulating film made of a material different from that of the first insulating film in the second channel region;
And a first insulating film forming step of forming the first insulating film so as to cover the first semiconductor layer, the second semiconductor layer, and the second insulating film. A method for manufacturing a thin film transistor substrate. - 絶縁基板と、該絶縁基板上に設けられ、第１のチャネル領域を有する第１の半導体層を備える第１の薄膜トランジスタと、前記絶縁基板上に設けられ、第２のチャネル領域を有する第２の半導体層を備える第２の薄膜トランジスタと、前記第１の半導体層、及び前記第２の半導体層を覆う絶縁膜とを備えた薄膜トランジスタ基板の製造方法であって、
前記絶縁基板上に、前記第１の半導体層及び前記第２の半導体層を形成する半導体層形成工程と、
前記第１のチャネル領域及び前記第２のチャネル領域に、前記第１のチャネル領域における厚みと前記第２のチャネル領域における厚みとが異なる前記絶縁膜を形成する絶縁膜形成工程と
を少なくとも備えることを特徴とする薄膜トランジスタ基板の製造方法。 A first thin film transistor provided with an insulating substrate, a first semiconductor layer provided on the insulating substrate and having a first channel region; and a second thin film transistor provided on the insulating substrate and having a second channel region. A method of manufacturing a thin film transistor substrate comprising: a second thin film transistor including a semiconductor layer; and an insulating film covering the first semiconductor layer and the second semiconductor layer,
A semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer on the insulating substrate;
An insulating film forming step for forming the insulating film in the first channel region and the second channel region in which the thickness in the first channel region and the thickness in the second channel region are different from each other. A method of manufacturing a thin film transistor substrate, characterized in that:
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| JP6151070B2 (en) * | 2013-04-11 | 2017-06-21 | 株式会社ジャパンディスプレイ | THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME |
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| TWI813217B (en) * | 2021-12-09 | 2023-08-21 | 友達光電股份有限公司 | Semiconductor device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08340116A (en) * | 1995-06-09 | 1996-12-24 | Sony Corp | Bottom gate type thin film transistor |
| JPH11337974A (en) * | 1998-05-29 | 1999-12-10 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and its production |
| JP2001250949A (en) * | 2000-03-02 | 2001-09-14 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2009260002A (en) * | 2008-04-16 | 2009-11-05 | Hitachi Ltd | Semiconductor device, and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6839108B1 (en) | 1998-05-16 | 2005-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method of manufacturing the same |
| JP5294651B2 (en) | 2007-05-18 | 2013-09-18 | キヤノン株式会社 | Inverter manufacturing method and inverter |
-
2011
- 2011-01-12 WO PCT/JP2011/000103 patent/WO2011129037A1/en active Application Filing
- 2011-01-12 US US13/640,381 patent/US8842229B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08340116A (en) * | 1995-06-09 | 1996-12-24 | Sony Corp | Bottom gate type thin film transistor |
| JPH11337974A (en) * | 1998-05-29 | 1999-12-10 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and its production |
| JP2001250949A (en) * | 2000-03-02 | 2001-09-14 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2009260002A (en) * | 2008-04-16 | 2009-11-05 | Hitachi Ltd | Semiconductor device, and method for manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794511A (en) * | 2012-10-30 | 2014-05-14 | 株式会社半导体能源研究所 | Display device and electronic device |
| JP2014090068A (en) * | 2012-10-30 | 2014-05-15 | Semiconductor Energy Lab Co Ltd | Display device and electronic apparatus |
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