WO2011129037A1 - Thin film transistor substrate, method for producing same, and display device - Google Patents

Thin film transistor substrate, method for producing same, and display device Download PDF

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Publication number
WO2011129037A1
WO2011129037A1 PCT/JP2011/000103 JP2011000103W WO2011129037A1 WO 2011129037 A1 WO2011129037 A1 WO 2011129037A1 JP 2011000103 W JP2011000103 W JP 2011000103W WO 2011129037 A1 WO2011129037 A1 WO 2011129037A1
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thin film
semiconductor layer
film transistor
substrate
channel region
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PCT/JP2011/000103
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French (fr)
Japanese (ja)
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宮本忠芳
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シャープ株式会社
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Priority to JP2010-095013 priority
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Abstract

Disclosed is an active matrix substrate (20a) which comprises: an insulating substrate (10a); a first thin film transistor (5a) that is formed on the insulating substrate (10a) and comprises a first oxide semiconductor layer (13a) having a first channel region (Ca); a second thin film transistor (5b) that is formed on the insulating substrate (10a) and comprises a second oxide semiconductor layer (13b) having a second channel region (Cb); and an interlayer insulating film (17) that covers the first oxide semiconductor layer (13a) and the second oxide semiconductor layer (13b). A channel protection film (25), which is formed from a material different from that of the interlayer insulating film (17), is provided between the second oxide semiconductor layer (13b) and the interlayer insulating film (17) in the second channel region (Cb) of the second oxide semiconductor layer (13b).

Description

Thin film transistor substrate, method for manufacturing the same, and display device

The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate using an oxide semiconductor layer, a method for manufacturing the same, and a display device.

In the active matrix substrate, for example, a thin film transistor (hereinafter also referred to as “TFT”) is provided as a switching element for each pixel which is the minimum unit of an image.

A typical bottom gate type TFT has, for example, a gate electrode provided on an insulating substrate, a gate insulating film provided so as to cover the gate electrode, and an island shape so as to overlap the gate electrode on the gate insulating film. And a source electrode and a drain electrode provided to face each other on the semiconductor layer.

Further, in a general peripheral circuit integrated display device, for example, a thin film transistor with a low leakage current used for a switching element of a pixel and a thin film transistor that has a low threshold voltage and can be driven at a high speed are used. The

Further, when a peripheral circuit is manufactured using a plurality of thin film transistors, the threshold voltage of the CMOS inverter that requires both the n-type channel and the p-type channel or the two thin film transistors that constitute the inverter from the viewpoint of high-speed driving. Enhancement-depletion (E / D) inverters with large differences are widely used.

In recent years, in an active matrix substrate, an IGZO (In—Ga—Zn—) that can move at high speed is used instead of a conventional thin film transistor using an amorphous silicon semiconductor layer as a switching element of each pixel that is the minimum unit of an image. A TFT using an oxide semiconductor layer (hereinafter also referred to as “oxide semiconductor layer”) formed of an O) -based oxide semiconductor film has been proposed.

Here, many high-speed moving oxide semiconductors such as amorphous IGZO have n-type (electron) conduction, and do not become p-type (hole) conduction even by doping, so that a CMOS circuit configuration cannot be used. Therefore, there is a problem that a CMOS inverter circuit cannot be used in a circuit using a high-speed moving oxide semiconductor, and an E / D inverter circuit capable of independently controlling the threshold voltage of each thin film transistor and capable of high-speed operation. The production of is needed.

Therefore, an E / D inverter composed of a thin film transistor having an oxide semiconductor as a channel layer is disclosed. More specifically, an E / D including a first thin film transistor and a second thin film transistor having different channel layer thicknesses, and at least one of the channel layers of the first and second thin film transistors is heat-treated. An inverter is disclosed. With such a configuration, a difference occurs in the threshold voltage due to a difference in channel layer thickness between the first and second thin film transistors constituting the E / D inverter or due to a difference in heat treatment conditions of the channel layer. Therefore, it is described that the difference between the threshold voltages of two thin film transistors constituting the E / D inverter can be sufficiently increased (see, for example, Patent Document 1).

JP 2009-4733 A

However, in the E / D inverter described in Patent Document 1, after an amorphous IGZO film serving as a channel layer is formed on a substrate, etching (dry etching or wet etching) is performed on the amorphous IGZO film. Since the first and second thin film transistors having different channel layer thicknesses are formed, if the substrate size is increased, it becomes difficult to control the channel layer thickness, resulting in a decrease in film thickness uniformity. was there.

More specifically, in the E / D inverter described in Patent Document 1, after forming an amorphous IGZO film with a thickness of 60 nm in a portion corresponding to each channel layer of the first and second thin film transistors, Etching is performed so that the film thickness of the amorphous IGZO film serving as the channel layer of the second thin film transistor is reduced to half the thickness (ie, 30 nm) at the time of film formation by dry etching. In order to etch uniformly to half the thickness at the time of film formation, both establishment of a highly advanced technique and introduction of an expensive apparatus are required. Therefore, it is difficult to manufacture the thin film transistor, and as a result, there is a problem that the yield is lowered.

In the E / D inverter described in Patent Document 1, after an amorphous IGZO film serving as a channel layer is formed on a substrate, for example, the channel layer is heated by contact heating or electromagnetic wave irradiation (high frequency irradiation). Or the ultraviolet light irradiation), the threshold voltage of the first and second thin film transistors is changed. However, the selective heat treatment in such a local region complicates the process and has high definition and fineness. It can be said that application to a thin film transistor is difficult. As a result, there is a problem that the yield decreases.

Therefore, the present invention has been made in view of the above problems, and a thin film transistor substrate capable of forming a plurality of thin film transistors having different threshold voltages with a simple configuration and suppressing a decrease in yield, and the thin film transistor substrate therefor An object is to provide a manufacturing method and a display device.

To achieve the above object, a thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and the insulating substrate. A second semiconductor film including a second thin film transistor provided with a second semiconductor layer having a second channel region, a first semiconductor layer, and a first insulating film covering the second semiconductor layer; A second insulating film formed of a material different from that of the first insulating film is provided between the layer and the first insulating film and in the second channel region of the second semiconductor layer; It is characterized by.

According to this configuration, the insulating film structure in the channel region of the first semiconductor layer in the first thin film transistor can be different from the insulating film structure in the channel region of the second semiconductor layer in the second thin film transistor. . Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.

In the thin film transistor substrate of the present invention, the second insulating film may be a channel protective film that protects the second channel region.

According to this configuration, for example, in the step of forming the source electrode and the drain electrode on the second semiconductor layer, when the source electrode and the drain electrode are formed by patterning by etching, the second semiconductor layer is formed. It becomes possible to protect the channel region from being etched.

In the thin film transistor substrate of the present invention, the first insulating film is a silicon oxide film made of TEOS (Tetra Ethyl Ortho Silicate), and the second insulating film is made of N 2 O and SiH 4 as materials. It may be a silicon oxide film.

In addition, the thin film transistor substrate of the present invention may further include a source electrode and a drain electrode provided on the second insulating film so as to face each other with the second channel region interposed therebetween.

In addition, the thin film transistor substrate of the present invention further includes a source electrode and a drain electrode provided to face each other with the second channel region interposed between the second semiconductor layer and the second insulating film. It may be.

The thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and a second channel region provided on the insulating substrate. A second thin film transistor having a second semiconductor layer having a first semiconductor layer, and an insulating film covering the second semiconductor layer, wherein the insulating film in the first channel region of the first semiconductor layer The thickness is different from the thickness of the insulating film in the second channel region of the second semiconductor layer.

According to the configuration, the thickness of the insulating film in the channel region of the first semiconductor layer in the first thin film transistor can be different from the thickness of the insulating film in the channel region of the second semiconductor layer in the second thin film transistor. become. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.

In the thin film transistor substrate of the present invention, the semiconductor layer may be an oxide semiconductor layer.

According to this configuration, it is possible to form a thin film transistor that has a higher electron mobility and can be processed at a lower temperature than a thin film transistor using amorphous silicon as a semiconductor layer.

In the thin film transistor substrate of the present invention, the oxide semiconductor layer includes at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). It is good also as a structure which consists of a metal oxide containing.

According to the same configuration, the oxide semiconductor layer made of these materials has high mobility even if it is amorphous, so that the on-resistance of the switching element can be increased.

In the thin film transistor substrate of the present invention, the oxide semiconductor layer may be formed of an In—Ga—Zn—O-based metal oxide.

According to the same configuration, good characteristics such as high mobility and low off-state current can be obtained in the thin film transistor.

In the thin film transistor substrate of the present invention, the semiconductor layer may be a silicon-based semiconductor layer.

In addition, the thin film transistor substrate of the present invention has a simple structure and includes a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor having different threshold voltages, without reducing the yield. It has excellent characteristics that it can be manufactured. Therefore, the thin film transistor substrate of the present invention can be suitably used for a display device including a thin film transistor substrate, a counter substrate disposed to face the thin film transistor substrate, and a display medium layer provided between the thin film transistor substrate and the counter substrate. . The display device of the present invention can be suitably used for a display device in which the display medium layer is a liquid crystal layer.

The thin film transistor substrate manufacturing method of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, an insulating substrate, A method for manufacturing a thin film transistor substrate, comprising: a second thin film transistor including a second semiconductor layer having a channel region; a first semiconductor layer; and a first insulating film covering the second semiconductor layer. A semiconductor layer forming step of forming a first semiconductor layer and a second semiconductor layer on the substrate; and a second insulating layer made of a material different from that of the first insulating film in the second channel region of the second semiconductor layer. And an insulating film formation step of forming a first insulating film so as to cover the first semiconductor layer, the second semiconductor layer, and the second insulating film.

According to this configuration, a thin film transistor substrate in which the insulating film structure in the channel region of the first semiconductor layer in the first thin film transistor is different from the insulating film structure in the channel region of the second semiconductor layer in the second thin film transistor is manufactured. be able to. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.

The method for manufacturing a thin film transistor substrate of the present invention includes an insulating substrate, a first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region, and a second thin film transistor provided on the insulating substrate. A method of manufacturing a thin film transistor substrate comprising: a second thin film transistor comprising a second semiconductor layer having a channel region; a first semiconductor layer; and an insulating film covering the second semiconductor layer, the method comprising: In addition, a semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer, and a thickness in the first channel region and a thickness in the second channel region are formed in the first channel region and the second channel region. And an insulating film forming step of forming an insulating film different from the above.

According to the configuration, the thickness of the insulating film in the channel region of the first semiconductor layer in the first thin film transistor can be different from the thickness of the insulating film in the channel region of the second semiconductor layer in the second thin film transistor. become. Accordingly, the threshold voltages of the first thin film transistor and the second thin film transistor can be made different, and the difference between the threshold voltages of the two thin film transistors can be made sufficiently large. As a result, a thin film transistor substrate including a thin film transistor (that is, an E / D inverter) including a first thin film transistor and a second thin film transistor with different threshold voltages can be manufactured with a simple configuration without reducing the yield.

According to the present invention, a plurality of thin film transistors having different threshold voltages can be formed with a simple configuration, and a reduction in yield of the thin film transistor substrate can be suppressed.

It is sectional drawing of the liquid crystal display device which has an active matrix substrate (thin film transistor substrate) provided with the thin-film transistor concerning the 1st Embodiment of this invention. 1 is a plan view of an active matrix substrate including a thin film transistor according to a first embodiment of the present invention. 1 is a plan view of an active matrix substrate including a thin film transistor according to a first embodiment of the present invention. 1 is a cross-sectional view of an active matrix substrate according to a first embodiment of the present invention. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of the 1st thin-film transistor which concerns on the 1st Embodiment of this invention, a 2nd thin-film transistor, and an active matrix substrate in a cross section. It is explanatory drawing which shows the manufacturing process of a counter substrate in a cross section. It is an Ids-Vg characteristic diagram showing the relationship between drain-source current (Ids) and gate voltage (Vg). It is an Ids-Vg characteristic diagram showing the relationship between drain-source current (Ids) and gate voltage (Vg). It is sectional drawing of an active matrix substrate provided with the thin-film transistor which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows the manufacturing process of the 2nd thin-film transistor and active matrix substrate which concern on the 2nd Embodiment of this invention in a cross section. It is sectional drawing which shows the modification of an active matrix substrate provided with the thin-film transistor which concerns on embodiment of this invention.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

FIG. 1 is a sectional view of a liquid crystal display device having an active matrix substrate (thin film transistor substrate) including a thin film transistor according to the first embodiment of the present invention, and FIG. 2 is a thin film transistor according to the first embodiment of the present invention. It is a top view of an active matrix substrate provided with. FIG. 3 is a plan view of an active matrix substrate including the thin film transistor according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional view of the active matrix substrate according to the first embodiment of the present invention. .

As shown in FIG. 1, the liquid crystal display device 50 includes an active matrix substrate 20a and a counter substrate 30, which are thin film transistor substrates provided so as to face each other, and a display provided between the active matrix substrate 20a and the counter substrate 30. And a liquid crystal layer 40 which is a medium layer. In addition, the liquid crystal display device 50 adheres the active matrix substrate 20a and the counter substrate 30 to each other, and seals 35 provided in a frame shape to enclose the liquid crystal layer 40 between the active matrix substrate 20a and the counter substrate 30. And.

Further, in the liquid crystal display device 50, as shown in FIG. 1 to FIG. 3, a display region D that is composed of a plurality of pixels and the like and that displays an image in an inner portion of the sealing material 35 is defined. A drive circuit region (terminal region) T is defined in a portion protruding from the counter substrate 30 of 20a. The drive circuit region T is provided around the display region D as shown in FIGS.

In the drive circuit region T, a gate driver region Tg and a source driver region Ts are provided. The gate driver region Tg is provided with a gate driver 26 for driving the scanning wiring (gate wiring) 11a of the display region D, and the signal wiring (source wiring) 16a of the display region D is provided in the source driver region Ts. A source driver 27 for driving is provided.

As shown in FIGS. 3 and 4, the active matrix substrate 20a includes an insulating substrate 10a, a plurality of scanning wirings 11a provided in the display region D so as to extend parallel to each other, and each scanning wiring. A plurality of auxiliary capacitance wirings 11b provided between 11a and a plurality of signal wirings 16a provided on the insulating substrate 10a so as to extend in parallel with each other.

The active matrix substrate 20a includes a thin film transistor 5. The thin film transistor 5 is an active element of a drive circuit (that is, a gate driver 26) as shown in FIG. 4, and is formed on the insulating substrate 10a. The first thin film transistor 5a and the second thin film transistor 5b and a third thin film transistor 5c which is a pixel switching element and is formed on the insulating substrate 10a.

Further, as shown in FIG. 4, the active matrix substrate 20a is an interlayer insulating film that is a first insulating film provided so as to cover the first thin film transistor 5a, the second thin film transistor 5b, and the third thin film transistor 5c. 17, a planarizing film 18 provided so as to cover the interlayer insulating film 17, a plurality of pixel electrodes 19 a provided in a matrix on the planarizing film 18 and connected to the third thin film transistor 5 c, and each pixel And an alignment film (not shown) provided so as to cover the electrode 19a.

As shown in FIG. 3, the scanning wiring 11a is led out to the gate driver region Tg of the driving circuit region T, and is connected to the gate terminal 19b in the gate driver region Tg.

Further, as shown in FIG. 3, the signal wiring 16a is led out as a relay wiring to the source driver region Ts in the driving circuit region T, and is connected to the source terminal 19c in the source driver region Ts.

The first thin film transistor 5a has a bottom gate structure. As shown in FIG. 4, the gate electrode 11aa provided on the insulating substrate 10a and the gate insulating layer 12 provided so as to cover the gate electrode 11aa. And. The first thin film transistor 5a includes a first oxide semiconductor layer 13a having a first channel region Ca provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a first oxide semiconductor layer 13a. A source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13a so as to overlap the gate electrode 11aa and to face each other across the first channel region Ca.

Similarly, the second thin film transistor 5b has a bottom gate structure, and is provided so as to cover the gate electrode 11aa provided on the insulating substrate 10a and the gate electrode 11aa as shown in FIG. And a gate insulating layer 12. The second thin film transistor 5b includes a second oxide semiconductor layer 13b having a second channel region Cb provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a second oxide semiconductor layer 13b. A source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13b so as to overlap the gate electrode 11aa and to face each other across the second channel region Cb.

Further, the third thin film transistor 5c has a bottom gate structure, and as shown in FIG. 4, a gate electrode 11aa provided on the insulating substrate 10a and a gate insulation provided so as to cover the gate electrode 11aa. Layer 12. The third thin film transistor 5c includes a third oxide semiconductor layer 13c having a third channel region Cc provided in an island shape so as to overlap the gate electrode 11aa on the gate insulating layer 12, and a third oxide semiconductor layer 13c. A source electrode 16aa and a drain electrode 16b are provided on the physical semiconductor layer 13c so as to overlap the gate electrode 11aa and to face each other across the third channel region Cc.

The first to third oxide semiconductor layers 13a, 13b, and 13c are formed of, for example, an IGZO (In—Ga—Zn—O) -based oxide semiconductor film.

Note that the gate electrode 11aa is a portion where the scanning wiring 11a protrudes to the side. Further, the source electrode 16aa is a portion from which the signal wiring 16a protrudes to the side, and is constituted by a laminated film of the first conductive layer 14a and the second conductive layer 15a as shown in FIG.

Furthermore, as shown in FIG. 4, the drain electrode 16b is composed of a laminated film of a first conductive layer 14b and a second conductive layer 15b.

The drain electrode 16b constituting the third thin film transistor 5c is connected to the pixel electrode 19a through a contact hole C formed in the laminated film of the interlayer insulating film 17 and the planarizing film 18. The drain electrode 16b constituting the third thin film transistor 5c forms an auxiliary capacitance by overlapping with the auxiliary capacitance wiring 11b via the gate insulating layer 12.

As shown in FIG. 12C, which will be described later, the counter substrate 30 includes an insulating substrate 10b, a black matrix 21 provided in a lattice shape on the insulating substrate 10b, and a red color provided between each lattice of the black matrix 21. And a color filter layer having a colored layer 22 such as a green layer and a blue layer. The counter substrate 30 includes a common electrode 23 provided so as to cover the color filter layer, a photo spacer 24 provided on the common electrode 23, and an alignment film (non-coated) provided so as to cover the common electrode 23. As shown).

The liquid crystal layer 40 is made of, for example, a nematic liquid crystal material having electro-optical characteristics.

In the liquid crystal display device 50 configured as described above, in each pixel, when the gate signal is sent from the gate driver 26 to the gate electrode 11aa via the scanning wiring 11a and the third thin film transistor 5c is turned on, the source driver 27, a source signal is sent to the source electrode 16aa through the signal wiring 16a, and a predetermined charge is written into the pixel electrode 19a through the oxide semiconductor layer 13c and the drain electrode 16b.

At this time, a potential difference is generated between each pixel electrode 19a of the active matrix substrate 20a and the common electrode 23 of the counter substrate 30, and the liquid crystal layer 40, that is, the liquid crystal capacitance of each pixel, and the liquid crystal capacitance connected to the liquid crystal layer in parallel. A predetermined voltage is applied to the auxiliary capacitor.

In the liquid crystal display device 50, in each pixel, an image is displayed by adjusting the light transmittance of the liquid crystal layer 40 by changing the alignment state of the liquid crystal layer 40 according to the magnitude of the voltage applied to the liquid crystal layer 40. .

Here, in this embodiment, as shown in FIG. 4, the second channel of the second oxide semiconductor layer 13b in the second thin film transistor 5b functioning as an active element of the drive circuit (that is, the gate driver 26). The region Cb is characterized in that a channel protective film 25 which is a second insulating film for protecting the channel region Cb is provided.

More specifically, as shown in FIG. 4, in the first and second thin film transistors 5a and 5b constituting the active element of the drive circuit, the first oxide semiconductor layer 13a of the first thin film transistor 5a is first. In the channel region Ca, the interlayer insulating film 17 is provided, the above-described channel protective film 25 is not provided, and the second channel region of the second oxide semiconductor layer 13b in the second thin film transistor 5b is provided. The channel protective film 25 is provided only on Cb.

With such a configuration, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second oxide semiconductor layer 13b in the second thin film transistor 5b. It is possible to vary the insulating film structure in the channel region Cb. Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. As a result, a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.

In the present embodiment, as shown in FIG. 4, the second thin film transistor is also provided in the third channel region Cc of the third oxide semiconductor layer 13c in the third thin film transistor 5c functioning as a pixel switching element. Similar to 5b, a channel protective film 25 which is a second insulating film for protecting the channel region Cc is provided.

In the present embodiment, the first thin film transistor 5a is used as a depletion type thin film transistor having a low threshold voltage, and the second thin film transistor 5b is used as an enhancement type thin film transistor having a high threshold voltage. These first and second thin film transistors 5a and 5b constitute an enhancement-depletion (E / D) inverter having a large difference in threshold voltage.

The third thin film transistor 5c is used as a switching element for a pixel as an enhancement type thin film transistor having a high threshold voltage and a low leakage current.

Next, an example of a method for manufacturing the liquid crystal display device 50 of the present embodiment will be described with reference to FIGS. 5 to 11 are explanatory views showing the manufacturing process of the first to third thin film transistors and the active matrix substrate in cross section, and FIG. 12 is an explanatory view showing the manufacturing process of the counter substrate in cross section. The manufacturing method of this embodiment includes a thin film transistor and active matrix substrate manufacturing step, a counter substrate manufacturing step, and a liquid crystal injection step.

First, a manufacturing process of a thin film transistor and an active matrix substrate will be described.

<Gate electrode formation process>
First, for example, a molybdenum film (thickness of about 150 nm) or the like is formed on the entire substrate of the insulating substrate 10a such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate by a sputtering method. Then, by performing photolithography, wet etching, and resist removal cleaning, the gate electrode 11aa and the auxiliary capacitor wiring 11b are formed on the insulating substrate 10a as shown in FIG. Note that the scanning wiring 11a and the signal wiring 16a are formed simultaneously with the formation of the gate electrode 11aa and the auxiliary capacitance wiring 11b.

In the present embodiment, the molybdenum film having a single-layer structure is exemplified as the metal film constituting the gate electrode 11aa. For example, a metal such as an aluminum film, a tungsten film, a tantalum film, a chromium film, a titanium film, or a copper film is used. The gate electrode 11aa may be formed with a thickness of 50 nm to 300 nm using a film or a film made of such an alloy film or metal nitride.

Also, as a material for forming the plastic substrate, for example, polyethylene terephthalate resin, polyethylene naphthalate resin, polyether sulfone resin, acrylic resin, and polyimide resin can be used.

<Semiconductor layer formation process>
Subsequently, for example, a silicon nitride film (with a thickness of about 200 nm to 500 nm) is formed by CVD on the entire substrate on which the gate electrode 11aa and the auxiliary capacitance wiring 11b are formed, and as shown in FIG. A gate insulating layer 12 is formed so as to cover the gate electrode 11aa and the auxiliary capacitance line 11b.

Note that the gate insulating layer 12 may have a two-layer structure. In this case, for example, a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy, x> y), a silicon nitride oxide film (SiNxOy, x> y), or the like is used in addition to the above-described silicon nitride film (SiNx). be able to.

Further, from the viewpoint of preventing diffusion of impurities and the like from the insulating substrate 10a, a silicon nitride film or a silicon nitride oxide film is used as a lower gate insulating film, and a silicon oxide film, as an upper gate insulating film, Alternatively, a structure using a silicon oxynitride film is preferable.

For example, a silicon nitride film having a thickness of 100 nm to 200 nm is formed as a lower gate insulating film using SiH 4 and NH 3 as reaction gases, and N 2 O and SiH 4 are reacted as an upper gate insulating film. A silicon oxide film with a thickness of 50 nm to 100 nm can be formed as the gas.

Further, from the viewpoint of forming a dense gate insulating layer 12 with a low gate leakage current at a low film formation temperature, it is preferable to include a rare gas such as argon gas in the reaction gas and mix it in the insulating film.

Thereafter, for example, an IGZO-based oxide semiconductor film (with a thickness of about 30 nm to 100 nm) is formed by sputtering, and then the photolithography, wet etching, and resist removal cleaning are performed on the oxide semiconductor film. As a result, first to third oxide semiconductor layers 13a, 13b, and 13c are formed as shown in FIG.

<Channel protective film forming step (second insulating film forming step)>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, and 13c are formed by a plasma CVD method. Thereafter, photolithography, etching, and resist peeling cleaning are performed using the resist as a mask, thereby protecting the channel region Cb in the second channel region Cb of the second oxide semiconductor layer 13b as shown in FIG. A channel protective film 25 is formed to a thickness of about 50 to 100 nm. Similarly, a channel protective film 25 for protecting the channel region Cc is formed to a thickness of about 50 to 100 nm in the third channel region Cc of the third oxide semiconductor layer 13c.

For example, as the channel protective film 25, a silicon oxide film with a thickness of 100 nm to 200 nm can be formed using SiH 4 and N 2 O as reaction gases.

<Source drain formation process>
Further, for example, a titanium film (thickness 30 nm to 150 nm) and a copper film (thickness 30 nm to 150 nm) are formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, 13c and the channel protective film 25 are formed by sputtering. A film having a thickness of about 50 nm to 400 nm) is sequentially formed. Thereafter, the copper film is subjected to photolithography and wet etching, and the titanium film is dry-etched and resist is peeled and washed, so that the signal wiring 16a (see FIG. 3) is obtained. ), The source electrode 16aa and the drain electrode 16b are formed.

At this time, the first channel region Ca of the first oxide semiconductor layer 13a, the second channel region Cb of the second oxide semiconductor layer 13b covered with the channel protective film 25, and the channel protective film 25 are covered. The third channel region Cc of the third oxide semiconductor layer 13c thus formed is exposed.

Also, as shown in FIG. 8, in the second thin film transistor 5b, the source electrode 16aa and the drain electrode 16b are provided on the channel protective film 25 so as to face each other with the second channel region Cb interposed therebetween.

Similarly, as shown in FIG. 8, in the third thin film transistor 5c, the source electrode 16aa and the drain electrode 16b are provided on the channel protective film 25 so as to face each other across the third channel region Cc. It is done.

In this embodiment, as the metal film constituting the source electrode 16aa and the drain electrode 16b, a titanium film and a copper film having a laminated structure are exemplified. However, for example, a metal such as an aluminum film, a tungsten film, a tantalum film, or a chromium film is used. The source electrode 16aa and the drain electrode 16b may be formed by a film, or a film of an alloy film or metal nitride thereof.

In addition, as a conductive material, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), indium oxide (In 2 O 3 ), tin oxide (SnO 2) ), Zinc oxide (ZnO), titanium nitride (TiN), or the like may be used.

As the etching process, either dry etching or wet etching described above may be used. However, when processing a large area substrate, it is preferable to use dry etching. As an etching gas, a fluorine-based gas such as CF 4 , NF 3 , SF 6 , or CHF 3 , a chlorine-based gas such as Cl 2 , BCl 3 , SiCl 4 , or CCl 4 , an oxygen gas, or the like can be used. Alternatively, an inert gas such as argon may be added.

<Interlayer Insulating Film Forming Step (First Insulating Film Forming Step)>
Next, on the entire substrate on which the source electrode 16aa and the drain electrode 16b are formed (that is, the first to third thin film transistors 5a, 5b, and 5c are formed), for example, a silicon nitride film, an oxide film, or the like is formed by plasma CVD. A silicon film, a silicon nitride oxide film, or the like is formed, and covers the first to third thin film transistors 5a, 5b, and 5c as shown in FIG. 9 (that is, the first to third oxide semiconductor layers 13a and 13b). , 13c, covering the source electrode 16aa, the drain electrode 16b, and the channel protective film 25), the interlayer insulating film 17 is formed to a thickness of about 200 to 300 nm.

In this embodiment, as the interlayer insulating film 17, a silicon oxide film having a thickness of 200 nm to 300 nm is formed by, for example, plasma CVD using TEOS (TetraTeEthyl Ortho Silicate) as a source gas. be able to.

Next, a resist mask is formed on the interlayer insulating film 17 by a photolithography process, and as shown in FIG. 9, the contact hole C is etched, and the entire surface of the substrate is heat-treated.

Here, the mechanism by which the threshold voltage of the thin film transistor changes due to the insulating film structure in contact with the oxide semiconductor layer will be described.

Generally, the semiconductor characteristics of a thin film transistor including an oxide semiconductor layer are extremely sensitively influenced by the oxygen vacancy concentration in the oxide semiconductor layer. Even after the oxide semiconductor layer is formed, the oxygen vacancy concentration in the oxide semiconductor layer increases or decreases due to the influence of surrounding moisture and oxygen.

As in this embodiment, in the case of an insulating film structure in which a protective insulating film (channel protective film) is provided over an oxide semiconductor layer, the film quality of the protective insulating film greatly affects the characteristics of the thin film transistor.

For example, as in the present embodiment, when a silicon oxide film having a film thickness of 100 nm to 200 nm is formed as a channel protective film 25 using SiH 4 and N 2 O as a reaction gas, the ratio (flow rate) of N 2 O is large. Since the oxygen concentration increases, the oxidation effect on the second oxide semiconductor layer 13b increases, and the proportion of SiH 4 decreases, so that the hydrogen concentration decreases and the second oxide semiconductor layer 13b is formed. The reduction effect of becomes smaller.

Then, 13, as in the Ids-Vg characteristics showing the relationship between the drain-source current (Ids) and the gate voltage (Vg), lowering the current value (i.e., a shift in the direction of arrow X 1 in FIG. ) to, together with the leakage current decreases, the threshold voltage Vth is increased (i.e., shifted in the direction of arrow Y 1 in the figure) will be.

Accordingly, the second thin film transistor 5b including the second oxide semiconductor layer 13b in which the channel protective film 25 is provided in the second channel region Cb can be used as an enhancement type thin film transistor having a high threshold voltage Vth. Become.

Further, according to the same principle, the third thin film transistor 5c including the third oxide semiconductor layer 13c in which the channel protective film 25 is provided in the third channel region Cc is enhanced with a high threshold voltage Vth and a low leakage current. It can be used as a thin film transistor.

Note that when the ratio (flow rate) of N 2 O is small, the oxygen concentration is decreased, so that the oxidation effect on the second oxide semiconductor layer 13b is reduced and the ratio of SiH 4 is increased, so that the hydrogen concentration is increased. As a result, the reduction effect on the second oxide semiconductor layer 13b is increased.

Then, 14, as shown in Ids-Vg characteristics showing the relationship between the drain-source current (Ids) and the gate voltage (Vg), the current value is increased (i.e., the direction of the arrow X 2 in FIG. while shifting), the threshold voltage Vth is lowered (i.e., shifted in the direction of the arrow Y 2 in the figure) will be.

<Planarization film formation process>
Next, a photosensitive organic insulating film made of photosensitive acrylic resin or the like is formed to a thickness of about 1.0 μm to 3.0 μm on the entire substrate on which the interlayer insulating film 17 is formed by spin coating or slit coating. By applying, a planarizing film 18 is formed on the surface of the interlayer insulating film 17 as shown in FIG.

<Opening step>
Next, by performing exposure and development on the planarizing film 18, a contact hole C reaching the drain electrode 16b is formed in the planarizing film 18, as shown in FIG.

<Pixel electrode formation process>
Next, a transparent conductive film such as, for example, an ITO film (thickness of about 50 nm to 200 nm) made of indium tin oxide is formed on the entire substrate on which the interlayer insulating film 17 and the planarizing film 18 are formed by sputtering. . Thereafter, the transparent conductive film is subjected to photolithography, wet etching, and resist peeling and cleaning, so that the pixel electrode 19a, the gate terminal 19b (see FIG. 3), and the source terminal 19c (see FIG. 3), as shown in FIG. (See FIG. 3).

At this time, as shown in FIG. 4, the pixel electrode 19a is formed on the surface of the planarizing film 18 and the interlayer insulating film 17 so as to cover the surface of the contact hole C.

In the case of forming the transmissive liquid crystal display device 50, the pixel electrode 19a is made of indium oxide or indium zinc oxide (IZO) containing tungsten oxide, indium oxide or indium tin oxide (ITO) containing titanium oxide. ) Etc. can be used. In addition to the above-mentioned indium zinc oxide and indium tin oxide, indium tin oxide containing silicon oxide (ITSO) can also be used.

Further, when the reflective liquid crystal display device 50 is formed, the conductive thin film is made of titanium, tungsten, nickel, gold, platinum, silver, aluminum, magnesium, calcium, lithium, or an alloy thereof. A film can be used, and this metal thin film can be used as the pixel electrode 19a.

As described above, the active matrix substrate 20a shown in FIG. 4 can be manufactured.

<Opposite substrate manufacturing process>
First, by applying, for example, a photosensitive resin colored in black to the entire substrate of the insulating substrate 10b such as a glass substrate by spin coating or slit coating, the coating film is exposed and developed. As shown in FIG. 12A, the black matrix 21 is formed to a thickness of about 1.0 μm.

Next, for example, a photosensitive resin colored in red, green, or blue is applied to the entire substrate on which the black matrix 21 is formed by spin coating or slit coating. Thereafter, the coating film is exposed and developed to form a colored layer 22 (for example, a red layer) of a selected color with a thickness of about 2.0 μm as shown in FIG. The same process is repeated for the other two colors to form the other two colored layers 22 (for example, a green layer and a blue layer) with a thickness of about 2.0 μm.

Further, by depositing, for example, a transparent conductive film such as an ITO film on the substrate on which the colored layer 22 of each color is formed by sputtering, the common electrode 23 has a thickness as shown in FIG. It is formed to have a thickness of about 50 nm to 200 nm.

Finally, after the photosensitive resin is applied to the entire substrate on which the common electrode 23 is formed by spin coating or slit coating, the coating film is exposed and developed, as shown in FIG. 12C. The photo spacer 24 is formed to a thickness of about 4 μm.

The counter substrate 30 can be manufactured as described above.

<Liquid crystal injection process>
First, a polyimide resin film is applied to each surface of the active matrix substrate 20a manufactured in the active matrix substrate manufacturing process and the counter substrate 30 manufactured in the counter substrate manufacturing process by a printing method, and then the coating film is applied. On the other hand, an alignment film is formed by performing baking and rubbing treatment.

Next, for example, after a sealing material 35 made of UV (ultraviolet) curing and thermosetting resin is printed on the surface of the counter substrate 30 on which the alignment film is formed in a frame shape, a liquid crystal material is formed inside the sealing material. Is dripped.

Furthermore, after the counter substrate 30 onto which the liquid crystal material is dropped and the active matrix substrate 20a on which the alignment film is formed are bonded together under reduced pressure, the bonded bonded body is released to atmospheric pressure. The surface and the back surface of the bonded body are pressurized.

And after irradiating UV light to the sealing material 35 pinched | interposed into the said bonding body, the sealing material 35 is hardened by heating the bonding body.

Finally, the unnecessary part is removed by dividing the bonded body in which the sealing material 35 is cured, for example, by dicing.

As described above, the liquid crystal display device 50 of the present embodiment can be manufactured.

According to the present embodiment described above, the following effects can be obtained.

(1) In the present embodiment, the second channel region of the second oxide semiconductor layer 13b is between the second oxide semiconductor layer 13b and the interlayer insulating film 17 that is the first insulating film. A channel protective film 25 that is a second insulating film formed of a material different from that of the interlayer insulating film 17 is provided on Cb. Therefore, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second channel region Cb of the second oxide semiconductor layer 13b in the second thin film transistor 5b. It is possible to vary the insulating film structure in. Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. As a result, an active matrix substrate 20a including a thin film transistor (that is, an E / D inverter) including a first thin film transistor 5a and a second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.

(2) In addition, a high-quality device capable of high current driving and low voltage driving can be realized, and for example, high-functional circuits such as a pixel memory circuit, a photosensor circuit, and an OLED driving circuit can be realized.

(3) In this embodiment, the channel protective film 25 that protects the channel region Cb is provided in the second channel region Cb of the second oxide semiconductor layer 13b. Therefore, in the step of forming the source electrode 16aa and the drain electrode 16b, when the source electrode 16aa and the drain electrode 16b are formed by patterning by etching, the second channel region Cb of the second oxide semiconductor layer 13b is formed. Can be protected from being etched.

(4) In this embodiment, the first and second oxide semiconductor layers 13a and 13b are used as the semiconductor layers. Accordingly, it is possible to form a thin film transistor that has a higher electron mobility and can be processed at a lower temperature than a thin film transistor using amorphous silicon as a semiconductor layer.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 15 is a cross-sectional view of an active matrix substrate including a thin film transistor according to the second embodiment of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The overall configuration and the manufacturing method of the liquid crystal display device are the same as those described in the first embodiment, and thus detailed description thereof is omitted here.

In the present embodiment, as shown in FIG. 15, another interlayer insulating film (hereinafter referred to as “interlayer insulating film”) 28 is provided as the second insulating film instead of the channel protective film 25 described above. There is a feature in that.

More specifically, as shown in FIG. 15, an interlayer insulating film 17 is formed in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a that functions as an active element of the drive circuit. The interlayer insulating film 28 is provided, but the interlayer insulating film 28 is not provided, and the interlayer insulating film 28 is provided in the second channel region Cb of the second oxide semiconductor layer 13b in the second thin film transistor 5b. There is a feature.

With such a configuration, the insulating film structure in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a and the second thin film transistor, as in the case of the first embodiment described above. The insulating film structure in the second channel region Cb of the second oxide semiconductor layer 13b in 5b can be made different.

Therefore, the threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different, and the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large. Therefore, an active matrix substrate including a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.

In the present embodiment, as shown in FIG. 15, the second thin film transistor is also provided in the third channel region Cc of the third oxide semiconductor layer 13c in the third thin film transistor 5c functioning as a switching element of the pixel. Similar to 5b, an interlayer insulating film 28 which is a second insulating film for protecting the channel region Cc is provided.

Next, an example of a method for manufacturing the liquid crystal display device of the present embodiment will be described with reference to FIG. FIG. 16 is an explanatory view showing the manufacturing process of the thin film transistor and the active matrix substrate in cross section.

First, in the thin film transistor and active matrix substrate manufacturing process, the gate electrode forming process and the semiconductor layer forming process are performed as in FIGS. 5 and 6 described in the first embodiment.

<Source drain formation process>
Next, for example, a titanium film (thickness of 30 nm to 150 nm) and a copper film (thickness of about 50 nm to 400 nm) are formed on the entire substrate on which the first to third oxide semiconductor layers 13a, 13b, and 13c are formed by sputtering. ) Etc. in order. Thereafter, the copper film is subjected to photolithography and wet etching, and the titanium film is dry-etched and the resist is peeled and washed, so that the signal wiring 16a (see FIG. 3) is obtained. ), The source electrode 16aa and the drain electrode 16b are formed. At this time, the first channel region Ca of the first oxide semiconductor layer 13a, the second channel region Cb of the second oxide semiconductor layer 13b, and the third channel region of the third oxide semiconductor layer 13c. Cc is exposed.

Further, as shown in FIG. 16, in the second thin film transistor 5b, the source electrode 16aa and the drain electrode 16b are opposed to each other on the second oxide semiconductor layer 13b with the second channel region Cb interposed therebetween. Provided.

Similarly, as shown in FIG. 16, in the third thin film transistor 5c, the source electrode 16aa and the drain electrode 16b are opposed to each other on the third oxide semiconductor layer 13c with the third channel region Cc interposed therebetween. To be provided.

<Interlayer Insulating Film Forming Step (Second Insulating Film Forming Step)>
Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the second and third thin film transistors 5b and 5c are formed by plasma CVD, and is selectively etched. As shown in FIG. 16, the second and third thin film transistors 5b and 5c are covered by patterning (that is, the second and third oxide semiconductor layers 13b and 13c, the source electrode 16aa, and the drain electrode 16b are covered). A cover) interlayer insulating film 28 is formed to a thickness of about 200 to 300 nm.

At this time, in this embodiment, as shown in FIG. 16, the source is arranged so as to face each other with the second channel region Cb interposed between the second oxide semiconductor layer 13b and the interlayer insulating film 28. An electrode 16aa and a drain electrode 16b are provided.

<Interlayer Insulating Film Forming Step (First Insulating Film Forming Step)>
Next, as in FIG. 9 described above, for example, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed on the entire substrate on which the first to third thin film transistors 5a, 5b, and 5c are formed by plasma CVD. Etc. to cover the first to third thin film transistors 5a, 5b, 5c (that is, the first to third oxide semiconductor layers 13a, 13b, 13c, the source electrode 16aa, the drain electrode 16b, and the interlayer insulation) An interlayer insulating film 17 (covering the film 28) is formed to a thickness of about 200 to 300 nm.

Next, similarly to FIG. 9 described above, a resist mask is formed on the interlayer insulating film 17 by a photolithography process, etching for the contact hole C is performed, and heat treatment is performed on the entire surface of the substrate.

In the present embodiment, as the other interlayer insulating film 28, for example, a silicon oxide film having a thickness of 200 nm to 300 nm can be formed using N 2 O and SiH 4 .

Next, similarly to FIGS. 10 and 11 described in the first embodiment, the planarization film forming step, the opening forming step, and the pixel electrode forming step are performed, whereby the active matrix substrate 20a shown in FIG. Can be produced.

Further, the liquid crystal display device 50 of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.

According to the present embodiment described above, the same effects as the effects (1) to (4) described above can be obtained.

Note that the above embodiment may be modified as follows.

In the above embodiment, an oxide semiconductor layer is used as the semiconductor layer. However, the semiconductor layer is not limited to this. For example, a silicon-based semiconductor layer made of amorphous silicon or polysilicon is used as a thin film transistor instead of the oxide semiconductor layer. The semiconductor layer may be used as a semiconductor layer.

In the above embodiment, an oxide semiconductor layer made of an In—Ga—Zn—O-based metal oxide is used as the oxide semiconductor layer. However, the oxide semiconductor layer is not limited to this, and indium (In ), Gallium (Ga), aluminum (Al), copper (Cu), zinc (Zn), magnesium (Mg), and cadmium (Cd), a material made of a metal oxide containing at least one kind may be used.

Since the oxide semiconductor layer 13a made of these materials has high mobility even if it is amorphous, the on-resistance of the switching element can be increased. Therefore, the difference in output voltage at the time of data reading becomes large, and the S / N ratio can be improved.

For example, in addition to IGZO (In—Ga—Zn—O), oxide semiconductor films such as InGaO 3 (ZnO) 5 , Mg x Zn 1-x O, Cd x Zn 1-x O, and CdO can be given. it can.

In addition, an amorphous state, a polycrystalline state, or a non-crystalline state of ZnO to which one or more kinds of impurity elements of Group 1 element, Group 13 element, Group 14 element, Group 15 element, or Group 17 element are added. It is also possible to use a microcrystalline state in which a crystalline state and a polycrystalline state are mixed, or a material to which the above impurities are not added.

Further, the thickness of the interlayer insulating film 17 may be different without providing the channel protective film 25 and the interlayer insulating film 28 described above. More specifically, as shown in FIG. 17, the thickness T 1 of the interlayer insulating film 17 in the first channel region Ca of the first oxide semiconductor layer 13a in the first thin film transistor 5a, and the second thin film transistor 5b. in (in FIG. 17, T 2> T 1) of the second thickness T 2 of the interlayer insulating film 17 in the channel region Cb is different of the second oxide semiconductor layer 13b may be configured.

In this case, in the liquid crystal display device 50 in which the bottom-gate thin film transistor is incorporated, moisture and ions (positive ions) in the liquid crystal layer 40 that is an electro-optical material are attracted by the potential of the gate electrode 11aa, It stays as a positive charge at the interface between the planarizing film 18 and the upper liquid crystal layer 40. Further, the moisture and ions diffuse downward in the planarization film 18, and charge (positive charge) is generated at the interface between the interlayer insulating film 17 and the planarization film 18.

Then, a back channel is formed in the channel region of the thin film transistor due to this charge, and the threshold voltage of the thin film transistor varies. As described above, in the first channel region Ca of the first oxide semiconductor layer 13a. the thickness T 1 of the interlayer insulating film 17, a second for the thickness T 2 of the interlayer insulating film 17 in the channel region Cb are different, the first channel region Ca and the second channel region of the second oxide semiconductor layer 13b In Cb, the charges generated at the interface between the interlayer insulating film 17 and the planarizing film 18 are different.

Accordingly, since the amount of variation in the threshold voltage of the first thin film transistor 5a is different from the amount of variation in the threshold voltage of the second thin film transistor 5b, the same as in the case where the channel protective film 25 and the interlayer insulating film 28 are provided. The threshold voltages of the first thin film transistor 5a and the second thin film transistor 5b can be made different. As a result, the difference between the threshold voltages of the two thin film transistors 5a and 5b can be made sufficiently large.

As a result, an active matrix substrate 20a having a thin film transistor (that is, an E / D inverter) including the first thin film transistor 5a and the second thin film transistor 5b having different threshold voltages can be manufactured with a simple configuration.

Also, a high-quality device capable of high current drive and low voltage drive can be realized, and for example, high-functional circuits such as a pixel memory circuit, a photo sensor circuit, and an OLED drive circuit can be realized.

In this case, in the thin film transistor and active matrix substrate manufacturing process, first, the gate electrode forming process, the semiconductor layer forming process, and the source / drain forming process are performed as in the second embodiment.

Next, for example, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or the like is formed on the surface of the substrate on which the first to third thin film transistors 5a, 5b, and 5c are formed by plasma CVD, and is etched. By selectively patterning, as shown in FIG. 17, the first to third thin film transistors 5a, 5b and 5c are covered (that is, the first to third oxide semiconductor layers 13a, 13b and 13c, the source electrode). An interlayer insulating film 17 is formed to cover 16aa and the drain electrode 16b.

At this time, as shown in FIG. 17, the first channel region Ca and the second channel region Cb, so that the thickness T 2 between the thickness T 1 in the second channel region Cb in the first channel region Ca is different Then, an interlayer insulating film 17 is formed.

In this case, as shown in FIG. 17, the thickness of the interlayer insulating film 17 in the third channel region Cc of the third oxide semiconductor layer 13c included in the third thin film transistor 5c functioning as a pixel switching element is The thickness is set to be the same as the thickness of the interlayer insulating film 17 in the second channel region Cb of the second oxide semiconductor layer 13b (that is, T 2 ).

Next, similarly to FIG. 9 described above, a resist mask is formed on the interlayer insulating film 17 by a photolithography process, etching for the contact hole C is performed, and heat treatment is performed on the entire surface of the substrate.

Next, as in FIGS. 10 and 11 described in the first embodiment, the planarization film forming step, the opening portion forming step, and the pixel electrode forming step are performed, whereby the active matrix substrate 20a shown in FIG. Can be produced.

Further, the liquid crystal display device 50 of the present embodiment can be manufactured by performing the counter substrate manufacturing process and the liquid crystal injection process described in the first embodiment.

Examples of utilization of the present invention include a thin film transistor substrate using an oxide semiconductor layer, a method for manufacturing the same, and a display device.

DESCRIPTION OF SYMBOLS 5 Thin-film transistor 5a 1st thin-film transistor 5b 2nd thin-film transistor 5c 3rd thin-film transistor 10a Insulating substrate 11aa Gate electrode 12 Gate insulating layer 13a 1st oxide semiconductor layer (1st semiconductor layer)
13b Second oxide semiconductor layer (second semiconductor layer)
13c Third oxide semiconductor layer 16aa Source electrode 16b Drain electrode 17 Interlayer insulating film (first insulating film)
18 Planarizing film 19a Pixel electrode 20a Active matrix substrate (thin film transistor substrate)
25 channel protective film (second insulating film)
28 Other interlayer insulating film (second insulating film)
30 Counter substrate 40 Liquid crystal layer (display medium layer)
50 Liquid crystal display device Ca First channel region Cb Second channel region Cc Third channel region T 1 Thickness of interlayer insulating film in first channel region T 2 Thickness of interlayer insulating film in second channel region

Claims (14)

  1. An insulating substrate;
    A first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region;
    A second thin film transistor provided on the insulating substrate and including a second semiconductor layer having a second channel region;
    A thin film transistor substrate comprising: the first semiconductor layer; and a first insulating film covering the second semiconductor layer,
    A second semiconductor layer formed between the second semiconductor layer and the first insulating film, in the second channel region of the second semiconductor layer, using a material different from that of the first insulating film; A thin film transistor substrate provided with an insulating film.
  2. 2. The thin film transistor substrate according to claim 1, wherein the second insulating film is a channel protective film for protecting the second channel region.
  3. The first insulating film is a silicon oxide film made of TEOS (Tetra Ethyl Ortho Silicate), and the second insulating film is a silicon oxide film made of N 2 O and SiH 4. The thin film transistor substrate according to claim 2, wherein the thin film transistor substrate is a thin film transistor substrate.
  4. The source electrode and the drain electrode further provided on the second insulating film so as to face each other across the second channel region. 2. The thin film transistor substrate according to claim 1.
  5. A source electrode and a drain electrode are further provided between the second semiconductor layer and the second insulating film so as to face each other with the second channel region interposed therebetween. The thin film transistor substrate according to claim 1.
  6. An insulating substrate;
    A first thin film transistor provided on the insulating substrate and including a first semiconductor layer having a first channel region;
    A second thin film transistor provided on the insulating substrate and including a second semiconductor layer having a second channel region;
    A thin film transistor substrate comprising: an insulating film covering the first semiconductor layer and the second semiconductor layer;
    A thin film transistor substrate, wherein the thickness of the insulating film in the first channel region of the first semiconductor layer is different from the thickness of the insulating film in the second channel region of the second semiconductor layer.
  7. 7. The thin film transistor substrate according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are oxide semiconductor layers.
  8. The oxide semiconductor layer is made of a metal oxide including at least one selected from the group consisting of indium (In), gallium (Ga), aluminum (Al), copper (Cu), and zinc (Zn). The thin film transistor substrate according to claim 7.
  9. The thin film transistor substrate according to claim 8, wherein the oxide semiconductor layer is made of an In-Ga-Zn-O-based metal oxide.
  10. The thin film transistor substrate according to any one of claims 1 to 6, wherein the semiconductor layer is a silicon-based semiconductor layer.
  11. The thin film transistor substrate according to any one of claims 1 to 10,
    A counter substrate disposed to face the thin film transistor substrate;
    And a display medium layer provided between the thin film transistor substrate and the counter substrate.
  12. The display device according to claim 11, wherein the display medium layer is a liquid crystal layer.
  13. A first thin film transistor provided with an insulating substrate, a first semiconductor layer provided on the insulating substrate and having a first channel region; and a second thin film transistor provided on the insulating substrate and having a second channel region. A method of manufacturing a thin film transistor substrate comprising: a second thin film transistor including a semiconductor layer; the first semiconductor layer; and a first insulating film covering the second semiconductor layer,
    A semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer on the insulating substrate;
    A second insulating film forming step of forming a second insulating film made of a material different from that of the first insulating film in the second channel region;
    And a first insulating film forming step of forming the first insulating film so as to cover the first semiconductor layer, the second semiconductor layer, and the second insulating film. A method for manufacturing a thin film transistor substrate.
  14. A first thin film transistor provided with an insulating substrate, a first semiconductor layer provided on the insulating substrate and having a first channel region; and a second thin film transistor provided on the insulating substrate and having a second channel region. A method of manufacturing a thin film transistor substrate comprising: a second thin film transistor including a semiconductor layer; and an insulating film covering the first semiconductor layer and the second semiconductor layer,
    A semiconductor layer forming step of forming the first semiconductor layer and the second semiconductor layer on the insulating substrate;
    An insulating film forming step for forming the insulating film in the first channel region and the second channel region in which the thickness in the first channel region and the thickness in the second channel region are different from each other. A method of manufacturing a thin film transistor substrate, characterized in that:
PCT/JP2011/000103 2010-04-16 2011-01-12 Thin film transistor substrate, method for producing same, and display device WO2011129037A1 (en)

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