JP2010283060A - Display apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor with improved mobility characteristics and characteristics stability, and a high-performance display apparatus using the same. <P>SOLUTION: This display apparatus has a thin film transistor, which is equipped with a gate electrode 2, a gate insulating film 3, semiconductor film 4 and a pair of electrodes that function as a source electrode 6 and a drain electrode 7 on a substrate. At least part of the source electrode and the drain electrode are located on the opposite side of the gate insulating film on both sides of the semiconductor film. The semiconductor film is composed of a lamination layer containing a microcrystal Si film of 1 to 8 nm thickness and an amorphous Si film located on the opposite side of the gate insulating film side of the microcrystal Si film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device and a manufacturing technique thereof, and more particularly to a display device having a thin film transistor and a manufacturing technique thereof.

  Thin film transistors are applied to many devices as switching elements. For example, it is incorporated in a liquid crystal display device or an organic EL (Electro Luminescence) display device that drives pixels arranged in a matrix. In recent years, in order to realize such low power consumption, high contrast ratio, and low cost, such display devices are required to be developed such as high performance and miniaturization of a thin film transistor and simplification of a manufacturing process.

  A thin film transistor has a semiconductor film in which a channel is formed, and an amorphous Si film is mainly used as the semiconductor film from the viewpoint of easy process and easy handling of a large area. However, a thin film transistor using an amorphous Si film has low carrier mobility and poor characteristic stability, so that it is suitable for peripheral circuits of liquid crystal display devices and organic EL display driving that requires a relatively large amount of current. Has become difficult to apply.

  On the other hand, a thin film transistor to which a low-temperature poly-Si film formed by applying a laser annealing method is applied for driving a small and medium-sized liquid crystal display device or an organic EL display device with a built-in peripheral circuit. However, it is difficult to form a low-temperature poly-Si film to which laser annealing is applied on a large substrate from the viewpoint of ensuring uniformity. In addition, the thin film transistor forming process to which the low-temperature poly-Si film is applied has a larger number of steps and the cost reduction is difficult as compared with the amorphous Si thin film transistor process.

  By the way, the mobility of a thin film transistor applied to some peripheral circuits such as a gate drive shift register of a liquid crystal display device or a thin film transistor applied to an organic EL drive does not need to be as high as that of low-temperature poly-Si. Therefore, recently, studies are being made to apply a thin film transistor using a microcrystalline Si film that can be formed in a large area to these drives. The mobility of the microcrystalline Si thin film transistor is higher than that of the a-Si thin film transistor, and the characteristic stability is also excellent. For this reason, by applying this thin film transistor to a liquid crystal display device or an organic EL display device, a large-screen display device can be provided at low cost.

  In a thin film transistor using microcrystalline Si, a structure in which a semiconductor film in which microcrystalline Si and amorphous Si are stacked is applied from the viewpoint of improving productivity. Prior art documents related to these technologies include the following.

JP 2004-304140 A JP-A-60-98680

  Patent Document 1 discloses a thin film transistor to which a semiconductor film in which a microcrystalline Si film having a thickness of 10 nm or more and an amorphous Si film are stacked is applied. Since the microcrystalline Si film has a lower deposition rate than the amorphous Si film, a structure is proposed in which the microcrystalline Si film is formed only in the vicinity of the channel region on the gate insulating film and then amorphous Si is stacked. In these thin film transistors, in a region where the drain voltage is relatively high, a high TFT mobility is shown as compared with an amorphous Si thin film transistor.

  However, in the region where the drain voltage (Vd) is as low as 0.1 V, the mobility characteristic is degraded. When this thin film transistor is applied to a liquid crystal pixel writing or voltage writing thin film transistor, there arises a problem that it becomes impossible to write up to a predetermined voltage.

  On the other hand, Patent Document 2 discloses a configuration in which a contact film is brought into direct contact with microcrystalline Si, and amorphous Si is laminated thereon. In this case, since carriers can be directly injected into the microcrystalline Si, TFT mobility in a low drain voltage region can be secured. However, in the configuration disclosed in FIG. 2 of Patent Document 2, it is difficult to obtain uniform characteristics because the selection ratio with respect to the microcrystalline Si film is small when etching the n + amorphous Si of the contact film. Become. Further, it is necessary to process amorphous Si formed on microcrystalline Si, which increases the number of processes.

  Further, in the configuration disclosed in FIG. 3 of Patent Document 2, the number of steps is increased because the gate insulating film is formed, the source electrode and the drain electrode are formed, and then the microcrystalline Si film is formed. To do. In addition, since the source electrode and the drain electrode are formed between the gate insulating film and the microcrystalline Si film, the interface between the gate insulating film and the microcrystalline Si is easily contaminated, and the characteristics are uniform. Problems arise in stability of characteristics.

  Accordingly, an object of the present invention is to provide a microcrystalline Si thin film transistor with excellent characteristics and a display device with excellent display characteristics by a simple process.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

(1) A gate electrode, a gate insulating film, a semiconductor film, and a pair of electrodes functioning as a source electrode and a drain electrode, and at least part of the source electrode and the drain electrode sandwich the semiconductor film A display device having a thin film transistor located on the opposite side of the gate insulating film,
The semiconductor film is composed of a stack including a microcrystalline Si film having a thickness of 1 to 8 nm and an amorphous Si film located on the opposite side of the microcrystalline Si film from the gate insulating film side. And

(2) A gate electrode, a gate insulating film, a semiconductor film, and a pair of electrodes functioning as a source electrode and a drain electrode are provided, and at least a part of the source electrode and the drain electrode sandwich the semiconductor film therebetween. A method of manufacturing a display device having a thin film transistor positioned on the opposite side of a gate insulating film,
Forming the semiconductor film comprising a stack including a microcrystalline Si film having a thickness of 1 to 8 nm and an amorphous Si film located on the opposite side of the microcrystalline Si film from the gate insulating film side. Have
The microcrystalline Si film and the amorphous Si film are continuously formed by a vacuum part process.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  By forming a microcrystalline Si film with a thickness of 1-8 nm according to the present invention, a band offset generated at the interface between microcrystalline Si and amorphous Si can be pushed into the channel region, which is as low as 0.1 V. Even when the drain voltage is used, the carrier travelability is improved.

  Further, by forming the microcrystalline Si film 8 in contact with the gate insulating film, a stable thin film transistor with less threshold shift can be formed.

  Further, in order to avoid contamination such as surface oxidation in a microcrystalline Si film having a thickness of 1-8 nm, a thin film transistor having excellent characteristic uniformity by continuously forming a microcrystalline Si film and an amorphous Si film. Can be formed. Further, the manufacturing process can be simplified and a thin film transistor can be manufactured at low cost.

  By applying the thin film transistor of the present invention to a display device such as a liquid crystal display device or an organic EL display device, a high-quality display device can be provided.

Sectional drawing which shows schematic structure of the conventional thin-film transistor. FIG. 2 is a diagram showing a band diagram in an A-A ′ portion of the thin film transistor of FIG. 1. 1 is a cross-sectional view illustrating a schematic configuration of an inverted staggered thin film transistor that is Embodiment 1 of the present invention. Sectional drawing which shows the manufacturing process of the reverse stagger type thin-film transistor which is Example 1 of this invention. FIG. 4 is a graph showing the relationship between the thickness of a microcrystalline Si film and TFT mobility in the thin film transistor of FIG. 3. FIG. 4 is a diagram showing the relationship between the thickness of a microcrystalline Si film and a threshold shift in the thin film transistor of FIG. 3. FIG. 4 is a diagram showing a band diagram in an A1-A1 ′ portion of the thin film transistor of FIG. 3. Sectional drawing which shows schematic structure of the positive stagger type | mold thin-film transistor which is Example 2 of this invention. Sectional drawing which shows the manufacturing process of the positive staggered thin-film transistor which is Example 2 of this invention. Sectional drawing which shows schematic structure of the liquid crystal display device which is Example 3 of this invention. Sectional drawing which shows schematic structure of the organic electroluminescence display which is Example 4 of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Example 1]
The structure and manufacturing method of the inverted staggered thin film transistor of this embodiment will be described with reference to FIGS. FIG. 3 is a cross-sectional view showing a schematic configuration (main components) of an inverted staggered thin film transistor that is Embodiment 1 of the present invention, and FIG. FIG. In Embodiment 1, an example in which the present invention is applied to an inverted staggered thin film transistor will be described.

  As shown in FIG. 3, the thin film transistor (TFT) Q1 of the first embodiment is an inverted stagger type, and is formed on a transparent insulating substrate 1 as a substrate, for example. The thin film transistor Q1 mainly covers the gate electrode 2 formed on the insulating substrate 1, the gate insulating film 3 formed on the insulating substrate 1 so as to cover the gate electrode 2, and the gate electrode 2. The semiconductor film 4 formed on the gate insulating film 3 is formed on the semiconductor film 4 so that at least a part of each of the semiconductor film 4 overlaps the semiconductor film 4 in a plane, and functions as the source electrode 6 and the drain electrode 7. And a contact film 5 formed between each of the source electrode 6 and the drain electrode 7 and the semiconductor film 4 and acting as an ohmic contact film. That is, the thin film transistor Q1 has a gate electrode 2, a gate insulating film 3, a semiconductor film 4, a contact film 5, a source electrode 6 and a drain electrode 7 stacked in order on the insulating substrate 1. It is configured.

  The semiconductor film 4 is formed of a laminated film including at least a microcrystalline Si film 8 and an amorphous Si film 9 located on the opposite side of the microcrystalline Si film 8 to the gate insulating film 3 side. The thickness of the microcrystalline Si film 8 is 1-8 nm, more preferably 3-8 nm, and the microcrystalline Si film 8 is disposed in contact with the gate insulating film 3 and the amorphous Si film 9. The thickness of the amorphous Si film 9 is 30-300 nm.

  The source electrode 6 and the drain electrode 7 are covered with a protective insulating film 10 formed on the insulating substrate 1. The source electrode 6 is electrically connected to the pixel electrode 12 formed on the protective insulating film 10 through the contact hole 11 formed in the protective insulating film 10.

Next, the manufacture of the thin film transistor Q1 having the above configuration will be described with reference to FIG.
First, a metal film is formed on the insulating substrate 1 by a sputtering method or the like. Then, the gate electrode 2 is formed on the insulating substrate 1 by patterning the metal film by applying photolithography.

Next, the gate insulating film 3, the semiconductor film 4, and the contact film 5 are continuously formed using a film forming method such as PECVD. Examples of the gate insulating film 3 include a SiN (silicon nitride) film and a SiO ₂ (silicon oxide) film. For forming the SiN film, a PECVD method or the like is applied, and SiH ₄ , NH ₃ , N ₂ or the like is used as a source gas. For forming the SiO ₂ film, SiH ₄ , N ₂ O, TEOS (Tetra Ethyl Ortho Silicate), or the like is used as a source gas. It is also possible to stack these films. Considering the threshold stability of TFT, stacked and SiN film in which the SiO ₂ film single layer or SiO ₂ film as an upper layer is preferable.

As the semiconductor film 4, a stack of a microcrystalline Si film 8 and an amorphous Si film 9 is applied. When the microcrystalline Si film 8 is formed by PECVD, SiH ₄ and H ₂ mixture, SiF ₄ and H ₂ mixture, SiH ₄ , SiF ₄ and H ₂ mixture, etc. are applied as source gases. it can. A rare gas such as Ar or He may be added to these gases. In particular, when SiF ₄ is used, F can be introduced into the film. The thickness of the microcrystalline Si film 8 is 1-8 nm, more preferably 3-8 nm. The microcrystalline Si film 8 is in contact with the gate insulating film 3 side of the amorphous Si film 9 and further in contact with the gate insulating film 3. Arrange.

Further, when the amorphous Si film 9 is formed by PECVD, the raw material gases include SiH ₄ and H ₂ mixture, SiF ₄ and H ₂ mixture, SiH ₄ and SiF ₄ and H ₂ mixture, etc. Is applicable. A rare gas such as Ar or He may be added to these gases. In this case, the amorphous Si film 9 can be formed by controlling the flow rate of SiH ₄ , SiF ₄ , H ₂ or a rare gas.

  In order to avoid contamination at the interface between the microcrystalline Si film 8 and the amorphous Si film 9, it is preferable to form these laminated films by a vacuum part process. In particular, when forming by PECVD, productivity can be improved because continuous film formation is possible by controlling the flow rate of the source gas. That is, the microcrystalline Si film 8 is preferably formed so as to be in contact with the gate insulating film 3 and the amorphous Si film 9.

Furthermore, a P-doped microcrystalline Si film or an amorphous Si film is used as the contact film 5, a source gas such as SiH ₄ or SiF ₄ , and a H ₂ or rare gas added with PH ₃ is used. It is formed by the PECVD method.

  Next, the semiconductor film 4 and the contact film 5 are processed into an island shape by applying a photolithography process. (See Fig. 4 (a))

Next, a metal film serving as a constituent portion of a pair of electrodes (source electrode 6 and drain electrode 7) functioning as a source electrode and a drain electrode is formed by sputtering or the like.
Thereafter, a photolithography process is applied, and the metal film is patterned to form the source electrode 6 and the drain electrode 7 as shown in FIG. Thereafter, the contact film 5 exposed from the source electrode 6 and the drain electrode 7 is selectively removed by etching or the like. At this time, since there is almost no etching selectivity between the contact film 5 and the amorphous Si film 9, it is necessary to set the amorphous Si film 9 to a thickness of 30 nm or more.

Next, a protective insulating film 10 is formed on the insulating substrate 1 by PECVD or the like so as to cover the source electrode 6 and the drain electrode 7. As the protective insulating film 10, it can be applied such as SiN or SiO _2. These films are formed by the PECVD method or the like as described above.
Thereafter, a photolithography process is applied to form a contact hole 11 or the like that enables electrical contact between the source electrode 6 and an external device. Further, after forming an electrode film made of a metal film or an oxide conductive film, a photolithography process is applied to pattern the electrode film to form the pixel electrode 12. The pixel electrode 12 is electrically connected to the source electrode 6 through the contact hole 11. The process so far is shown in FIG.

  According to this embodiment, the thin film transistor Q1 having good characteristics and excellent stability can be formed. Further, in the inverted staggered thin film transistor Q1 formed in this embodiment, light incident on the semiconductor film 4 from the substrate side can be shielded by the gate electrode 2, so that light leakage current can also be reduced.

Now, the present invention will be described in detail.
In the inverted staggered thin film transistor disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2004-304140), as shown in FIG. 1 (a cross-sectional view showing a schematic configuration of a conventional inverted staggered thin film transistor), a gate insulating film An interface between the microcrystalline Si film 8 and the amorphous Si film 9 exists in the carrier travel path between the channel region 24 and the drain electrode 7 at the interface. Since the band gap with the microcrystalline Si film 8 is smaller than that with the amorphous Si film 9, the band diagram of this portion (AA ′ portion in FIG. 1) is as shown in FIG. As can be seen from FIG. 2, a band offset occurs at the interface between the microcrystalline Si film 8 and the amorphous Si film 9, and the travel of the electron carriers is hindered. In particular, when the drain voltage is small, the gradient of the entire band diagram is small, so that the influence of this offset portion is large, and the mobility of the TFT is lowered.

  Therefore, in the present invention, by reducing the film thickness of the microcrystalline Si film 8, the interface between the microcrystalline Si film 8 and the amorphous Si film 9 is formed in the channel region 24, thereby reducing the low drain voltage region. The structure which improves the TFT mobility of was devised.

The relationship between the thickness of the microcrystalline Si film 8 in the thin film transistor Q1 of FIG. 3 and the characteristics of the thin film transistor Q1 was examined. FIG. 5 shows the relationship between the thickness of the microcrystalline Si film 8 and the TFT mobility in the thin film transistor Q1 of FIG. FIG. 5 shows that the TFT mobility at Vd = 10 V shows a high value of 0.8 cm ² / Vs or higher. On the other hand, the TFT mobility at Vd = 0.1 V shows a maximum when the film thickness of the microcrystalline Si film 8 is 5 nm, and shows a minimum at 30 nm. It is desired that the TFT mobility is 0.5 cm ² / Vs or more for a gate-driven shift register or pixel liquid crystal drive. Therefore, it is necessary to set the film thickness of the microcrystalline Si film 8 to 8 nm or less.

  FIG. 6 shows the relationship between the thickness of the microcrystalline Si film 8 in the thin film transistor Q1 of FIG. 3 and the threshold shift after the stress voltage is applied. From FIG. 6, when the film thickness of the microcrystalline Si film 8 is 0 nm, a large threshold shift of about 7 V is shown, but this value is improved to 2 V by setting the film thickness of the microcrystalline Si film 8 to 1 nm. I understand that The thin film transistor Q1 can be applied to a gate drive circuit, a pixel drive, and the like. Further, when the thickness of the microcrystalline Si film 8 is 3 nm or more, the threshold shift is 0.5 V or less. This thin film transistor Q1 can also be applied to organic EL driving.

  To summarize the above results, the film thickness of the microcrystalline Si film 8 is set to 1-8 nm, more preferably 3-8 nm, so that the TFT mobility characteristic at a low drain voltage is good and the stability is excellent. It was found that a thin film transistor can be produced.

  FIG. 7 shows a band diagram in the A1-A1 ′ portion of the thin film transistor of FIG. In the thin film transistor Q1 of the present invention, as shown in FIG. 7, since the interface between the microcrystalline Si film 8 and the amorphous Si film 9 is formed in the channel, the barrier against electron carriers in the band offset portion is reduced. ing. For this reason, in the structure of this invention, the mobility of a low drain voltage area | region can be improved.

  The above description is about the inverted staggered thin film transistor Q1 shown in FIG. 3, but can also be applied to the forward staggered thin film transistor Q2 shown in FIG. Also in this configuration, the film thickness of the microcrystalline Si film 8 is preferably set to 1-8 nm, more preferably 3-8 nm.

  In the microcrystalline Si film 8, crystal grains are observed when the cross section is observed with a transmission electron microscope or the like. In particular, when the film thickness is thin, the crystal grains may be observed as being dispersed in the amorphous matrix. In this case, the thickness at which crystal grains are observed is the microcrystalline Si film thickness.

Moreover, by adding F element to the microcrystalline Si film 8, as disclosed in Appl. Phys. Lett. 90, 1922112 (2007), it is possible to control the Fermi level away from the conduction band. It is. Therefore, the band offset at the interface between the microcrystalline Si film 8 and the amorphous Si film 9 can be reduced, and the characteristics of the thin film transistors (Q1, Q2) can be improved. The F concentration is preferably set to 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ from the viewpoint of reducing the band offset and maintaining the crystallinity.

  The film thickness of the amorphous Si film 9 is preferably set to 30 nm or more from the viewpoint of securing the etching margin of the P-doped Si film as the contact film 5 and reducing the influence of the back channel. Moreover, it is preferable to set the thickness to 300 nm or less in order to reduce the cross-sectional resistance of the amorphous Si film.

As the gate insulating film 3, a SiO ₂ (silicon oxide) film, a SiN (silicon nitride) film, a SiO ₂ / SiN laminated film, or the like can be applied. In particular, in order to manufacture a thin film transistor with a small threshold shift, it is preferable to dispose a SiO ₂ film with a small charge injection in contact with the microcrystalline Si film 8.

As a method of forming the microcrystalline Si film 8 and the amorphous Si film 9, it is desirable that the microcrystalline Si film 8 and the amorphous Si film 9 are continuously formed by a vacuum part process in order to avoid contamination of the interface. In particular, in the film formation by PECVD (Plasma Enhanced Chemical Vapor Deposition) method, since continuous film formation can be easily performed by adjusting the flow rate of introduced gas, productivity can be improved. Further, it is possible to add F to the microcrystalline Si film 8 by applying SiF ₄ as a source gas when forming the microcrystalline Si film.

  The thin film transistors (Q1, Q2) of the present invention have high mobility and excellent threshold stability. Therefore, by applying this thin film transistor to a peripheral circuit of a liquid crystal display device, pixel drive, or organic EL display device drive, a high-quality display can be manufactured at low cost.

[Example 2]
The structure and manufacturing method of the positive staggered thin film transistor of this embodiment will be described with reference to FIGS. FIG. 8 is a cross-sectional view showing a schematic configuration (main components) of a positive staggered thin film transistor that is Embodiment 2 of the present invention, and FIG. FIG. In Embodiment 2, an example in which the present invention is applied to a positive staggered thin film transistor will be described.

  As shown in FIG. 8, a thin film transistor (TFT) Q2 according to the second embodiment is formed on a transparent insulating substrate 1 as a substrate, for example. The thin film transistor Q2 is of a positive stagger type, and mainly has a source electrode 6 and a drain electrode 7, a contact film 5 made of a Si film doped with P, a semiconductor film 4, and a gate insulating film on the insulating substrate 1. 3 and the gate electrode 2 are sequentially stacked. The gate insulating film 3 of this embodiment is formed of a laminate including an insulating film 3a formed on the semiconductor film 4 and an insulating film 3b formed so as to cover the insulating film 3a.

  The semiconductor film 4 is formed of a laminated film including at least a microcrystalline Si film 8 and an amorphous Si film 9 located on the opposite side of the microcrystalline Si film 8 from the gate insulating film 3 (3a, 3b) side. ing. The thickness of the microcrystalline Si film 8 is 1-8 nm, more preferably 3-8 nm, and the microcrystalline Si film 8 is disposed in contact with the gate insulating film 3 and the amorphous Si film 9. The thickness of the amorphous Si film 9 is 30-300 nm.

Next, the manufacture of the thin film transistor Q2 having the above configuration will be described with reference to FIG.
First, a metal film is formed on the insulating substrate 1 by a sputtering method or the like. Thereafter, a Si film doped with P is formed as the contact film 5 in the same manner as in the first embodiment. A source electrode 6 and a drain electrode 7 are formed on the insulating substrate 1 by patterning the laminate of the metal film and the contact film by applying photolithography.

  Next, after removing the oxide film on the surface of the contact film 5 with HF or the like, the semiconductor film 4 and the insulating film 3a are continuously formed by using a film forming method such as PECVD. As the semiconductor film 4, a stack of an amorphous Si film 9 and a microcrystalline Si film 8 is applied. The amorphous Si film 9 and the microcrystalline Si film 8 are formed by the same method as in the first embodiment. Further, the insulating film 3a is also formed by the same method as in the first embodiment. The thickness of the microcrystalline Si film 8 is 1-8 nm, more preferably 3-8 nm. The microcrystalline Si film 8 is disposed in contact with the insulating film 3 a and the amorphous Si film 9. Next, the insulating film 3a and the semiconductor film 4 are processed into an island shape by applying photolithography. (See Fig. 9 (a))

Next, the insulating film 3b is formed using PECVD or the like, and further a metal film is formed by sputtering or the like. By forming the insulating film 3b, the gate insulating film 3 composed of the insulating films 3a and 3b is formed.
Thereafter, a photolithography process is applied, and the metal film is patterned to form the gate electrode 2 as shown in FIG. 9B.

Next, a protective insulating film 10 is formed by PECVD or the like so as to cover the gate electrode 2. As the protective insulating film 10, a SiN (silicon nitride) film, a SiO ₂ (silicon oxide) film, or the like can be applied. These films are formed by the PECVD method or the like as described above.
Thereafter, a photolithography process is applied to form a contact hole 11 or the like that enables electrical contact between the source electrode 6 and an external device. Further, after forming an electrode film made of a metal film or an oxide conductive film, a photolithography process is applied, and the electrode film is patterned to form the pixel electrode 12. The pixel electrode 12 is electrically connected to the source electrode 6 through the contact hole 11. The process so far is shown in FIG.

  According to this embodiment, a positive staggered thin film transistor Q2 having good characteristics and excellent stability can be formed.

Example 3
In the liquid crystal display device of the embodiment shown here, a spacer is further formed on the insulating substrate having the thin film transistor manufactured in the above-described embodiment 1 or 2, and then the counter substrate is bonded to complete the liquid crystal. FIG. 10 shows a schematic configuration of the liquid crystal display device of this example. Note that FIG. 10 illustrates the inverted staggered thin film transistor Q1 illustrated in FIG. 3 as an example of the thin film transistor.

  A method for manufacturing the liquid crystal display device of this embodiment will be described below. After forming up to the pixel electrode 12 by the method described in Example 1 or 2, the spacer 14 is formed. As this forming method, there is a method in which a photosensitive resin is applied to a predetermined thickness and then exposed and developed. Next, the alignment film 15 is formed. Next, the counter substrate 16 is bonded together, and the liquid crystal 17 is sealed to complete the liquid crystal display device.

  The liquid crystal display device of this embodiment has a liquid crystal display panel in which a plurality of pixel regions each including a pixel electrode 12 and an active element electrically connected to the pixel electrode 12 are arranged in a matrix. The liquid crystal display panel has a configuration in which liquid crystal is sandwiched between an insulating substrate 1 (first substrate) and a counter substrate 16 (second substrate). 2 thin film transistors (Q1 or Q2).

  In the liquid crystal display device according to the present embodiment, the thin film transistors (Q1, Q2) of the first and second embodiments are used as active elements (thin film transistors) that form a pixel region together with the pixel electrode 12 and are electrically connected to the pixel electrode 12. By using it, the voltage writing characteristics of the thin film transistors (Q1, Q2) are good, so that an image excellent in color reproducibility can be displayed. Further, by applying the thin film transistors (Q1, Q2) of Embodiment 1 or 2 to the peripheral circuit of the liquid crystal display device, a high-definition display device can be manufactured.

Example 4
In the organic EL display device of the embodiment shown here, an organic EL light emitting element is formed by laminating a charge transport layer, a light emitting layer, and a charge transport layer on an insulating substrate having the thin film transistor manufactured in the above-described embodiment 1 or 2. . FIG. 11 shows a schematic configuration of the organic EL display device of this example. Note that FIG. 11 illustrates the inverted staggered thin film transistor Q1 illustrated in FIG. 3 as an example of the thin film transistor.

A method for manufacturing the organic EL display device of this example will be described below.
After forming the protective insulating film 10 by the method described in Example 1 or 2, the planarizing layer 18 is formed. The planarizing layer 18 is formed by applying a photosensitive resin and then opening the contact hole 11 by exposure and development. Next, the pixel electrode 12 is formed by the same method as in the first and second embodiments. Thereafter, the charge transport layer 19, the light emitting layer 20, and the charge transport layer 21 of the organic EL light emitting device are formed thereon by vapor deposition, and a transparent conductive film is formed as the upper electrode 22 by vapor deposition and sputtering, and a sealing film A SiN film was formed as Cat No. 23 using Cat-CVD to produce an organic EL display device.

  The organic EL display device of this example is an organic EL device in which a plurality of pixel regions each including an organic EL light emitting element and a switching element electrically connected to the pixel electrode 12 of the organic EL light emitting element are arranged in a matrix. In the EL display device, the switching element is the thin film transistor (Q1, Q2) of the first or second embodiment.

  In the organic EL display device of the present embodiment, the thin film transistor of the first or second embodiment is used as a switching element (thin film transistor) that forms a display area together with the organic EL light emitting element and the pixel electrode 12 and is electrically connected to the pixel electrode 12. By using (Q1, Q2), the high-brightness and good stability of the thin film transistor Q showed long life characteristics.

  As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Gate electrode 3 ... Gate insulating film 3a, 3b ... Insulating film 4 ... Semiconductor film 5 ... Contact film 6 ... Source electrode 7 ... Drain electrode 8 ... Microcrystalline Si film 9 ... Amorphous Si film 10 Protective insulating film 11 Contact hole 12 Pixel electrode 14 Spacer 15 Orientation film 16 Counter substrate 17 Liquid crystal 18 Flattening layer 19 Charge transport layer 20 Light emitting layer 21 Charge transport layer 22 Upper electrode 23 ... Sealing film 24 ... Channel region

Claims (13)

A gate electrode; a gate insulating film; a semiconductor film; and a pair of electrodes functioning as a source electrode and a drain electrode. At least a part of the source electrode and the drain electrode sandwich the semiconductor film, and the gate insulating film A display device having a thin film transistor located on the opposite side of
The semiconductor film is composed of a stack including a microcrystalline Si film having a thickness of 1 to 8 nm and an amorphous Si film located on the opposite side of the microcrystalline Si film from the gate insulating film side. A display device. The display device according to claim 1,
The display device, wherein the microcrystalline Si film is in contact with the gate insulating film and the amorphous Si film. The display device according to claim 1,
A display device, wherein the amorphous Si film has a thickness of 30-300 nm. The display device according to claim 1,
The display device, wherein the microcrystalline Si film contains an F element. The display device according to claim 4,
The display device, wherein the concentration of F element in the microcrystalline Si film is 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ . The display device according to claim 1,
The display device, wherein the gate insulating film includes at least a silicon oxide film. The display device according to claim 1,
The thin film transistor has an inverted staggered structure in which the gate electrode, the gate insulating film, the semiconductor film, the contact film, the source electrode, and the drain electrode are sequentially stacked on an insulating substrate. . The display device according to claim 1,
The thin film transistor has a positive stagger type structure in which the source and drain electrodes, the contact film, the semiconductor film, the gate electrode, and the gate insulating film are sequentially stacked on an insulating substrate. . The display device according to claim 1 is a liquid crystal display device having a liquid crystal display panel in which a plurality of pixel regions each including a pixel electrode and an active element electrically connected to the pixel electrode are arranged in a matrix. ,
The display device, wherein the thin film transistor is the active element. The display device according to claim 1 is an organic EL display in which a plurality of pixel regions each including an organic EL light emitting element and a switching element electrically connected to a pixel electrode of the organic EL light emitting element are arranged in a matrix. Device,
The display device, wherein the thin film transistor is the switching element. A gate electrode; a gate insulating film; a semiconductor film; and a pair of electrodes functioning as a source electrode and a drain electrode. At least a part of the source electrode and the drain electrode sandwich the semiconductor film, and the gate insulating film A method of manufacturing a display device having a thin film transistor located on the opposite side of
Forming the semiconductor film comprising a stack including a microcrystalline Si film having a thickness of 1 to 8 nm and an amorphous Si film located on the opposite side of the microcrystalline Si film from the gate insulating film side. Have
The method for manufacturing a display device, wherein the microcrystalline Si film and the amorphous Si film are continuously formed by a vacuum part process. In the manufacturing method of the display device according to claim 11,
The method for manufacturing a display device, wherein the microcrystalline Si film and the amorphous Si film are formed by a PECVD method. In the manufacturing method of the display device according to claim 12,
The method for manufacturing a display device, wherein the microcrystalline Si film is formed by PECVD using SiF ₄ gas.

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