CN115050840A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN115050840A CN115050840A CN202210863617.0A CN202210863617A CN115050840A CN 115050840 A CN115050840 A CN 115050840A CN 202210863617 A CN202210863617 A CN 202210863617A CN 115050840 A CN115050840 A CN 115050840A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
A semiconductor device and a method for manufacturing the same are provided. The first thin film transistor comprises a first grid electrode, a first stacked structure, a second grid electrode, a source electrode and a drain electrode. The first stacked structure includes a first metal oxide layer and a second metal oxide layer that overlap each other. The first stacked structure is located between the first gate and the second gate. The variable resistive memory includes a first electrode, a second stacked structure, and a second electrode. The first electrode is electrically connected with the first grid. The second stacked structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other. The second stacked structure is located between the first electrode and the second electrode and is connected with the first electrode and the second electrode.
Description
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same.
Background
Since the thin film transistor including the metal oxide semiconductor is susceptible to oxygen, hydrogen, and water in the environment, after long-term use, performance degradation is likely to occur, which affects the electrical properties of the thin film transistor. For example, in a display device including a thin film transistor array, if the performance of a part of the metal oxide semiconductor of the thin film transistor is degraded, the problem of non-uniformity (Mura) of the picture displayed by the display device is easily caused. In general, in order to reduce such a problem of non-uniformity, a pixel circuit is connected to an external chip, and a large amount of current information is stored through an external compensation memory. The current information is calculated by an algorithm to obtain a compensation current or voltage, and the compensation current or voltage is fed back to the pixel circuit. However, the circuit design of the external chip is complicated and costly.
Disclosure of Invention
The invention provides a semiconductor device, the variable resistive memory of which has excellent resistance switching performance.
The present invention provides a method for manufacturing a semiconductor device having a variable resistance memory with excellent resistance switching performance.
At least one embodiment of the present invention provides a semiconductor device. The semiconductor device comprises a substrate, a first thin film transistor and a variable resistance type memory. The first thin film transistor is disposed on the substrate and includes a first gate, a first stacked structure, a second gate, a source, and a drain. The first stacked structure includes a first metal oxide layer and a second metal oxide layer that overlap each other. The first stacked structure is located between the first gate and the second gate. The source and the drain are electrically connected with the first stacking structure. The variable resistive memory is disposed on the substrate and includes a first electrode, a second stacked structure, and a second electrode. The first electrode is electrically connected with the first grid. The second stacked structure includes a third metal oxide layer and a fourth metal oxide layer overlapping each other. The second stacked structure is located between the first electrode and the second electrode and is connected with the first electrode and the second electrode.
At least one embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a first gate and a first electrode on a substrate; forming a first gate dielectric layer on the first gate and the first electrode, the first gate dielectric layer having a first opening exposing the first electrode; forming a first stack structure and a second stack structure on the first gate dielectric layer, wherein the first stack structure includes a first metal oxide layer and a second metal oxide layer overlapped with each other, the second stack structure includes a third metal oxide layer and a fourth metal oxide layer overlapped with each other, and the third metal oxide layer is filled in the first opening; forming a second gate dielectric layer on the first stacked structure and the second stacked structure, the second gate dielectric layer having a second opening exposing the fourth metal oxide layer; forming a second gate and a second electrode on the second gate dielectric layer, wherein the first stacked structure is located between the first gate and the second gate, and the second electrode is filled in the second opening; and forming a source electrode and a drain electrode which are electrically connected with the first stacking structure.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 2A to 2H are schematic cross-sectional views illustrating a method of manufacturing the semiconductor device of fig. 1.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 5 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the invention.
Fig. 6 is a flowchart illustrating a pixel compensation operation of the display device in the pixel circuit configuration of fig. 5 according to an embodiment of the invention.
Description of reference numerals:
10A,10B, 10C: semiconductor device with a plurality of semiconductor chips
100: substrate
110: first gate dielectric layer
120: second gate dielectric layer
130: interlayer dielectric layer
2 DEG: two-dimensional electron gas
202: a first grid electrode
204: a first electrode
212: a first metal oxide layer
212 a: first doped region
212 c: second doped region
214: a third metal oxide layer
222,222': second metal oxide layer
222 a: source region
222 b: channel region
222 c: drain region
224: a fourth metal oxide layer
232: second grid
234: second electrode
242: source electrode
244: drain electrode
a: first node
b: second node
c: third node
Cst: storage capacitor
EL: light emitting element
ND: normal direction
P: doping process
PX: pixel circuit
O1: first opening
O2: second opening
R1: variable resistive memory
ST1, ST 1': first stacking structure
ST 2: second stack structure
T1: a first thin film transistor
T2: second thin film transistor
T3: third thin film transistor
t1, t 2: thickness of
V1, V2, V3: opening of the container
V S1 ,V data ,V DD ,V S2 ,V sus ,V SS : voltage of
Detailed Description
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Referring to fig. 1, a semiconductor device 10A includes a substrate 100, a first thin film transistor T1, and a variable resistive memory R1.
The substrate 100 may be made of glass, quartz, organic polymer, opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable materials. If a conductive material or metal is used, an insulating layer (not shown) is formed on the substrate 100 to prevent short circuit. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene terephthalate (PEN), Polyester (PES), polymethyl methacrylate (PMMA), Polycarbonate (PC), Polyimide (PI), or Metal Foil (Metal Foil), or other flexible materials.
The first thin film transistor T1 and the variable resistive memory R1 are disposed on the substrate 100. In some embodiments, one or more buffer layers (not shown) are further disposed between the first thin film transistor T1 and the substrate 100 and between the variable resistive memory R1 and the substrate 100, but the invention is not limited thereto. The first thin film transistor T1 includes a first gate 202, a first stacked structure ST1, a second gate 232, a source 242, and a drain 244. The variable resistive memory R1 includes a first electrode 204, a second stack structure ST2, and a second electrode 234.
The first gate 202 and the first electrode 204 are disposed on the substrate 100. In an embodiment, the first gate electrode 202 and the first electrode 204 may be non-active metals that are not easily oxidized and have a high work function (work function), such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum, or a combination thereof. In some embodiments, the first gate 202 and the first electrode 204 comprise materials of the same or different compositions. In some embodiments, the first gate 202 and the first electrode 204 comprise the same or different thicknesses. In some embodiments, the first gate 202 and the first electrode 204 belong to the same patterned layer, and the first gate 202 and the first electrode 204 are integrally connected.
The first gate dielectric layer 110 is disposed on the first gate 202 and the first electrode 204. The first gate dielectric layer 110 covers the first gate 202 and the first electrode 204, and the first gate dielectric layer 110 has a first opening overlapping the first electrode 204. The material of the first gate dielectric layer 110 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or other suitable materials.
The first stack structure ST1 and the second stack structure ST2 are located on the first gate dielectric layer 110. The first stack structure ST1 includes a first metal oxide layer 212 and a second metal oxide layer 222 overlapping each other. The second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 overlapping each other.
The first metal oxide layer 212 overlaps the first gate electrode 202 in the normal direction ND of the top surface of the substrate 100, and the third metal oxide layer 214 overlaps the first electrode 204 in the normal direction ND of the top surface of the substrate 100. The third metal oxide layer 214 fills the first opening of the first gate dielectric layer 110 and is connected to the first electrode 204. In some embodiments, the third metal oxide layer 214 has a schottky contact with the first electrode 204. In some embodiments, the first metal oxide layer 212 and the third metal oxide layer 214 belong to the same patterned layer.
The second metal oxide layer 222 and the fourth metal oxide layer 224 respectively overlap the first metal oxide layer 212 and the third metal oxide layer 214 in a normal direction ND of the top surface of the substrate 100. The second metal oxide layer 222 includes a source region 222a, a drain region 222c, and a channel region 222b located between the source region 222a and the drain region 222c, wherein the channel region 222b overlaps the first gate 202 in the normal direction ND. In some embodiments, the source region 222a and the drain region 222c are doped to have a lower resistivity than the channel region 222 b. In some embodiments, the fourth metal oxide layer 224 has substantially the same resistivity as the channel region 222b of the second metal oxide layer 222. In some embodiments, the second metal oxide layer 222 and the fourth metal oxide layer 224 belong to the same patterned layer.
The carrier concentration of the first metal oxide layer 212 is greater than that of the channel region 222b of the second metal oxide layer 222. The oxygen concentration of the first metal oxide layer 212 is less than that of the channel region 222b of the second metal oxide layer 222. In some embodiments, the oxygen concentration of the first metal oxide layer 212 is 10 at% to 50 at%, and the oxygen concentration of the channel region 222b of the second metal oxide layer 222 is 30 at% to 70 at%. In some embodiments, the oxygen concentration is adjusted such that the Band Gap (Band Gap) of the first metal oxide layer 212 is smaller than the Band Gap of the second metal oxide layer 222, thereby forming a two-dimensional electron gas 2DEG at the interface between the first metal oxide layer 212 and the second metal oxide layer 222. The thickness t2 of the second metal oxide layer 222 is less than or equal to the thickness t1 of the first metal oxide layer 212, thereby allowing the two-dimensional electron gas 2DEG to be more easily formed at the interface. In some embodiments, the thickness t1 of the first metal oxide layer 212 is 10 nanometers to 50 nanometers, and the thickness t2 of the second metal oxide layer 222 is 5 nanometers to 50 nanometers. In some embodiments, the material of the first metal oxide layer 212 and the second metal oxide layer 222 includes a quaternary compound of indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or a ternary compound including two metal elements of the foregoing quaternary compounds and an oxygen element.
The carrier concentration of the third metal oxide layer 214 is greater than the carrier concentration of the fourth metal oxide layer 224. The oxygen concentration of third metal oxide layer 214 is less than the oxygen concentration of fourth metal oxide layer 224. In some embodiments, the oxygen concentration of the third metal oxide layer 214 is 10 at% to 50 at%, and the oxygen concentration of the fourth metal oxide layer 224 is 30 at% to 70 at%. In some embodiments, applying a voltage to the second stack structure ST2 may switch the second stack structure ST2 between states of different resistivities, in other words, the second stack structure ST2 has a plurality of states of different resistivities. Since the carrier concentration of the third metal oxide layer 214 is different from that of the fourth metal oxide layer 224, the resistivity of the second stack structure ST2 in different states is graded, in other words, the variable resistive memory R1 may store single-level cells, multi-level cells, three-level cells, four-level cells, or even analog information. Thickness t2 of fourth metal oxide layer 224 is less than or equal to thickness t1 of third metal oxide layer 214. In some embodiments, the thickness t1 of the third metal oxide layer 214 is 10 nanometers to 50 nanometers and the thickness t2 of the fourth metal oxide layer 224 is 5 nanometers to 50 nanometers. In some embodiments, the material of the third metal oxide layer 214 and the fourth metal oxide layer 224 includes a quaternary compound of indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or a ternary compound containing two metal elements of the foregoing quaternary compounds and an oxygen element.
The second gate dielectric layer 120 covers the first stack structure ST1 and the second stack structure ST2, and the second gate dielectric layer 120 has a second opening overlapping the second stack structure ST 2. The material of the second gate dielectric layer 120 is, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or other suitable materials.
The second gate 232 and the second electrode 234 are disposed on the second gate dielectric layer 120. The second gate electrode 232 overlaps the channel region 222b of the third metal oxide layer 222 in the normal direction ND of the top surface of the substrate 100. The first stacked structure ST1 is located between the first gate 202 and the second gate 232. The second electrode 234 overlaps the fourth metal oxide layer 224 in the normal direction ND of the top surface of the substrate 100. The second electrode 234 fills the second opening of the second gate dielectric layer 120 and is connected to the fourth metal oxide layer 224. In some embodiments, the second electrode 234 has a schottky contact with the fourth metal oxide layer 224. The second stack structure ST2 is located between the first electrode 204 and the second electrode 234, and connects the first electrode 204 and the second electrode 234.
In an embodiment, the second gate electrode 232 and the second electrode 234 may be non-active metals that are not easily oxidized and have a high work function (work function), such as tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum, or a combination thereof. In some embodiments, the second gate electrode 232 and the second electrode 234 comprise materials of the same or different compositions. In some embodiments, second gate 232 and second electrode 234 comprise the same or different thicknesses. In some embodiments, the second gate 232 and the second electrode 234 belong to the same patterned layer, and the second gate 232 and the second electrode 234 are separated from each other.
The interlayer dielectric layer 130 is disposed on the second gate 232 and the second electrode 234, and covers the second gate 232 and the second electrode 234. The material of the interlayer dielectric layer 130 is, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.
The source 242 and the drain 244 are disposed on the ild layer 130, and are respectively filled into the openings penetrating the ild layer 130 and the second gate dielectric layer 120 to be electrically connected to the first stacked structure ST 1. In some embodiments, the source 242 and the drain 244 are electrically connected to the source region 222a and the drain region 222c of the second metal oxide layer 222, respectively. In addition, the source electrode 242 is filled in the opening penetrating the interlayer dielectric layer 130 and electrically connected to the second electrode 234.
Based on the above, the two-dimensional electron gas 2DEG is provided in the first thin film transistor T1 of the semiconductor device 10A, and thus the magnitude of the output current of the first thin film transistor T1 can be increased. In addition, the second stack structure ST2 of the variable resistive memory R1 includes the third metal oxide layer 214 and the fourth metal oxide layer 224 having different carrier concentrations, so that the variable resistive memory R1 can store analog information. In addition, the first electrode 204 of the variable resistive memory R1 is electrically connected to the first gate 202 of the first thin film transistor T1, so that the first gate 202 can be used as a shielding electrode for blocking the adverse effect of the external electric field on the first thin film transistor T1.
Fig. 2A to 2H are schematic cross-sectional views illustrating a method of manufacturing the semiconductor device of fig. 1.
Referring to fig. 2A, a first gate 202 and a first electrode 204 are formed on the substrate 100. In some embodiments, the method of forming the first gate 202 and the first electrode 204 includes the steps of: first, a blanket layer of conductive material (not shown) is formed on a substrate 100; next, a patterned photoresist (not shown) is formed on the conductive material layer using a photolithography process; then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the conductive material layer to form a first gate 202 and a first electrode 204; and removing the patterned photoresist. In other words, the first gate 202 and the first electrode 204 are formed at the same time.
Referring to fig. 2B, a first gate dielectric layer 110 is formed on the first gate 202 and the first electrode 204. The first gate dielectric layer 110 has a first opening O1 exposing the first electrode 204.
Referring to fig. 2C and fig. 2D, a first stacked structure ST 1' and a second stacked structure ST2 are formed on the first gate dielectric layer 110. The first stack structure ST1 'includes a first metal oxide layer 212 and a second metal oxide layer 222' overlapping each other, and the second stack structure ST2 includes a third metal oxide layer 214 and a fourth metal oxide layer 224 overlapping each other.
The method of forming the first stack structure ST 1' and the second stack structure ST2 includes: as shown in fig. 2C, a first metal oxide layer 212 and a third metal oxide layer 214 are formed on the first gate dielectric layer 110, wherein the third metal oxide layer 214 fills the first opening O1 of the first gate dielectric layer 110 to contact the first electrode 204. Next, as shown in fig. 2D, a second metal oxide layer 222' and a fourth metal oxide layer 224 are formed on the first metal oxide layer 212 and the third metal oxide layer 214.
In some embodiments, the method of forming the first metal oxide layer 212 and the third metal oxide layer 214 includes the steps of: first, a blanket layer of semiconductor material (not shown) is formed on first gate dielectric layer 110; next, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the semiconductor material layer to form a first metal oxide layer 212 and a third metal oxide layer 214; and removing the patterned photoresist. In other words, the first metal oxide layer 212 and the third metal oxide layer 214 are formed at the same time.
In some embodiments, the method of forming the second metal oxide layer 222' and the fourth metal oxide layer 224 includes the steps of: first, a blanket layer of semiconductor material (not shown) is formed on first gate dielectric layer 110, first metal oxide layer 212, and third metal oxide layer 214; next, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the semiconductor material layer to form a second metal oxide layer 222' and a fourth metal oxide layer 224; and removing the patterned photoresist. In other words, the second metal oxide layer 222' and the fourth metal oxide layer 224 are formed at the same time.
In other embodiments, the method of forming the first stack structure ST 1' and the second stack structure ST2 includes a single photolithography etching process. For example, two blanket layers of semiconductor material are formed over first gate dielectric layer 110; next, a patterned photoresist (not shown) is formed on the semiconductor material layer using a photolithography process; then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the semiconductor material layer to form a first stacked structure ST 1' and a second stacked structure ST 2; and removing the patterned photoresist.
Referring to fig. 2E, a second gate dielectric layer 120 is formed on the first stacked structure ST 1' and the second stacked structure ST2, the second gate dielectric layer 120 having a second opening O2 exposing the fourth metal oxide layer 224.
Referring to fig. 2F, a second gate 232 and a second electrode 234 are formed on the second gate dielectric layer 120. The second electrode 234 fills the second opening O2 of the second gate dielectric layer 120 to contact the fourth metal oxide layer 224.
Next, a doping process P is performed on the second metal oxide layer 222' by using the second gate 232 and the second electrode 234 as masks, so as to form the second metal oxide layer 222 including the source region 222a, the channel region 222b and the drain region 222 c. In some embodiments, the doping process P comprises a hydrogen plasma process or an ion implantation process. In the present embodiment, since the fourth metal oxide layer 224 is covered by the second electrode 234, the doping process P does not dope the fourth metal oxide layer 224.
Referring to fig. 2G, an interlayer dielectric layer 130 is formed on the second gate dielectric layer 120, the second gate electrode 232 and the second electrode 234. In some embodiments, the interlayer dielectric layer 130 is an insulating layer containing no hydrogen, so as to prevent hydrogen atoms in the interlayer dielectric layer 130 from diffusing into the first stacked structure ST1 and the second stacked structure ST2, but the invention is not limited thereto. In some embodiments, hydrogen atoms are contained in the interlayer dielectric layer 130, and thus, the hydrogen atoms may be diffused into the first stacked structure ST1 by the heat treatment to adjust the resistivity of the first stacked structure ST 1. In some embodiments, when the doping of the first stacked structure ST1 is performed using hydrogen atoms in the interlayer dielectric layer 130, the doping process P of fig. 2F may be omitted.
Referring to fig. 2H, the openings V1, V2, V3 are formed, the method includes the following steps: first, a patterned photoresist (not shown) is formed on the interlayer dielectric layer 130 using a photolithography process; then, using the patterned photoresist as a mask, a wet or dry etching process is performed to form openings V1 and V2 in the ild 130 and the second gate dielectric 120, and to form an opening V3 in the ild 130; and removing the patterned photoresist. The openings V1 and V2 respectively expose the drain region 222c and the source region 222a of the second metal oxide layer 222, and the opening V3 exposes the second electrode 234.
Finally, referring back to fig. 1, a drain 244 and a source 242 are formed on the ild layer 130. The drain 244 and the source 242 are filled in the openings V1 and V2 respectively to electrically connect the drain region 222c and the source region 222 a. In addition, the source electrode 242 also fills the opening V3 to electrically connect to the second electrode 234. In some embodiments, the method of forming the drain 244 and the source 242 includes the steps of: first, a blanket layer of conductive material (not shown) is formed on the interlayer dielectric layer 130; next, a patterned photoresist (not shown) is formed on the conductive material layer using a photolithography process; then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the conductive material layer to form a drain 244 and a source 242; and removing the patterned photoresist. In other words, the drain 244 and the source 242 are formed at the same time.
The fabrication of the active device substrate 10A can be substantially completed by the above processes.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment in fig. 3 follows the element numbers and partial contents of the embodiment in fig. 1, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, which are not repeated herein.
The main difference between the semiconductor device 10B of fig. 3 and the semiconductor device 10A of fig. 1 is that: the drain 244 and the source 242 of the semiconductor device 10B extend through the second metal oxide layer 222.
Referring to fig. 3, the drain electrode 244 and the source electrode 242 extend through the second metal oxide layer 222 and contact the interface between the first metal oxide layer 212 and the second metal oxide layer 222. In other words, the drain electrode 244 and the source electrode 242 directly contact the two-dimensional electron gas 2DEG, thereby increasing the magnitude of the output current of the first thin film transistor T1.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. It should be noted that the embodiment of fig. 4 follows the element numbers and partial contents of the embodiment of fig. 1, wherein the same or similar element numbers are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
The main difference between the semiconductor device 10C of fig. 4 and the semiconductor device 10A of fig. 1 is that: the first metal oxide layer 212 of the semiconductor device 10C includes a first doped region 212a and a second doped region 212C.
In the present embodiment, a doping process is performed to form a source region 222a and a drain region 222c in the second metal oxide layer 222, and the doping process forms a first doped region 212a and a second doped region 212c in the first metal oxide layer 212. In other words, the dopants (e.g., hydrogen atoms) in the doping process reach the first metal oxide layer 212 after passing through the second metal oxide layer 222, and form the first doped region 212a and the second doped region 212c in the first metal oxide layer 212. The first doped region 212a and the second doped region 212c contact the bottom of the source region 222c and the drain region 222a, respectively.
In some embodiments, the thickness of the first doped region 212a and the thickness of the second doped region 212c are less than the thickness of the first metal oxide layer 212.
In some embodiments, the widths of the source region 222a, the drain region 222c, the first doped region 212a and the second doped region 212c gradually decrease as the substrate 100 approaches. The surfaces of the source region 222a and the drain region 222c facing the channel region 222b are arc surfaces.
Fig. 5 is an equivalent circuit diagram of a pixel circuit PX according to an embodiment of the invention. The pixel circuit PX of fig. 5 includes, for example, the semiconductor device in any one of the embodiments described above.
Referring to fig. 5, the pixel circuit PX includes a first thin film transistor T1, a variable resistive memory R1, a second thin film transistor T2, a third thin film transistor T3, a storage capacitor Cst, and a light emitting element EL.
The second thin film transistor T2 may be used as a switching transistor. The gate of the second TFT T2 is electrically connected to the voltage V S1 (e.g., the scan line voltage), the drain (or source) of the second TFT T2 is electrically connected to the voltage V data (e.g., the data line voltage), the source (or drain) of the second thin film transistor T2 is electrically connected to the first node a.
The first thin film transistor T1 may be used as a driving transistor. The second gate of the first thin film transistor T1 is electrically connected to the first node a. The drain of the first TFT T1 is electrically connected to a voltage V DD The source of the first thin film transistor T1 is electrically connected to one end (the second electrode) of the variable resistive memory R1. The first gate of the first thin film transistor T1 and the other end (the first electrode) of the variable resistive memory R1 are electrically connected to the second node b.
The third thin film transistor T3 can be used as a sense transistor, for example. The gate of the third TFT T3 is electrically connected to the voltage V S2 A drain of the third TFT T3 is electrically connected to the third node c, and a source of the third TFT T3 is electrically connected to the voltage V sus . Voltage V S2 And a switch for controlling the third thin film transistor T3 to transmit information of the driving current to an external chip through the third thin film transistor T3.
One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the third node c. The second node b is electrically connected with the third node c. Since the second gate of the first thin film transistor T1 is electrically connected to the storage capacitor Cst, the first thin film transistor T1 can be turned on for a short time even when the second thin film transistor T2 is turned off.
One end of the light emitting element EL is electrically connected to the second node b, and the other end of the light emitting element EL is electrically connected to the voltage V SS . The luminance of the light emitting element EL varies due to the magnitude of the driving current through the first thin film transistor T1. The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode, or another light emitting element.
In the present embodiment, at the first node a, the source (or drain) of the second thin film transistor T2, the second gate of the first thin film transistor T1 and one end of the storage capacitor Cst are electrically connected to each other. At the second node b, the first gate of the first thin film transistor T1 and the other end of the variable resistive memory R1 are electrically connected to each other. At the third node c, the drain of the third thin film transistor T3 and the other end of the storage capacitor Cst are electrically connected to each other. The drain of the third thin film transistor T3 is electrically connected to the other end of the variable resistive memory R1 and the first gate of the first thin film transistor T1 through a third node c and a second node b.
Fig. 6 is a flowchart illustrating a pixel compensation operation of the display device in the pixel circuit configuration of fig. 5 according to an embodiment of the invention.
The operation of the display device with pixel compensation under the arrangement of the pixel circuit PX is briefly described below, please refer to fig. 5 and fig. 6. First, the display device is in an off state, so that the pixel circuit PX performs gray level (gray level) sensing in the background. The gray sensing is performed by, for example, turning on the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3, so that the driving current passing through the first thin film transistor T1 can be transmitted to the external chip through the third semiconductor device T3.
Then, the external chip establishes a corresponding model through signal processing and calculation, and further calculates corresponding compensation information. Then, the compensation information is written into the pixel circuit PX. For example, the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are turned on to write the compensation information calculated by the external chip into the variable resistive memory R1. Specifically, the resistance value of the variable resistive memory R1 is changed by a voltage difference between the first electrode and the second electrode of the variable resistive memory R1.
Then, the display device is turned on. Since the compensation information has been written into the variable resistive memory R1, the driving current passing through the first thin film transistor T1 and the variable resistive memory R1 can be adjusted, thereby implementing the pixel compensation function. In some embodiments, the third thin film transistor T3 is in an off state when the display device is turned on.
In summary, the variable resistive memory R1 of the present invention has the function of a memory, and therefore, it is not necessary to provide a compensation memory in an external chip, so that the overall system is simplified and the cost is reduced. In addition, since the variable resistive memory R1 can store analog information, the driving current of the pixel at different positions can be more finely adjusted to improve the problem of picture non-uniformity.
Claims (15)
1. A semiconductor device, comprising:
a substrate;
a first thin film transistor disposed on the substrate and including:
a first gate;
a first stacked structure including a first metal oxide layer and a second metal oxide layer overlapped with each other;
a second gate, wherein the first stacked structure is located between the first gate and the second gate; and
a source and a drain electrically connected to the first stacked structure; and
a variable resistive memory disposed on the substrate and comprising:
a first electrode electrically connected to the first gate;
a second stacked structure including a third metal oxide layer and a fourth metal oxide layer overlapped with each other; and
and the second stacking structure is positioned between the first electrode and the second electrode and is connected with the first electrode and the second electrode.
2. The semiconductor device of claim 1, wherein the first electrode is integrally connected to the first gate, and the first electrode, the second electrode, the first gate, and the second gate are made of a material comprising tungsten, molybdenum, platinum, palladium, gold, molybdenum/aluminum/molybdenum, or a combination thereof.
3. The semiconductor device of claim 1, wherein the second electrode has a schottky contact with the fourth metal oxide layer.
4. The semiconductor device as claimed in claim 1, wherein the carrier concentration of the first metal oxide layer is greater than the carrier concentration of a channel region of the second metal oxide layer.
5. The semiconductor device of claim 4, wherein a two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer.
6. The semiconductor device of claim 4, wherein the first metal oxide layer has an oxygen concentration less than that of a channel region of the second metal oxide layer, and the thickness of the second metal oxide layer is less than or equal to that of the first metal oxide layer.
7. The semiconductor device as claimed in claim 1, wherein the carrier concentration of the third metal oxide layer is greater than the carrier concentration of the fourth metal oxide layer.
8. The semiconductor device of claim 7, wherein an oxygen concentration of said third metal oxide layer is less than an oxygen concentration of said fourth metal oxide layer, a thickness of said fourth metal oxide layer being less than or equal to a thickness of said third metal oxide layer.
9. The semiconductor device of claim 1, wherein said first metal oxide layer and said third metal oxide layer belong to a same patterned layer, and said second metal oxide layer and said fourth metal oxide layer belong to another same patterned layer.
10. The semiconductor device according to claim 1, further comprising:
a light emitting element electrically connected to the first electrode; and
a second thin film transistor electrically connected to the light emitting element and the first electrode.
11. The semiconductor device of claim 1, wherein the first metal oxide layer and the third metal oxide layer have a thickness of 10 nm to 50 nm, and the second metal oxide layer and the fourth metal oxide layer have a thickness of 5 nm to 50 nm.
12. The semiconductor device of claim 1, wherein the first metal oxide layer and the third metal oxide layer have oxygen concentrations of 10 at% to 50 at%, and the second metal oxide layer has a channel region and the fourth metal oxide layer have oxygen concentrations of 30 at% to 70 at%.
13. The semiconductor device of claim 1, wherein the first source is electrically connected to the second electrode.
14. A method of manufacturing a semiconductor device, comprising:
forming a first gate and a first electrode on a substrate;
forming a first gate dielectric layer on the first gate and the first electrode, the first gate dielectric layer having a first opening exposing the first electrode;
forming a first stack structure and a second stack structure on the first gate dielectric layer, wherein the first stack structure includes a first metal oxide layer and a second metal oxide layer overlapped with each other, the second stack structure includes a third metal oxide layer and a fourth metal oxide layer overlapped with each other, and the third metal oxide layer is filled in the first opening;
forming a second gate dielectric layer on the first stacked structure and the second stacked structure, the second gate dielectric layer having a second opening exposing the fourth metal oxide layer;
forming a second gate and a second electrode on the second gate dielectric layer, wherein the first stacked structure is located between the first gate and the second gate, and the second electrode is filled in the second opening; and
forming a source and a drain electrically connected to the first stacked structure.
15. The method of claim 14, wherein the first metal oxide layer and the third metal oxide layer are formed simultaneously, and the second metal oxide layer and the fourth metal oxide layer are formed simultaneously.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163287695P | 2021-12-09 | 2021-12-09 | |
| US63/287,695 | 2021-12-09 | ||
| TW111116869 | 2022-05-04 | ||
| TW111116869A TWI799253B (en) | 2021-12-09 | 2022-05-04 | Semiconductor device and manufactoring method thereof |
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| CN115050840A true CN115050840A (en) | 2022-09-13 |
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| CN202210863617.0A Pending CN115050840A (en) | 2021-12-09 | 2022-07-21 | Semiconductor device and method for manufacturing the same |
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