KR102138037B1 - Thin film transistor and display panel having the same, method for fabricating the thin film transistor - Google Patents

Abstract

The thin film transistor according to the present invention is disposed on a base substrate and includes a source region, a drain region, and a semiconductor layer including a channel region disposed between the source region and the drain region, a source electrode connected to the source region, and a drain connected to the drain region. An electrode, a gate electrode disposed on the semiconductor layer, a first portion disposed between the gate electrode and the semiconductor layer, covered by the gate electrode, and exposed from the gate electrode, forming a step difference with the first portion And a first insulating layer including a second portion to be formed, and a spacer disposed on the second portion and disposed at an edge of the first portion.

Description

A thin film transistor, a display panel including the same, and a method of manufacturing a thin film transistor {THIN FILM TRANSISTOR AND DISPLAY PANEL HAVING THE SAME, METHOD FOR FABRICATING THE THIN FILM TRANSISTOR}

The present invention relates to a thin film transistor, a display panel including the same, and a method of manufacturing the thin film transistor, and more particularly, to a thin film transistor including a spacer, a display panel including the same, and a method of manufacturing the thin film transistor.

The display panel includes a plurality of pixels. Each of the pixels includes at least one thin film transistor and a capacitor. The thin film transistor includes a control electrode, a semiconductor pattern, an input electrode, and an output electrode.

The thin film transistor is turned on and off according to the voltage applied to the thin film transistor, and the display panel embodies an image. When a driving voltage is applied to the control electrode, a channel is formed in the semiconductor pattern to operate the thin film transistor.

An object of the present invention is to provide a thin film transistor capable of securing an effective channel length and preventing a decrease in response speed in a high resolution display panel, a display panel including the same, and a method of manufacturing the thin film transistor.

A thin film transistor according to an embodiment of the present invention is disposed on a base substrate, a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region, and a source connected to the source region. An electrode, a drain electrode connected to the drain region, a gate electrode disposed on the semiconductor layer, a first portion disposed between the gate electrode and the semiconductor layer, covered by the gate electrode, and exposed from the gate electrode , A first insulating layer including a second portion forming a step difference from the first portion, and a spacer disposed on the second portion and disposed at an edge of the first portion.

The semiconductor layer is an oxide semiconductor layer, and at least one of the source region and the gate region may include a precipitate of the oxide semiconductor.

The thin film transistor according to an embodiment of the present invention may further include a second insulating layer disposed between the semiconductor layer and the base substrate.

The thin film transistor according to an embodiment of the present invention further includes a third insulating film disposed between the first insulating film and the gate electrode, and the spacer is disposed on the second part, and the first part and the first part 3 It is placed on the edge of the insulating film.

The spacer may be transparent, and the spacer may include the same material as at least one of the first insulating layer, the second insulating layer, and the third insulating layer.

The thin film transistor according to an embodiment of the present invention is disposed between the gate electrode and the semiconductor layer, a first insulating film overlapping the gate electrode, and disposed between the first insulating film and the semiconductor layer, and the gate And a second insulating layer including a region exposed from the electrode and a spacer disposed on the exposed region of the second insulating layer and disposed at an edge of the first insulating layer.

A thin film transistor according to an embodiment of the present invention includes forming a semiconductor layer including a channel region on a substrate, applying an insulating layer on the semiconductor layer;

A method of manufacturing a thin film transistor according to an embodiment of the present invention includes forming a gate electrode on the insulating layer, etching the insulating layer, a first portion overlapping the gate electrode, and an outer side of the first portion. Forming a first insulating film extending from the gate electrode and including a second portion forming a step difference from the first portion, disposed on the second portion, and disposed at an edge of the first portion And forming a formed spacer, and forming a source region and a drain region facing each other in the semiconductor layer with the channel region therebetween.

The forming of the semiconductor layer includes forming a protective film on the substrate, applying a semiconductor material layer on the protective film, and patterning the semiconductor material layer.

The forming of the source region and the drain region includes exposing a portion of the semiconductor layer, and reducing the exposed semiconductor layer.

The forming of the first insulating layer includes forming the first portion forming the step by etching a portion of the first insulating layer, and exposing an upper surface of the second portion.

The forming of the spacer may include applying an insulating material layer on the gate electrode and the first insulating layer, and exposing a partial region of the semiconductor layer by etching the insulating material layer and the first insulating layer. And the partial region may be at least one of the source region and the drain region.

A method of manufacturing a thin film transistor according to an embodiment of the present invention includes forming a semiconductor layer including a channel region on a substrate, applying a first insulating layer on the semiconductor layer, and applying a first insulating layer on the first insulating layer. Applying a second insulating layer, forming a gate electrode on the second insulating layer, etching the second insulating layer to expose a part of the first insulating layer from the gate electrode, the second insulating layer And forming a spacer disposed on the first insulating layer and surrounding the second insulating layer, and forming a source region and a drain region facing each other on the semiconductor layer with the channel region therebetween.

A display panel according to an embodiment of the present invention includes a first substrate on which a plurality of signal lines are disposed, a second substrate on the first substrate, and a thin film connected to corresponding signal lines among the plurality of signal lines. Including a plurality of pixels each including a transistor, the thin film transistor, a first insulating layer disposed on the first substrate, disposed on the first insulating layer, a source region, a drain region, and the source region and the A semiconductor layer including a channel region disposed between drain regions, a gate electrode disposed on the semiconductor layer, a source electrode connected to the source region and a drain electrode connected to the drain region, and disposed between the gate electrode and the semiconductor layer A second insulating film including a first portion overlapping the gate electrode, and a second portion exposed from the gate electrode and forming a step difference from the first portion, and disposed on the second portion, the And a spacer disposed on the edge of the first portion.

The display panel according to an exemplary embodiment of the present invention may further include a liquid crystal layer sealed between the first substrate and the second substrate.

The display panel according to an exemplary embodiment of the present invention further includes the second insulating layer and a third insulating layer disposed between the gate electrode, the third insulating layer overlapping the first portion, and the spacer is the third insulating layer. It may be disposed on the insulating layer and the edge of the first portion.

The thin film transistor according to an embodiment of the present invention can secure an effective channel length in a high resolution display panel in which a gate electrode is miniaturized. In addition, it is possible to prevent a decrease in response speed by reducing the capacitance between gate electrodes between adjacent pixels.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.
2 is a plan view of a thin film transistor according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2 of a thin film transistor according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view taken along line I-I' of FIG. 2 of a thin film transistor according to an embodiment of the present invention.
5 is a cross-sectional view taken along line I-I' of FIG. 2 of the thin film transistor according to an embodiment of the present invention.
6A to 6J are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.
7A to 7J are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

In the present invention, various modifications may be made and various forms may be applied, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form disclosed, it should be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, scales of some components are exaggerated or reduced in order to clearly express various layers and regions.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention. A display device according to an exemplary embodiment of the present invention includes a display panel DP, a timing controller TD, a scan driver GD, and a data driver DD.

The timing controller TC receives input image signals, and outputs image data I _DATA and various control signals DCS converted to conform to the operation mode of the display panel DP.

The scan driver SD receives a scan drive control signal SCS from the timing controller TC. The scan driver SD receiving the scan drive control signal SCS generates a plurality of scan signals. The scan signals are sequentially supplied to a plurality of scan lines S1 to Sn.

The data driver DD receives a data driving control signal DCS and the converted image data I _DATA from the timing controller TC. The data driver DD generates a plurality of data signals based on the data driving control signal DCS and the converted image data I _DATA . The data signals are supplied to a plurality of data lines D1 to Dm.

The display panel DP is not particularly limited, and for example, an organic light emitting display panel, a liquid crystal display panel, a plasma display panel, and electrophoresis An electrophoretic display panel and an electrowetting display panel may be applied.

The display panel DP includes a plurality of signal lines and a plurality of pixels PX ₁₁ to PX _nm connected to the signal lines. The signal lines include the plurality of scan lines S1 to Sn and the plurality of data lines D1 to Dm. The scan lines S1 to Sn extend in a first direction DR1 and are arranged in a second direction DR2 crossing the first direction DR1.

The scan lines S1 to Sn extend in the second direction DR2 and are arranged in the first direction DR1. The data lines D1 to Dm intersect to be insulated from the scan lines S1 to Sn.

The pixels PX ₁₁ to PX _nm may be disposed in a region where the scan lines S1 to Sn and the data lines D1 to Dm cross. The pixels PX ₁₁ to PX _nm may be arranged in a matrix form. Each of the pixels PX ₁₁ to PX _nm is connected to a corresponding scan line among the scan lines S1 to Sn, and to a corresponding data line among the data lines D1 to Dm. Each of the pixels PX ₁₁ to PX _nm is turned on in response to a scan signal received from a corresponding scan line.

The display panel DP includes a plurality of thin film transistors TFT ₁₁ to TFT _nm and a plurality of capacitors C11 to Cnm. Each of the pixels includes a corresponding thin film transistor among the thin film transistors TFT ₁₁ to TFT _nm and a corresponding capacitor among the capacitors C ₁₁ to C _nm . The thin film transistor and the capacitor are connected to each other in the pixel.

Each of the thin film transistors TFT ₁₁ to TFT _nm includes a control electrode connected to a corresponding scan line, an input electrode and an output electrode connected to a corresponding data line. Each of the thin film transistors TFT ₁₁ to TFT _nm outputs a data signal applied to a corresponding data line in response to a scan signal applied to a corresponding scan line.

Each of the capacitors C ₁₁ to C _nm includes a first capacitor electrode connected to a corresponding transistor and a second capacitor electrode opposite to the first capacitor electrode. Each of the capacitors C ₁₁ to C _nm charges an amount of charge corresponding to a difference between a voltage corresponding to the data signal received from a corresponding transistor and a voltage received by the second capacitor electrode.

Each of the capacitors C ₁₁ to C _nm may control light emission of the plurality of pixels PX ₁₁ to PX _nm . For example, each of the capacitors C ₁₁ to C _nm may be at least one of a liquid crystal capacitor, a parasitic capacitor, and a storage capacitor. Also, although not shown, each of the capacitors C ₁₁ to C _nm may be connected to a light emitting device.

FIG. 2 is a plan view of a thin film transistor according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2. In FIG. 2, a transistor TFT _ij disposed in one pixel is illustrated as an example. Hereinafter, a thin film transistor according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3.

As illustrated in FIGS. 1 and 2, the thin film transistor TFT _ij includes a control electrode GE, an input electrode SE, a semiconductor layer AL, and an output electrode DE. In this embodiment, the control electrode GE is described as a gate electrode, and the input electrode SE is described as a source electrode. In addition, the output electrode DE is described as a drain electrode.

The semiconductor layer AL is disposed on the base substrate 100. The gate electrode GE is disposed on the semiconductor layer AL. In this embodiment, the thin film transistor TFTij has a top-gate structure.

A protective layer 200 may be further disposed between the semiconductor layer AL and the base substrate 100. The protective layer 200 separates the semiconductor layer AL from the base substrate 100. The passivation layer 200 may minimize impurities from flowing into the semiconductor layer AL from the base substrate 100. The protective layer 200 protects the semiconductor layer AL and improves interface characteristics.

For example, the passivation layer 200 may be a buffer layer. The protective layer 200 may include insulating oxides such as silicon oxide, aluminum oxide, hafnium oxide, and yttrium oxide. For example, when the protective layer 200 includes silicon oxide, silicon nitride, or silicon oxynitride, impurities of the substrate 100 may effectively prevent intrusion into the semiconductor layer AL. The protective layer 200 may include a multilayer thin film.

The semiconductor layer AL includes an input area SA, an output area DA, a channel area CA, and at least one intermediate area DR. The intermediate area DR is an area in which the channel area CA and the input area SA, or the channel area CA and the output area DA can coexist. The intermediate area DR may be formed between the channel area CA and the input area SA, or between the channel area CA and the output area DA.

In this embodiment, each of the input region SA and the output region DA is described as a source region and a drain region. The source region SA, the channel region CA, the intermediate region DR, and the drain region DA may be arranged in a row on a plane and continuously arranged.

The source region SA and the drain region DA have conductivity. Each of the source region SA and the drain region DA may include a metal precipitate. The metal precipitate is determined according to the oxide semiconductor material included in the semiconductor layer AL. For example, when the semiconductor layer AL includes indium gallium zinc oxide (IGZO), the source region SA and the drain region DA may each contain indium (In).

The channel region CA overlaps the gate electrode GE. The channel region CA may include a metal oxide semiconductor. The channel region CA may include metals such as zinc, indium, gallium, tin, and titanium, and oxides thereof. For example, the channel region CA may include at least one of zinc oxide, titanium oxide, indium gallium zinc oxide, and indium zinc tin oxide.

As shown in FIG. 3, the thin film transistor according to the exemplary embodiment of the present invention includes an insulating layer disposed between the gate electrode GE and the semiconductor layer AL. In FIG. 3, an embodiment including the first insulating layer 300 forming a predetermined step D is shown.

The first insulating layer 300 includes a plurality of portions forming the step D. The plurality of portions includes a first portion 310 and a second portion 320 extending from the first portion 310.

The first portion 310 includes a region corresponding to the gate electrode GE of the first insulating layer 300. On a plane, the first portion 310 is covered by the gate electrode GE. The first portion 310 includes an upper surface 310u and a side surface 310w.

The upper surface 310u of the first portion contacts the gate electrode GE. The side surface 310w of the first portion is bent from the upper surface 310u of the first portion. The side surface 310w of the first portion may be aligned in a straight line with the side surface of the gate electrode GE. The side surface 310w of the first portion forms the step D. Accordingly, the degree of the step D is determined by the length of the side surface 310w of the first portion.

The second portion 320 extends from the first portion 310. In a plan view, the second portion 320 protrudes outside the gate electrode GE. The second portion 320 includes an upper surface 320u and a side surface 320w.

The upper surface 320u of the second portion is exposed without being covered by the gate electrode GE. The side surface 320w of the second portion is bent toward the semiconductor layer AL from the upper surface 320u of the second portion. The side surface 320w of the second portion is exposed without being covered by the spacer SW.

The first portion 310 covers the channel region CA of the semiconductor layer AL, and the second portion 320 covers the intermediate region DR of the semiconductor layer AL. The upper surface of the first part 310 and the upper surface of the second part 320 form the step D.

As shown in FIG. 3, the second portion 320 has a thickness smaller than that of the first portion 310. However, it is not particularly limited, and the first portion 310 and the second portion 320 may have various thicknesses within a range capable of forming the step difference.

In this case, the spacer SW is disposed on the second part 320. The spacer SW includes an upper surface 320u of the second portion and a side surface 310w of the first portion. And a side surface of the gate electrode GE. The spacer SW may secure an effective length of the channel region CA by preventing the source region SA and the drain region DA from overlapping with the gate electrode GE.

The gate electrode GE is disposed on the first insulating layer 300. In particular, the gate electrode GE may be disposed on the first portion 310. The gate electrode GE may have the same cross-sectional area as the first portion 310 on a plane.

The gate electrode GE may include a metal or a conductive polymer material, a conductive oxide, or the like. For example, the gate electrode GE may be made of a metal such as aluminum, silver, copper, molybdenum, chromium, tantalum, titanium, or an alloy thereof. The gate electrode GE may include a single layer or a multilayer layer. For example, the gate electrode GE may be a double layer composed of a first layer including any one of molybdenum, chromium, tantalum, titanium, and indium tin oxide, and a second layer including copper. Alternatively, the gate electrode GE may include a triple layer composed of molybdenum/aluminum/molybdenum.

The thin film transistor according to an embodiment of the present invention includes a spacer SW. The spacer SW is disposed along the edge of the gate electrode GE. The spacer SW is disposed on the second part 320, and the spacer SW is a side surface of the first part 310 of the first insulating layer 300 and a side surface of the gate electrode GE Covers.

The spacer SW may be made of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The spacer SW may be made of the same material as the first insulating layer 300 or the protective layer 200.

In this embodiment, the spacer SW may be formed of a transparent insulating material. In this case, the spacer SW may improve the aperture ratio of the display panel including the thin film transistor.

As shown in FIG. 2, the spacer SW is formed to surround the edge of the gate electrode GE. The spacer SW covers a side surface of the gate electrode GE. This forms a structure in which an insulating layer is added between the gate electrode GE and the gate electrode of an adjacent pixel.

The spacer SW decreases parasitic capacitance by increasing the distance between the gate electrodes disposed in adjacent pixels. Accordingly, RC delay of the display panel can be prevented.

As shown in FIG. 3, a passivation layer PS covering the gate electrode GE is disposed on the passivation layer 200. The passivation layer PS covers the source region SA, the drain region DA, and the spacer SW of the semiconductor layer AL.

The passivation layer PS may be made of an inorganic material such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiON). The passivation layer PS may include a multilayer thin film.

A source electrode SE and a drain electrode DE may be disposed on the passivation layer PS. The source electrode SE is connected to the scan line, and the drain electrode DE is connected to the data line.

The source electrode SE may be connected to the source region SA through a first contact hole CH1 penetrating the passivation layer PS. The drain electrode DE may be connected to the drain region DE through a second contact hole CH2 penetrating the passivation layer PS.

Meanwhile, in another embodiment, the source electrode SE and the drain electrode DE may be disposed on the protective layer 200. In this case, the source electrode SE and the drain electrode DE may be directly connected to each other by contacting the source region SA and the drain region DA.

When a voltage (hereinafter, a gate voltage) is applied to the gate electrode GE, a channel is formed, and a current flows between the source electrode SE and the drain electrode DE through the channel. The threshold voltage is a gate voltage at which current begins to flow between the source electrode SE and the drain electrode DE.

The spacer SW prevents the source region SA and the drain region DA from overlapping with the gate electrode GE. Since the source region SA and the drain region DA of the semiconductor layer AL do not overlap the gate electrode GE, an effective channel region CA may be secured. For example, when the spacer SW is formed to have a width of 5000A, the channel region CA may secure an effective channel length of at least 1 μm.

In the thin film transistor according to an embodiment of the present invention, the channel length can be adjusted by adjusting the width of the spacer SW. Accordingly, the spacer SW secures the length of the channel region CA to prevent a short channel effect of the thin film transistor.

In addition, the spacer SW may reduce parasitic capacitance generated between adjacent pixels. As the spacer SW is added between the gate electrode GE and the gate electrode of an adjacent pixel, the distance between the two gate electrodes may be increased and the capacitance may be reduced. Accordingly, RC delay can be prevented.

FIG. 4 is a cross-sectional view taken along line I-I' of FIG. 2 of a thin film transistor according to an embodiment of the present invention. The embodiment shown in FIG. 4 is the same as the embodiment of FIG. 3 except for the difference between the first insulating layer 300 and the second insulating layer 400 (see FIG. 3 ). Hereinafter, the same reference numerals are assigned to the same components as those described in FIGS. 1 to 3, and detailed descriptions are omitted.

As shown in FIG. 4, the thin film transistor according to an embodiment of the present invention shows an embodiment in which the gate electrode GE, the first insulating layer 300 and the second insulating layer 400 are further added. In the present invention, the second insulating layer 400 may correspond to the second insulating layer.

The second insulating layer 400 may have the same area as the gate electrode GE on a plane. The second insulating layer 400 may be disposed on the first portion 310. The second insulating layer 400 covers the top surface 310u of the first portion, and exposes the top surface 320u of the second portion. The first portion 310 and the second portion form a predetermined step D1. The step D1 may be the same as or smaller than the step D of FIG. 3 (see FIG. 3 ).

The first insulating layer 300 and the second insulating layer 400 may have various thicknesses. The thin film transistor has a tendency to increase in height as the gate electrode GE becomes smaller. The first insulating layer 300 and the second insulating layer 400 may be thickened or thinned to meet the height required by the thin film transistor.

The spacer SW is disposed on the second part 320 of the first insulating layer 300. The spacer SW covers an upper surface 320u of the second portion, a side surface 320w of the first portion, a side surface of the second insulating layer 400, and a side surface of the gate electrode GE.

The plurality of insulating layers 300 and 400 disposed between the gate electrode GE and the semiconductor layer AL reduce a leakage current of the thin film transistor. In order to realize the structure of the thin film transistor, the thickness of the insulating layer disposed between the gate electrode GE and the semiconductor layer AL is reduced. When the thickness of the insulating layer becomes thinner, the capacitance increases, but deterioration is liable to occur and a leakage current is generated. A structure in which a plurality of insulating layers are stacked may prevent deterioration and tunneling, thereby implementing a thin film device with improved reliability.

5 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention taken along line I-I' of FIG. 2. The embodiment shown in FIG. 5 is the same as the embodiment of FIG. 4 except for the difference in the first insulating layer 300-1. Hereinafter, the same reference numerals are assigned to the same components as those described in FIGS. 1 to 4, and detailed descriptions are omitted.

As shown in FIG. 5, the first insulating layer 300-1 and the second insulating layer 400 are sequentially stacked on the semiconductor layer AL. In this case, the first insulating layer 300-1 does not include a step. However, a partial region of the first insulating layer 300-1 is exposed by the gate electrode GE to include a predetermined step D2 between the semiconductor layer AL and the gate electrode GE. An insulating layer is formed.

The first insulating layer 300-1 covers a partial area of the semiconductor layer AL. The first insulating layer 300-1 is disposed in a central region of the semiconductor layer AL to cover at least the channel region CA. In this embodiment, the first insulating layer 300-1 covers the channel region CA and the intermediate region DR. The first insulating layer 300-1 exposes the source region SA and the drain region DA.

The second insulating layer 400 is disposed between the first insulating layer 300-1 and the gate electrode GE. The second insulating layer 400 is disposed on the central region of the semiconductor layer AL and overlaps at least the channel region CA. The second insulating layer 400 may have the same area as the gate electrode GE on a plane.

Since the second insulating layer 400 covers only a partial area of the first insulating layer 300-1, a predetermined step D2 is provided in the insulating layer disposed between the gate electrode GE and the semiconductor layer AL. Is formed. The step D2 is determined by the thickness of the second insulating layer 400.

The first insulating layer 300-1 and the second insulating layer 400 may have various thicknesses. The thin film transistor has a tendency to increase in height as the gate electrode GE becomes smaller. The first insulating layer 300-1 and the second insulating layer 400 may be thickened or thinned to meet the height required by the thin film transistor.

The first insulating layer 300-1 and the second insulating layer 400 are not particularly limited, and may include various insulating materials. The first insulating layer 300-1 and the second insulating layer 400 do not need to be different from each other, but may include, for example, the same material. Alternatively, the first insulating layer 300-1 and the second insulating layer 400 may include the same material as the protective layer 200.

The gate electrode GE is disposed on the second insulating layer 400. The gate electrode GE may have the same area as the second insulating layer 400 on a plane. A side surface of the gate electrode GE may be aligned with a side surface of the second insulating layer 400.

The spacer SW is disposed on the first insulating layer 300. In particular, the spacer SW may be disposed on a region of the first insulating layer 300-1 protruding from the outside of the second insulating layer 400 and the gate electrode GE.

The spacer SW is disposed on a region corresponding to the intermediate region DR of the semiconductor layer AL. The spacer SW covers an area of the first insulating layer 300-1 exposed by the second insulating layer 400, a side surface of the second insulating layer 400, and a side surface of the gate electrode GE. .

The spacer SW may be made of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The spacer SW may be made of the same material as at least one of the first insulating layer 300-1, the second insulating layer 400, and the protective layer 200.

In the thin film transistor according to an embodiment of the present invention, the channel length can be adjusted by adjusting the width of the spacer SW. In this case, the width of the spacer SW may be determined according to a difference in area between the first insulating layer 300-1 and the second insulating layer 400. The spacer SW may secure the length of the channel region CA to prevent a short channel effect of the thin film transistor.

In addition, the spacer SW may reduce parasitic capacitance generated between adjacent pixels. As the spacer SW is added between the gate electrode GE and the gate electrode of an adjacent pixel, the distance between the two gate electrodes may be increased and the capacitance may be reduced. Accordingly, RC delay can be prevented.

6A to 6J are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention. 6A to 6J exemplarily illustrate a method of manufacturing a thin film transistor corresponding to the embodiment disclosed in FIG. 4. Meanwhile, the same reference numerals are assigned to the same configurations as those described in FIGS. 1 to 4.

As shown in FIG. 6A, a protective layer 200 is applied on the base substrate 100. The protective layer 200 may be formed using a chemical vapor deposition method, a plasma deposition method, a sputtering method, or the like.

A layer (ALL: hereinafter, a semiconductor material layer) containing a semiconductor material is applied on the protective layer 200. The semiconductor material layer ALL may include zinc oxide, zinc tin oxide, indium zinc oxide, indium oxide, titanium oxide, indium gallium zinc oxide, or indium zinc tin oxide. The semiconductor material layer ALL is applied on the entire surface of the substrate 100.

A photoresist pattern PR is formed on the semiconductor material layer ALL. The photosensitive layer pattern PR may be formed by coating and exposing a photosensitive layer on the semiconductor material layer ALL. The photoresist pattern PR is formed in a region in which the thin film transistor according to the present invention is to be formed.

As shown in FIGS. 6A and 6B, after forming the photoresist pattern PR, the semiconductor layer AL is formed through an etching process DRY1. Light is irradiated on the photoresist pattern PR or an etching gas is injected. Since the photosensitive layer pattern PR serves as a mask, the semiconductor layer AL is formed in a shape corresponding to the photosensitive layer pattern PR.

As shown in FIG. 6C, a first insulating layer 300 and a second insulating layer 400 are sequentially stacked on the semiconductor layer AL to form. 6C illustrates an embodiment in which the first insulating layer 300 and the second insulating layer 400 are formed to have a similar thickness. However, the present invention is not limited thereto, and the first insulating layer 300 and the second insulating layer 400 may have different thicknesses.

Each of the first insulating layer 300 and the second insulating layer 400 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). Alternatively, each of the first insulating layer 300 and the second insulating layer 400 may be formed as a multilayer thin film.

A gate electrode GE is formed on the second insulating layer 400. The gate electrode GE is formed by laminating and patterning a conductive material on the second insulating layer 400. The gate electrode GE may be formed to overlap the central region of the semiconductor layer AL. Although not shown, the second insulating layer 400 may be omitted. In this case, the gate electrode GE may be directly formed on the first insulating layer.

As illustrated in FIGS. 6D and 6E, after the gate electrode GE is formed, the second insulating layer 400 and a portion of the first insulating layer 300 are etched through an etching process DRY2. The etching process DRY2 may use dry etching.

At this time, the semiconductor layer AL is not exposed by controlling the etching gas and the etching time of the etching process DRY2. Only a part of the first insulating layer 300 may be etched. Accordingly, a step D1 is formed in the first insulating layer 300.

The step D1 separates the first portion 310 (see FIG. 6H) and the second portion 320 (see FIG. 6H) of the first insulating layer 300. The first insulating layer 300 has an outer side lower by the step D1. Accordingly, the first insulating layer 300 has a shape in which a central portion protrudes by the step D1.

The step D1 may be formed in various ways, but has a maximum step difference such that a minimum insulating layer capable of covering the semiconductor layer AL from the etching gas may exist.

As shown in FIG. 6F, after etching the first insulating layer 300 and the second insulating layer 400, an insulating material is applied on the first insulating layer 300 and the second insulating layer 400 An insulating layer INL is formed. The insulating layer INL covers all of the side surfaces of the first insulating layer 300 and the second insulating layer 400 and the gate electrode GE.

As shown in FIG. 6G, the insulating layer INL undergoes an etching process DRY3 to form a spacer SW. The etching process (DRY3) may use a dry etching method. In this case, a part of the first insulating layer 300 is removed by adjusting the etching gas and the etching time of the etching process DRY3.

The etching gas performs anisotropic etching. Since the gate electrode GE serves as a mask, a partial region of the insulating layer INL adjacent to the gate electrode GE remains without being etched. The remaining insulating layer becomes a spacer SW.

The first insulating layer 300 forms the first portion 310 and the second portion 320. The spacer SW is disposed on the second portion 320 and covers a side surface of the first portion 310, a side surface of the second insulating layer 400, and a side surface of the gate electrode GE. do.

The first portion 310 is covered by the gate electrode GE and the second insulating layer 400. Since the gate electrode GE serves as a mask, the first portion 310 has the initial thickness of the first insulating layer 300, that is, the thickness before etching.

The second portion 320 protrudes outward from the first portion 320. The second part 320 is formed by etching a part of the first insulating layer 300 in a previous etching process DRY2, and then etching another part of the first insulating layer 300 in an etching process DRY3. . Since the spacer SW serves as a mask, a part of the first insulating layer 300 disposed under the spacer SW is not etched to form the second part 320. Accordingly, the second portion 320 is formed to have a thickness lower than that of the first portion 310 by the step D (see FIG. 6E).

As illustrated in FIG. 6G, while the first portion 310 and the second portion 320 are formed, a part of the semiconductor layer AL is exposed.

As shown in FIG. 6H, an etching process DRY4 is performed on the exposed partial area of the semiconductor layer AL. Although not shown, the etching process DRY4 may be continuously performed from the previous etching process DRY3, and may be a part of the previous etching process DRY3. In this embodiment, the etching process DRY4 is described as a reduction treatment.

The reduction treatment may include a heat treatment performed in a reducing atmosphere on the semiconductor layer AL. Or, for example, including plasma treatment using gas plasma such as hydrogen, helium, phosphine, ammonia, silane, methane, acetylene, diborane, carbon dioxide, germain, hydrogen selenide, hydrogen sulfide, argon, nitrogen, nitrogen oxide, fluoroform, etc. can do.

In the reduction treatment, the gate electrode GE and the spacer SW serve as a mask. Accordingly, only the exposed area of the semiconductor layer AL may be reduced. Through the reduction treatment, a conductive source region SA and a drain region DA are formed in the semiconductor layer AL.

The source region SA and the drain region DA are formed by reducing some of the materials constituting the semiconductor layer AL. Through the reduction treatment, conductive precipitates are formed in the source region SA and the drain region DA. In this case, when the semiconductor layer AL includes a metal oxide, each of the source region SA and the drain region DA may include a metal precipitate.

A region of the semiconductor layer AL that is not exposed to the etching gas becomes a relatively channel region CA. The channel region CA is formed in a region corresponding to the gate electrode GE.

In this case, the source region SA and the drain region DA may extend to a region overlapping the spacer WS. As the etching gas penetrates into the semiconductor layer AL, it gradually diffuses over time. In this case, an intermediate region DR is formed in the semiconductor layer AL.

The intermediate area DR is an area covered by the spacer WS. However, reduction may proceed in a partial region adjacent to the source region SA or the drain region DA of the intermediate region DR due to diffusion of the etching gas.

Accordingly, each of the source region SA and the drain region DA may include a part of the intermediate region DR. For example, when the reduction treatment time is prolonged, the source region SA or the drain region DA may include the entire middle region DR. Alternatively, the channel region CA may include a part or all of the intermediate region DR.

That is, the spacer SW serves to form the intermediate region DR of the semiconductor layer AL. The spacer SW blocks a region adjacent to the gate electrode GE in the reduction treatment. In addition, the spacer SW protects the channel region CA from diffusion of the source region SA and the drain region DA. The spacer SW may prevent a decrease in channel length that occurs when the gate electrode GE is miniaturized, and may secure a margin so that the channel region CA has a length corresponding to the gate electrode GE. .

As illustrated in FIG. 6I, a passivation layer PS is formed on the passivation layer 200. The passivation layer PS includes the passivation layer 200, the semiconductor layer AL, a side surface of the second portion 320 of the first insulating layer 300, the spacer SW, and the gate electrode GE. ) To cover all.

It is formed by applying an insulating film using the passivation layer (PS) deposition method or sputtering method. The passivation layer PS may be formed of an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and aluminum nitride. The passivation layer PS may be formed as a single layer or a multilayer thin film.

As illustrated in FIG. 6J, a plurality of contact holes CH1 and CH2 are formed in the passivation layer PS. The first contact hole CH1 penetrates the passivation layer PS to expose the source region SA. The second contact hole CH2 penetrates the passivation layer PS to expose the drain region DA. The contact holes CH1 and CH2 may be formed by patterning the passivation PS.

A source electrode SE and a drain electrode DE are formed on the passivation layer PS. The source electrode SE is formed to overlap the source region SA, and the drain electrode DE is formed to overlap the drain region DA. The source electrode SE is connected to the source region SA through the first contact hole CH1, and the drain electrode GE is the drain region DA through the second contact hole CH2. Is connected to

The thin film transistor according to the present invention may protect the channel region CA to have a length corresponding to the gate electrode GE by including the spacer SW. In the step of forming the source region SA and the drain region DA, even if the source region SA and the drain region DA are diffused, the intermediate region DR formed by the spacer SW ), the channel area CA may be protected.

7A to 7J are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention. 7A to 7J illustrate a method of manufacturing a thin film transistor corresponding to the embodiment disclosed in FIG. 5 by way of example. Meanwhile, the same reference numerals are assigned to the same components as those described in FIGS. 1 to 6J, and redundant descriptions are omitted.

As shown in FIGS. 7A to 7C, a protective layer 200 and a semiconductor material layer ALL may be sequentially formed on the base substrate 100. In this case, the passivation layer 200 may function as a buffer layer preventing a phenomenon in which foreign substances are injected from the base substrate 100 to the semiconductor material layer ALL.

When the photosensitive pattern PR is disposed and the etching process DRY1 is performed on the photosensitive pattern PR, the semiconductor layer AL is formed. Since this is duplicated with the contents described in FIGS. 6A to 6B, detailed descriptions are omitted.

A first insulating layer 300 and a second insulating layer 400 are sequentially applied on the semiconductor layer AL. A gate electrode GE is formed by patterning a conductive material on the second insulating layer 400.

In this case, the first insulating layer 300 may be formed to have a thickness smaller than that of the second insulating layer 400. For example, the first insulating layer 300 may be formed to have a minimum thickness to protect the semiconductor layer AL from an external environment.

As shown in FIGS. 7D and 7E, a part of the second insulating layer 400 is removed through an etching process DRY2. In this case, the gate electrode GE serves as a mask. The etching process DRY2 may include an exposure process or a dry etching process. When the etching process DRY2 is a dry etching process, only the second insulating layer 400 is removed by adjusting an etching gas and an etching time.

As shown in FIGS. 7F and 7G, an insulating layer INL is applied on the first insulating layer 300. The insulating layer INL covers all of the first insulating layer 300, a side surface of the second insulating layer 400, and the gate electrode GE.

The semiconductor layer AL is exposed on the insulating layer INL through an etching process DRY3. The etching process DRY3 may include a dry etching process. In the etching process DRY3, the gate electrode GE serves as a mask.

In addition, dry etching generally exhibits anisotropic etching. Accordingly, the insulating layer adjacent to the gate electrode GE is not removed but remains to form the spacer SW. The width of the spacer has a size corresponding to the thickness of the first insulating layer 300 to be etched. Accordingly, by adjusting the variables of the etching process, the width of the spacer SW can be adjusted.

As shown in FIG. 7G, the first insulating layer 300-1 and the second insulating layer 400 form a predetermined step D2. The step D2 is formed by selectively etching the second insulating layer 400 in a previous etching process (DRY2: see FIG. 7E). Accordingly, the step D2 may correspond to the thickness of the second insulating layer 400.

As shown in FIG. 7H, a source region SA and a drain region DA are formed on the exposed semiconductor layer AL through an etching process DRY4. In this embodiment, the etching process DRY4 is described as a reduction treatment. The reduction treatment may include a heat treatment performed in a reducing atmosphere on the semiconductor layer AL. This is the same as that described in Fig. 6H, and thus will be omitted.

7I and 7J, a passivation layer PS covering the first insulating layer 300, the gate electrode GE, the source region SA, and the gate region GE is formed. . A first contact hole CH1 is formed in a region corresponding to the source region SA of the passivation layer PS, and a second contact hole CH2 is formed in a region corresponding to the drain region DA. .

A source electrode SE and a drain electrode DE are formed on the passivation layer PS. The source electrode SE and the drain electrode DE cover the first contact hole CH1 and the second contact hole CH2, respectively. The source electrode SE and the drain electrode DE are respectively connected to the source region SA and the drain region DA through contact holes. A detailed description of this will be omitted since it is duplicated in FIGS. 6I and 6J.

In the method of manufacturing a thin film transistor according to an embodiment of the present invention, an insulating film having a stepped difference is formed between a gate electrode and a semiconductor layer, and a spacer is formed on the insulating film and covering a side surface of the gate electrode. Accordingly, in a high-resolution display panel in which the gate electrode is miniaturized, an effective channel length can be secured and parasitic capacitance between adjacent pixels can be reduced to prevent a decrease in response speed.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art or those of ordinary skill in the art will not depart from the spirit and scope of the present invention described in the claims to be described later. It will be appreciated that various modifications and changes can be made to the present invention within the scope of not.

Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: substrate 200: protective film
300: first insulating film 400: second insulating film
AL: semiconductor layer SA: source region
DA: drain region CA: channel region
DR: middle area SW: spacer
GE: gate electrode

Claims (20)

A semiconductor layer disposed on a base substrate and including a source region, a drain region, and a channel region disposed between the source region and the drain region;
A source electrode connected to the source region;
A drain electrode connected to the drain region;
A gate electrode disposed on the semiconductor layer;
A first insulating layer disposed between the gate electrode and the semiconductor layer and including a first portion covered by the gate electrode, and a second portion exposed from the gate electrode and forming a step difference from the first portion; And
A spacer disposed on the second part and disposed at an edge of the first part,
When viewed in plan view, the first insulating layer and the spacer are non-overlapping with the source region and the drain region. The method of claim 1,
The semiconductor layer is a thin film transistor, characterized in that the oxide semiconductor layer. The method of claim 2,
At least one of the source region and the drain region comprises a precipitate of the oxide semiconductor. The method of claim 2,
And a second insulating layer disposed between the semiconductor layer and the base substrate.
The method of claim 4,
Further comprising a third insulating film disposed between the first insulating film and the gate electrode,
The spacer is disposed on the second portion, and is disposed at the edges of the first portion and the third insulating layer. The method of claim 1,
The thin film transistor, characterized in that the spacer is transparent. The method of claim 5,
The spacer includes the same material as at least one of the first insulating layer, the second insulating layer, and the third insulating layer. A semiconductor layer disposed on a base substrate and including a source region, a drain region, and a channel region disposed between the source region and the drain region;
A source electrode connected to the source region;
A drain electrode connected to the drain region;
A gate electrode connected to the semiconductor layer;
A first insulating layer disposed between the gate electrode and the semiconductor layer and overlapping the gate electrode;
A second insulating film disposed between the first insulating film and the semiconductor layer and including a region exposed from the gate electrode on a plane; And
A spacer disposed on the exposed area of the second insulating layer and disposed at an edge of the first insulating layer,
On a plane, the second insulating layer and the spacer are non-overlapping with the source region and the drain region. The method of claim 8,
And a third insulating layer disposed between the semiconductor layer and the base substrate. Forming a semiconductor layer including a channel region on a substrate;
Applying an insulating layer on the semiconductor layer;
Forming a gate electrode on the insulating layer;
A second portion including a first portion overlapping the gate electrode by etching the insulating layer, and a second portion extending outward of the first portion to be exposed from the gate electrode and forming a step difference from the first portion 1 forming an insulating film;
Forming a spacer disposed on the second portion and disposed at an edge of the first portion; And
Forming a source region and a drain region on the semiconductor layer facing each other with the channel region therebetween and non-overlapping with the first insulating film and the spacer when viewed in a plan view. The method of claim 10,
The step of forming the semiconductor layer,
Forming a protective film on the substrate; And
And applying a semiconductor material layer on the protective layer and patterning the semiconductor material layer. The method of claim 10,
The forming of the source region and the drain region,
Exposing a portion of the semiconductor layer; And
A method of manufacturing a thin film transistor comprising the step of reducing the exposed semiconductor layer. The method of claim 12,
Forming a passivation layer covering the source region, the drain region, and the gate electrode;
Forming a source electrode disposed on the passivation layer, passing through the passivation layer, and connected to the source region; And
Forming a drain electrode disposed on the passivation layer and passing through the passivation layer and connected to the drain region. The method of claim 10,
Forming the first insulating layer,
Forming the first portion forming the step by etching a portion of the first insulating layer; And
And exposing the upper surface of the second portion. The method of claim 14,
The step of forming the spacer,
Applying an insulating material layer on the gate electrode and the first insulating layer; And
Etching the insulating material layer and the first insulating layer to expose a partial area of the semiconductor layer,
The partial region is at least one of the source region and the drain region. Forming a semiconductor layer including a channel region on a substrate;
Applying a first insulating layer on the semiconductor layer;
Applying a second insulating layer on the first insulating layer;
Forming a gate electrode on the second insulating layer;
Etching the second insulating layer to expose a portion of the first insulating layer from the gate electrode;
Forming a spacer disposed on the first insulating layer and surrounding the second insulating layer; And
And forming a source region and a drain region on the semiconductor layer facing each other with the channel region interposed therebetween and non-overlapping with the first insulating layer and the spacer when viewed in a plan view. A first substrate on which a plurality of signal lines are disposed;
A second substrate disposed on the first substrate; And
A plurality of pixels each including a thin film transistor connected to corresponding signal lines among the plurality of signal lines,
The thin film transistor,
A first insulating layer disposed on the first substrate;
A semiconductor layer disposed on the first insulating layer and including a source region, a drain region, and a channel region disposed between the source region and the drain region;
A gate electrode disposed on the semiconductor layer, a source electrode connected to the source region, and a drain electrode connected to the drain region;
A second insulating film disposed between the gate electrode and the semiconductor layer and including a first portion overlapping the gate electrode, and a second portion exposed from the gate electrode and forming a step difference from the first portion; And
A spacer disposed on the second part and disposed at an edge of the first part,
When viewed from a plan view, the second insulating layer and the spacer are non-overlapping with the source region and the drain region. The method of claim 17,
And a liquid crystal layer sealed between the first substrate and the second substrate. The method of claim 17,
Further comprising a third insulating film disposed between the second insulating film and the gate electrode,
The third insulating layer overlaps the first portion, and the spacer is disposed at an edge of the third insulating layer and the first portion. The method of claim 17,
The display panel, wherein the spacer is transparent.

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