TWI796200B - Active device substrate - Google Patents

Abstract

An active device substrate includes a substrate, a first semiconductor layer, a gate insulating layer, a first gate electrode, a first source electrode, a first drain electrode and a shielding electrode. The first semiconductor layer includes a first heavily doped region, a first lightly doped region, a channel region, a second lightly doped region, and a second heavily doped region that are sequentially connected. The first gate is located on the gate insulating layer and overlaps the channel region. The first source is electrically connected to the first heavily doped region. The first drain is electrically connected to the second heavily doped region. The shielding electrode overlaps the second lightly doped region in the normal direction of the substrate.

Description

Active component substrate

The invention relates to an active component substrate.

Generally speaking, electronic devices contain many semiconductor elements. For example, a display device often includes many thin film transistors, and these thin film transistors are formed by depositing various thin films (such as semiconductors, metals, dielectric layers, etc.) on a substrate. In the display device, the thin film transistor can be arranged in the pixel structure, and can also be arranged in the driving circuit.

With the advancement of technology, the critical size (Critical size) of various process technologies is gradually reduced. In order to manufacture smaller thin film transistors, the distance between different electrodes of the thin film transistors is gradually reduced, which increases the negative impact of the electric field between different electrodes on the quality of the thin film transistors.

The invention provides an active component substrate, which can improve the hot carrier effect of the active component.

At least one embodiment of the present invention provides an active device substrate. The active device substrate includes a substrate, a first semiconductor layer, a gate insulating layer, a first gate, a first source, a first drain and a shielding electrode. The first semiconductor layer is located on the substrate and includes a first heavily doped region, a first lightly doped region, a channel region, a second lightly doped region and a second heavily doped region connected in sequence. The gate insulating layer is located on the first semiconductor layer. The first gate is located on the gate insulating layer and overlaps the channel region of the first semiconductor layer in a normal direction of the substrate. The first source is electrically connected to the first heavily doped region of the first semiconductor layer. The first drain is electrically connected to the second heavily doped region of the first semiconductor layer. The first active device includes a first semiconductor layer, a first gate, a first source and a first drain. The shielding electrode overlaps the second lightly doped region of the first semiconductor layer in the normal direction of the substrate, wherein the shielding electrode is a floating electrode.

At least one embodiment of the present invention provides an active device substrate. The active device substrate includes a substrate, a semiconductor pattern, a gate insulating layer, a first conductive layer, a first dielectric layer, a shielding electrode, a second dielectric layer and a second conductive layer. The semiconductor pattern is located on the substrate and includes a first semiconductor layer. The first semiconductor layer includes a first heavily doped region, a first lightly doped region, a channel region, a second lightly doped region and a second heavily doped region connected in sequence. A gate insulating layer is formed on the semiconductor pattern. The first conductive layer is formed on the gate insulating layer and includes a first gate. The first gate overlaps the channel region of the first semiconductor layer in the normal direction of the substrate. The first dielectric layer is formed on the first conductive layer and the gate insulating layer. The shielding electrode is formed on the first dielectric layer and overlaps the second lightly doped region of the first semiconductor layer in the normal direction of the substrate. The second dielectric layer is formed on the first dielectric layer and the shielding electrode. The second conductive layer is formed on the second dielectric layer and includes a first source and a first drain. The first source is electrically connected to the first heavily doped region of the first semiconductor layer. The first drain is electrically connected to the second heavily doped region of the first semiconductor layer.

Based on the above, through the arrangement of the shielding electrode, the electric field between the second heavily doped region and the first gate can be dispersed by the shielding electrode, thereby improving the hot carrier effect of the active device.

FIG. 1A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of line A-A' in Fig. 1A.

1A and 1B, the active device substrate 10 includes a substrate 100, a semiconductor pattern 110, a gate insulating layer 120, a first conductive layer 130, a first dielectric layer 140, an auxiliary conductive layer 150, and a second dielectric layer 160. and the second conductive layer 170 . In this embodiment, the first active device T1 is located on the substrate 100 and includes a first semiconductor layer 112 , a first gate 132 , a first source 172 and a first drain 174 .

The material of the substrate 100 includes glass, quartz, organic polymer, or opaque/reflective material (eg, conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. The buffer layer 102 is formed on the substrate 100 . The buffer layer 102 includes, for example, a single or multiple insulating layers.

The semiconductor pattern 110 includes a first semiconductor layer 112 . In this embodiment, the semiconductor pattern 110 further includes a first capacitor electrode C1. The semiconductor pattern 110 is located on the substrate 100 . In some embodiments, the semiconductor pattern 110 is formed on the buffer layer 102 . For example, the first semiconductor layer 112 and the first capacitor electrode C1 are directly deposited on the buffer layer 102 . In some embodiments, the material of the semiconductor pattern 110 includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (for example: indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above), III-V compound semiconductors, or other suitable materials or a combination of the above materials.

The first semiconductor layer 112 is a doped semiconductor layer, and includes a first heavily doped region 112A, a first lightly doped region 112B, a channel region 112C, a second lightly doped region 112D and a second heavily doped region connected in sequence. Doped region 112E. The channel region 112C is located between the first lightly doped region 112B and the second lightly doped region 112D, the first lightly doped region 112B is located between the first heavily doped region 112A and the channel region 112C, and the second lightly doped region The region 112D is located between the second heavily doped region 112E and the channel region 112C. The doping concentration of the first heavily doped region 112A and the second heavily doped region 112E is greater than the doping concentration of the first lightly doped region 112B and the second lightly doped region 112D, and the first lightly doped region 112B and the second lightly doped region 112B The doping concentration of the second lightly doped region 112D is greater than that of the channel region 112C. The first semiconductor layer 112 is a P-type semiconductor or an N-type semiconductor.

The first capacitor electrode C1 is a doped semiconductor, and the doping concentration of the first capacitor electrode C1 is, for example, approximately equal to the doping concentration of the first heavily doped region 112A and the second heavily doped region 112E.

A gate insulating layer 120 is formed on the semiconductor pattern 110 . In this embodiment, the gate insulating layer 120 is formed on the first semiconductor layer 112 , the first capacitor electrode C1 and the buffer layer 102 . For example, the gate insulating layer 120 is directly deposited on the first semiconductor layer 112 and the buffer layer 102 . The material of the gate insulating layer 120 includes, for example, inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or stacked layers of at least two of the above materials), organic materials or Other suitable materials or combinations of the above. In this embodiment, the thickness t1 of the gate insulating layer 120 is 50 nm to 150 nm.

The first conductive layer 130 includes a first gate 132 . In this embodiment, the first conductive layer 130 further includes a second capacitive electrode C2. The first conductive layer 130 is formed on the gate insulating layer 120 . For example, the first gate 132 and the second capacitor electrode C2 are directly deposited on the gate insulating layer 120 and directly contact the upper surface of the gate insulating layer 120 . The material of the first conductive layer 130 includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, alloys of the aforementioned metals or stacked layers of the aforementioned metals, or other conductive materials . The first gate 132 overlaps the channel region 112C of the first semiconductor layer 112 in the normal direction ND of the substrate 100 . In some embodiments, the method for forming the first lightly doped region 112B and the second lightly doped region 112D of the first semiconductor layer 112 includes performing an ion implantation process using the first gate 132 as a mask. Therefore, the second A gate 132 is aligned with the channel region 112C of the first semiconductor layer 112 in the normal direction ND. In addition, FIG. 1A omits the signal line connected to the first gate 132 . In some embodiments, the signal line (not shown) connected to the first gate 132 and the first gate 132 both belong to the first conductive layer 130, and both are integrated, but the present invention is not limited thereto. . In other embodiments, the signal line (not shown) connected to the first gate 132 and the first gate 132 belong to different conductive layers, and are connected to each other through via holes penetrating more than one insulating layer.

The second capacitive electrode C2 overlaps the first capacitive electrode C1 in the normal direction ND of the substrate 100 .

In some embodiments, besides the first gate 132 and the capacitor electrode C2 , the first conductive layer 130 also includes other conductive structures, such as signal lines or other electrodes.

The first dielectric layer 140 is formed on the first conductive layer 130 and the gate insulating layer 120 . In some embodiments, the first dielectric layer 140 is directly deposited on the first conductive layer 130 and the gate insulating layer 120 , and directly contacts the upper surface of the first gate 132 and the upper surface of the gate insulating layer 120 . The material of the first dielectric layer 140 includes, for example, inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or stacked layers of at least two of the above materials), organic materials Or other suitable materials or combinations of the above. In this embodiment, the thickness t2 of the first dielectric layer 140 is 50 nm to 300 nm.

The auxiliary conductive layer 150 includes a shielding electrode 152 . In this embodiment, the auxiliary conductive layer 150 further includes a third capacitive electrode C3. The auxiliary conductive layer 150 is formed on the first dielectric layer 140 . For example, the shielding electrode 152 and the third capacitor electrode C3 are directly deposited on the first dielectric layer 140 and directly contact the upper surface of the first dielectric layer 140 . The shielding electrode 152 overlaps the second lightly doped region 112D of the first semiconductor layer 112 in the normal direction ND of the substrate 100 . In some embodiments, the shielding electrode 152 completely covers the second lightly doped region 112D in the normal direction ND of the substrate 100 . In this embodiment, the vertical distance D1 between the shielding electrode 152 and the second lightly doped region 112D of the first semiconductor layer 112 is 100 nm to 450 nm. The material of the auxiliary conductive layer 150 is the same as or different from that of the first conductive layer 130 . In this embodiment, the material of the auxiliary conductive layer 150 is the same as that of the first conductive layer 130, and includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, Zinc, alloys of the aforementioned metals, stacked layers of the aforementioned metals, or other conductive materials.

In this embodiment, the shielding electrode 152 is a floating electrode. In other words, in this embodiment, the shielding electrode 152 is not connected to the signal line, and no voltage is directly applied to the shielding electrode 152 .

The third capacitive electrode C3 overlaps the first capacitive electrode C1 and the second capacitive electrode C2 in the normal direction ND of the substrate 100 .

In some embodiments, besides the shielding electrode 152 and the third capacitive electrode C3 , the auxiliary conductive layer 150 also includes other conductive structures, such as signal lines or other electrodes.

In this embodiment, since the shielding electrode 152 and the third capacitor electrode C3 are formed on the same conductive layer, the number of photomasks required for the manufacturing process can be saved.

In this embodiment, the second dielectric layer 160 is formed on the first dielectric layer 140 and the auxiliary conductive layer 150 . For example, the second dielectric layer 160 is directly deposited on the first dielectric layer 140, the shielding electrode 152 and the third capacitive electrode C3, and directly contacts the upper surface of the first dielectric layer 140 and the upper surface of the shielding electrode 152. and the upper surface of the third capacitive electrode C3. The material of the second dielectric layer 160 includes, for example, inorganic materials (for example: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, other suitable materials, or stacked layers of at least two of the above materials), organic materials Or other suitable materials or combinations of the above. In this embodiment, the thickness t3 of the second dielectric layer 160 is 50 nm to 600 nm.

The second conductive layer 170 includes a first source 172 and a first drain 174 . The second conductive layer 170 is formed on the second dielectric layer 160 . For example, the first source 172 and the first drain 174 are directly deposited on the second dielectric layer 160 and directly contact the upper surface of the second dielectric layer 160 . The material of the second conductive layer 170 is the same as or different from that of the auxiliary conductive layer 150 . In this embodiment, the material of the second conductive layer 170 is different from that of the auxiliary conductive layer 150, and the second conductive layer 170 includes chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum , aluminum, zinc, alloys of the aforementioned metals or stacked layers of the aforementioned metals, or other conductive materials.

The first source 172 is electrically connected to the first heavily doped region 112A of the first semiconductor layer 112 . In this embodiment, the first source 172 is electrically connected to the first source electrode 172 through the through hole TH1 of the gate insulating layer 120, the through hole TH2 of the first dielectric layer 140, and the through hole TH3 of the second dielectric layer 160. heavily doped region 112A. In this embodiment, the through hole TH1 , the through hole TH2 and the through hole TH3 completely overlap each other, but the invention is not limited thereto. In other embodiments, the through hole TH1 , the through hole TH2 and the through hole TH3 may partially overlap each other.

The first drain 174 is electrically connected to the second heavily doped region 112E of the first semiconductor layer 112 . In this embodiment, the first drain electrode 174 is electrically connected to the first drain electrode 174 through the through hole TH4 of the gate insulating layer 120, the through hole TH5 of the first dielectric layer 140, and the through hole TH6 of the second dielectric layer 160. heavily doped region 112E. In this embodiment, the through hole TH4 , the through hole TH5 and the through hole TH6 completely overlap each other, but the invention is not limited thereto. In other embodiments, the through hole TH4 , the through hole TH5 and the through hole TH6 may partially overlap each other.

In this embodiment, when a voltage is applied to the first gate 132 and the first drain 174, an electric field will be formed between the first heavily doped region 112E and the first gate 132 (as shown by the dotted arrow in the drawing ). In this embodiment, the shielding electrode 152 can be used to disperse the electric field between the first heavily doped region 112E and the first gate 132 to reduce the electric field between the first heavily doped region 112E and the first gate 132 , so as to improve the influence of the hot carrier effect on the first active device T1 and prevent the first active device T1 from deteriorating due to the hot carrier effect. In some embodiments, regardless of whether the first active element T1 is a P-type thin film transistor or an N-type thin film transistor, the shielding electrode 152 can be used to disperse the electric field between the semiconductor layer and the gate, thereby improving the effect of hot carriers on the The influence caused by the first active element T1.

The passivation layer 180 is formed on the second conductive layer 170 and covers the first active device T1.

Based on the above, through the arrangement of the shielding electrode 152 , the hot carrier effect of the first active device T1 can be reduced, thereby improving the degradation problem of the first active device T1 . In addition, by forming the shielding electrode 152 and the third capacitor electrode C3 on the same conductive layer, the manufacturing cost of the device can be saved.

FIG. 2A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view of line B-B' in Fig. 2A. Fig. 2C is a schematic cross-sectional view of line C-C' in Fig. 2A.

It must be noted here that the embodiment of FIG. 2A to FIG. 2C follows the component numbers and part of the content of the embodiment of FIG. 1A and FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

2A to 2C, in this embodiment, the active device substrate 20 includes a substrate 100, a semiconductor pattern 110, a gate insulating layer 120, a first conductive layer 130, a first dielectric layer 140, an auxiliary conductive layer 150, The second dielectric layer 160 and the second conductive layer 170 . In this embodiment, the first active device T1 and the second active device T2 are located on the substrate 100 . The first active device T1 includes a first semiconductor layer 112 , a first gate 132 , a first source 172 and a first drain 174 . The second active device T2 includes a second semiconductor layer 114 , a second gate 134 , a second source 176 and a second drain 178 .

In this embodiment, the semiconductor pattern 110 includes a first semiconductor layer 112 and a second semiconductor layer 114 .

The second semiconductor layer 114 is a doped semiconductor layer, and includes a first heavily doped region 114A, a first lightly doped region 114B, a channel region 114C, a second lightly doped region 114D and a second heavily doped region connected in sequence. Doped region 114E. The channel region 114C is located between the first lightly doped region 114B and the second lightly doped region 114D, the first lightly doped region 114B is located between the first heavily doped region 114A and the channel region 114C, and the second lightly doped region Region 114D is located between second heavily doped region 114E and channel region 114C. The doping concentration of the first heavily doped region 114A and the second heavily doped region 114E is greater than the doping concentration of the first lightly doped region 114B and the second lightly doped region 114D, and the first lightly doped region 114B and the second lightly doped region 114B The doping concentration of the second lightly doped region 114D is greater than that of the channel region 114C. The first semiconductor layer 114 is a P-type semiconductor or an N-type semiconductor.

Although in this embodiment, the first semiconductor layer 112 and the second semiconductor layer 114 belong to the same film layer (both belong to the semiconductor pattern 110 ) and are formed at the same time, the present invention is not limited thereto. In other embodiments, the first semiconductor layer 112 and the second semiconductor layer 114 include different materials, and the first semiconductor layer 112 and the second semiconductor layer 114 belong to different film layers (that is, the semiconductor pattern 110 includes the first semiconductor layer 112, but The semiconductor pattern 110 does not include the second semiconductor layer 114 , in other words, the first semiconductor layer 112 and the second semiconductor layer 114 can be formed by different patterning processes).

The first conductive layer 130 includes a first gate 132 and a second gate 134 . The second gate 134 overlaps the second semiconductor layer 114 in the normal direction ND of the substrate 100 . In some embodiments, the method for forming the first lightly doped region 114B and the second lightly doped region 114D of the second semiconductor layer 114 includes performing an ion implantation process using the second gate 134 as a mask. The second gate 134 is aligned with the channel region 114C of the second semiconductor layer 114 in the normal direction ND.

In this embodiment, the first conductive layer 130 further includes scan lines SL. The scan line SL is connected to the second gate 134 .

The second conductive layer 170 includes a first source 172 , a first drain 174 , a second source 176 and a second drain 178 .

The second source 176 is electrically connected to the first heavily doped region 114A of the second semiconductor layer 114 . In this embodiment, the second source 176 is electrically connected to the first through hole TH7 of the gate insulating layer 120, the through hole TH8 of the first dielectric layer 140, and the through hole TH9 of the second dielectric layer 160. heavily doped region 114A. In this embodiment, the through hole TH7 , the through hole TH8 and the through hole TH9 completely overlap each other, but the invention is not limited thereto. In other embodiments, the through hole TH7 , the through hole TH8 and the through hole TH9 may partially overlap each other.

The second drain 178 is electrically connected to the second heavily doped region 114E of the second semiconductor layer 114 . In this embodiment, the second drain 178 is electrically connected to the first through hole TH10 of the gate insulating layer 120 , the through hole TH11 of the first dielectric layer 140 and the through hole TH12 of the second dielectric layer 160 . heavily doped region 114E. In this embodiment, the through holes TH10 , the through holes TH11 and the through holes TH12 completely overlap each other, but the invention is not limited thereto. In other embodiments, the through hole TH10 , the through hole TH11 and the through hole TH12 may partially overlap each other.

The second drain 178 is electrically connected to the first gate 132 . For example, the second through hole TH13 in the first dielectric layer 140 and the through hole TH14 in the second dielectric layer 160 are electrically connected to the first gate 132 . In this embodiment, the through holes TH13 and the through holes TH14 completely overlap each other, but the invention is not limited thereto. In other embodiments, the through hole TH13 and the through hole TH14 may partially overlap each other.

In this embodiment, the second conductive layer 170 further includes data lines DL and signal lines VL. The data line DL is connected to the second source 176 , and the signal line VL is connected to the first source 172 .

The passivation layer 180 is formed on the second conductive layer 170 and covers the first active device T1 and the second active device T2 .

The electrode PE is located on the passivation layer 180 and is electrically connected to the first drain 174 of the first active device T1 through the opening O of the passivation layer 180 . The electrode PE can be used, for example, to control liquid crystals, light emitting diodes, photosensitive elements or other electronic elements.

In this embodiment, the shielding electrode 152 overlaps the second lightly doped region 112D of the first semiconductor layer 112 and the first gate 132 in the normal direction ND of the substrate 100 . Part of the first gate 132 is located between the shielding electrode 152 and the first semiconductor layer 112 . Therefore, in addition to improving the impact of the hot carrier effect on the first active device T1 , the shielding electrode 152 can also be used to increase the capacitance in the first active device T1 .

FIG. 3A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view of line D-D' in Fig. 3A.

It must be noted here that the embodiment in Figure 3A and Figure 3B continues to use the element numbers and parts of the embodiment in Figure 1A and Figure 1B, where the same or similar symbols are used to represent the same or similar elements, and the same or similar elements are omitted. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 3A and FIG. 3B , the shielding electrode 152 of the active device substrate 30 overlaps the first lightly doped region 112B, the channel region 112C, and the second lightly doped region 112 of the first semiconductor layer 112 in the normal direction ND of the substrate 100 . region 112D and the first gate 132 . In this embodiment, in addition to improving the impact of the hot carrier effect on the first active element T1, the shielding electrode 152 can also be used to increase the capacitance in the first active element T1 (the shielding electrode 152 and the first gate capacitance between 132).

In this embodiment, the shielding electrode 152 extends from above the second lightly doped region 112D to above the first lightly doped region 112B, thereby increasing the overlapping area between the shielding electrode 152 and the first gate 132 . Based on this, the capacitance between the shielding electrode 152 and the first gate 132 is increased.

FIG. 4A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 4B is a schematic cross-sectional view of line E-E' in Fig. 4A.

It must be noted here that the embodiment of FIG. 4A and FIG. 4B continues to use the component numbers and part of the content of the embodiment of FIG. 4A and FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Referring to FIG. 4A and FIG. 4B , in the active device substrate 40 , the second conductive layer 170 includes a shielding electrode 173 , and the second conductive layer 170 is formed on the second dielectric layer 160 . For example, the first source 172 , the shielding electrode 173 and the first drain 174 are directly deposited on the second dielectric layer 160 and directly contact the upper surface of the second dielectric layer 160 . The material of the second conductive layer 170 is the same as or different from that of the first conductive layer 130 . The first source 172 , the shielding electrode 173 and the first drain 174 are the same conductive layer and are formed at the same time. The shielding electrode 173 is separated from the first source 172 and the first drain 174 . The shielding electrode 173 is located between the first source 172 and the first drain 174 . The horizontal distance HD1 between the shielding electrode 173 and the first source electrode 172 depends on the exposure limit (or critical dimension (CD)) of the tool used in the patterning process. For example, the horizontal distance HD1 is greater than or equal to the combination of the aforementioned exposure limit and the length of the channel region 112C, and the horizontal distance HD2 between the shielding electrode 173 and the first drain 174 is greater than or equal to the aforementioned exposure limit. In some embodiments, the horizontal distance HD1 between the shielding electrode 173 and the first source 172 is greater than the horizontal distance HD2 between the shielding electrode 173 and the first drain 174 .

The shielding electrode 173 overlaps the second lightly doped region 112D of the first semiconductor layer 112 in the normal direction ND of the substrate 100 . In some embodiments, the shielding electrode 173 completely covers the second lightly doped region 112D in the normal direction ND of the substrate 100 . In this embodiment, the vertical distance D1' between the shielding electrode 173 and the second lightly doped region 112D of the first semiconductor layer 112 is 100 nm to 1000 nm. In this embodiment, the shielding electrode 173 is a floating electrode. In other words, in this embodiment, the shielding electrode 173 is not connected to other signal lines, and no voltage is directly applied to the shielding electrode 173 .

Based on the above, through the arrangement of the shielding electrode 173 , the hot carrier effect of the first active device T1 can be reduced, thereby improving the degradation problem of the first active device T1 . In addition, by forming the first source electrode 172 , the shielding electrode 173 and the first drain electrode 174 on the same conductive layer, the number of photomasks required for the process can be saved.

FIG. 5A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 5B is a schematic cross-sectional view of line F-F' in Fig. 5A.

It must be noted here that the embodiment in Figure 5A and Figure 5B continues to use the element numbers and parts of the embodiment in Figure 1A and Figure 1B, where the same or similar symbols are used to indicate the same or similar elements, and the same elements are omitted. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 5A and FIG. 5B , in the active device substrate 50 , the shielding electrode 152 is electrically connected to the first drain 174 .

The first drain 174 is electrically connected to the first heavily doped through hole TH4 of the gate insulating layer 120 , the through hole TH5 of the first dielectric layer 140 and the through hole TH6 of the second dielectric layer 160 which are sequentially connected. Miscellaneous region 112E. In this embodiment, the through hole TH6 overlaps the through hole TH5 and the through hole TH4 in the normal direction ND of the substrate 100 , and the size of the through hole TH6 is larger than the size of the through hole TH5 and the through hole TH4 .

In some embodiments, a portion of the shielding electrode 152 is located between the first dielectric layer 140 and the through hole TH6. In some embodiments, the method of forming the through hole TH4, the through hole TH5 and the through hole TH6 is, for example, forming a mask layer on the second dielectric layer 160, and the mask layer has an opening whose size corresponds to that of the through hole TH6, And the opening partially overlaps the shielding electrode 152 . Based on the etching of the second dielectric layer 160, the first dielectric layer 140 and the gate insulating layer 120 based on the aforementioned openings, since the shielding electrode 152 can protect the first dielectric layer 140 and the gate insulating layer 120 located therebelow, the etching process The size of the through hole TH6 of the formed second dielectric layer 160 is larger than the size of the through hole TH5 of the first dielectric layer 140 and the size of the through hole TH4 of the gate insulating layer 120

Based on the above, through the arrangement of the shielding electrode 152 , the hot carrier effect of the first active device T1 can be reduced, thereby improving the degradation problem of the first active device T1 . .

FIG. 6A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 6B is a schematic cross-sectional view of line G-G' in Fig. 6A.

It must be noted here that the embodiment of FIG. 6A and FIG. 6B continues to use the component numbers and part of the content of the embodiment of FIG. 5A and FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 6A and FIG. 6B , the shielding electrode 152 of the active device substrate 60 overlaps the first lightly doped region 112B, the channel region 112C, and the second lightly doped region 112 of the first semiconductor layer 112 in the normal direction ND of the substrate 100 . region 112D and the first gate 132 . In this embodiment, the shielding electrode 152 can not only improve the impact of the hot carrier effect on the first active element T1, but also be used to increase the capacitance in the first active element T1.

In this embodiment, the shielding electrode 152 extends from above the second lightly doped region 112D to above the first lightly doped region 112B, thereby increasing the overlapping area between the shielding electrode 152 and the first gate 132 . Based on this, the capacitance between the shielding electrode 152 and the first gate 132 is increased.

FIG. 7A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 7B is a schematic cross-sectional view taken along the line H-H' of Fig. 7A.

It must be noted here that the embodiment in Figure 7A and Figure 7B continues to use the component numbers and parts of the embodiment in Figure 1A and Figure 1B, wherein the same or similar symbols are used to represent the same or similar components, and the same or similar components are omitted. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 7A and FIG. 7B , in the active device substrate 70 , the shielding electrode 152 is electrically connected to the first source 172 .

The gate insulating layer 120 has a through hole TH1 in it, the first dielectric layer 140 has a through hole TH2 in it, and the second dielectric layer 160 has a through hole TH3 in it. The first source electrode 172 is electrically connected to the first heavily doped electrode through the through hole TH1 of the gate insulating layer 120, the through hole TH2 of the first dielectric layer 140, and the through hole TH3 of the second dielectric layer 160 connected in sequence. heterogeneous region 112A. In addition, the first source electrode 172 is electrically connected to the shielding electrode 152 through the through hole TH15 of the second dielectric layer 160 .

In this embodiment, the first source electrode 172 overlaps the first lightly doped region 112B, the channel region 112C and the second lightly doped region 112D in the normal direction ND of the substrate 100 .

Based on the above, through the arrangement of the shielding electrode 152 , the hot carrier effect of the first active device T1 can be reduced, thereby improving the degradation problem of the first active device T1 . In addition, by forming the shielding electrode 152 and the third capacitor electrode C3 on the same conductive layer, the manufacturing cost of the device can be saved.

FIG. 8A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 8B is a schematic cross-sectional view of line I-I' in Fig. 8A.

It must be noted here that the embodiment of FIG. 8A and FIG. 8B follows the component numbers and part of the content of the embodiment of FIG. 7A and FIG. A description of the technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

Please refer to FIG. 8A and FIG. 8B , in the active device substrate 80 , the shielding electrode 152 is electrically connected to the first source 172 .

In this embodiment, the first source 172 has an extension 172E bypassing the first lightly doped region 112B and the channel region 112C, and the extension 172E of the first source 172 is connected to the shielding electrode 152, so that the first source 172 The first lightly doped region 112B and the channel region 112C do not overlap in the normal direction ND of the substrate 100 .

With the design of the extension portion 172E, the parasitic capacitance between the first source 172 and the first gate 132 is reduced.

Based on the above, through the arrangement of the shielding electrode 152 , the hot carrier effect of the first active device T1 can be reduced, thereby improving the degradation problem of the first active device T1 . In addition, by forming the shielding electrode 152 and the third capacitor electrode C3 on the same conductive layer, the manufacturing cost of the device can be saved.

10, 20, 30, 40, 50, 60, 70, 80: active component substrate 100: Substrate 102: buffer layer 110: Semiconductor pattern 112, 114: the first semiconductor layer 112A, 114A: the first heavily doped region 112B, 114B: the first lightly doped region 112C, 114C: channel area 112D, 114D: the second lightly doped region 112E, 114E: the second heavily doped region 120: gate insulating layer 130: the first conductive layer 132: the first gate 134: second gate 140: the first dielectric layer 150: auxiliary conductive layer 152, 173: Shading electrodes 160: second dielectric layer 170: second conductive layer 172: first source 172E: Extension 174: The first drain 176: Second source 178: The second drain 180: passivation layer A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I': line C1: the first capacitor electrode C2: second capacitor electrode C3: The third capacitor electrode D1, D1': vertical distance DL: data line HD1: Horizontal Spacing HD2: Horizontal Spacing ND: normal direction O: open PE: electrode SL: scan line t1, t2, t3: Thickness T1: The first active component T2: The second active component VL: signal line TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8, TH9, TH10, TH11, TH12, TH13, TH14, TH15: Through hole

FIG. 1A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of line A-A' in Fig. 1A. FIG. 2A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view of line B-B' in Fig. 2A. Fig. 2C is a schematic cross-sectional view of line C-C' in Fig. 2A. FIG. 3A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view of line D-D' in Fig. 3A. FIG. 4A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 4B is a schematic cross-sectional view of line E-E' in Fig. 4A. FIG. 5A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 5B is a schematic cross-sectional view of line F-F' in Fig. 5A. FIG. 6A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 6B is a schematic cross-sectional view of line G-G' in Fig. 6A. FIG. 7A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 7B is a schematic cross-sectional view taken along the line H-H' of Fig. 7A. FIG. 8A is a schematic top view of an active device substrate according to an embodiment of the present invention. Fig. 8B is a schematic cross-sectional view of line I-I' in Fig. 8A.

10: Active component substrate 100: Substrate 102: buffer layer 110: Semiconductor pattern 112: the first semiconductor layer 112A: the first heavily doped region 112B: the first lightly doped region 112C: Passage area 112D: the second lightly doped region 112E: the second heavily doped region 120: gate insulating layer 130: the first conductive layer 132: the first gate 140: the first dielectric layer 150: auxiliary conductive layer 152: Shading electrodes 160: second dielectric layer 170: second conductive layer 172: first source 174: The first drain 180: passivation layer A-A': line C1: the first capacitor electrode C2: second capacitor electrode C3: The third capacitor electrode D1: vertical distance ND: normal direction t1, t2, t3: Thickness T1: The first active component TH1, TH2, TH3, TH4, TH5, TH6: Through holes

Claims (6)

An active element substrate, comprising: a substrate; a first semiconductor layer located on the substrate and including a first heavily doped region, a first lightly doped region, a channel region, and a second a lightly doped region and a second heavily doped region; a gate insulating layer located on the first semiconductor layer; a first gate located on the gate insulating layer and in a normal direction of the substrate Overlapping the channel region of the first semiconductor layer; a first source, electrically connected to the first heavily doped region of the first semiconductor layer; a first drain, electrically connected to the first The second heavily doped region of the semiconductor layer, wherein a first active device includes the first semiconductor layer, the first gate, the first source and the first drain; and a shielding electrode, on the substrate The second lightly doped region overlapping the first semiconductor layer in the normal direction, wherein the shielding electrode is a floating electrode, wherein the first source, the first drain and the shielding electrode belong to the same conductive layer, and the shielding electrode is separated from the first source and the first drain. The active device substrate as claimed in claim 1, wherein the shielding electrode completely covers the second lightly doped region along the normal direction of the substrate. The active device substrate as claimed in claim 1, further comprising: a first dielectric layer formed on the first gate and the gate insulating layer; and a second dielectric layer formed on the first dielectric layer, wherein the shielding electrode is formed on the second dielectric layer. The active device substrate as claimed in claim 1, wherein the vertical distance between the shielding electrode and the second lightly doped region of the first semiconductor layer is 100 nm to 1000 nm. The active device substrate as claimed in claim 1, wherein at least part of the first gate is located between the shielding electrode and the first semiconductor layer. The active device substrate as claimed in claim 1, wherein a horizontal distance between the shielding electrode and the first source is larger than a horizontal distance between the shielding electrode and the first drain.

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