CN203871327U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203871327U CN203871327U CN201420280147.6U CN201420280147U CN203871327U CN 203871327 U CN203871327 U CN 203871327U CN 201420280147 U CN201420280147 U CN 201420280147U CN 203871327 U CN203871327 U CN 203871327U
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Abstract
The utility model discloses an array substrate and a display device. Since a metal shielding layer is electrically connected with a common electrode, and a first connection portion for electrically connecting the metal shielding layer and the common electrode is in same-layer arrangement with a source/ drain electrode and is electrically connected the metal shielding electrode through a via hole running through a first insulating layer and a buffer layer, the array substrate in the embodiment can form a storage capacitor between an active layer and the metal shielding layer, thereby realizing the purpose of enlarging the array substrate capacitance; and during the preparation process, the first connection portion and the source/ drain electrode which are in same-layer arrangement are formed through the one-time picture composition process, thereby reducing production processes, simplifying the production process, and finally, realizing the purpose of saving the production cost and reducing the production time.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of array base palte and display unit.
Background technology
Due to amorphous silicon, there is the problems such as the ON state current causing because of own defect itself is low, mobility is low, poor stability, it is restricted in a lot of fields, in order to make up the defect of amorphous silicon own, expansion is in the application of association area, low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) technology is arisen at the historic moment.
Along with the development of tft liquid crystal Display Technique (Thin Film Transistor Liquid Crystal Display, TFT-LCD) technology, the Display Technique based on low temperature polycrystalline silicon becomes main flow gradually.As depicted in figs. 1 and 2, low-temperature polysilicon film transistor array base palte of the prior art mainly comprises: underlay substrate 01, resilient coating 02, active layer 03, gate electrode 06, source electrode 05, drain electrode 04, public electrode 07, pixel electrode 08, gate insulation layer 09, intermediate dielectric layer 10, flatness layer 11 and passivation layer 12.Further, at thin-film transistor, be in the array base palte of top gate type structure, as shown in Figure 2, thereby be irradiated to for fear of light the performance that active layer 03 affects thin-film transistor, in array base palte, between resilient coating 02 and active layer 03, be also provided with and avoid light to be irradiated to the metal screen layer 13 on active layer 03.
Demand along with pixel technique exploitation, how to increase storage capacitance and become an important focus, in prior art, be to reach the object that increases storage capacitance, as shown in Figure 2, at thin-film transistor, be in the array base palte of top gate type structure, utilize the metal screen layer 13 that is positioned at resilient coating 02 below to increase storage capacitance with active layer 03 formation storage capacitance.Particularly, in order to apply common electrode signal on metal screen layer 13, metal screen layer 13 need to be by being positioned at the first connecting portion 14 on gate insulator 09, and the second connecting portion 15 being positioned in intermediate dielectric layer 10 is electrically connected with public electrode 07; Wherein, the first connecting portion 14 is electrically connected by running through via hole and the metal screen layer 13 of gate insulator 09 and resilient coating 02, second connects 15 is electrically connected by running through via hole and first connecting portion 14 of intermediate dielectric layer 10, and public electrode 07 is electrically connected by running through via hole and second connecting portion 15 of flatness layer 11.
The low-temperature polysilicon film transistor array base palte of said structure, although can utilize metal screen layer and active layer to form storage capacitance, but in order to realize metal screen layer 13 and active layer 03, form the object of storage capacitance, in the preparation, for metal screen layer 13 and public electrode 07 are electrically connected, need to increase separately one mask (Mask) technique and form the via hole that runs through gate insulator 09 and resilient coating 02, the first connecting portion 14 that is used in electric connection public electrode 07 and metal screen layer 13 is electrically connected by this via hole and metal screen layer 13, thereby it is more various to cause above-mentioned low-temperature polysilicon film transistor array base palte to produce in the preparation manufacturing process, cost compare is high, the problem such as long consuming time.
Utility model content
A kind of array base palte and display unit that the utility model embodiment provides, in order to solve in the situation that realize increasing array base palte storage capacitance, complex process of the prior art, cost are high, the problem of length consuming time.
A kind of array base palte that the utility model embodiment provides, comprises underlay substrate, is positioned at metal screen layer, resilient coating, top gate type thin film transistor and the public electrode on described underlay substrate successively; Wherein, the source-drain electrode of described top gate type thin film transistor is being electrically connected above active layer and by running through the first via hole and the described active layer of the first insulating barrier between described source-drain electrode and described active layer, also comprises:
Arrange with layer with described source-drain electrode, for being electrically connected described metal screen layer and described public electrode and by running through the second via hole of described the first insulating barrier and described resilient coating and the first connecting portion of described metal screen layer electric connection.
The above-mentioned array base palte that the utility model embodiment provides, because metal screen layer is not only electrically connected with public electrode, and for being electrically connected the first connecting portion and the source-drain electrode of metal screen layer and public electrode, with layer, arrange, and be to be electrically connected by running through via hole and the metallic shield electrode of the first insulating barrier and resilient coating.Therefore the above-mentioned array base palte that the utility model embodiment provides not only can form storage capacitance between active layer and metal screen layer, thereby reach the order that increases array base palte electric capacity, and can form the first connecting portion and the source-drain electrode arranging with layer by a composition technique in the preparation, thereby can reduce making flow process, simplify manufacture craft, finally can reach the object of saving cost of manufacture, shortening Production Time.
Preferably, for the ease of implementing, in the above-mentioned array base palte providing at the utility model embodiment, also comprise: the second insulating barrier between described source-drain electrode and described public electrode;
Described public electrode is electrically connected by running through the 3rd via hole and described first connecting portion of described the second insulating barrier.
Preferably, for the ease of implementing, in the above-mentioned array base palte providing at the utility model embodiment, also comprise:
Be positioned at the pixel electrode of described public electrode top, the 3rd insulating barrier between described pixel electrode and described public electrode, and with the same layer setting of described public electrode and for being electrically connected the second connecting portion of the drain electrode of described pixel electrode and described source-drain electrode; Wherein,
Described the second connecting portion is electrically connected by running through the 4th via hole of described the second insulating barrier and the drain electrode in described source-drain electrode; Described pixel electrode is electrically connected by running through the 5th via hole and described second connecting portion of described the 3rd insulating barrier.
Preferably, for the ease of implementing, in the above-mentioned array base palte providing at the utility model embodiment, also comprise:
Between described source-drain electrode and described public electrode and with the pixel electrode of described public electrode mutually insulated, and the second insulating barrier between described pixel electrode and described source-drain electrode;
Described pixel electrode is electrically connected by running through the 6th via hole of described the second insulating barrier and the drain electrode in described source-drain electrode.
Preferably, for the ease of implementing, in the above-mentioned array base palte providing at the utility model embodiment, also comprise:
The 3rd insulating barrier between described pixel electrode and described public electrode, and with the same layer setting of described pixel electrode, for being electrically connected the 3rd connecting portion of described public electrode and described the first connecting portion; Wherein,
Described the 3rd connecting portion is electrically connected by running through the 7th via hole and described first connecting portion of described the second insulating barrier; Described public electrode is electrically connected by running through the 8th via hole and described the 3rd connecting portion of described the 3rd insulating barrier.
A kind of display unit that the utility model embodiment provides, comprises above-mentioned any array base palte that the utility model embodiment provides.
Accompanying drawing explanation
Fig. 1 is one of structural representation of existing low-temperature polysilicon film transistor array base palte;
Fig. 2 be existing low-temperature polysilicon film transistor array base palte structural representation two;
Fig. 3 a and Fig. 3 b are respectively the structural representation of the array base palte that the utility model embodiment provides;
Fig. 4 is the schematic top plan view of the array base palte shown in Fig. 3 a;
Fig. 5 a to Fig. 5 k is respectively the manufacture method of the array base palte that the utility model example one provides and carries out the structural representation after each step;
Fig. 6 a to Fig. 6 c is respectively the manufacture method of the array base palte that the utility model example two provides and carries out the structural representation after each step.
Embodiment
Below in conjunction with accompanying drawing, the array base palte that the utility model embodiment is provided and the embodiment of display unit are described in detail.
In accompanying drawing, the size and shape of each parts does not reflect the true ratio of array base palte, and object is signal explanation the utility model content just.
A kind of array base palte that the utility model embodiment provides, as shown in Fig. 3 a, Fig. 3 b and Fig. 4 (wherein Fig. 4 is the schematic top plan view of array base palte shown in Fig. 3 a), comprise underlay substrate 100, be positioned at metal screen layer 200, resilient coating 300, top gate type thin film transistor and the public electrode 500 on underlay substrate 100 successively; Wherein, the source-drain electrode 410 of top gate type thin film transistor is being electrically connected above active layer 420 and by running through the first via hole V1 and the active layer 420 of the first insulating barrier 610 between source-drain electrode 410 and active layer 420, also comprises:
Arrange with layer with source-drain electrode 410, for being electrically connected metal screen layer 200 with public electrode 500 and by running through the second via hole V2 of the first insulating barrier 610 and resilient coating 300 and the first connecting portion 510 of metal screen layer 200 electric connections.
The above-mentioned array base palte that the utility model embodiment provides, because metal screen layer is not only electrically connected with public electrode, and for being electrically connected the first connecting portion and the source-drain electrode of metal screen layer and public electrode, with layer, arrange, and be electrically connected by running through via hole and the metallic shield electrode of the first insulating barrier and resilient coating.Therefore the above-mentioned array base palte that the utility model embodiment provides not only can form storage capacitance between active layer and metal screen layer, thereby reach the object that increases array base palte electric capacity, and can form the first connecting portion and the source-drain electrode arranging with layer by a composition technique in the preparation, thereby can reduce making flow process, simplify manufacture craft, finally can reach the object of saving cost of manufacture, shortening Production Time.
It should be noted that, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 a and Figure 3 b shows, in order to form storage capacitance between active layer 420 and metal screen layer 200, metal screen layer 200 is overlapping at least partly in the orthographic projection of underlay substrate 100 at orthographic projection and the active layer 420 of underlay substrate 100.
Particularly, in the specific implementation, in the above-mentioned array base palte providing at the utility model embodiment, active layer can adopt low temperature polycrystalline silicon material, also can adopt oxide material, at this, does not limit.
Further, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 a and Figure 3 b shows, gate electrode is at least one.In the specific implementation, two gate electrodes 430 are set, gate electrode 430 is set to two, and object is in order to play the effect of the leakage current that reduces thin-film transistor.
Further, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 a and Figure 3 b shows, 421He light doping section, heavily doped region 422 can also be set in active layer 420, heavily doped region 421 lays respectively at the region that active layer 420 is corresponding with source-drain electrode 410, for reducing the contact resistance between source-drain electrode 410 and active layer 420.Between 422 heavily doped region, light doping section 421, and be distributed in the both sides in the region of two gate electrode 430 correspondences.Light doping section 422 is set and can plays the effect of the leakage current that reduces thin-film transistor.The setting position of 421He light doping section, heavily doped region shown in figure 422 is only a kind of example, when practical application, for some thin-film transistor, also heavily doped region or light doping section can be set, also can at diverse location, a plurality of heavily doped regions or light doping section be set as required, be not limited to shown in figure.
Particularly, in the above-mentioned array base palte providing at the utility model embodiment, in top gate type thin film transistor, gate electrode can be positioned at the top of source-drain electrode, also can be positioned at the below of source-drain electrode, at this, does not limit.All to take below that gate electrode is positioned at source-drain electrode to describe as example below.
Particularly, in the above-mentioned array base palte providing at the utility model embodiment, when gate electrode is positioned at the below of source-drain electrode, as shown in Figure 3 a and Figure 3 b shows, at the first insulating barrier 610 fingers between source-drain electrode 410 and active layer 420, at the gate insulator 611 between active layer 420 and gate electrode 430 and the interlayer dielectric layer 612 between gate electrode 430 and source-drain electrode 410, be specifically not limited to this.
Preferably, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 a, also comprise: the second insulating barrier 620 between source-drain electrode 410 and public electrode 500;
Public electrode 500 is electrically connected by running through the 3rd via hole V3 and first connecting portion 510 of the second insulating barrier 620.
Preferably, for the ease of implementing, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 a, also comprise: the pixel electrode 700 that is positioned at public electrode 500 tops, the 3rd insulating barrier 630 between pixel electrode 700 and public electrode 500, and with the same layer setting of public electrode 500 and for being electrically connected the second connecting portion 710 of the drain electrode of pixel electrode 700 and source-drain electrode 410; Wherein,
The second connecting portion 710 is electrically connected by running through the 4th via hole V4 of the second insulating barrier 620 and the drain electrode in source-drain electrode 410; Pixel electrode 700 is electrically connected by running through the 5th via hole V5 and second connecting portion 710 of the 3rd insulating barrier 630.
Further, in the specific implementation, in the above-mentioned array base palte providing at the utility model embodiment, when pixel electrode is positioned at the top of public electrode, pixel electrode can be slit-shaped, and the material of pixel electrode can be the transparent conductive materials such as tin indium oxide; Public electrode can be tabular or slit-shaped, and the material of public electrode can be the transparent conductive materials such as tin indium oxide.
Or, preferably, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 b, also comprise: between source-drain electrode 410 and public electrode 500 and with the pixel electrode 700 of public electrode 500 mutually insulateds, and the second insulating barrier 620 between pixel electrode 700 and source-drain electrode 410;
Pixel electrode 700 is electrically connected by running through the 6th via hole V6 of the second insulating barrier 620 and the drain electrode in source-drain electrode 410.
Preferably, in the above-mentioned array base palte providing at the utility model embodiment, as shown in Figure 3 b, also comprise: the 3rd insulating barrier 630 between pixel electrode 700 and public electrode 500, and with the same layer setting of pixel electrode 700, for being electrically connected the 3rd connecting portion 520 of public electrode 500 and the first connecting portion 510; Wherein,
The 3rd connecting portion 520 is electrically connected by running through the 7th via hole V7 and first connecting portion 510 of the second insulating barrier 620; Public electrode 500 is electrically connected by running through the 8th via hole V8 and the 3rd connecting portion 520 of the 3rd insulating barrier 630.
Further, in the specific implementation, in the above-mentioned array base palte providing at the utility model embodiment, when public electrode is positioned at the top of pixel electrode, public electrode can be slit-shaped, and the material of public electrode can be the transparent conductive materials such as tin indium oxide; Pixel electrode can be tabular or slit-shaped, and the material of pixel electrode can be the transparent conductive materials such as tin indium oxide.
It should be noted that, the above-mentioned array base palte that the utility model embodiment provides all be take top gate type TFT that active layer is polysilicon layer and is described as example, the top gate type TFT that is amorphous silicon layer etc. for active layer, and the utility model embodiment is applicable equally.
Based on same utility model design, the utility model embodiment also provides a kind of display unit, comprise the above-mentioned array base palte that the utility model embodiment provides, this display unit can be: any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.For other requisite part of this display unit, be and will be understood by those skilled in the art that to have, at this, do not repeat, should be as to restriction of the present utility model yet.The enforcement of this display unit can, referring to the embodiment of above-mentioned array base palte, repeat part and repeat no more.
Based on same utility model design, the utility model embodiment also provides a kind of manufacture method of array base palte, forms successively the figure of metal screen layer, resilient coating, top gate type thin film transistor and public electrode on underlay substrate; Wherein, the source-drain electrode of top gate type thin film transistor is being electrically connected above active layer and by running through the first via hole and the active layer of the first insulating barrier between source-drain electrode and active layer, also comprises:
When formation runs through described first via hole of the first insulating barrier, adopt half-tone mask plate or gray mask plate to form the second via hole that runs through the first insulating barrier and resilient coating;
When forming the figure of source-drain electrode, by a composition technique, be formed for being electrically connected metal screen layer and public electrode and pass through the second via hole and the figure of the first connecting portion that metal screen layer is electrically connected.
The manufacture method of the above-mentioned array base palte that the utility model embodiment provides, owing to running through the first via hole of the first insulating barrier in formation when, adopts half-tone mask plate or gray mask plate to form the second via hole that runs through the first insulating barrier and resilient coating; When forming the figure of source-drain electrode, by a composition technique, be formed for being electrically connected metal screen layer and public electrode and pass through the second via hole and the figure of the first connecting portion that metal screen layer is electrically connected.Therefore, with in prior art by the first connecting portion be positioned at the second connecting portion on the first connecting portion and realize metal screen layer and compare with the electric connection of public electrode, the above-mentioned manufacture method that the utility model embodiment provides can be saved together for forming separately the Mask technique of the via hole that the first connecting portion and metal screen layer be electrically connected.Therefore, the above-mentioned manufacture method that the utility model embodiment provides can reduce making flow process, simplifies manufacture craft, finally can reach the object of saving cost of manufacture, shortening Production Time.
It should be noted that, in the manufacture method of the above-mentioned array base palte providing at the utility model embodiment, composition technique can only include photoetching process, or, can comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.In the specific implementation, can be according to the corresponding composition technique of formed structure choice in the utility model.
Preferably, in the above-mentioned manufacture method providing at the utility model embodiment, after forming the figure of source-drain electrode, before forming the figure of public electrode, also comprise: the film that forms the second insulating barrier between source-drain electrode and the public electrode that will form; The 3rd via hole that forms the film that runs through the second insulating barrier by composition technique, public electrode is electrically connected by the 3rd via hole and the first connecting portion.
Preferably, in order to simplify manufacture craft, reduce production costs, with the shortening production cycle, in the above-mentioned manufacture method providing at the utility model embodiment, also comprise: when forming the 3rd via hole, by a composition technique, form the 4th via hole that runs through the second insulating barrier; When forming the figure of public electrode, by composition technique, be formed for being electrically connected the figure of the second connecting portion of the pixel electrode that will form and the drain electrode in source-drain electrode, the second connecting portion is electrically connected by the 4th via hole and drain electrode;
After forming the figure of public electrode, also comprise: the film that forms the 3rd insulating barrier on public electrode; By composition technique, form the 5th via hole of the film that runs through the 3rd insulating barrier; On the 3rd insulating barrier, form the figure of pixel electrode, described pixel electrode is electrically connected by described the 5th via hole and described the second connecting portion.
Or, preferably, in the above-mentioned manufacture method providing at the utility model embodiment, after forming the figure of source-drain electrode, before forming the figure of public electrode, also comprise: the film that forms the second insulating barrier between source-drain electrode and the public electrode that will form; By composition technique, form the 6th via hole of the film that runs through the second insulating barrier; The figure that forms pixel electrode on the film of the second insulating barrier that is formed with the 6th via hole, pixel electrode is electrically connected by the drain electrode in the 6th via hole and source-drain electrode.
Preferably, in order to simplify manufacture craft, reduce production costs, with the shortening production cycle, in the above-mentioned manufacture method providing at the utility model embodiment, also comprise: when forming the 6th via hole, by a composition technique, form the 7th via hole that runs through the second insulating barrier; When forming the figure of pixel electrode, by composition technique, be formed for being electrically connected the figure of the 3rd connecting portion of the public electrode that will form and the first connecting portion, the 3rd connecting portion is electrically connected by the 7th via hole and the first connecting portion;
After forming the figure of described pixel electrode, also comprise: the film that forms the 3rd insulating barrier between pixel electrode and the public electrode that will form; The 8th via hole that forms the film that runs through the 3rd insulating barrier by composition technique, the public electrode that will form is electrically connected by the 8th via hole and the 3rd connecting portion.
It should be noted that; above embodiment take double grid top gate type low temperature polycrystalline silicon (LTPS) TFT to describe as example; be understandable that; can also be applicable to single grid type TFT; non-crystalline silicon tft; the TFT of the top gate structures such as oxide TFT, as long as can realize the scheme of increase array base palte storage capacitance by what increase active layer and metal screen layer over against area, is protection range of the present utility model.
Particularly, take respectively the manufacture method that the array base palte shown in Fig. 3 a and Fig. 3 b is example pair array substrate is below described in detail.
Example one:
As shown in Figure 3 a, in array base palte, pixel electrode 700 is positioned at the top of public electrode 500, and the manufacturing process of array base palte comprises following step:
(1) on underlay substrate 100, form the figure of metal screen layer 200, as shown in Figure 5 a;
(2) on metal screen layer 200, form resilient coating 300, as shown in Figure 5 b;
In the specific implementation, can strengthen chemical gaseous phase depositing process deposition resilient coating by using plasma, resilient coating specifically can adopt silicon dioxide or silicon nitride material.
(3) on resilient coating 300, form the figure of active layer 420, as shown in Figure 5 c;
In the specific implementation, by plasma enhanced chemical vapor deposition method or other similar approach, above resilient coating, form amorphous silicon membrane layer, then by technical processs such as laser annealing technique or solid-phase crystallization techniques, make recrystallized amorphous silicon, form layer polysilicon film, and form by composition technique the figure that comprises low temperature polycrystalline silicon active layer.
(4) on active layer 420, form gate insulator 611, as shown in Fig. 5 d;
In the specific implementation, gate insulator can adopt silica or silicon nitride material.
(5) on gate insulator 611, form the figure of gate electrode 430, as shown in Fig. 5 e;
In the specific implementation, particularly, the material of gate electrode can be the metals such as molybdenum (Mo), aluminium (Al) or cadmium (Cr).
(6) in active layer 420, form 421He light doping section, heavily doped region 422, as shown in Fig. 5 f;
In the specific implementation, adopt Implantation mode to carry out heavy doping to the relative both sides of active layer, form heavily doped region, and light dope is carried out in the part active layer region between heavily doped region, form light doping section, this light doping section is distributed in the both sides in the region that gate electrode is corresponding.Wherein, when Implantation, can in appointed area, carry out the Implantation of variable concentrations by mask plate realization is set, also can block by the figure of gate electrode and carry out Implantation, or block and carry out Implantation by the photoresist using in composition technique, similarly to the prior art, repeat no more herein.
(7) on gate electrode 430, form interlayer dielectric layer 612, and adopt half-tone mask plate or gray mask plate to form the first via hole V1 that runs through interlayer dielectric layer 612 and gate insulator 611 and the second via hole V2 that runs through interlayer dielectric layer 612, gate insulator 611 and resilient coating 300, as shown in Fig. 5 g;
In the specific implementation, the region of corresponding first via hole of complete transmission region of half-tone mask plate or gray mask plate, the region of corresponding the second via hole of part transmission region.
Further, in the specific implementation, interlayer dielectric layer can adopt silica or silicon nitride material, at this, does not limit.
(8) on interlayer dielectric layer 612, form the figure of source-drain electrode 410 and the first connecting portion 510, as shown in Fig. 5 h;
In the specific implementation, can on interlayer dielectric layer, form source-drain electrode film, by a composition technique, in this source-drain electrode film, form the figure of source-drain electrode and the first connecting portion, and source-drain electrode is electrically connected by the first via hole and active layer, the first connecting portion is electrically connected by the second via hole and metal screen layer.
(9) on source-drain electrode 410, form the film of the second insulating barrier 620, and form by a composition technique the 3rd via hole V3 and the 4th via hole V4 that runs through this second insulating barrier 620, as shown in Fig. 5 i;
(10) on the second insulating barrier 620, form the film of public electrode 500, by composition technique, in the film of public electrode 500, form the figure of public electrode 500 and the second connecting portion 710, as shown in Fig. 5 j;
In the specific implementation, public electrode can be tabular or slit-shaped, the material of public electrode can be the transparent conductive materials such as tin indium oxide, and public electrode is electrically connected by the 3rd via hole and the first connecting portion, and the second connecting portion is electrically connected by drain electrode in the 4th via hole and source-drain electrode.
(11) on public electrode 500, form the 3rd insulating barrier 630, and form by composition technique the 5th via hole V5 that runs through the 3rd insulating barrier 630, as shown in Fig. 5 k;
(12) on the 3rd insulating barrier 630, form the figure of pixel electrode 700, as shown in Figure 3 a.
In the specific implementation, pixel electrode can be slit-shaped, and the material of pixel electrode can be the transparent conductive materials such as tin indium oxide, and pixel electrode is electrically connected by the 5th via hole and the second connecting portion.
Particularly, through above-mentioned steps (1) to (12) afterwards, obtain the array base palte that the utility model embodiment provides, particularly, the structural representation of resulting array base palte as shown in Figure 3 a.
Example two:
As shown in Figure 3 b, in array base palte, public electrode 500 is positioned at the top of pixel electrode 700, and the manufacturing process of array base palte is except comprising that above-mentioned steps (1), to (8), comprises following step:
(9) on source-drain electrode 410, form the film of the second insulating barrier 620, and form by a composition technique the 6th via hole V6 and the 7th via hole V7 that runs through this second insulating barrier 620, as shown in Figure 6 a;
(10) on the second insulating barrier 620, form the film of pixel electrode 700, by composition technique, in the film of pixel electrode 700, form the figure of pixel electrode 700 and the 3rd connecting portion 520, as shown in Figure 6 b;
In the specific implementation, pixel electrode can be tabular or slit-shaped, the material of pixel electrode can be the transparent conductive materials such as tin indium oxide, and pixel electrode is electrically connected by drain electrode in the 6th via hole and source-drain electrode, and the 3rd connecting portion is electrically connected by the 7th via hole and the first connecting portion.
(11) on pixel electrode 700, form the 3rd insulating barrier 630, and form by composition technique the 8th via hole V8 that runs through the 3rd insulating barrier 630, as shown in Fig. 6 c;
(12) on the 3rd insulating barrier 630, form the figure of public electrode 500, as shown in Figure 3 b.
In the specific implementation, public electrode can be slit-shaped, and the material of public electrode can be the transparent conductive materials such as tin indium oxide, and public electrode is electrically connected by the 8th via hole and the 3rd connecting portion.
Particularly, through above-mentioned steps (1) to (12) afterwards, obtain the array base palte that the utility model embodiment provides, particularly, the structural representation of resulting array base palte as shown in Figure 3 b.
A kind of array base palte and display unit that the utility model embodiment provides, because metal screen layer is not only electrically connected with public electrode, and for being electrically connected the first connecting portion and the source-drain electrode of metal screen layer and public electrode, with layer, arrange, and be to be electrically connected by running through via hole and the metallic shield electrode of the first insulating barrier and resilient coating.Therefore the above-mentioned array base palte that the utility model embodiment provides not only can form storage capacitance between active layer and metal screen layer, thereby reach the order that increases array base palte electric capacity, and can form the first connecting portion and the source-drain electrode arranging with layer by a composition technique in the preparation, thereby can reduce making flow process, simplify manufacture craft, finally can reach the object of saving cost of manufacture, shortening Production Time.
Obviously, those skilled in the art can carry out various changes and modification and not depart from spirit and scope of the present utility model the utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model is also intended to comprise these changes and modification interior.
Claims (6)
1. an array base palte, comprises underlay substrate, is positioned at metal screen layer, resilient coating, top gate type thin film transistor and the public electrode on described underlay substrate successively; Wherein, the source-drain electrode of described top gate type thin film transistor being electrically connected above active layer and by running through the first via hole and the described active layer of the first insulating barrier between described source-drain electrode and described active layer, is characterized in that, also comprises:
Arrange with layer with described source-drain electrode, for being electrically connected described metal screen layer and described public electrode and by running through the second via hole of described the first insulating barrier and described resilient coating and the first connecting portion of described metal screen layer electric connection.
2. array base palte as claimed in claim 1, is characterized in that, also comprises: the second insulating barrier between described source-drain electrode and described public electrode;
Described public electrode is electrically connected by running through the 3rd via hole and described first connecting portion of described the second insulating barrier.
3. array base palte as claimed in claim 2, is characterized in that, also comprises:
Be positioned at the pixel electrode of described public electrode top, the 3rd insulating barrier between described pixel electrode and described public electrode, and with the same layer setting of described public electrode and for being electrically connected the second connecting portion of the drain electrode of described pixel electrode and described source-drain electrode; Wherein,
Described the second connecting portion is electrically connected by running through the 4th via hole of described the second insulating barrier and the drain electrode in described source-drain electrode; Described pixel electrode is electrically connected by running through the 5th via hole and described second connecting portion of described the 3rd insulating barrier.
4. array base palte as claimed in claim 1, is characterized in that, also comprises:
Between described source-drain electrode and described public electrode and with the pixel electrode of described public electrode mutually insulated, and the second insulating barrier between described pixel electrode and described source-drain electrode;
Described pixel electrode is electrically connected by running through the 6th via hole of described the second insulating barrier and the drain electrode in described source-drain electrode.
5. array base palte as claimed in claim 4, is characterized in that, also comprises:
The 3rd insulating barrier between described pixel electrode and described public electrode, and with the same layer setting of described pixel electrode, for being electrically connected the 3rd connecting portion of described public electrode and described the first connecting portion; Wherein,
Described the 3rd connecting portion is electrically connected by running through the 7th via hole and described first connecting portion of described the second insulating barrier; Described public electrode is electrically connected by running through the 8th via hole and described the 3rd connecting portion of described the 3rd insulating barrier.
6. a display unit, is characterized in that, comprises the array base palte as described in claim 1-5 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420280147.6U CN203871327U (en) | 2014-05-28 | 2014-05-28 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201420280147.6U CN203871327U (en) | 2014-05-28 | 2014-05-28 | Array substrate and display device |
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| CN104022126A (en) * | 2014-05-28 | 2014-09-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| WO2016106923A1 (en) * | 2014-12-31 | 2016-07-07 | 深圳市华星光电技术有限公司 | Ltps tft pixel unit and manufacturing method therefor |
| WO2017008346A1 (en) * | 2015-07-16 | 2017-01-19 | 武汉华星光电技术有限公司 | Display panel and thin-film transistor array substrate |
| WO2017197913A1 (en) * | 2016-05-16 | 2017-11-23 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and display device using same |
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| CN104022126A (en) * | 2014-05-28 | 2014-09-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
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| WO2017197913A1 (en) * | 2016-05-16 | 2017-11-23 | 京东方科技集团股份有限公司 | Thin film transistor array substrate and display device using same |
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| WO2022141169A1 (en) * | 2020-12-29 | 2022-07-07 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method for display panel |
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