CN106328715B - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing method Download PDFInfo
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- CN106328715B CN106328715B CN201610681586.1A CN201610681586A CN106328715B CN 106328715 B CN106328715 B CN 106328715B CN 201610681586 A CN201610681586 A CN 201610681586A CN 106328715 B CN106328715 B CN 106328715B
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- 239000010409 thin film Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 202
- 229920002120 photoresistant polymer Polymers 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 43
- 239000011229 interlayer Substances 0.000 claims description 30
- 238000012545 processing Methods 0.000 claims description 19
- 238000004380 ashing Methods 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 7
- 230000000717 retained effect Effects 0.000 claims description 7
- 238000010408 sweeping Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 230000002159 abnormal effect Effects 0.000 abstract description 5
- 238000006073 displacement reaction Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003724 hair brightness Effects 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The present invention provides a kind of thin film transistor and its manufacturing method, in the second overlapping region between the first overlapping region, grid and source electrode by corresponding to scan line and data line infall in scan line and grid and the third overlapping region between grid and drain electrode at least one at groove is set, so that the pole plate spacing of the parasitic capacitance of the overlapping region at least one increases, to reduce parasitic capacitance, increase device stability, avoids occurring when display that image is viscous and the abnormal phenomenon such as color displacement.
Description
Technical field
The present invention relates to thin-film transistor technologies field more particularly to a kind of thin film transistor and its manufacturing methods.
Background technique
Liquid crystal display device (Liquid Crystal Display, LCD) has thin fuselage, power saving, radiationless etc. numerous
Advantage is widely used, such as: mobile phone, personal digital assistant (PDA), digital camera, computer screen or notes
This computer screen etc..
OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display, also referred to as Organic Electricity
Electroluminescent display is a kind of emerging panel display apparatus, since it is simple with preparation process, at low cost, low in energy consumption, hair
Brightness height, operating temperature wide adaptation range, volume be frivolous, fast response time, and is easily achieved colored display and large screen
It shows, be easily achieved and match with driver ic, be easily achieved the advantages that Flexible Displays, thus there is wide application
Prospect.
OLED according to driving method can be divided into passive matrix OLED (Passive Matrix OLED, PMOLED) and
Active array type OLED (Active Matrix OLED, AMOLED) two major classes, i.e. directly addressing and film transistor matrix are sought
Two class of location.Wherein, AMOLED has the pixel in array arrangement, belongs to active display type, and luminous efficacy is high, is typically used as
Large scale display device high-definition.
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) is current liquid crystal display device and active matrix
Main driving element in drive-type organic electroluminescence display device and method of manufacturing same, is directly related to the development of high performance flat display device
Direction.
Existing thin film transistor (TFT) generally includes grid, scan line, data line, source electrode and drain electrode, the grid and sweeps
It retouches between line and data line, source electrode and drain electrode and usually there is lap, these laps parasitic capacitance easy to form, by
In on the external voltage source that the both ends of parasitic capacitance are connected respectively to data line and scan line, so that parasitic capacitance can become data
The driving of line and scan line loads, and so as to cause the generation of certain visual artifacts, such as image is viscous, color displacement and other face
Color mistake.
Summary of the invention
The purpose of the present invention is to provide a kind of production methods of thin film transistor (TFT), can reduce scan line and grid and number
According to the parasitic capacitance at the overlapping region of line, source electrode and drain electrode, increase device stability.
The object of the invention is also to provide a kind of thin film transistor (TFT), scan line and grid and data line, source electrode and leakage
Parasitic capacitance at the overlapping region of pole is small, and device stability is good.
To achieve the above object, present invention firstly provides a kind of thin film transistor (TFT)s, comprising: underlay substrate is set to the lining
Scan line on substrate, the grid on the underlay substrate, the grid on the scan line, grid and underlay substrate
Pole insulating layer, is set to the active layer and gate insulating layer at the active layer on the gate insulating layer and corresponding to grid
On data line and source electrode and drain electrode on the active layer and gate insulating layer；
The grid is connected to the scan line side；The source electrode is connected to the data line side, the drain electrode with
The source space setting；The source electrode and drain electrode are in contact with the two sides of the active layer respectively；
The scan line intersects with data line, and infall forms the first overlapping region；The grid has with positioned at described
Form the second overlapping region between the source electrode of active layer side, at the same the grid be located at the active layer other side drain electrode it
Between formed third overlapping region；
Correspond on the scan line and grid first, second and third overlapping region at least one at be equipped with groove.
Correspond to the third overlapping region between the grid and drain electrode on the grid and is equipped with a groove.
Correspond to the second overlapping region between the grid and source electrode and the grid and drain electrode on the grid
Between third overlapping region be respectively equipped with a groove.
The first overlapping region for corresponding to the infall of the scan line and data line in the scan line is equipped with a groove.
The thin film transistor (TFT) further includes the interlayer dielectric on the active layer, source electrode, drain electrode and gate insulating layer
Layer and the pixel electrode on the interlayer dielectric layer；
The interlayer dielectric layer is equipped with the via hole corresponded to above the drain electrode, and the pixel electrode is via via hole and institute
Drain electrode is stated to be in contact.
The present invention also provides a kind of production methods of above-mentioned thin film transistor (TFT), include the following steps:
Step 1 provides a underlay substrate, forms scan line on the underlay substrate and is connected to the scan line one
The grid of side；
The data line, source electrode and leakage for corresponding to the scan line and grid in the scan line and grid and being subsequently formed
Groove is equipped at least one in first, second and third overlapping region between pole；
First, second and third between the scan line and grid and the data line being subsequently formed, source electrode and drain electrode
Overlapping region includes the first overlapping region, the grid and the subsequent shape of the scan line and the data line infall being subsequently formed
At source electrode between the second overlapping region and the grid and the drain electrode being subsequently formed between third overlapping region；
Step 2 forms gate insulating layer on scan line, grid and underlay substrate；
Active layer is formed on the gate insulating layer；
Formed data line on the active layer and gate insulating layer, source electrode and drain electrode；
The source electrode is connected to the data line side, and the drain electrode is arranged with the source space；The source electrode and leakage
Pole is in contact with the two sides of the active layer respectively.
The step 1 specifically includes:
Step 11 provides a underlay substrate, and a conductive layer is formed on the underlay substrate；
Step 12 forms photoresist layer on the conductive layer, carries out figure to the photoresist layer using a halftone mask
Change processing, the photoresist layer of reservation is used to define the figure of scan line and grid, and the photoresist layer of the reservation is equipped at least
One groove；
At least one described groove corresponds to the first overlapping region of scan line and the data line infall being subsequently formed, grid
The third overlay region between the second overlapping region and grid and the drain electrode being subsequently formed between pole and the source electrode being subsequently formed
In domain at least one at；
The region that retained photoresist layer does not block on the conductive layer is etched, scan line and grid are formed；
Step 13 carries out ashing processing to the photoresist layer of reservation, and the photoresist layer of the reservation is equipped at least one groove
Position become at least one through-hole, the thickness of remaining position reduces；
Step 14, using be ashed after photoresist layer as barrier bed, at least one of the scan line and grid are lost
It carves, forms at least one groove at least one of the scan line and grid；
Remove remaining photoresist layer.
In a specific embodiment, the leakage for corresponding to the grid in the step 1, on the grid and being subsequently formed
Third overlapping region between pole is equipped with a groove；
The step 1 specifically includes:
Step 11 provides a underlay substrate, and a conductive layer is formed on the underlay substrate；
Step 12 forms photoresist layer on the conductive layer, carries out figure to the photoresist layer using a halftone mask
Change processing, the photoresist layer of reservation is used to define the figure of scan line and grid, and the photoresist layer of the reservation is recessed equipped with one
Slot；The groove corresponds to the third overlapping region between grid and the drain electrode being subsequently formed；
The region that retained photoresist layer does not block on the conductive layer is etched, scan line and grid are formed；
Step 13 carries out ashing processing to the photoresist layer of reservation, and the photoresist layer of the reservation is equipped with the position of a groove
Become a through-hole, the thickness of remaining position reduces；
Step 14, using the photoresist layer after being ashed as barrier bed, grid is etched, is formed on the grid one recessed
Slot；
Remove remaining photoresist layer.
In another specific embodiment, corresponds to the grid in the step 1, on the grid and be subsequently formed
The third overlapping region between the second overlapping region and the grid and the drain electrode being subsequently formed between source electrode is respectively equipped with
One groove；
The step 1 specifically includes:
Step 11 provides a underlay substrate, and a conductive layer is formed on the underlay substrate；
Step 12 forms photoresist layer on the conductive layer, carries out figure to the photoresist layer using a halftone mask
Change processing, the photoresist layer of reservation are used to define the figure of scan line and grid, and there are two setting on the photoresist layer of the reservation
Groove；The second overlapping region that described two grooves correspond respectively to grid between the source electrode that is subsequently formed and grid with
Third overlapping region between the drain electrode being subsequently formed；
The region that retained photoresist layer does not block on the conductive layer is etched, scan line and grid are formed；
Step 13 carries out ashing processing to the photoresist layer of reservation, and the position there are two groove is set on the photoresist layer of the reservation
Setting becomes two through-holes, and the thickness of remaining position reduces；
Step 14, using be ashed after photoresist layer as barrier bed, grid is etched, on the grid formed two it is recessed
Slot；
Remove remaining photoresist layer.
The production method of the thin film transistor (TFT) further includes step 3, in the active layer, source electrode, drain electrode and gate insulator
Interlayer dielectric layer is formed on layer, processing is patterned to the interlayer dielectric layer, is formed and is corresponded on the interlayer dielectric layer
Via hole above the drain electrode；
Pixel electrode is formed on the interlayer dielectric layer, the pixel electrode is in contact via via hole with the drain electrode.
Beneficial effects of the present invention: a kind of thin film transistor and its manufacturing method provided by the invention, by scan line
With correspond to scan line and data line infall on grid the first overlapping region, grid and source electrode between the second overlay region
Groove is set at least one in third overlapping region between domain and grid and drain electrode, so that the overlay region at least one
The pole plate spacing of the parasitic capacitance in domain increases, to reduce parasitic capacitance, increases device stability, avoids image occur when display
The abnormal phenomenon such as viscous and color displacement.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is the schematic top plan view of thin film transistor (TFT) of the invention；
Fig. 2 is schematic cross-sectional view of the first embodiment along Figure 1A-A line of thin film transistor (TFT) of the invention；
Fig. 3 is schematic cross-sectional view of the second embodiment along Figure 1A-A line of thin film transistor (TFT) of the invention；
Fig. 4 is schematic cross-sectional view of the 3rd embodiment along Figure 1B-B line of thin film transistor (TFT) of the invention；
Fig. 5 is the flow chart of the production method of thin film transistor (TFT) of the invention；
Fig. 6 is that the first embodiment of the production method of thin film transistor (TFT) of the invention and the step 11 of second embodiment are shown
It is intended to；
Fig. 7 is the schematic diagram of the step 12 of the first embodiment of the production method of thin film transistor (TFT) of the invention；
Fig. 8 is the schematic diagram of the step 13 of the first embodiment of the production method of thin film transistor (TFT) of the invention；
Fig. 9 is the schematic diagram of the step 14 of the first embodiment of the production method of thin film transistor (TFT) of the invention；
Figure 10-11 is the schematic diagram of the step 2 of the first embodiment of the production method of thin film transistor (TFT) of the invention；
Figure 12 is the schematic diagram of the step 12 of the second embodiment of the production method of thin film transistor (TFT) of the invention；
Figure 13 is the schematic diagram of the step 13 of the second embodiment of the production method of thin film transistor (TFT) of the invention；
Figure 14 is the schematic diagram of the step 14 of the second embodiment of the production method of thin film transistor (TFT) of the invention；
Figure 15-16 is the schematic diagram of the step 2 of the second embodiment of the production method of thin film transistor (TFT) of the invention.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Fig. 1-4 is please referred to, the present invention provides a kind of thin film transistor (TFT), comprising: underlay substrate 10 is set to the underlay substrate
Scan line 11 on 10, is set to the scan line 11, grid 12 and underlay substrate at the grid 12 on the underlay substrate 10
Gate insulating layer 20 on 10 on the gate insulating layer 20 and corresponds to the active layer 30 of grid 12, has set on described
Data line 41 in active layer 30 and gate insulating layer 20 and the source electrode 42 on the active layer 30 and gate insulating layer 20
With drain electrode 43；
The grid 12 is connected to 11 side of scan line；The source electrode 42 is connected to 41 side of data line, institute
Drain electrode 43 is stated to be arranged with the source electrode 42 interval；The source electrode 42 and drain electrode 43 connect with the two sides of the active layer 30 respectively
Touching；
The scan line 11 intersects with data line 41, and infall forms the first overlapping region 100；The grid 12 and position
The second overlapping region 200 is formed between the source electrode 42 of 30 side of active layer, while the grid 12 has with positioned at described
Third overlapping region 300 is formed between the drain electrode 43 of 30 other side of active layer；
The scan line 11 corresponds in first, second and third overlapping region 100,200,300 extremely on grid 12
Groove 50 is equipped at few one.
Further, the thin film transistor (TFT) further includes exhausted set on the active layer 30, source electrode 42, drain electrode 43 and grid
Interlayer dielectric layer 60 in edge layer 20 and the pixel electrode 70 on the interlayer dielectric layer 60；
The interlayer dielectric layer 60 be equipped with correspond to it is described drain electrode 43 top via hole 61, the pixel electrode 70 via
Via hole 61 is in contact with the drain electrode 43.
Specifically, the underlay substrate 10 is glass substrate.
Specifically, the scan line 11 and the material of grid 12 include in molybdenum (Mo), aluminium (Al), copper (Cu) and titanium (Ti)
One or more combinations.
Specifically, the gate insulating layer 20 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Specifically, the material of the active layer 30 include in amorphous silicon, polysilicon and metal-oxide semiconductor (MOS) at least
It is a kind of.
Specifically, the data line 41, source electrode 42 and drain 43 material include molybdenum (Mo), aluminium (Al), copper (Cu) and
One of titanium (Ti) or a variety of combinations.
Specifically, the interlayer dielectric layer 60 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Specifically, the material of the pixel electrode 70 is transparent conductive metal oxide, such as tin indium oxide (ITO).
Referring to Fig. 2, for the first embodiment of thin film transistor (TFT) of the invention, in the first embodiment, the grid 12
The upper third overlapping region 300 corresponding between the grid 12 and drain electrode 43 is equipped with a groove 50.
Referring to Fig. 3, for the second embodiment of thin film transistor (TFT) of the invention, in the second embodiment, the grid 12
It is upper to correspond between the second overlapping region 200 between the grid 12 and source electrode 42 and the grid 12 and drain electrode 43
Third overlapping region 300 is respectively equipped with a groove 50.
Referring to Fig. 4, for the 3rd embodiment of thin film transistor (TFT) of the invention, in the 3rd embodiment, the scan line
Correspond to the scan line 11 on 11 and the first overlapping region 100 of the infall of data line 41 is equipped with a groove 50.
According to the formula C=ε * S/4 π kd of parasitic capacitance, wherein C is parasitic capacitance, and ε is dielectric constant, S be pole plate just
To area, d is pole plate spacing, and k is electrostatic force constant.When pole plate spacing d increases, parasitic capacitance C is reduced.
Above-mentioned thin film transistor (TFT), by corresponding to scan line 11 and 41 infall of data line in scan line 11 and grid 12
The first overlapping region 100, the second overlapping region 200 between the grid 12 and source electrode 42 and the grid 12 and leakage
Groove 50 is set at least one in third overlapping region 300 between pole 43, so that the parasitism of the overlapping region at least one
The pole plate spacing of capacitor increases, to reduce parasitic capacitance, increases device stability, avoid occurring when display image it is viscous and
The abnormal phenomenon such as color displacement.
Referring to Fig. 5, including the following steps: the present invention also provides a kind of production method of above-mentioned thin film transistor (TFT)
Step 1, referring to Fig. 1, simultaneously refering to Fig. 9 or Figure 14, a underlay substrate 10 is provided, on the underlay substrate 10
The grid 12 for forming scan line 11 and being connected to 11 side of scan line；
The scan line 11 with correspond on grid 12 scan line 11, grid 12 and the data line 41 being subsequently formed,
Groove is equipped at least one in first, second and third overlapping region 100,200,300 between source electrode 42 and drain electrode 43
50；
First, the between the scan line 11, grid 12 and the data line 41 being subsequently formed, source electrode 42 and drain electrode 43
Two and third overlapping region 100,200,300 include the first of the scan line 11 and 41 infall of data line being subsequently formed
The second overlapping region 200 and the grid 12 between overlapping region 100, the grid 12 and the source electrode 42 being subsequently formed
With the third overlapping region 300 between the drain electrode 43 that is subsequently formed.
Specifically, the step 1 includes:
Step 11, referring to Fig. 6, provide a underlay substrate 10, a conductive layer 80 is formed on the underlay substrate 10；
Step 12 please refers to Fig. 7 or Figure 12, photoresist layer 90 is formed on the conductive layer 80, using a halftone mask
Processing is patterned to the photoresist layer 90, the photoresist layer 90 of reservation is used to define the figure of scan line 11 Yu grid 12, and
And the photoresist layer 90 of the reservation is equipped at least one groove 91；
It is first Chong Die to correspond to scan line 11 and 41 infall of data line being subsequently formed at least one described groove 91
The second overlapping region 200 and grid 12 between region 100, grid 12 and the source electrode 42 being subsequently formed be subsequently formed
At at least one in third overlapping region 300 between drain electrode 43；
The region that retained photoresist layer 90 does not block on the conductive layer 80 is etched, scan line 11 and grid are formed
Pole 12；
Step 13 please refers to Fig. 8 or Figure 13, carries out ashing processing, the photoresist layer of the reservation to the photoresist layer 90 of reservation
90 positions for being equipped at least one groove 91 become at least one through-hole 92, and the thickness of remaining position reduces；
Step 14 please refers to Fig. 9 or Figure 14, is barrier bed with the photoresist layer 90 after being ashed, to the scan line 11 and grid
At least one of pole 12 is etched, and forms at least one groove at least one of the scan line 11 and grid 12
50；
Remove remaining photoresist layer 90.
Step 2 please refers to Figure 10-11 or Figure 15-16, forms grid on scan line 11, grid 12 and underlay substrate 10
Pole insulating layer 20；
Active layer 30 is formed on the gate insulating layer 20；
41, source electrode 42 and drain electrode 43 are formed data line on the active layer 30 and gate insulating layer 20；
The source electrode 42 is connected to 41 side of data line, and the drain electrode 43 is arranged with the source electrode 42 interval；It is described
Source electrode 42 and drain electrode 43 are in contact with the two sides of the active layer 30 respectively.
Step 3 please refers to Fig. 2 or Fig. 3, the shape on the active layer 30, source electrode 42, drain electrode 43 and gate insulating layer 20
At interlayer dielectric layer 60, processing is patterned to the interlayer dielectric layer 60, is formed and is corresponded on the interlayer dielectric layer 60
Via hole 61 above the drain electrode 43；
Pixel electrode 70 is formed on the interlayer dielectric layer 60, the pixel electrode 70 is via via hole 61 and the drain electrode
43 are in contact.
Fig. 1, Fig. 2 and Fig. 6-11 is please referred to, is the first embodiment of the production method of thin film transistor (TFT) of the invention,
The embodiment includes:
Step 1 please refers to Fig. 6-9, provides a underlay substrate 10, on the underlay substrate 10 formed scan line 11 and
It is connected to the grid 12 of 11 side of scan line；
Correspond to the third overlapping region 300 between the grid 12 and the drain electrode 43 being subsequently formed on the grid 12 to set
There is a groove 50.
Specifically, the step 1 includes:
Step 11, referring to Fig. 6, provide a underlay substrate 10, a conductive layer 80 is formed on the underlay substrate 10；
Step 12, referring to Fig. 7, on the conductive layer 80 formed photoresist layer 90, using a halftone mask to described
Photoresist layer 90 is patterned processing, and the photoresist layer 90 of reservation is used to define the figure of scan line 11 Yu grid 12, and described
The photoresist layer 90 of reservation is equipped with a groove 91；The groove 91 corresponds to the between grid 12 and the drain electrode 43 being subsequently formed
Triple-overlapped region 300；
The region that retained photoresist layer 90 does not block on the conductive layer 80 is etched, scan line 11 and grid are formed
Pole 12；
Step 13, referring to Fig. 8, carrying out ashing processing to the photoresist layer 90 of reservation, set on the photoresist layer 90 of the reservation
There is the position of a groove 91 to become a through-hole 92, the thickness of remaining position reduces；
Step 14, referring to Fig. 9, be ashed after photoresist layer 90 be barrier bed, grid 12 is etched, in the grid
A groove 50 is formed on pole 12；
Remove remaining photoresist layer 90.
Step 2 please refers to Figure 10-11, and gate insulating layer 20 is formed on scan line 11, grid 12 and underlay substrate 10；
Active layer 30 is formed on the gate insulating layer 20；
41, source electrode 42 and drain electrode 43 are formed data line on the active layer 30 and gate insulating layer 20；
The source electrode 42 is connected to 41 side of data line, and the drain electrode 43 is arranged with the source electrode 42 interval；It is described
Source electrode 42 and drain electrode 43 are in contact with the two sides of the active layer 30 respectively.
Step 3, referring to Fig. 2, the active layer 30, source electrode 42, drain electrode 43 and gate insulating layer 20 on form interlayer
Dielectric layer 60 is patterned processing to the interlayer dielectric layer 60, is formed described in corresponding on the interlayer dielectric layer 60
The via hole 61 of 43 top of drain electrode；
Pixel electrode 70 is formed on the interlayer dielectric layer 60, the pixel electrode 70 is via via hole 61 and the drain electrode
43 are in contact.
Fig. 1, Fig. 3, Fig. 6 and Figure 12-16 is please referred to, is that the second of the production method of thin film transistor (TFT) of the invention is real
Example is applied, which includes:
Step 1 please refers to Fig. 6 and Figure 12-14, provides a underlay substrate 10, and scanning is formed on the underlay substrate 10
Line 11 and the grid 12 for being connected to 11 side of scan line；
Correspond on the grid 12 the second overlapping region 200 between the grid 12 and the source electrode 42 being subsequently formed,
And the third overlapping region 300 between the grid 12 and the drain electrode 43 being subsequently formed is respectively equipped with a groove 50.
Specifically, the step 1 includes:
Step 11, referring to Fig. 6, provide a underlay substrate 10, a conductive layer 80 is formed on the underlay substrate 10；
Step 12 please refers to Figure 12, photoresist layer 90 is formed on the conductive layer 80, using a halftone mask to described
Photoresist layer 90 is patterned processing, and the photoresist layer 90 of reservation is used to define the figure of scan line 11 Yu grid 12, and described
Groove 91 there are two being set on the photoresist layer 90 of reservation；The source electrode that described two grooves 91 correspond respectively to grid 12 and are subsequently formed
The third overlapping region 300 between the second overlapping region 200 and grid 12 and the drain electrode 43 being subsequently formed between 42；
The region that retained photoresist layer 90 does not block on the conductive layer 80 is etched, scan line 11 and grid are formed
Pole 12；
Step 13 please refers to Figure 13, carries out ashing processing to the photoresist layer 90 of reservation, sets on the photoresist layer 90 of the reservation
There are two the positions of groove 91 to become two through-holes 92, and the thickness of remaining position reduces；
Step 14 please refers to Figure 14, is barrier bed with the photoresist layer 90 after being ashed, is etched to grid 12, described
Two grooves 50 are formed on grid 12；
Remove remaining photoresist layer 90.
Step 2 please refers to Figure 15-16, and gate insulating layer 20 is formed on scan line 11, grid 12 and underlay substrate 10；
Active layer 30 is formed on the gate insulating layer 20；
41, source electrode 42 and drain electrode 43 are formed data line on the active layer 30 and gate insulating layer 20；
The source electrode 42 is connected to 41 side of data line, and the drain electrode 43 is arranged with the source electrode 42 interval；It is described
Source electrode 42 and drain electrode 43 are in contact with the two sides of the active layer 30 respectively.
Step 3, referring to Fig. 3, the active layer 30, source electrode 42, drain electrode 43 and gate insulating layer 20 on form interlayer
Dielectric layer 60 is patterned processing to the interlayer dielectric layer 60, is formed described in corresponding on the interlayer dielectric layer 60
The via hole 61 of 43 top of drain electrode；
Pixel electrode 70 is formed on the interlayer dielectric layer 60, the pixel electrode 70 is via via hole 61 and the drain electrode
43 are in contact.
The production method of above-mentioned thin film transistor (TFT), by corresponding to scan line 11 and data in scan line 11 and grid 12
The second overlapping region 200 between first overlapping region 100 of 41 infall of line, the grid 12 and source electrode 42 and described
Grooving is carried out at least one in third overlapping region 300 between grid 12 and drain electrode 43, so that the overlay region at least one
The pole plate spacing of the parasitic capacitance in domain increases, to reduce parasitic capacitance, increases device stability, avoids image occur when display
The abnormal phenomenon such as viscous and color displacement.
In conclusion the present invention provides a kind of thin film transistor and its manufacturing method, by scan line with it is right on grid
Should between the first overlapping region of scan line and data line infall, grid and source electrode the second overlapping region and grid
Groove is set at least one in third overlapping region between drain electrode, so that the parasitic capacitance of the overlapping region at least one
Pole plate spacing increase, to reduce parasitic capacitance, increase device stability, avoid occurring when display that image is viscous and color
The abnormal phenomenon such as offset.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the claims in the present invention
Protection scope.
Claims (5)
1. a kind of thin film transistor (TFT) characterized by comprising underlay substrate (10) is set to sweeping on the underlay substrate (10)
It retouches line (11), the grid (12) being set on the underlay substrate (10), be set to the scan line (11), grid (12) and substrate base
Gate insulating layer (20) on plate (10), the active layer on the gate insulating layer (20) and corresponding to grid (12)
(30), the active layer (30) and data line (41) on gate insulating layer (20) are set to and is set to the active layer (30)
And the source electrode (42) on gate insulating layer (20) and drain electrode (43)；
The grid (12) is connected to the scan line (11) side；The source electrode (42) is connected to the data line (41) one
Side, the drain electrode (43) and the source electrode (42) interval are arranged；The source electrode (42) and drain electrode (43) respectively with the active layer
(30) two sides are in contact；
The scan line (11) intersects with data line (41), and infall forms the first overlapping region (100)；The grid (12)
It is formed the second overlapping region (200) between the source electrode (42) of the active layer (30) side, while the grid (12)
Third overlapping region (300) are formed between the drain electrode (43) of the active layer (30) other side；
Correspond in first, second and third overlapping region (100,200,300) on the scan line (11) and grid (12)
Groove (50) are equipped at least one.
2. thin film transistor (TFT) as described in claim 1, which is characterized in that further include being set to the active layer (30), source electrode
(42), it drains (43) and interlayer dielectric layer (60) on gate insulating layer (20) and is set on the interlayer dielectric layer (60)
Pixel electrode (70)；
The interlayer dielectric layer (60) is equipped with the via hole (61) corresponded to above the drain electrode (43), the pixel electrode (70)
It is in contact via via hole (61) with the drain electrode (43).
3. a kind of production method of thin film transistor (TFT) as described in claim 1, which comprises the steps of:
Step 1 provides a underlay substrate (10), forms scan line (11) on the underlay substrate (10) and is connected to described
The grid (12) of scan line (11) side；
Correspond to the scan line (11) on the scan line (11) and grid (12) and grid (12) and the data that are subsequently formed
In first, second and third overlapping region (100,200,300) between line (41), source electrode (42) and drain electrode (43) at least
Groove (50) are equipped at one；
Between the scan line (11) and grid (12) and the data line (41) being subsequently formed, source electrode (42) and drain electrode (43)
First, second and third overlapping region (100,200,300) include the scan line (11) and the data line (41) that is subsequently formed
The second overlapping region between the first overlapping region (100) of infall, the grid (12) and the source electrode (42) being subsequently formed
(200) and the third overlapping region (300) between the grid (12) and the drain electrode (43) being subsequently formed；
Step 2 forms gate insulating layer (20) on scan line (11), grid (12) and underlay substrate (10)；
Active layer (30) are formed on the gate insulating layer (20)；
(41), source electrode (42) and drain electrode (43) are formed data line on the active layer (30) and gate insulating layer (20)；
The source electrode (42) is connected to the data line (41) side, and the drain electrode (43) and the source electrode (42) interval are arranged；
The source electrode (42) and drain electrode (43) are in contact with the two sides of the active layer (30) respectively.
4. the production method of thin film transistor (TFT) as claimed in claim 3, which is characterized in that the step 1 specifically includes:
Step 11 provides a underlay substrate (10), and a conductive layer (80) are formed on the underlay substrate (10)；
Step 12 forms photoresist layer (90) on the conductive layer (80), using a halftone mask to the photoresist layer (90)
It is patterned processing, the photoresist layer (90) of reservation is used to define the figure of scan line (11) Yu grid (12), and the guarantor
The photoresist layer (90) stayed is equipped at least one groove (91)；
At least one described groove (91) corresponds to the first weight of scan line (11) with data line (41) infall being subsequently formed
The second overlapping region (200) and grid (12) between folded region (100), grid (12) and the source electrode (42) being subsequently formed
At at least one in the third overlapping region (300) between the drain electrode (43) that is subsequently formed；
The region blocked to photoresist layer (90) not retained on the conductive layer (80) is etched, formed scan line (11) with
Grid (12)；
Step 13 carries out ashing processing to the photoresist layer (90) of reservation, and the photoresist layer (90) of the reservation is equipped at least one
The position of groove (91) becomes at least one through-hole (92), and the thickness of remaining position reduces；
Step 14, with the photoresist layer (90) after being ashed for barrier bed, at least one in the scan line (11) and grid (12)
It is a to be etched, at least one groove (50) is formed at least one of the scan line (11) and grid (12)；
Remove remaining photoresist layer (90).
5. the production method of thin film transistor (TFT) as claimed in claim 3, which is characterized in that further include step 3, described active
Interlayer dielectric layer (60) are formed on layer (30), source electrode (42), drain electrode (43) and gate insulating layer (20), to the interlayer dielectric
Layer (60) is patterned processing, and the via hole corresponded to above the drain electrode (43) is formed on the interlayer dielectric layer (60)
(61)；
Formed on the interlayer dielectric layer (60) pixel electrode (70), the pixel electrode (70) via via hole (61) with it is described
Drain electrode (43) is in contact.
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| CN109283758B (en) * | 2017-07-21 | 2021-09-28 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN107248393B (en) * | 2017-07-24 | 2019-04-26 | 上海交通大学 | Pixel drive unit and forming method thereof, display backboard, pixel-driving circuit |
| CN109004032B (en) * | 2018-08-01 | 2020-07-28 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof and array substrate |
| CN110890386B (en) * | 2018-09-11 | 2023-08-25 | 夏普株式会社 | Thin film transistor substrate, liquid crystal display device, and organic electroluminescent display device |
| CN110707109B (en) * | 2019-11-28 | 2022-12-02 | 京东方科技集团股份有限公司 | Display panel, driving backboard and manufacturing method thereof |
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