CN115050839A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first oxide layer, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The first oxide layer is located on the substrate. The insulation pattern is positioned on the first oxide layer and comprises a silicon nitride layer and a second oxide layer. The silicon nitride layer is located between the first oxide layer and the second oxide layer. The metal oxide layer contacts the upper surface of the first oxide layer, the sidewalls of the insulating pattern, and the upper surface of the insulating pattern. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. Part of the insulation pattern is located between the gate and the substrate. The source electrode and the drain electrode are electrically connected with the metal oxide layer.

Description

Semiconductor device and method of manufacturing the same

technical field

The present invention relates to a semiconductor device and a method of manufacturing the same.

Background technique

At present, common thin film transistors usually use amorphous silicon semiconductors as channels, wherein amorphous silicon semiconductors are widely used in various thin film transistors due to their simple process and low cost.

With the advancement of display technology, the resolution of display panels has increased year by year. In order to shrink thin film transistors in pixel circuits, many manufacturers are working on developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device and a manufacturing method thereof, which can improve the hot carrier effect at the drain, thereby improving reliability.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first oxide layer, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The first oxide layer is over the substrate. The insulating pattern is on the first oxide layer and includes a silicon nitride layer and a second oxide layer. A silicon nitride layer is located between the first oxide layer and the second oxide layer. The metal oxide layer contacts the upper surface of the first oxide layer, the sidewalls of the insulating pattern, and the upper surface of the insulating pattern. A gate dielectric layer is on the metal oxide layer. The gate is on the gate dielectric layer. Part of the insulating pattern is located between the gate and the substrate. The source electrode and the drain electrode are electrically connected to the metal oxide layer.

At least one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising: forming a first oxide layer on a substrate; forming an insulating pattern on the first oxide layer, wherein the insulating pattern includes a silicon nitride layer and a first oxide layer. A silicon dioxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer; a metal oxide layer is formed on the upper surface of the first oxide layer, the sidewalls of the insulating pattern and the top of the insulating pattern on the surface; forming a gate dielectric layer on the metal oxide layer; forming a gate electrode on the gate dielectric layer, wherein part of the insulating pattern is located between the gate electrode and the substrate; forming a source electrode and a drain electrode electrically connected to the metal oxide layer pole.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a drain electrode, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate electrode, and a source electrode. The drain is on the substrate. The insulating pattern is over the drain, and the drain is under the first contact hole of the insulating pattern. The metal oxide layer is on the insulating pattern and fills the first contact hole. The metal oxide layer contacts the upper surface of the insulating pattern, the sidewall of the first contact hole of the insulating pattern, and the drain electrode. A gate dielectric layer is on the metal oxide layer. The gate is on the gate dielectric layer. The source electrode is electrically connected to the metal oxide layer.

At least one embodiment of the present invention provides a method for fabricating a semiconductor device, including forming a drain electrode on a substrate; forming a silicon nitride layer blanketing the drain electrode; forming an oxide blanket blanketing the silicon nitride layer layer; performing a first patterning process on the silicon nitride layer and the oxide layer to form first contact holes and openings, wherein the first contact holes pass through the oxide layer and the silicon nitride layer, and the openings pass through the oxide layer and does not pass through the silicon nitride layer; a metal oxide layer is formed on the silicon nitride layer and the oxide layer, and the metal oxide layer fills the first contact hole and contacts the upper surface of the oxide layer and the first contact The sidewall of the hole and the drain; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer; forming a source electrode electrically connected to the metal oxide layer.

Description of drawings

FIG. 1A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line a-a' of Fig. 1A.

2A to 2E are schematic cross-sectional views of a method for fabricating a semiconductor device according to an embodiment of the present invention.

3A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view taken along the line a-a' of Fig. 3A.

4A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 4B is a schematic cross-sectional view taken along the line a-a' of Fig. 4A.

5A to 10A are top views of a method of fabricating a semiconductor device according to an embodiment of the present invention.

5B to 10B are schematic cross-sectional views along line a-a' of FIGS. 5A to 10A, respectively.

FIG. 11A is a top view of a display device according to an embodiment of the present invention.

FIG. 11B is a partial enlarged schematic view of FIG. 11A .

Description of reference numbers:

10A, 10B, 10C: Semiconductor devices

100: Substrate

110: first oxide layer

120: Insulation pattern

122: Silicon nitride layer

124 second oxide layer

130: Gate Dielectric Layer

140: Interlayer dielectric layer

AA: display area

a-a': line

BA: Surrounding area

ch: channel area

D: Drain

dr: drain region

G: Gate

HD: Height difference

HDF: Thermal Structure

h: hydrogen concentration gradient area

ND: normal direction

OP: open mouth

OS,OS': metal oxide layer

P: doping process

PR: patterned photoresist layer

S: source

sr: source region

sw, sw1a, sw1b, sw2: sidewalls

T: Connection electrode

t1,t2,t3,t4: Thickness

ts1, ts2: upper surface

V1: first contact hole

V2: second contact hole

V3: third contact hole

Detailed ways

FIG. 1A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view taken along line a-a' of Fig. 1A.

1A and FIG. 1B , the semiconductor device 10A includes a substrate 100 , a first oxide layer 110 , an insulating pattern 120 , a metal oxide layer OS, a gate dielectric layer 130 , a gate G, a source S and a drain D, The insulating pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124 . In this embodiment, the semiconductor device 10A further includes an interlayer dielectric layer 140 . For convenience of description, FIG. 1A shows the metal oxide layer OS, the silicon nitride layer 122 , the gate electrode G, the source electrode S, and the drain electrode D, and other components are omitted.

The material of the substrate 100 can be glass, quartz, organic polymer or opaque/reflective material (eg, conductive material, metal, wafer, ceramic or other applicable materials) or other applicable materials. If conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid the short circuit problem. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester ( polyester, PES), polymethylmethacrylate (polymethylmethacrylate, PMMA), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI) or metal soft plate (Metal Foil) or other flexible materials.

The first oxide layer 110 is located on the substrate 100 . In some embodiments, the first oxide layer 110 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, or other suitable materials. In some embodiments, the thickness t1 of the first oxide layer 110 is 500 angstroms to 3000 angstroms.

The insulating pattern 120 is located on the first oxide layer 110 and includes a silicon nitride layer 122 and a second oxide layer 124 . In some embodiments, the silicon nitride layer 122 contains hydrogen. In some embodiments, the thickness t2 of the silicon nitride layer 122 is 100 angstroms to 1500 angstroms. The second oxide layer 124 is located on the silicon nitride layer 122 , and the silicon nitride layer 122 is located between the first oxide layer 110 and the second oxide layer 124 . The second oxide layer 124 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, or other suitable materials. In some embodiments, the first oxide layer 110 and the second oxide layer 124 are both silicon oxide or silicon oxynitride, and the oxygen concentration of the first oxide layer 110 is greater than that of the second oxide layer 124 . For example, the first oxide layer 110 includes SiOx, the second oxide layer 124 includes SiOy, and x is greater than y. In some embodiments, the thickness t3 of the second oxide layer 124 is 100 angstroms to 1500 angstroms.

The metal oxide layer OS is located on the first oxide layer 110 and the insulating pattern 120 . The metal oxide layer OS contacts the upper surface ts1 of the first oxide layer 110 , the sidewall sw of the insulating pattern 120 , and the upper surface ts2 of the insulating pattern 120 . In some embodiments, the sidewall sw of the insulating pattern 120 includes the silicon nitride layer 122 and the second oxide layer 124 , and the metal oxide layer OS contacts the silicon nitride layer 122 and the second oxide layer at the position of the sidewall sw layer 124.

The metal oxide layer OS includes a source region sr, a drain region dr, and a channel region ch between the source region sr and the drain region dr. The source region sr and the drain region dr are doped to have a lower resistivity than the channel region ch. In this embodiment, the source region sr contacts the upper surface ts1 of the first oxide layer 110 , the channel region ch contacts the upper surface ts1 of the first oxide layer 110 and the sidewall sw of the insulating pattern 120 , and the drain region dr The upper surface ts2 of the insulating pattern 120 is contacted. In some embodiments, the distance between the source region sr and the substrate 100 is smaller than the distance between the drain region dr and the substrate 100 . In some embodiments, there is a height difference HD between the bottom surface of the drain region dr and the bottom surface of the source region sr, and the height difference HD is, for example, approximately equal to the thickness of the insulating pattern 120 . In this embodiment, the part of the channel region ch connected to the drain region dr extends along the vertical direction (the normal direction ND), which can reduce the hot carrier generated by the lateral electric field in the metal oxide layer OS near the drain D. effect.

In some embodiments, since the drain region dr is located on the silicon nitride layer 122 containing hydrogen element, the hydrogen concentration of the drain region dr is greater than that of the source region sr. Therefore, the hydrogen resistivity of the drain region dr is lower than that of the source region sr.

In some embodiments, the material of the metal oxide layer OS includes quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin (AZTO), and indium tungsten zinc oxide (IWZO). Or an oxide composed of a ternary metal including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W).

The gate dielectric layer 130 is on the metal oxide layer OS. The gate dielectric layer 130 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the thickness t4 of the gate dielectric layer 130 is 500 angstroms to 3000 angstroms.

The gate G is on the gate dielectric layer 130 . Part of the insulating pattern 120 is located between the gate G and the substrate 100 . In this embodiment, in the normal direction ND of the top surface of the substrate 100 , part of the gate G overlaps the insulating pattern 120 , and another part of the gate G does not overlap the insulating pattern 120 . In this embodiment, the drain region dr extends between the gate G and the substrate 100 . Part of the gate G overlaps the drain region dr, and another part overlaps the channel region ch.

In some embodiments, the material of the gate G may include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or any combination of the foregoing metals Alloys or stacks of the above metals and/or alloys, but the present invention is not limited thereto. The gate G can also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, a stacked layer of metal and other conductive materials, or other materials with conductive properties.

The interlayer dielectric layer 140 is disposed on the gate dielectric layer 130 . The interlayer dielectric layer 140 covers the gate G. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials.

The drain electrode D and the source electrode S are disposed on the interlayer dielectric layer 140 . In the normal direction ND, the drain electrode D overlaps the insulating pattern 120 , and the source electrode S does not overlap the insulating pattern 120 . The drain electrode D and the source electrode S are respectively electrically connected to the drain electrode region dr and the source electrode region sr of the metal oxide layer OS through the first contact hole V1 and the second contact hole V2 in the interlayer dielectric layer 140 . In some embodiments, the material of the drain electrode D and the source electrode S may include metals, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc or the above metals Any combination of alloys or stacks of the above metals and/or alloys, but the present invention is not limited thereto. The drain electrode D and the source electrode S can also use other conductive materials, such as metal nitride, metal oxide, metal oxynitride, a stacked layer of metal and other conductive materials, or other materials with conductive properties.

2A to 2E are schematic cross-sectional views illustrating a method of manufacturing the semiconductor device 10A of FIGS. 1A and 1B .

Referring to FIG. 2A , a first oxide layer 110 is formed on the substrate 100 . Next, an insulating pattern 120 is formed on the first oxide layer 110 . In some embodiments, the method of forming the insulating pattern 120 includes forming a silicon nitride material layer blanketed on the first oxide layer 110 . Next, an oxide material layer blanketed on the silicon nitride material layer is formed. The oxide material layer and the silicon nitride material layer are then patterned through a photolithography etching process to form the silicon nitride layer 122 and the second oxide layer 124 . In some embodiments, the method for forming the oxide material layer and the silicon nitride material layer includes chemical vapor deposition or plasma enhanced chemical vapor deposition, and the gas used for forming the silicon nitride material layer includes silicon methane (SiH ₄ ), Nitrogen gas (N ₂ ), ammonia gas (NH ₃ ), and other suitable gases, therefore, the silicon nitride layer 122 includes hydrogen element.

Referring to FIG. 2B , a metal oxide OS' is formed on the upper surface ts1 of the first oxide layer 110 , the sidewall sw of the insulating pattern 120 and the upper surface ts2 of the insulating pattern 120 . In this embodiment, there is a discontinuity between the upper surface ts1 of the first oxide layer 110 and the upper surface ts2 of the insulating pattern 120 , and the metal oxide OS′ covers the upper surface ts1 of the first oxide layer 110 and the insulating pattern The position of the break between the upper surfaces ts2 of 120.

In some embodiments, the first oxide layer 110 has a function of storing oxygen elements. When the metal oxide OS' is deposited, part of the oxygen element diffuses into the first oxide layer 110. At this time, the first oxide layer 110 has a relatively high oxygen concentration. However, since the second oxide layer 124 of the insulating pattern 120 has a poor ability to store oxygen elements, the second oxide layer 124 has a relatively low oxygen concentration.

A gate dielectric layer 130 is formed on the metal oxide layer OS'. In some embodiments, the metal oxide layer OS' is heated when the gate dielectric layer 130 is deposited, so that oxygen in the metal oxide layer OS' diffuses out, eg, to the first oxide layer 110 or the gate dielectric. In the layer 130, oxygen vacancies are generated in the metal oxide layer OS', so that the resistivity of the metal oxide layer OS' decreases. Oxygen in the metal oxide layer OS' located above the second oxide layer 124 is less likely to diffuse down into the second oxide layer 124 due to the poor ability of the second oxide layer 124 to store oxygen elements . In addition, in some embodiments, the hydrogen of the silicon nitride layer 122 diffuses upward into the metal oxide layer OS′ located above the second oxide layer 124 , further reducing the metal oxide layer above the second oxide layer 124 The resistivity of OS'.

Referring to FIG. 2C , in some embodiments, after the gate dielectric layer 130 is deposited, an annealing process is performed to diffuse the oxygen elements stored in the first oxide layer 110 and the gate dielectric layer 130 to the metal oxide layer OS 'middle. The oxygen element combines with the oxygen vacancies of the metal oxide layer OS' to increase the resistivity of the metal oxide layer OS', for example, the resistivity is increased from about 1E+4ohm/sq to more than 1E+8ohm/sq.

In some embodiments, since more oxygen is stored in the first oxide layer 110 than in the second oxide layer 124 , more oxygen will diffuse to the portion located on the first oxide layer 110 In the metal oxide layer OS', the oxygen concentration of the part of the metal oxide layer OS' located on the first oxide layer 110 is increased more, and the oxygen concentration of another part of the metal oxide layer OS' located on the second oxide layer 124 The oxygen concentration is relatively small. In other words, after the formation annealing process, the resistivity of the part of the metal oxide layer OS' on the first oxide layer 110 is higher than that of the other part of the metal oxide layer OS' on the second oxide layer 124 resistivity.

Referring to FIG. 2D , a gate G is formed on the gate dielectric layer 130 . Next, using the gate G as a mask, a doping process P is performed on the metal oxide layer OS', so as to form a source region sr, a drain region dr, and a source region sr and a drain region in the metal oxide layer OS' The channel region ch between the polar regions dr. In some embodiments, the doping process P is, for example, a hydrogen plasma doping process or other suitable processes.

In some embodiments, the hydrogen element in the silicon nitride layer 122 can maintain the hydrogen concentration of the drain region dr of the metal oxide layer OS, so that the hydrogen in the drain region dr is not easily dissipated in subsequent processes. In addition, in some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the drain region dr, so that the hydrogen concentration of the drain region dr is greater than that of the source region sr. In addition, since part of the silicon nitride layer 122 is located between the gate G and the substrate 100 , the metal oxide layer OS′/OS partially overlapping the gate G will also be doped with hydrogen, so that part of the metal oxide layer OS′/OS overlapping the gate G will be doped with hydrogen. The metal oxide layer OS'/OS is transformed into the drain region dr, which further reduces the hot carrier effect generated by the electric field at the edge of the gate G. In some embodiments, the drain region dr overlapping the gate G and the drain region dr not overlapping the gate G have different hydrogen concentrations, wherein the hydrogen concentration of the drain region dr not overlapping the gate G is greater than The hydrogen concentration of the drain region dr overlapping the drain region dr of the gate G.

Referring to FIG. 2E , an interlayer dielectric layer 140 is formed on the gate dielectric layer 130 . The interlayer dielectric layer 140 covers the gate G.

Next, one or more etching processes are performed to form the first contact hole V1 and the second contact hole V2 through the interlayer dielectric layer 140 and the gate dielectric layer 130 . The first contact hole V1 and the second contact hole V2 overlap and expose the drain region dr and the source region sr of the metal oxide layer OS.

Finally, returning to FIG. 1 , the drain electrode D and the source electrode S are formed on the interlayer dielectric layer 140 , and the drain electrode D and the source electrode S are formed in the first contact hole V1 and the second contact hole V2 . The drain electrode D and the source electrode S are respectively connected to the drain electrode region dr and the source electrode region sr of the metal oxide layer OS. So far, the semiconductor device 10A is substantially completed.

Based on the above, the silicon nitride layer 122 in the insulating pattern 120 can improve the problem that the hydrogen element in the metal oxide layer OS escapes during the heating process, and can even provide additional hydrogen element to the metal oxide layer OS. Therefore, the silicon nitride layer 122 in the insulating pattern 120 can avoid the increase of the resistivity of the drain region dr of the metal oxide layer OS due to the escape of hydrogen, thereby improving the hot carrier effect near the drain D.

3A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view taken along the line a-a' of Fig. 3A. It must be noted here that the embodiments of FIGS. 3A and 3B use the element numbers and part of the content of the embodiment of FIGS. 1A and 1B , wherein the same or similar numbers are used to represent the same or similar elements, and the same elements are omitted. Description of technical content. For the description of the omitted part, reference may be made to the foregoing embodiments, which will not be repeated here.

The main difference between the semiconductor device 10B of FIGS. 3A and 3B and the semiconductor device 10A of FIGS. 1A and 1B is that the silicon nitride layer 122 of the insulating pattern 120 of the semiconductor device 10B does not extend below the gate G.

Referring to FIG. 3A and FIG. 3B , in this embodiment, the silicon nitride layer 122 does not overlap the gate G in the normal direction ND. The drain region dr of the metal oxide layer OS does not extend below the gate G.

In this embodiment, the sidewall sw of the insulating pattern 120 only includes the second oxide layer 124 , and the metal oxide layer OS does not directly contact the silicon nitride layer 122 .

In addition, in this embodiment, the silicon nitride layer 122 and the second oxide layer 124 of the insulating pattern 120 include different shapes. The silicon nitride layer 122 and the second oxide layer 124 are defined by different lithographic etching processes.

Based on the above, the silicon nitride layer 122 in the insulating pattern 120 can improve the problem that the hydrogen element in the metal oxide layer OS escapes during the heating process, and can even provide additional hydrogen element to the metal oxide layer OS. Therefore, the silicon nitride layer 122 in the insulating pattern 120 can avoid the increase of the resistivity of the drain region dr of the metal oxide layer OS due to the escape of hydrogen, thereby improving the hot carrier effect near the drain D.

4A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the line a-a' of Fig. 4A.

4A and 4B, the semiconductor device 10C includes a substrate 100, a drain D, an insulating pattern 120, a metal oxide layer OS, a gate dielectric layer 130, a gate G and a source S, wherein the insulating pattern 120 includes a nitride The silicon layer 122 and the second oxide layer 124 . In this embodiment, the semiconductor device 10C further includes a heat dissipation structure HDF, an interlayer dielectric layer 140 and a connection electrode T. As shown in FIG. For convenience of description, FIG. 4A shows the heat dissipation structure HDF, the drain D, the metal oxide layer OS, the gate G, the source S, and the connection electrode T, and other components are omitted.

The heat dissipation structure HDF is located on the substrate 100 . In this embodiment, the heat dissipation structure HDF is directly formed on the substrate 100, but the invention is not limited to this. In other embodiments, other buffer layers such as silicon oxide, silicon nitride, silicon oxynitride or other insulating materials are sandwiched between the heat dissipation structure HDF and the substrate 100 . In some embodiments, the heat dissipation structure HDF is a thermally conductive insulating material, such as aluminum nitride, aluminum oxide, or other materials. In some embodiments, the thermal conductivity of the heat dissipation structure HDF is greater than 2W·m ⁻¹ °C ⁻¹ . The thickness of the heat dissipation structure HDF can be adjusted according to actual needs.

The drain D is located on the substrate 100 . In this embodiment, the drain D is directly formed on the heat dissipation structure HDF. The heat dissipation structure HDF is located between the drain D and the substrate 100 and is thermally connected to the drain D. The vertical projection area of the drain D on the substrate 100 is smaller than the vertical projection area of the heat dissipation structure HDF on the substrate 100 .

The insulating pattern 120 is located on the drain D. The insulating pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124 . In some embodiments, the silicon nitride layer 122 contains hydrogen. In some embodiments, the thickness t2 of the silicon nitride layer 122 is 30 nm to 300 nm. The second oxide layer 124 is located on the silicon nitride layer 122 , and the silicon nitride layer 122 is located between the second oxide layer 124 and the substrate 100 . The second oxide layer 124 includes silicon oxide, silicon oxynitride, aluminum oxide, or other insulating materials. In some embodiments, the thickness t3 of the second oxide layer 124 is 50 nm to 200 nm.

The insulating pattern 120 has a first contact hole V1 and a second contact hole V2. The sidewalls sw1a and sw1b of the first contact hole V1 include a silicon nitride layer 122 and a second oxide layer 124 . The sidewall sw2 of the second contact hole V2 includes the second oxide layer 124 . The drain D is located under the first contact hole V1 and the second contact hole V2 of the insulating pattern 120 . In this embodiment, the second oxide layer 124 of the insulating pattern 120 has an opening OP, and the second contact hole V2 passes through the silicon nitride layer 122 at the bottom of the opening OP. In some embodiments, the width of the opening OP is greater than the width of the second contact hole V2.

The metal oxide layer OS is located on the insulating pattern 120 and filled in the first contact hole V1. The metal oxide layer OS contacts the upper surface ts2 of the insulating pattern 120 , the sidewalls sw1a and sw1b of the first contact hole V1 of the insulating pattern 120 , and the drain electrode D. In this embodiment, the metal oxide layer OS contacts the silicon nitride layer 122 and the oxide layer 124 .

The metal oxide layer OS includes a source region sr, a channel region ch, a hydrogen concentration gradient region h, and a drain region dr which are connected in sequence. The channel region ch is connected between the hydrogen concentration gradient region h and the source region sr. The hydrogen concentration gradient region h is connected between the channel region ch and the drain region dr. The source region sr, the hydrogen concentration gradient region h, and the drain region dr are doped to have a lower resistivity than the channel region ch. In this embodiment, the resistivity of the drain D is lower than the resistivity of the source region sr and the drain region dr, the resistivity of the source region sr and the drain region dr is lower than the resistivity of the hydrogen concentration gradient region h, And the resistivity of the hydrogen concentration gradient region h is lower than that of the channel region ch.

The source region sr contacts the upper surface ts2 of the second oxide layer 124 . The channel region ch contacts the upper surface ts2 and the second oxide layer 124 at the sidewall sw1a. The hydrogen concentration gradient region h contacts the silicon nitride layer 122 at the sidewall sw1a and the upper surface of the drain electrode D. As shown in FIG. The drain region dr is electrically connected to the drain D, and contacts the upper surface of the drain D, the silicon nitride layer 122 at the sidewall sw1b, and the second oxide layer 124 at the sidewall sw1b. In this embodiment, there is a height difference HD between the bottom surface of the drain region dr and the bottom surface of the source region sr, and the height difference HD is, for example, approximately equal to the depth of the first contact hole V1. In this embodiment, part of the channel region ch extends along the sidewall sw1a of the first contact hole V1.

In some embodiments, the hydrogen element in the silicon nitride layer 122 may diffuse into the hydrogen concentration gradient region h. In some embodiments, the drain region dr and the source region sr have a hydrogen concentration greater than that of the hydrogen concentration gradient region h through hydrogen plasma treatment. In some embodiments, since a portion of the drain region dr contacts the silicon nitride layer 122 at the sidewall sw1b, the hydrogen concentration of the drain region dr is greater than that of the source region sr.

In some embodiments, the material of the metal oxide layer OS includes quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin (AZTO), and indium tungsten zinc oxide (IWZO). Or an oxide composed of a ternary metal including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W).

The gate dielectric layer 130 is on the metal oxide layer OS. The gate dielectric layer 130 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the thickness t4 of the gate dielectric layer 130 is 50 nm to 200 nm. A portion of the gate dielectric layer 130 is filled in the first contact hole V1 and the opening OP.

The gate G is on the gate dielectric layer 130 . Part of the insulating pattern 120 is located between the gate G and the substrate 100 . The drain D extends between the gate G and the substrate 100 . In this embodiment, in the normal direction ND of the top surface of the substrate, part of the gate G overlaps the insulating pattern 120 , and another part of the gate G does not overlap the insulating pattern 120 . In this embodiment, part of the gate G overlaps with the hydrogen concentration gradient region h, and another part overlaps with the channel region ch. In this embodiment, part of the gate G is filled in the first contact hole V1.

The inter-dielectric layer 140 is disposed on the gate dielectric layer 130 . The interlayer dielectric layer 140 covers the gate G. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials. Part of the interlayer dielectric layer 140 is filled in the first contact hole V1 and the opening OP.

The connection electrode T and the source electrode S are disposed on the interlayer dielectric layer 140 . The connection electrode T and the source electrode S pass through the interlayer dielectric layer 140 , the gate dielectric layer 130 and the second contact hole V2 in the insulating pattern 120 and the interlayer dielectric layer 140 and the third contact hole in the gate dielectric layer 130 V3 is electrically connected to the drain D and the source region sr of the metal oxide layer OS, respectively. In this embodiment, the sidewall sw2 of the second contact hole V2 includes the interlayer dielectric layer 140 , the gate dielectric layer 130 and the silicon nitride layer 122 , and the sidewall of the third contact hole V3 includes the interlayer dielectric layer 140 and the gate dielectric layer 130 .

5A to 10A are plan views of a method of manufacturing the semiconductor device 10C of FIGS. 4A and 4B . 5B to 10B are schematic cross-sectional views along line a-a' of FIGS. 5A to 10A, respectively.

Please refer to FIGS. 5A to 6A and FIGS. 5B to 6B , a heat dissipation structure HDF and a drain D are formed on the substrate 100 . An insulating pattern 120 including a first contact hole V1 is formed on the drain electrode D. As shown in FIG. The drain D is located under the first contact hole V1 and is exposed by the first contact hole V1.

The method of forming the insulating pattern 120 including the first contact hole V1 includes: forming a silicon nitride layer 122 blanketing the drain electrode D; forming a second oxide layer 124 blanketing the silicon nitride layer 122; and then, A first patterning process is performed on the silicon nitride layer 122 and the second oxide layer 124 to form a first contact hole V1 and an opening OP, wherein the first contact hole V1 passes through the silicon nitride layer 122 and the second oxide layer 124 , and the opening OP passes through the second oxide layer 124 and does not pass through the silicon nitride layer 122 . The first contact hole V1 exposes the drain electrode D, and the opening OP exposes the silicon nitride layer 122 .

For example, the first patterning process includes: forming a patterned photoresist layer PR on the second oxide layer 124, wherein the patterned photoresist layer PR includes portions with different thicknesses; The photoresist layer PR is used as a mask to etch the silicon nitride layer 122 and the second oxide layer 124 . The thinner part of the patterned photoresist layer PR corresponds to the location of the opening OP, and the opening of the patterned photoresist layer PR corresponds to the location of the first contact hole V1. In this embodiment, the first patterning process includes, for example, a half-tone mask process.

Referring to FIGS. 7A and 7B , the patterned photoresist layer PR is removed. Next, a metal oxide layer OS' is formed on the silicon nitride layer 122 and the oxide layer 124, and the metal oxide layer OS' fills the first contact hole V1 and contacts the upper surface ts2 of the oxide layer 124, the first contact hole V1, and the first contact hole V1. The sidewalls sw1a, sw1b and the drain D of a contact hole V1.

In some embodiments, the method of forming the metal oxide layer OS' includes: first, forming a semiconductor material layer (not shown) blanketed on the silicon nitride layer 122, the oxide layer 124 and the drain electrode D; then, forming a patterned photoresist layer on the semiconductor material layer (not shown); then, using the patterned photoresist layer as a mask to etch the semiconductor material layer (not shown) to form a metal oxide layer OS'; Finally, the patterned photoresist layer is removed. In this embodiment, since the drain D at the opening OP is covered by the silicon nitride layer 122, when the semiconductor material layer (not shown) is formed, the semiconductor material layer (not shown) will not directly pass through the opening OP The drain electrode D is contacted, thereby preventing the drain electrode D under the opening OP from being damaged when the semiconductor material layer (not shown) is etched.

Referring to FIG. 8A and FIG. 8B, a gate dielectric layer 130 is formed on the metal oxide layer OS'. A gate G is formed on the gate dielectric layer 130 .

Using the gate G as a mask, a doping process P is performed on the metal oxide layer OS' to form a source region sr, a drain region dr, a hydrogen concentration gradient region h and a channel region ch in the metal oxide layer OS' . The channel region ch is connected between the source region sr and the hydrogen concentration gradient region h. The hydrogen concentration gradient region h is connected between the channel region ch and the drain region dr. The hydrogen concentration gradient region h and the channel region ch overlap the gate G. In some embodiments, the doping process P is, for example, a hydrogen plasma doping process or other suitable processes.

In some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the metal oxide layer OS'/OS. However, since the source region sr and the drain region dr are directly doped with hydrogen by the doping process P, the hydrogen concentration of the source region sr and the drain region dr is greater than that of the hydrogen concentration gradient region h. Therefore, the resistivity of the source region sr and the drain region dr is lower than that of the hydrogen concentration gradient region h, and the resistivity of the hydrogen concentration gradient region h is lower than that of the channel region ch. The hot carrier effect generated by the electric field at the edge of the gate G can be reduced by the arrangement of the hydrogen concentration gradient region h.

Referring to FIGS. 9A and 9B , an interlayer dielectric layer 140 is formed on the gate dielectric layer 130 . The interlayer dielectric layer 140 covers the gate G. In some embodiments, the interlayer dielectric layer 140 also contains hydrogen. In some embodiments, the hydrogen element in the interlayer dielectric layer 140 is diffused into the source region sr and the drain region dr of the metal oxide layer OS to further increase the hydrogen concentration of the source region sr and the drain region dr, And reduce the resistivity of the source region sr and the drain region dr. In some embodiments, the material of the gate G includes aluminum, and aluminum can be used as a hydrogen element blocking layer to prevent the hydrogen element in the interlayer dielectric layer 140 from diffusing into the channel region ch and the hydrogen concentration gradient region h.

Referring to FIGS. 10A and 10B , a second patterning process is performed on the interlayer dielectric layer 140 , the gate dielectric layer 130 and the silicon nitride material layer 122 to form through the interlayer dielectric layer 140 at the position of the opening OP , the gate dielectric layer 130 and the second contact hole V2 of the silicon nitride material layer 122, and at the same time, the source region sr of the metal oxide layer OS is formed through the interlayer dielectric layer 140 and the gate dielectric layer 130. The third contact hole V3.

4A and FIG. 4B, the connection electrode T and the source electrode S are formed on the interlayer dielectric layer 140, and the connection electrode T and the source electrode S are formed in the second contact hole V2 and the third contact hole V3. The connection electrode T and the source electrode S are respectively connected to the drain electrode D and the source region sr of the metal oxide layer OS. So far, the semiconductor device 10C is substantially completed.

11A is a top view of a display device according to an embodiment of the present invention, wherein FIG. 11A shows a substrate 100 and a heat dissipation structure DHF of the display device, and other components are omitted. FIG. 11B is a partial enlarged schematic view of FIG. 11A .

Referring to FIG. 11A , the display device includes a display area AA and a peripheral area BA. The heat dissipation structure DHF is located in the display area AA. In this embodiment, the heat dissipation structure DHF is in the shape of a mesh. Compared with the whole surface heat dissipation structure DHF, the mesh heat dissipation structure DHF has a better heat dissipation technical effect, and can improve the problem of cracking of the substrate 100 caused by the stress of the heat dissipation structure DHF.

Referring to FIG. 11B , the display device includes a plurality of semiconductor devices 10C in an array. For the description of the semiconductor devices 10C, reference may be made to the relevant paragraphs in FIGS. 4A and 4B , and details are not repeated here. In this embodiment, the drain electrodes D of the plurality of semiconductor devices 10C are electrically connected to each other through the multi-connection electrodes T. As shown in FIG. The sources S of the plurality of semiconductor devices 10C are electrically connected to each other. The gates G of the plurality of semiconductor devices 10C are electrically connected to each other. By connecting a plurality of semiconductor devices 10C in parallel, the driving current of each semiconductor device 10C can be reduced, thereby increasing the reliability of the semiconductor device 10C.

In this embodiment, the drains D of the plurality of semiconductor devices 10C are connected to the same mesh-shaped heat dissipation structure DHF. The semiconductor device 10C is electrically connected to, for example, organic light emitting diodes, micro light emitting diodes or other light emitting elements.

Claims (20)

1. A semiconductor device comprising: a substrate; a first oxide layer on the substrate; an insulating pattern on the first oxide layer and comprising: a silicon nitride layer; and a second oxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer; a metal oxide layer contacting the upper surface of the first oxide layer, the sidewall of the insulating pattern and the upper surface of the insulating pattern; a gate dielectric layer on the metal oxide layer; a gate on the gate dielectric layer, wherein a portion of the insulating pattern is located between the gate and the substrate; and A source electrode and a drain electrode are electrically connected to the metal oxide layer. 2. The semiconductor device of claim 1, wherein the oxygen concentration of the first oxide layer is greater than the oxygen concentration of the second oxide layer. 3. The semiconductor device of claim 1, wherein the silicon nitride layer contains hydrogen. 4. The semiconductor device of claim 1, wherein the drain electrode overlaps the insulating pattern. 5. The semiconductor device of claim 1, wherein the metal oxide layer comprises a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region The distance between the region and the substrate is smaller than the distance between the drain region and the substrate. 6. The semiconductor device of claim 5, wherein a hydrogen concentration in the drain region is greater than a hydrogen concentration in the source region. 7. A method of manufacturing a semiconductor device, comprising: forming a first oxide layer on a substrate; An insulating pattern is formed on the first oxide layer, and the insulating pattern includes: a silicon nitride layer; and a second oxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer; forming a metal oxide layer on the upper surface of the first oxide layer, the sidewall of the insulating pattern and the upper surface of the insulating pattern; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer, wherein a portion of the insulating pattern is located between the gate and the substrate; and A source electrode and a drain electrode electrically connected to the metal oxide layer are formed. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising: Using the gate as a mask, a doping process is performed on the metal oxide layer to form a source region, a drain region and a region between the source region and the drain region in the metal oxide layer a channel region, wherein the hydrogen concentration of the drain region is greater than the hydrogen concentration of the source region. 9. The method of claim 7, further comprising performing an annealing process to diffuse oxygen in the first oxide layer into the metal oxide layer. 10. A semiconductor device comprising: a substrate; a drain located on the substrate; an insulating pattern located above the drain, and the drain is located below a first contact hole of the insulating pattern; a metal oxide layer on the insulating pattern and filling the first contact hole, wherein the metal oxide layer contacts the upper surface of the insulating pattern, the sidewall of the first contact hole of the insulating pattern and the drain; a gate dielectric layer on the metal oxide layer; a gate on the gate dielectric layer; and A source electrode is electrically connected to the metal oxide layer. 11. The semiconductor device of claim 10, wherein a portion of the insulating pattern is located between the gate electrode and the substrate. 12. The semiconductor device of claim 10, wherein the insulating pattern comprises: an oxide layer; and a silicon nitride layer between the oxide layer and the substrate, wherein the sidewall of the first contact hole includes the silicon nitride layer and the oxide layer, and the metal oxide layer contacts the silicon nitride layer and the oxide layer. 13. The semiconductor device of claim 12, wherein the metal oxide layer comprises: a source region electrically connected to the source; a drain region electrically connected to the drain; a channel region overlapping the gate and connected to the source region; and A hydrogen concentration gradient region overlaps the gate electrode and is connected between the channel region and the drain region, wherein the hydrogen concentration gradient region contacts the silicon nitride layer, and the channel region contacts the oxide layer. 14. The semiconductor device of claim 13, wherein the hydrogen concentration of the hydrogen concentration gradient region is smaller than the hydrogen concentration of the drain region. 15. The semiconductor device of claim 12, wherein the drain electrode extends between the gate electrode and the substrate. 16. The semiconductor device of claim 12, further comprising: a connection electrode, wherein the drain electrode is located under a second contact hole of the insulating pattern, and the connection electrode fills the second contact hole to electrically connect the drain electrode. 17. The semiconductor device of claim 12, further comprising: A heat dissipation structure is located between the drain electrode and the substrate, and is thermally connected to the drain electrode. 18. A method of manufacturing a semiconductor device, comprising: forming a drain on a substrate; forming a silicon nitride layer blanket covering the drain; forming an oxide layer blanketed on the silicon nitride layer; performing a first patterning process on the silicon nitride layer and the oxide layer to form a first contact hole and an opening, wherein the first contact hole passes through the oxide layer and the silicon nitride layer, and the opening passes through the oxide layer and not through the silicon nitride layer; A metal oxide layer is formed on the silicon nitride layer and the oxide layer, and the metal oxide layer fills the first contact hole and contacts the upper surface of the oxide layer and the first contact hole. sidewalls and the drain; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer; and A source electrode electrically connected to the metal oxide layer is formed. 19. The method of manufacturing a semiconductor device according to claim 18, further comprising: performing a second patterning process on the silicon nitride material layer to form a second contact hole through the silicon nitride material layer at the position of the opening; and A connection electrode is formed in the second contact hole to connect the drain electrode. 20. The method of manufacturing a semiconductor device according to claim 18, further comprising: Using the gate as a mask, a doping process is performed on the metal oxide layer to form a source region, a drain region, a hydrogen concentration gradient region and a channel region in the metal oxide layer, wherein the A channel region is connected between the source region and the hydrogen concentration gradient region, and the hydrogen concentration gradient region is connected between the channel region and the drain region, wherein the hydrogen concentration gradient region and the channel region overlap the gate electrode, and the hydrogen concentration of the hydrogen concentration gradient region is smaller than the hydrogen concentration of the drain region.

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