CN115050839A

CN115050839A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN115050839A
Application number: CN202210863090.1A
Authority: CN
Inventors: 吴尚霖; 陈衍豪
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-12-09
Filing date: 2022-07-21
Publication date: 2022-09-13

Abstract

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first oxide layer, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The first oxide layer is located on the substrate. The insulation pattern is positioned on the first oxide layer and comprises a silicon nitride layer and a second oxide layer. The silicon nitride layer is located between the first oxide layer and the second oxide layer. The metal oxide layer contacts the upper surface of the first oxide layer, the sidewalls of the insulating pattern, and the upper surface of the insulating pattern. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. Part of the insulation pattern is located between the gate and the substrate. The source electrode and the drain electrode are electrically connected with the metal oxide layer.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing the same.

Background

At present, a common thin film transistor generally uses an amorphous silicon semiconductor as a channel, wherein the amorphous silicon semiconductor is widely applied to various thin film transistors due to simple process and low cost.

With the progress of display technology, the resolution of display panels is increasing year by year. In order to shrink the thin film transistor in the pixel circuit, many manufacturers are working on developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, Indium Gallium Zinc Oxide (IGZO) has advantages of both small area and high electron mobility, and thus is considered as an important novel semiconductor material.

Disclosure of Invention

The invention provides a semiconductor device and a manufacturing method thereof, which can improve the hot carrier effect at a drain electrode, thereby improving the reliability.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first oxide layer, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate electrode, a source electrode, and a drain electrode. The first oxide layer is located on the substrate. The insulation pattern is positioned on the first oxide layer and comprises a silicon nitride layer and a second oxide layer. The silicon nitride layer is located between the first oxide layer and the second oxide layer. The metal oxide layer contacts the upper surface of the first oxide layer, the sidewalls of the insulating pattern, and the upper surface of the insulating pattern. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. Part of the insulation pattern is located between the gate and the substrate. The source electrode and the drain electrode are electrically connected with the metal oxide layer.

At least one embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a first oxide layer on the substrate; forming an insulation pattern on the first oxide layer, wherein the insulation pattern comprises a silicon nitride layer and a second oxide layer, and the silicon nitride layer is positioned between the first oxide layer and the second oxide layer; forming a metal oxide layer on an upper surface of the first oxide layer, sidewalls of the insulation patterns, and an upper surface of the insulation patterns; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer, wherein a part of the insulation pattern is located between the gate and the substrate; and forming a source electrode and a drain electrode which are electrically connected with the metal oxide layer.

At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a drain electrode, an insulating pattern, a metal oxide layer, a gate dielectric layer, a gate electrode, and a source electrode. The drain electrode is positioned on the substrate. The insulation pattern is positioned on the drain electrode, and the drain electrode is positioned below the first contact hole of the insulation pattern. The metal oxide layer is located on the insulation pattern and filled in the first contact hole. The metal oxide layer contacts the upper surface of the insulation pattern, the side wall of the first contact hole of the insulation pattern and the drain electrode. The gate dielectric layer is located on the metal oxide layer. The gate is located on the gate dielectric layer. The source electrode is electrically connected with the metal oxide layer.

At least one embodiment of the present invention provides a method of manufacturing a semiconductor device, including forming a drain on a substrate; forming a silicon nitride layer blanket on the drain electrode; forming an oxide layer blanket on the silicon nitride layer; performing a first patterning process on the silicon nitride layer and the oxide layer to form a first contact hole and an opening, wherein the first contact hole penetrates through the oxide layer and the silicon nitride layer, and the opening penetrates through the oxide layer and does not penetrate through the silicon nitride layer; forming a metal oxide layer on the silicon nitride layer and the oxide layer, wherein the metal oxide layer is filled in the first contact hole and contacts the upper surface of the oxide layer, the side wall of the first contact hole and the drain electrode; forming a gate dielectric layer on the metal oxide layer; forming a gate on the gate dielectric layer; and forming a source electrode electrically connected with the metal oxide layer.

Drawings

Fig. 1A is a top view of a semiconductor device according to an embodiment of the invention.

FIG. 1B is a schematic cross-sectional view of line a-a' of FIG. 1A.

Fig. 2A to 2E are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention.

Fig. 3A is a top view of a semiconductor device according to an embodiment of the invention.

Fig. 3B is a schematic cross-sectional view of line a-a' of fig. 3A.

Fig. 4A is a top view of a semiconductor device according to an embodiment of the invention.

Fig. 4B is a schematic cross-sectional view of line a-a' of fig. 4A.

Fig. 5A to 10A are top views illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention.

Fig. 5B to 10B are schematic cross-sectional views of the line a-a' of fig. 5A to 10A, respectively.

Fig. 11A is a top view of a display device according to an embodiment of the invention.

Fig. 11B is a partially enlarged schematic view of fig. 11A.

Description of reference numerals:

10A,10B, 10C: semiconductor device with a plurality of semiconductor chips

100: substrate

110: first oxide layer

120: insulating pattern

122: silicon nitride layer

124 second oxide layer

130: gate dielectric layer

140: interlayer dielectric layer

AA: display area

a-a': thread

BA: peripheral zone

ch: channel region

D: drain electrode

dr: drain region

G: grid electrode

HD: height difference

HDF: heat radiation structure

h: hydrogen concentration gradient region

ND: normal direction

OP: opening of the container

OS, OS': metal oxide layer

P: doping process

PR: patterned photoresist layer

S: source electrode

sr: source region

sw, sw1a, sw1b, sw 2: side wall

T: connecting electrode

t1, t2, t3, t 4: thickness of

ts1, ts 2: upper surface of

V1: first contact hole

V2: second contact hole

V3: third contact hole

Detailed Description

Fig. 1A is a top view of a semiconductor device according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view of line a-a' of FIG. 1A.

Referring to fig. 1A and 1B, a semiconductor device 10A includes a substrate 100, a first oxide layer 110, an insulating pattern 120, a metal oxide layer OS, a gate dielectric layer 130, a gate G, a source S, and a drain D, wherein the insulating pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124. In the present embodiment, the semiconductor device 10A further includes an interlayer dielectric layer 140. For convenience of explanation, fig. 1A shows the metal oxide layer OS, the silicon nitride layer 122, the gate G, the source S, and the drain D, and other components are omitted.

The substrate 100 may be made of glass, quartz, organic polymer, opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable materials. If a conductive material or metal is used, an insulating layer (not shown) is formed on the substrate 100 to prevent short circuit. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), Polyester (PES), polymethyl methacrylate (PMMA), Polycarbonate (PC), Polyimide (PI), or Metal Foil (Metal Foil), or other flexible materials.

The first oxide layer 110 is located over the substrate 100. In some embodiments, first oxide layer 110 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, or other suitable material. In some embodiments, the thickness t1 of first oxide layer 110 is 500 to 3000 angstroms.

The insulation pattern 120 is on the first oxide layer 110, and includes a silicon nitride layer 122 and a second oxide layer 124. In some embodiments, the silicon nitride layer 122 includes hydrogen elements therein. In some embodiments, the thickness t2 of silicon nitride layer 122 is 100 to 1500 angstroms. The second oxide layer 124 is located on the silicon nitride layer 122, and the silicon nitride layer 122 is located between the first oxide layer 110 and the second oxide layer 124. The second oxide layer 124 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, or other suitable material. In some embodiments, the first oxide layer 110 and the second oxide layer 124 are both silicon oxide or silicon oxynitride, and the oxygen concentration of the first oxide layer 110 is greater than the oxygen concentration of the second oxide layer 124. For example, the first oxide layer 110 includes SiOx, the second oxide layer 124 includes SiOy, and x is greater than y. In some embodiments, thickness t3 of second oxide layer 124 is 100 to 1500 angstroms.

The metal oxide layer OS is on the first oxide layer 110 and the insulation pattern 120. The metal oxide layer OS contacts the upper surface ts1 of the first oxide layer 110, the sidewall sw of the insulation pattern 120, and the upper surface ts2 of the insulation pattern 120. In some embodiments, the sidewall sw of the insulation pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124, and the metal oxide layer OS contacts the silicon nitride layer 122 and the second oxide layer 124 at the position of the sidewall sw.

The metal oxide layer OS includes a source region sr, a drain region dr, and a channel region ch between the source region sr and the drain region dr. The source region sr and the drain region dr are doped to have a lower resistivity than the channel region ch. In the present embodiment, the source region sr contacts the upper surface ts1 of the first oxide layer 110, the channel region ch contacts the upper surface ts1 of the first oxide layer 110 and the sidewall sw of the insulation pattern 120, and the drain region dr contacts the upper surface ts2 of the insulation pattern 120. In some embodiments, the distance between the source region sr and the substrate 100 is smaller than the distance between the drain region dr and the substrate 100. In some embodiments, the bottom surface of the drain region dr and the bottom surface of the source region sr have a height difference HD therebetween, for example, approximately equal to the thickness of the insulating pattern 120. In the present embodiment, the portion of the channel region ch connecting to the drain region dr extends along the vertical direction (the normal direction ND), so that the hot carrier effect of the metal oxide layer OS near the drain D due to the lateral electric field can be reduced.

In some embodiments, since the drain region dr is located above the silicon nitride layer 122 containing hydrogen element, the hydrogen concentration of the drain region dr is greater than that of the source region sr. Therefore, the hydrogen resistivity of the drain region dr is lower than that of the source region sr.

In some embodiments, the material of the metal oxide layer OS includes a quaternary metal compound such as Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Aluminum Zinc Tin Oxide (AZTO), and indium tungsten zinc oxide (IWZO), or an oxide made of a ternary metal including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W).

The gate dielectric layer 130 is on the metal oxide layer OS. Gate dielectric layer 130 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable material. In some embodiments, thickness t4 of gate dielectric layer 130 is 500 to 3000 angstroms.

The gate G is on the gate dielectric layer 130. A portion of the insulation pattern 120 is located between the gate electrode G and the substrate 100. In the present embodiment, in the normal direction ND of the top surface of the substrate 100, a portion of the gate G overlaps the insulating pattern 120, and another portion of the gate G does not overlap the insulating pattern 120. In the present embodiment, the drain region dr extends between the gate G and the substrate 100. Part of the gate G overlaps the drain region dr, and the other part overlaps the channel region ch.

In some embodiments, the material of the gate G may include a metal, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or an alloy of any combination of the above metals, or a stack of the above metals and/or alloys, but the invention is not limited thereto. Other conductive materials may also be used for the gate G, such as: metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

The interlayer dielectric 140 is disposed on the gate dielectric 130. The interlayer dielectric layer 140 covers the gate G. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials.

The drain D and the source S are disposed on the interlayer dielectric layer 140. In the normal direction ND, the drain electrode D overlaps the insulating pattern 120, and the source electrode S does not overlap the insulating pattern 120. The drain D and the source S are electrically connected to the drain region dr and the source region sr of the metal oxide layer OS through the first contact hole V1 and the second contact hole V2 in the interlayer dielectric layer 140, respectively. In some embodiments, the material of the drain electrode D and the source electrode S may include a metal, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or an alloy of any combination of the above metals, or a stack of the above metals and/or alloys, but the invention is not limited thereto. Other conductive materials can be used for the drain D and the source S, such as: metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

Fig. 2A to 2E are schematic cross-sectional views illustrating a method of manufacturing the semiconductor device 10A of fig. 1A and 1B.

Referring to fig. 2A, a first oxide layer 110 is formed on the substrate 100. Next, an insulating pattern 120 is formed on the first oxide layer 110. In some embodiments, the method of forming the insulation pattern 120 includes forming a silicon nitride material layer that is blanket on the first oxide layer 110. Then, an oxide material layer is formed to cover the silicon nitride material layer. The layer of oxide material and the layer of silicon nitride material are then patterned by a photolithographic etching process to form a layer of silicon nitride 122 and a second layer of oxide 124. In some embodiments, the method of forming the oxide material layer and the silicon nitride material layer comprises chemical vapor deposition or plasma enhanced chemical vapor deposition, and the gas used to form the silicon nitride material layer comprises Silane (SiH) ₄ ) Nitrogen (N) ₂ ) Ammonia (NH) ₃ ) And other suitable gases, and thus, the silicon nitride layer 122 includes elemental hydrogen.

Referring to fig. 2B, a metal oxide OS' is formed on the top surface ts1 of the first oxide layer 110, the sidewall sw of the insulating pattern 120, and the top surface ts2 of the insulating pattern 120. In the present embodiment, there is a step between the upper surface ts1 of the first oxide layer 110 and the upper surface ts2 of the insulation pattern 120, and the metal oxide OS' covers a step between the upper surface ts1 of the first oxide layer 110 and the upper surface ts2 of the insulation pattern 120.

In some embodiments, the first oxide layer 110 has a function of storing oxygen. When the metal oxide OS' is deposited, a part of the oxygen element is diffused into the first oxide layer 110. At this time, the first oxide layer 110 has a relatively high oxygen concentration. However, since the second oxide layer 124 of the insulation pattern 120 has a poor ability to store oxygen elements, the second oxide layer 124 has a relatively low oxygen concentration.

A gate dielectric layer 130 is formed on the metal oxide layer OS'. In some embodiments, the metal oxide layer OS 'is heated during the deposition of the gate dielectric layer 130, so that oxygen in the metal oxide layer OS' diffuses out, for example, into the first oxide layer 110 or the gate dielectric layer 130, and oxygen vacancies are generated in the metal oxide layer OS 'to lower the resistivity of the metal oxide layer OS'. Since the second oxide layer 124 has a poor ability to store oxygen element, oxygen in the metal oxide layer OS' located above the second oxide layer 124 is less likely to diffuse down into the second oxide layer 124. In addition, in some embodiments, hydrogen of the silicon nitride layer 122 diffuses upward into the metal oxide layer OS 'over the second oxide layer 124, further reducing the resistivity of the metal oxide layer OS' over the second oxide layer 124.

Referring to fig. 2C, in some embodiments, after depositing the gate dielectric layer 130, an annealing process is performed to diffuse oxygen elements stored in the first oxide layer 110 and the gate dielectric layer 130 into the metal oxide layer OS'. The oxygen element bonds with oxygen vacancies of the metal oxide layer OS 'to increase the resistivity of the metal oxide layer OS', for example, from about 1E +4ohm/sq to 1E +8ohm/sq or more.

In some embodiments, since the oxygen element stored in the first oxide layer 110 is more than the oxygen element stored in the second oxide layer 124, more oxygen element will diffuse into a portion of the metal oxide layer OS ' on the first oxide layer 110, so that the oxygen concentration of the portion of the metal oxide layer OS ' on the first oxide layer 110 is increased more, and the oxygen concentration of another portion of the metal oxide layer OS ' on the second oxide layer 124 is relatively increased less. In other words, after the forming annealing process, the resistivity of a portion of the metal oxide layer OS 'on the first oxide layer 110 may be higher than the resistivity of another portion of the metal oxide layer OS' on the second oxide layer 124.

Referring to fig. 2D, a gate G is formed on the gate dielectric layer 130. Then, a doping process P is performed on the metal oxide layer OS 'by using the gate G as a mask, so as to form a source region sr, a drain region dr, and a channel region ch between the source region sr and the drain region dr in the metal oxide layer OS'. In some embodiments, the doping process P is, for example, a hydrogen plasma doping process or other suitable process.

In some embodiments, the hydrogen element in the silicon nitride layer 122 can maintain the hydrogen concentration in the drain region dr of the metal oxide layer OS, so that the hydrogen in the drain region dr is not easy to escape in the subsequent process. In addition, in some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the drain region dr, so that the hydrogen concentration of the drain region dr is greater than that of the source region sr. In addition, since a portion of the silicon nitride layer 122 is located between the gate G and the substrate 100, a portion of the metal oxide layer OS '/OS overlapping the gate G is also doped with hydrogen, so that the portion of the metal oxide layer OS'/OS overlapping the gate G is converted into the drain region dr, thereby further reducing the hot carrier effect generated by the electric field at the edge of the gate G. In some embodiments, the drain region dr overlapped with the gate G and the drain region dr not overlapped with the gate G have different hydrogen concentrations, wherein the hydrogen concentration of the drain region dr not overlapped with the gate G is greater than that of the drain region dr overlapped with the drain region dr of the gate G.

Referring to fig. 2E, an interlayer dielectric 140 is formed on the gate dielectric 130. The interlayer dielectric 140 covers the gate G.

Then, one or more etching processes are performed to form a first contact hole V1 and a second contact hole V2 through the interlayer dielectric layer 140 and the gate dielectric layer 130. The first contact hole V1 and the second contact hole V2 overlap and expose the drain region dr and the source region sr of the metal oxide layer OS.

Finally, referring back to fig. 1, the drain electrode D and the source electrode S are formed on the interlayer dielectric layer 140, and the drain electrode D and the source electrode S are formed in the first contact hole V1 and the second contact hole V2. The drain D and the source S are connected to the drain region dr and the source region sr of the metal oxide layer OS, respectively. Thus, the semiconductor device 10A is substantially completed.

Based on the above, the silicon nitride layer 122 in the insulating pattern 120 may improve the problem that the hydrogen element in the metal oxide layer OS escapes during the heating process, and may even provide an additional hydrogen element to the metal oxide layer OS. Therefore, the silicon nitride layer 122 in the insulating pattern 120 can prevent the drain region dr of the metal oxide layer OS from increasing in resistivity due to the dissipation of hydrogen, thereby improving the hot carrier effect near the drain D.

Fig. 3A is a top view of a semiconductor device according to an embodiment of the invention. Fig. 3B is a schematic cross-sectional view of line a-a' of fig. 3A. It should be noted that the embodiment of fig. 3A and 3B uses the element numbers and part of the contents of the embodiment of fig. 1A and 1B, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

The main difference between the semiconductor device 10B of fig. 3A and 3B and the semiconductor device 10A of fig. 1A and 1B is that: the silicon nitride layer 122 of the insulating pattern 120 of the semiconductor device 10B does not extend below the gate G.

Referring to fig. 3A and 3B, in the present embodiment, the silicon nitride layer 122 does not overlap the gate G in the normal direction ND. The drain region dr of the metal oxide layer OS does not extend below the gate G.

In the present embodiment, the sidewall sw of the insulating pattern 120 includes only the second oxide layer 124, and the metal oxide layer OS does not directly contact the silicon nitride layer 122.

In addition, in the present embodiment, the silicon nitride layer 122 of the insulating pattern 120 and the second oxide layer 124 include different shapes. The silicon nitride layer 122 and the second oxide layer 124 are defined by different photolithography processes.

Fig. 4A is a top view of a semiconductor device according to an embodiment of the invention. Fig. 4B is a schematic cross-sectional view of line a-a' of fig. 4A.

Referring to fig. 4A and 4B, the semiconductor device 10C includes a substrate 100, a drain electrode D, an insulation pattern 120, a metal oxide layer OS, a gate dielectric layer 130, a gate electrode G and a source electrode S, wherein the insulation pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124. In the present embodiment, the semiconductor device 10C further includes a heat dissipation structure HDF, an interlayer dielectric layer 140, and a connection electrode T. For convenience of explanation, fig. 4A shows the heat dissipation structure HDF, the drain electrode D, the metal oxide layer OS, the gate electrode G, the source electrode S, and the connection electrode T, and other components are omitted.

The heat sink structure HDF is located on the substrate 100. In the embodiment, the heat dissipation structure HDF is directly formed on the substrate 100, but the invention is not limited thereto. In other embodiments, other buffer layers, such as silicon oxide, silicon nitride, silicon oxynitride or other insulating materials, are sandwiched between the heat sink structure HDF and the substrate 100. In some embodiments, the heat sink structure HDF is a thermally conductive and insulating material, such as aluminum nitride, aluminum oxide, or other materials. In some embodiments, the heat dissipation structure HDF has a thermal conductivity greater than 2W m ^-1 ℃ ^-1 . The thickness of the heat dissipation structure HDF can be adjusted according to actual requirements.

The drain D is located on the substrate 100. In the present embodiment, the drain D is directly formed on the heat dissipation structure HDF. The heat dissipation structure HDF is located between the drain D and the substrate 100 and is thermally connected to the drain D. The area of the vertical projection of the drain D on the substrate 100 is smaller than the area of the vertical projection of the heat dissipation structure HDF on the substrate 100.

The insulating pattern 120 is positioned over the drain electrode D. The insulation pattern 120 includes a silicon nitride layer 122 and a second oxide layer 124. In some embodiments, the silicon nitride layer 122 includes hydrogen elements therein. In some embodiments, the thickness t2 of the silicon nitride layer 122 is 30 nanometers to 300 nanometers. The second oxide layer 124 is located on the silicon nitride layer 122, and the silicon nitride layer 122 is located between the second oxide layer 124 and the substrate 100. The second oxide layer 124 includes silicon oxide, silicon oxynitride, aluminum oxide, or other insulating material. In some embodiments, the thickness t3 of the second oxide layer 124 is 50 nanometers to 200 nanometers.

The insulating pattern 120 has a first contact hole V1 and a second contact hole V2. The sidewalls sw1a and sw1b of the first contact hole V1 include a silicon nitride layer 122 and a second oxide layer 124. The sidewall sw2 of the second contact hole V2 includes the second oxide layer 124. The drain electrode D is positioned under the first contact hole V1 and the second contact hole V2 of the insulating pattern 120. In the present embodiment, the second oxide layer 124 of the insulating pattern 120 has an opening OP, and the second contact hole V2 passes through the silicon nitride layer 122 at the bottom of the opening OP. In some embodiments, the width of the opening OP is greater than the width of the second contact hole V2.

The metal oxide layer OS is on the insulation pattern 120 and fills the first contact hole V1. The metal oxide layer OS contacts the upper surface ts2 of the insulation pattern 120, the sidewalls sw1a and sw1b of the first contact hole V1 of the insulation pattern 120, and the drain electrode D. In the present embodiment, the metal oxide layer OS contacts the silicon nitride layer 122 and the oxide layer 124.

The metal oxide layer OS includes a source region sr, a channel region ch, a hydrogen concentration gradient region h, and a drain region dr which are connected in this order. The channel region ch is connected between the hydrogen concentration gradient region h and the source region sr. The hydrogen concentration gradient region h is connected between the channel region ch and the drain region dr. The source region sr, the hydrogen concentration gradient region h, and the drain region dr are doped to have a lower resistivity than the channel region ch. In the present embodiment, the resistivity of the drain D is lower than the resistivity of the source region sr and the drain region dr, the resistivity of the source region sr and the drain region dr is lower than the resistivity of the hydrogen concentration gradient region h, and the resistivity of the hydrogen concentration gradient region h is lower than the resistivity of the channel region ch.

The source region sr contacts the upper surface ts2 of the second oxide layer 124. The channel region ch contacts the upper surface ts2 and the second oxide layer 124 at the sidewall sw1 a. The hydrogen concentration gradient region h contacts the silicon nitride layer 122 at the sidewall sw1a and the upper surface of the drain D. The drain region dr is electrically connected to the drain D and contacts the upper surface of the drain D, the silicon nitride layer 122 at the sidewall sw1b, and the second oxide layer 124 at the sidewall sw1 b. In the present embodiment, the bottom surface of the drain region dr and the bottom surface of the source region sr have a height difference HD, which is, for example, approximately equal to the depth of the first contact hole V1. In the present embodiment, a part of the channel region ch extends along the sidewall sw1a of the first contact hole V1.

In some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the hydrogen concentration gradient region h. In some embodiments, the drain region dr and the source region sr have a hydrogen concentration greater than the hydrogen concentration gradient region h through the hydrogen plasma treatment. In some embodiments, the hydrogen concentration of the drain region dr is greater than the hydrogen concentration of the source region sr because part of the drain region dr contacts the silicon nitride layer 122 at the sidewall sw1 b.

The gate dielectric layer 130 is on the metal oxide layer OS. Gate dielectric layer 130 includes, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable material. In some embodiments, the thickness t4 of gate dielectric layer 130 is 50 nanometers to 200 nanometers. A portion of the gate dielectric layer 130 fills the first contact hole V1 and the opening OP.

The gate G is on the gate dielectric layer 130. A portion of the insulation pattern 120 is located between the gate electrode G and the substrate 100. The drain D extends between the gate G and the substrate 100. In the present embodiment, in the normal direction ND of the top surface of the substrate, a portion of the gate G overlaps the insulating pattern 120, and another portion of the gate G does not overlap the insulating pattern 120. In the present embodiment, a portion of the gate G overlaps the hydrogen concentration gradient region h, and another portion overlaps the channel region ch. In the present embodiment, a portion of the gate electrode G fills the first contact hole V1.

The inter-layer dielectric 140 is disposed on the gate dielectric 130. The interlayer dielectric layer 140 covers the gate G. In some embodiments, the material of the interlayer dielectric layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials. A portion of the interlayer dielectric layer 140 fills the first contact hole V1 and the opening OP.

The connecting electrode T and the source S are disposed on the interlayer dielectric layer 140. The connection electrode T and the source electrode S are electrically connected to the drain electrode D and the source region sr of the metal oxide layer OS through the interlayer dielectric layer 140, the gate dielectric layer 130, and the second contact hole V2 in the insulating pattern 120 and the third contact hole V3 in the interlayer dielectric layer 140 and the gate dielectric layer 130, respectively. In the present embodiment, the sidewall sw2 of the second contact hole V2 includes the interlayer dielectric layer 140, the gate dielectric layer 130 and the silicon nitride layer 122, and the sidewall of the third contact hole V3 includes the interlayer dielectric layer 140 and the gate dielectric layer 130.

Fig. 5A to 10A are plan views illustrating a method of manufacturing the semiconductor device 10C of fig. 4A and 4B. Fig. 5B to 10B are schematic cross-sectional views of the line a-a' of fig. 5A to 10A, respectively.

Referring to fig. 5A to 6A and 5B to 6B, a heat sink structure HDF and a drain D are formed on the substrate 100. An insulating pattern 120 including a first contact hole V1 is formed on the drain electrode D. The drain electrode D is positioned under the first contact hole V1 and exposed by the first contact hole V1.

The method of forming the insulating pattern 120 including the first contact hole V1 includes: forming a silicon nitride layer 122 that is blanket on the drain D; forming a second oxide layer 124 blanket over the silicon nitride layer 122; next, a first patterning process is performed on the silicon nitride layer 122 and the second oxide layer 124 to form a first contact hole V1 and an opening OP, wherein the first contact hole V1 penetrates through the silicon nitride layer 122 and the second oxide layer 124, and the opening OP penetrates through the second oxide layer 124 and does not penetrate through the silicon nitride layer 122. The first contact hole V1 exposes the drain D, and the opening OP exposes the silicon nitride layer 122.

For example, the first patterning process includes: forming a patterned photoresist layer PR on the second oxide layer 124, wherein the patterned photoresist layer PR includes portions having different thicknesses; next, the silicon nitride layer 122 and the second oxide layer 124 are etched using the patterned photoresist layer PR as a mask. The thinner portion of the patterned photoresist layer PR corresponds to the position of the opening OP, and the opening of the patterned photoresist layer PR corresponds to the position of the first contact hole V1. In the present embodiment, the first patterning process includes, for example, a Half-tone Mask (Half-tone Mask) process.

Referring to fig. 7A and 7B, the patterned photoresist layer PR is removed. Next, a metal oxide layer OS 'is formed on the silicon nitride layer 122 and the oxide layer 124, and the metal oxide layer OS' fills the first contact hole V1 and contacts the upper surface ts2 of the oxide layer 124, the sidewalls sw1a, sw1b of the first contact hole V1, and the drain D.

In some embodiments, a method of forming a metal oxide layer OS' includes: first, a semiconductor material layer (not shown) is formed to cover the silicon nitride layer 122, the oxide layer 124 and the drain D; then, forming a patterned photoresist layer on the semiconductor material layer (not shown); then, the semiconductor material layer (not shown) is etched using the patterned photoresist layer as a mask to form a metal oxide layer OS'; finally, the patterned photoresist layer is removed. In the present embodiment, since the drain D at the opening OP is covered by the silicon nitride layer 122, when forming the semiconductor material layer (not shown), the semiconductor material layer (not shown) does not directly contact the drain D through the opening OP, thereby preventing the drain D under the opening OP from being damaged when etching the semiconductor material layer (not shown).

Referring to fig. 8A and 8B, a gate dielectric layer 130 is formed on the metal oxide layer OS'. A gate G is formed on the gate dielectric layer 130.

With the gate G as a mask, a doping process P is performed on the metal oxide layer OS 'to form a source region sr, a drain region dr, a hydrogen concentration gradient region h, and a channel region ch in the metal oxide layer OS'. The channel region ch is connected between the source region sr and the hydrogen concentration gradient region h. The hydrogen concentration gradient region h is connected between the channel region ch and the drain region dr. The hydrogen concentration gradient region h and the channel region ch overlap the gate G. In some embodiments, the doping process P is, for example, a hydrogen plasma doping process or other suitable process.

In some embodiments, the hydrogen element in the silicon nitride layer 122 diffuses into the metal oxide layer OS'/OS. However, since the source region sr and the drain region dr are directly doped with hydrogen in the doping process P, the hydrogen concentration of the source region sr and the drain region dr is greater than that of the hydrogen concentration gradient region h. Therefore, the resistivity of the source region sr and the drain region dr is lower than that of the hydrogen concentration gradation region h, and the resistivity of the hydrogen concentration gradation region h is lower than that of the channel region ch. The hot carrier effect generated by the electric field at the edge of the gate G can be reduced by the arrangement of the hydrogen concentration gradient region h.

Referring to fig. 9A and 9B, an interlayer dielectric 140 is formed on the gate dielectric 130. The interlayer dielectric 140 covers the gate G. In some embodiments, the interlayer dielectric layer 140 also contains hydrogen. In some embodiments, the hydrogen element in the interlayer dielectric layer 140 diffuses into the source region sr and the drain region dr of the metal oxide layer OS, so as to further increase the hydrogen concentration of the source region sr and the drain region dr and reduce the resistivity of the source region sr and the drain region dr. In some embodiments, the material of the gate G includes aluminum, and the aluminum may serve as a hydrogen blocking layer to prevent the hydrogen in the interlayer dielectric layer 140 from diffusing into the channel region ch and the hydrogen concentration gradient region h.

Referring to fig. 10A and 10B, a second patterning process is performed on the interlayer dielectric layer 140, the gate dielectric layer 130 and the silicon nitride material layer 122 to form a second contact hole V2 passing through the interlayer dielectric layer 140, the gate dielectric layer 130 and the silicon nitride material layer 122 at the position of the opening OP, and simultaneously form a third contact hole V3 passing through the interlayer dielectric layer 140 and the gate dielectric layer 130 on the source region sr of the metal oxide layer OS.

Finally, referring back to fig. 4A and 4B, the connecting electrode T and the source S are formed on the interlayer dielectric layer 140, and the connecting electrode T and the source S are formed in the second contact hole V2 and the third contact hole V3. The connection electrode T and the source S are connected to the drain D and the source region sr of the metal oxide layer OS, respectively. Thus, the semiconductor device 10C is substantially completed.

Fig. 11A is a top view of a display device according to an embodiment of the invention, in which fig. 11A illustrates a substrate 100 and a heat dissipation structure DHF of the display device, and other components are omitted. Fig. 11B is a partially enlarged schematic view of fig. 11A.

Referring to fig. 11A, the display device includes a display area AA and a peripheral area BA. The heat dissipation structure DHF is located in the display area AA. In the present embodiment, the heat dissipation structure DHF is a mesh. Compared with the overall heat dissipation structure DHF, the mesh-shaped heat dissipation structure DHF has a better heat dissipation effect, and can improve the problem that the stress of the heat dissipation structure DHF causes the substrate 100 to crack.

Referring to fig. 11B, the display device includes a plurality of semiconductor devices 10C in an array, and the description of the semiconductor devices 10C may refer to the related paragraphs of fig. 4A and 4B, which are not repeated herein. In the present embodiment, the drains D of the plurality of semiconductor devices 10C are electrically connected to each other through the multi-connection electrode T. The sources S of the plurality of semiconductor devices 10C are electrically connected to each other. The gates G of the plurality of semiconductor devices 10C are electrically connected to each other. By connecting a plurality of semiconductor devices 10C in parallel, the drive current per semiconductor device 10C can be reduced, thereby increasing the reliability of the semiconductor device 10C.

In the present embodiment, the drains D of the plurality of semiconductor devices 10C are connected to the same mesh-shaped heat dissipation structure DHF. The semiconductor device 10C is electrically connected to an organic light emitting diode, a micro light emitting diode, or other light emitting elements, for example.

Claims

1. A semiconductor device, comprising:

a substrate;

a first oxide layer on the substrate;

an insulating pattern on the first oxide layer, comprising:

a silicon nitride layer; and

a second oxide layer, wherein the silicon nitride layer is located between the first oxide layer and the second oxide layer;

a metal oxide layer contacting the upper surface of the first oxide layer, the sidewall of the insulation pattern and the upper surface of the insulation pattern;

a gate dielectric layer on the metal oxide layer;

a gate electrode on the gate dielectric layer, wherein a part of the insulation pattern is between the gate electrode and the substrate; and

a source and a drain electrically connected to the metal oxide layer.

2. The semiconductor device of claim 1, wherein an oxygen concentration of said first oxide layer is greater than an oxygen concentration of said second oxide layer.

3. The semiconductor device according to claim 1, wherein the silicon nitride layer contains a hydrogen element.

4. The semiconductor device of claim 1, wherein said drain electrode overlaps said insulating pattern.

5. The semiconductor device of claim 1, wherein the metal oxide layer comprises a source region, a drain region, and a channel region between the source region and the drain region, wherein a distance between the source region and the substrate is less than a distance between the drain region and the substrate.

6. The semiconductor device of claim 5, wherein a hydrogen concentration of said drain region is greater than a hydrogen concentration of said source region.

7. A method of manufacturing a semiconductor device, comprising:

forming a first oxide layer on a substrate;

forming an insulation pattern on the first oxide layer, wherein the insulation pattern comprises:

a silicon nitride layer; and

forming a metal oxide layer on the upper surface of the first oxide layer, the sidewall of the insulation pattern and the upper surface of the insulation pattern;

forming a gate dielectric layer on the metal oxide layer;

forming a gate on the gate dielectric layer, wherein a portion of the insulation pattern is located between the gate and the substrate; and

forming a source and a drain electrically connected to the metal oxide layer.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising:

and performing a doping process on the metal oxide layer by using the gate as a mask to form a source region, a drain region and a channel region between the source region and the drain region in the metal oxide layer, wherein the hydrogen concentration of the drain region is greater than that of the source region.

9. The method of claim 7, further comprising performing an annealing process to diffuse oxygen in the first oxide layer into the metal oxide layer.

10. A semiconductor device, comprising:

a substrate;

a drain electrode on the substrate;

an insulating pattern on the drain electrode, wherein the drain electrode is positioned below a first contact hole of the insulating pattern;

a metal oxide layer on the insulation pattern and filled in the first contact hole, wherein the metal oxide layer contacts the upper surface of the insulation pattern, the side wall of the first contact hole of the insulation pattern and the drain electrode;

a gate dielectric layer on the metal oxide layer;

a gate electrode on the gate dielectric layer; and

a source electrode electrically connected to the metal oxide layer.

11. The semiconductor device of claim 10, wherein a portion of said insulating pattern is located between said gate and said substrate.

12. The semiconductor device of claim 10, wherein the insulation pattern comprises:

an oxide layer; and

a silicon nitride layer between the oxide layer and the substrate, wherein the sidewall of the first contact hole comprises the silicon nitride layer and the oxide layer, and the metal oxide layer contacts the silicon nitride layer and the oxide layer.

13. The semiconductor device of claim 12, wherein said metal oxide layer comprises:

a source region electrically connected to the source electrode;

a drain region electrically connected to the drain electrode;

a channel region overlapping the gate and connected to the source region; and

and a hydrogen concentration gradient region overlapping the gate and connected between the channel region and the drain region, wherein the hydrogen concentration gradient region contacts the silicon nitride layer, and the channel region contacts the oxide layer.

14. The semiconductor device according to claim 13, wherein a hydrogen concentration of the hydrogen concentration gradient region is smaller than a hydrogen concentration of the drain region.

15. The semiconductor device of claim 12, wherein said drain extends between said gate and said substrate.

16. The semiconductor device according to claim 12, further comprising:

and a connection electrode, wherein the drain electrode is positioned below a second contact hole of the insulation pattern, and the connection electrode fills the second contact hole to electrically connect the drain electrode.

17. The semiconductor device according to claim 12, further comprising:

and the heat dissipation structure is positioned between the drain electrode and the substrate and is thermally connected with the drain electrode.

18. A method of manufacturing a semiconductor device, comprising:

forming a drain on a substrate;

forming a silicon nitride layer covering the drain electrode;

forming an oxide layer blanket on the silicon nitride layer;

performing a first patterning process on the silicon nitride layer and the oxide layer to form a first contact hole and an opening, wherein the first contact hole penetrates through the oxide layer and the silicon nitride layer, and the opening penetrates through the oxide layer and does not penetrate through the silicon nitride layer;

forming a metal oxide layer on the silicon nitride layer and the oxide layer, wherein the metal oxide layer is filled in the first contact hole and contacts the upper surface of the oxide layer, the side wall of the first contact hole and the drain electrode;

forming a gate dielectric layer on the metal oxide layer;

forming a gate on the gate dielectric layer; and

forming a source electrode electrically connected with the metal oxide layer.

19. The method for manufacturing a semiconductor device according to claim 18, further comprising:

performing a second patterning process on the silicon nitride material layer to form a second contact hole penetrating through the silicon nitride material layer at the position of the opening; and

forming a connection electrode in the second contact hole to connect the drain electrode.

20. The method for manufacturing a semiconductor device according to claim 18, further comprising:

and performing a doping process on the metal oxide layer by taking the gate as a mask to form a source region, a drain region, a hydrogen concentration gradient region and a channel region in the metal oxide layer, wherein the channel region is connected between the source region and the hydrogen concentration gradient region, the hydrogen concentration gradient region is connected between the channel region and the drain region, the hydrogen concentration gradient region and the channel region are overlapped on the gate, and the hydrogen concentration of the hydrogen concentration gradient region is less than that of the drain region.