TWI792412B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI792412B TWI792412B TW110125631A TW110125631A TWI792412B TW I792412 B TWI792412 B TW I792412B TW 110125631 A TW110125631 A TW 110125631A TW 110125631 A TW110125631 A TW 110125631A TW I792412 B TWI792412 B TW I792412B
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- silicide
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- 238000000034 method Methods 0.000 title claims description 87
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 276
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- 229910052793 cadmium Inorganic materials 0.000 description 2
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- 239000012159 carrier gas Substances 0.000 description 2
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- 238000010926 purge Methods 0.000 description 2
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- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 2
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- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- WEAMLHXSIBDPGN-UHFFFAOYSA-N (4-hydroxy-3-methylphenyl) thiocyanate Chemical compound CC1=CC(SC#N)=CC=C1O WEAMLHXSIBDPGN-UHFFFAOYSA-N 0.000 description 1
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
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- 229910052688 Gadolinium Inorganic materials 0.000 description 1
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- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910003839 Hf—Si Inorganic materials 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- OHSVLFRHMCKCQY-UHFFFAOYSA-N lutetium atom Chemical compound [Lu] OHSVLFRHMCKCQY-UHFFFAOYSA-N 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- PMTRSEDNJGMXLN-UHFFFAOYSA-N titanium zirconium Chemical compound [Ti].[Zr] PMTRSEDNJGMXLN-UHFFFAOYSA-N 0.000 description 1
- 229910001428 transition metal ion Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- 229910021355 zirconium silicide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
本文公開了具有不同接觸結構之設置的半導體裝置及其製造方法。半導體裝置包括設置於第一及第二鰭片結構上的第一及第二閘極結構、設置於第一及第二鰭片結構上的第一及第二源極/汲極(source/drain, S/D)區、設置於第一及第二S/D區上的第一及第二接觸結構、以及設置於第一nWFM矽化物層及第一S/D區之間的界面處的偶極層。第一接觸結構包括設置於第一S/D區上的第一nWFM矽化物層及設置於第一nWFM矽化物層上的第一接觸插塞。第二接觸結構包括設置於第二S/D區上的pWFM矽化物層、設置於pWFM矽化物層上的第二nWFM矽化物層、以及設置於pWFM矽化物層上的第二接觸插塞。
Description
本發明實施例是關於一種半導體裝置及其形成方法,特別是關於一種具有接觸結構的半導體裝置及其形成方法。
隨著半導體技術的進步增加了對更高的存儲容量、更快的處理系統、更高的性能、以及更低的成本的需求。為了滿足這些需求,半導體工業持續微縮化半導體裝置的尺寸,上述半導體裝置例如金屬氧化物半導體場效電晶體(metal oxide semiconductor field eF-Fect transistors, MOSFETs),包括平面MOSFETs及鰭式場效電晶體(fin field eF-Fect transistors, finFETs)。如此微縮化增加了半導體製造製程的複雜性。
本發明實施例提供一種半導體裝置,包括:基板;第一鰭片結構及第二鰭片結構,設置於基板上;第一閘極結構及第二閘極結構,分別設置於第一鰭片結構及第二鰭片結構上;第一源極/汲極(source/drain, S/D)區及第二源極/汲極區,分別設置鄰近位於第一鰭片結構及第二鰭片結構上的第一第一閘極結構及第二閘極結構;第一接觸結構及第二接觸結構,分別設置於第一S/D區及第二S/D區上,其中第一接觸結構包括第一n型功函數金屬(n-type work function metal, nWFM)矽化物層及第一接觸插塞,第一nWFM矽化物層設置於第一S/D區上,第一接觸插塞設置於第一nWFM矽化物層上;及偶極層,設置於位於第一nWFM矽化物層及第一S/D區之間的界面處。其中第一接觸結構包括第一n型功函數金屬(n-type work function metal, nWFM)矽化物層及第一接觸插塞,第一nWFM矽化物層設置於第一S/D區上,第一接觸插塞設置於第一nWFM矽化物層上。其中第二接觸結構包括p型功函數金屬(p-type work function metal, pWFM)矽化物層、第二nWFM矽化物層、及第二接觸插塞,pWFM矽化物層設置於第二S/D區上,第二nWFM矽化物層設置於pWFM矽化物層上,第二接觸插塞設置於pWFM矽化物層上。
本發明實施例提供一種半導體裝置,包括:第一閘極結構及第二閘極結構,分別設置於第一鰭片結構及第二鰭片結構上;n型源極/汲極(source/drain, S/D)區及p型S/D區,分別設置於第一鰭片結構及第二鰭片結構上;第一接觸結構及第二接觸結構,分別設置於n型S/D區及p型S/D區上;及偶極層,設置於位於三元化合物層及n型S/D區之間的界面處。其中第一接觸結構包括三元化合物層、第一n型功函數金屬(n-type work function metal, nWFM)矽化物層、及第一接觸插塞,三元化合物層設置於n型S/D區上,第一nWFM矽化物層設置於三元化合物層上,第一接觸插塞設置於nWFM矽化物層上。其中第二接觸結構包括p型功函數金屬(p-type work function metal, pWFM)矽化物層、第二nWFM矽化物層、及第二接觸插塞,pWFM矽化物層設置於p型S/D區上,第二nWFM矽化物層設置於pWFM矽化物層上,第二接觸插塞設置於pWFM矽化物層上。
本發明實施例提供一種半導體裝置的形成方法,包括:形成第一鰭片結構及第二鰭片結構於一基板上;分別形成第一源極/汲極(source/drain, S/D)區及第二源極/汲極區於第一鰭片結構及第二鰭片結構上;分別形成第一接觸開口及第二接觸開口於第一S/D區及第二S/D區上。選擇性地形成p型功函數金屬(p-type work function metal, pWFM)矽化物層於第二S/D區上;形成摻雜的n型功函數金屬矽化物層於pWFM矽化物層上及第一S/D區上;形成三元化合物層於摻雜的nWFM矽化物層及第一S/D區之間;及形成第一接觸插塞及第二接觸插塞於第一接觸開口及第二接觸開口內。
以下揭露提供了許多的實施例或範例,用於實施所提供的標的物之不同元件。各元件及其配置的具體範例描述如下,以簡化本發明實施例之說明。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例而言,敘述中若提及第一元件形成在第二元件之上,可能包含第一及第二元件直接接觸的實施例,也可能包含額外的元件形成在第一及第二元件之間,使得它們不直接接觸的實施例。如本文所使用的,在第二元件上形成第一元件指的是第一元件與第二元件直接接觸。此外,本發明實施例可能在各種範例中重複參照數值以及∕或字母。如此重複是為了簡明及清楚之目的,而非用以表示所討論的不同實施例及∕或配置之間的關係。
本文中可能用到與空間相對用詞,例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
應注意的是,說明書中對“一個實施例”、“一實施例”、“例示性實施例”、“例示性”等的引用意指所描述的實施例可包括特定的特徵、結構、或特性,但每個實施例不一定包括特定的特徵、結構、或特性。此外,這樣的用語不一定是參照相同的實施例。再者,當一實施例中描述特定的特徵、結構、或特性時,無論是否明確描述,將這樣的特徵、結構、或特性實現在其他實施例是在本領域具有通常知識者的知識範圍內。
應理解的是,本文的措詞或用語是出於描述的目的而非限制,使得本說明書的用語或措辭將由本領域具有通常知識者根據本文的教導進行解釋。
在一些實施例中,用語“約”及“實質上地”可表示一給定量的數值在目標值之5%的範圍(例如,目標值的±1%,±2%,±3%,±4 %及±5%)。 這些數值僅為示例,並不意於進行限制。相關領域的技術人員根據本文的教導來解讀“約”及“實質上”的數值百分比。
本文公開的鰭片結構可藉由任何合適的方法來圖案化。舉例而言,可使用一種或多種光學微影製程來將鰭片圖案化,包括雙重圖案化製程或多重圖案化製程。雙重圖案化或多重圖案化製程結合了光學微影及自對準製程,從而允許創建具有例如節距小於使用單一、直接光學微影刻製程得到之節距的圖案。舉例而言,在基板上方形成犧牲層並使用光學微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。然後移除犧牲層,然後可使用剩餘的間隔物來圖案化鰭片。
本公開提供了具有具有彼此不同的源極/汲極(source/drain, S/D)接觸結構之FETs(例如,finFETs)的例示性半導體裝置,並且提供了在相同的基板上形成這樣的FETs的例示性方法,其中上述FETs具有在S/D區及S/D接觸結構之間減小的接觸電阻。例示性方法在半導體裝置的n型FETs(n-type FETs, NFETs)及p型FETs(p-type FETs, PFETs)的鰭片結構上分別形成n型及p型S/D區的陣列。在一些實施例中,n型S/D區上的S/D接觸結構具有與p型S/D區上之p型S/D接觸結構的矽化物層不同的矽化物層。
S/D區及S/D接觸結構之間的接觸電阻與S/D區的材料及S/D接觸結構的矽化物層之間的肖特基阻障高度(Schottky barrier heights, SBH)成正比。對於n型S/D區而言,減小矽化物層的功函數值與S/D區的n型材料的導帶能量之間的差可減小n型S/D區及S/D接觸結構之間的SBH。相反地,對於p型S/D區而言,減小矽化物層的功函數值與S/D區的p型材料的價帶能量之間的差可減小p型S/D區及S/D接觸結構之間的SBH。在一些實施例中,由於NFETs及PFETs的S/D區是由各自的n型及p型材料所形成,所以NFETs及PFETs的S/D接觸結構是由與彼此不同的矽化物層所形成,以減少S/D接觸結構與S/D區的不同材料之間的接觸電阻。
在一些實施例中,NFET S/D接觸結構是由n型功函數金屬(n-type work function metal, nWFM)矽化物層(例如,矽化鈦)所形成,其具有相較於n型S/D區之價帶能量而言更接近導帶能量的功函數值。相反地,PFET S/D接觸結構是由p型WFM(p-type WFM, pWFM)矽化物層(例如,矽化鎳或矽化鈷)所形成,其具有相較於p型S/D之價帶能量而言更接近導帶能量的功函數值。可藉由n型S/D區以及設置於n型S/D區上的nWFM層之間的矽化反應來形成nWFM矽化物層。可藉由p型S/D區及設置於p型S/D區上的pWFM層之間的矽化反應來形成pWFM矽化物層。
在一些實施例中,偶極層可形成在NFETs的S/D區及矽化物層之間的界面處,以進一步減小n型S/D區及S/D接觸結構之間的SBHs。可藉由用電負值低於矽化物層之金屬的金屬摻雜矽化物層來形成偶極層。金屬摻質可誘發(induce)在金屬摻質與n型S/D區的半導體元件之間形成偶極(dipoles)。相較於具有類似的矽化物層的NFETs及PFETs,這種選擇性形成在NFETs及PFETs中的矽化物層可將半導體裝置的接觸電阻降低約50%至約70%,並因此提高半導體裝置的性能。
第1圖係根據一些實施例,繪示出具有NFET 102N及PFET 102P的半導體裝置100的等距視圖。如第2A圖至第2D圖、第3A圖至第3D圖、第4A圖至第4D圖及第5A圖至第5D圖所示,NFET 102N及PFET 102P可具有不同的剖面圖。第2A圖至第5A圖及第2C圖至第5C圖分別繪示出了沿第1圖的線A-A及線C-C的NFET 102N的剖面圖。第2B圖至第5B圖及第2D圖至第5D圖分別繪示出沿著第1圖的線B-B及D-D的PFET 102P的剖面圖。第2A圖至第2D圖、第3A圖至第3D圖、第4A圖至第4D圖及第5A圖至第5D圖繪示出具有為簡化起見在第1圖中未繪示之額外結構的半導體裝置100的剖面圖。除非另有說明,否則對具有相同註記的NFET 102N及PFET 102P的元件的討論適用於彼此。
參照第1圖,NFET 102N可包括設置在鰭片結構106N上的閘極結構112N的陣列,且PFET 102P可包括設置在鰭片結構106P上的閘極結構112P的陣列。NFET 102N可更包括設置在未被閘極結構112N所覆蓋之鰭片結構106N的部分上的S/D區108N的陣列(在第1圖中可見的S/D區108N之一)。類似地,PFET 102P可更包括設置在未被閘極結構112P所覆蓋之鰭片結構106P的部分上的磊晶S/D區108P的陣列(第1圖中可見的S/D區108P之一)。
半導體裝置100可更包括閘極間隔物114、淺溝槽隔離(shallow trench isolation, STI)區116、蝕刻停止層(etch stop layer, ESL)117、及層間介電(interlayer dielectric, ILD)層118A-118B(ILD層118B為簡單起見在第1圖中未繪示,其在第2A圖至第2D圖、第3A圖至第3D圖、第4A圖至第4D圖及第5A圖至第5D圖中繪示)。ILD層118A可設置在ESL 117上。可將ESL117設置為保護閘極結構112N及112P及/或S/D區108N及108P。在一些實施例中,閘極間隔物114、STI區116、ESL 117、及ILD層118A-118B可包括例如下列絕緣材料:氧化矽、氮化矽(silicon nitride, SiN)、碳氮化矽(silicon carbon nitride, SiCN)、氮碳氧化矽(silicon oxycarbon nitride, SiOCN)、及氧化矽鍺。在一些實施例中,閘極間隔物114可具有約2nm至約9nm的厚度,以使閘極結構112N及112P與鄰近結構充分電性隔離。
半導體裝置100可形成在基板104上,並且具有NFET 102N及PFET 102P形成在基板104的不同區上。在基板104上的NFET 102N及PFET 102P之間可形成其他FETs及/或結構(例如,隔離結構)。基板104可為半導體材料,例如矽、鍺(germanium, Ge)、矽鍺(silicon germanium, SiGe)、絕緣體上覆矽(silicon-on-insulator, SOI)結構、及其組合。再者, 基板104可摻雜p型摻質(例如,硼、銦、鋁、或鎵)或n型摻質(例如,磷或砷)。在一些實施例中, 鰭片結構106N-106P可包括類似於基板104的材料並且沿著X軸延伸。
參照第2A圖至第2D圖,NFET-PFET 102N-102P可包括閘極結構112N-112P、S/D區108N-108P、及設置在S/D區108N-108P上的S/D接觸結構120N-120P。閘極結構112N-112P可為多層結構。每個閘極結構112N-112P可包括界面氧化物(interfacial oxide, IO)層122、設置在IO層122上的高k(high-k, HK)閘極介電層124、設置在HK閘極介電層124上的功函數金屬(work function metal, WFM)層126、設置在WFM層126上的閘極金屬填充層128、以及設置在HK閘極介電層124、WFM層126及閘極金屬填充層128上的閘極蓋層130。
IO層122可包括氧化矽(silicon oxide, SiO2
)、氧化矽鍺(silicon germanium oxide, SiGeOx
)、或氧化鍺(germanium oxide, GeOx
)。HK閘極介電層124可包括例如下列高k介電質材料:氧化鉿(hafnium oxide, HfO2
)、氧化鈦(titanium oxide, TiO2
)、氧化鉿鋯(hafnium zirconium oxide, HfZrO)、氧化鉭(tantalum oxide, Ta2
O3
)、矽酸鉿(hafnium silicate, HfSiO4
)、氧化鋯(zirconium oxide, ZrO2
)、及矽酸鋯(zirconium silicate, ZrSiO2
)。閘極結構112N的WFM層126可包括鈦鋁(titanium aluminum, TiAl)、碳化鈦鋁(titanium aluminum carbide, TiAlC)、鉭鋁(tantalum aluminum, TaAl)、碳化鉭鋁(tantalum aluminum carbide, TaAlC)、摻雜Al的Ti、摻雜Al的TiN、摻雜Al的Ta、摻雜Al的TaN、其組合、或其他合適的Al基(Al-based)材料。閘極結構112P的WFM層126可包括實質上無鋁的(Al-free)(例如,沒有Al)Ti基(Ti-based)、或Ta基(Ta-based)的氮化物或合金,例如氮化鈦(titanium nitride, TiN)、氮化鈦矽(titanium silicon nitride, TiSiN)、鈦金(titanium gold, Ti-Au)合金、鈦銅(titanium copper, Ti-Cu)合金、氮化鉭(tantalum nitride, TaN)、氮化鉭矽(tantalum silicon nitride, TaSiN)、鉭金(tantalum gold, Ta-Au)合金、鉭銅(tantalum copper, Ta-Cu)、及其組合。閘極金屬填充層128可包括例如下列合適的導電材料:鎢(tungsten, W)、Ti、銀(silver, Ag)、釕(ruthenium, Ru)、鉬(molybdenum, Mo)、銅(copper, Cu)、鈷(cobalt, Co)、Al、銥(iridium, Ir)、鎳(nickel, Ni)、金屬合金及其組合。在一些實施例中,閘極結構112N-112P可藉由閘極蓋層130與上方的內連線結構(未繪示)電性隔離,上述閘極蓋層130可包括氮化物層。
每個S/D區108N可包括磊晶疊層—磊晶成長在鰭片結構106N上的輕摻雜(lightly doped, LD)n型層109N、磊晶成長在LD n型層109N上的重摻雜(heavily doped, HD)n型層110N、及在HD n型層110N上磊晶成長的p型蓋層111N。在一些實施例中,LD及HD n型層109N-110N可包括磊晶成長的半導體材料,例如矽以及n型摻質,上述n型摻質例如磷及其他合適的n型摻質。LD n型層109N可包括在約1015
原子/cm3
至約1018
原子/cm3
的範圍內的摻雜濃度,其低於HD n型層110N的摻雜濃度,HD n型層110N的摻雜濃度可在約1019
原子/cm3
至約1023
原子/cm3
的範圍內。在一些實施例中,HD n型層110N比LD n型層109N厚。
類似地,每個S/D區108P可包括磊晶疊層—磊晶成長在鰭片結構106P上的LD p型層109P、磊晶成長在LD p型層109P上的HD p型層110P、以及在HD p型層110P上磊晶成長的n型蓋層111 P。在一些實施例中,LD及HD p型層109P-110P可包括磊晶成長的半導體材料,例如SiGe以及p型摻質,上述p型摻質例如硼及其他合適的p型摻質。LD p型層109P可包括在約1015
原子/ cm3
至約1018
原子/ cm3
範圍內的摻雜濃度,其低於HD p型層110P的摻雜濃度,上述HD p型層110P的摻雜濃度可在約1019
原子/ cm3
至約1023
原子/ cm3
的範圍內。在一些實施例中,LD p型層109P可包括在約5原子百分比至約45原子百分比的範圍內的Ge濃度,其低於HD p型層110P的Ge濃度,上述HD p型層110P的Ge濃度可在約50原子百分比至約80%的原子百分比的範圍內。在一些實施例中,HD p型層110P比LD p型層109P厚。
P型蓋層111N包括與HD p型層110P相似的材料及摻質,且n型蓋層111P包括與HD n型層110N相似的材料及摻質。在一些實施例中,p型及n型蓋層111N-111P可包括約1019
原子/cm3
至約1023
原子/cm3
之範圍的摻雜濃度。P型及n型蓋層111N-111P被稱為反向蓋層(reverse capping layer)111N-111P,因為這些層分別設置在導電性相反的HD n型及p型層110N-110P上。這些反向蓋層111N-111P用於在相應的S/D區108P及108N中選擇性地形成矽化物層131及132N,這將在後文詳細描述。在一些實施例中,p型及n型蓋層111N-111P沿著Z軸的厚度可在約1nm至約3nm的範圍內。低於此範圍的厚度可能不會形成連續的層,並且可能不足以選擇性地形成矽化物層131及132N。另一方面,如果厚度大於此範圍,則製程時間(例如,磊晶成長時間)增加,並且因此增加了裝置製造成本。
參照第2A圖及第2C圖,S/D接觸結構120N設置在S/D區108N上。在一些實施例中,S/D接觸結構120N可包括(i)設置在HD n型層110N上的nWFM矽化物層132N、(ii)設置在nWFM矽化物層132N上的接觸插塞134N、(iii)設置在接觸插塞134N的側壁上的金屬基(metal-based)襯層的堆疊135N、以及(iv)設置在金屬基襯層的堆疊135N上的阻障層142N。NFET 102N可更包括位於nWFM矽化物層132N與HD n型層110N之間的界面(“界面132N-110N”)處的偶極層144。在一些實施例中,界面132N-110N可在S/D區108N內並在S/D區108N的頂表面下方。
在一些實施例中,nWFM矽化物層132N的頂表面可在S/D區108N的頂表面上方(如第2A圖及第2C圖所示),或者可與S/D區108N的頂表面實質上平共平面(未繪示)。在一些實施例中,如第2C圖所示,nWFM矽化物層132N可與金屬基襯層的堆疊135N形成角度A及B。角度A及B可彼此相似或不同,並且可在約45度至約60度的範圍內。在一些實施例中,nWFM矽化物層132N可包括具有功函數值相較於HD n型層110N之材料的價帶邊緣能量(valence band-edge energy)而言更接近導帶邊緣能量(conduction band-edge energy)的金屬或金屬矽化物。舉例而言,金屬或金屬矽化物可具有小於4.5eV(例如,約3.5eV至約4.4eV)的功函數值,其相較於HD n型層110N的Si基(Si-based)或SiGe基(SiGe-based)材料的價帶能量(例如Si的5.2eV或SiGe的4.8eV)而言,可更接近導帶能量(例如,Si的4.1eV或SiGe 的3.8eV)。在一些實施例中,nWFM矽化物層132N的金屬矽化物可包括矽化鈦(titanium silicide, Tix
Siy
)、矽化鉭(tantalum silicide, Tax
Siy
)、矽化鉬(molybdenum silicide, Mox
Siy
)、矽化鋯(zirconium silicide, Zrx
Siy
)、矽化鉿(hafnium silicide, Hfx
Siy
)、矽化鈧(scandium silicide, Scx
Siy
)、矽化釔(yttrium silicide, Yx
Siy
)、矽化鋱(terbium silicide, Tbx
Siy
)、矽化鎦(lutetium silicide, Lux
Siy
)、矽化鉺(erbium silicide, Erx
Siy
)、矽化鐿(ybtterbium silicide, Ybx
Siy
)、矽化銪(europium silicide, Eux
Siy
)、矽化釷(thorium silicide, Thx
Siy
)、或其組合。
在一些實施例中,nWFM矽化物層132N可更包括過渡金屬的摻質,其電負值(electronegativity value)小於nWFM矽化物層132N中包括的金屬矽化物之金屬的電負值。舉例而言,摻質可包括例如下列過渡金屬:鋯(zirconium, Zr)、鉿(hafnium, Hf)、鐿(ybtterbium, Yb)、釔(yttrium, Y)、鉺(erbium, Er)、鈰(cerium, Ce)、鈧(scandium, Sc)及其組合。在一些實施例中,一些摻質可擴散至HD n型層110N中。摻質可誘發在界面132N-110N處之偶極層144中的帶電偶極的形成。偶極層144可包括來自HD n型層110N之矽離子的帶電偶極以及來自nWFM矽化物層132N中之摻質的過渡金屬離子的帶電偶極。舉例而言,當nWFM矽化物層132N包括Zr、Hf、Yb、Y、Er、Ce、或Sc摻質時,偶極層144可分別包括Zr-Si、Hf-Si、Yb-Si、Y-Si、Er-Si、Ce-Si、或Sc-Si偶極。
偶極層144中的偶極在界面132N-110N處產生的電場可減小nWFM矽化物層132N及HD n型層110N之間的SBH,因此減小了S/D接觸結構120N及S/D區108N之間的接觸電阻。相較於nWFM矽化物層132N及沒有偶極層144的HD n型層110N之間的SBH,基於界面132N-110N上偶極層144中偶極的類型及濃度,nWFM矽化物層132N及HD n型層110N之間的SBH可降低約35%至約70%。界面132N-110N處的偶極濃度與nWFM矽化物層132N及/或界面132N-110N中的摻質濃度成正比。nWFM矽化物層132N及/或界面132N-110N中的摻質濃度可在約1原子百分比至約10原子百分比的範圍內。低於此範圍的摻質濃度可能不會誘發偶極層144中的偶極的形成。另一方面,如果摻質濃度高於此範圍,則摻雜製程的持續時間及復雜性增加,並因此增加了裝置製造成本。
如第2E圖所示,係根據各種實施例,摻質濃度可具有沿著第2A圖及第2C圖之線E-E橫跨nWFM矽化物層132N及HD n型層110N的輪廓246、248、及/或250。如後文詳述地,當在不包括高溫(例如,溫度大於500)退火製程的摻雜製程中用過渡金屬(例如,Zr、Hf等)來摻雜nWFM矽化物層132N時,摻質濃度可在界面132N-110N處具有峰值摻質濃度C1的輪廓246。當在不包括高溫退火製程的摻雜製程中用非Zr基(non-Zr-based)的過渡金屬(例如,Hf、Ce、Er等)來摻雜nWFM矽化物層132N時,摻質濃度可具有輪廓248。非Zr基過渡摻質相較於Zr摻質而言在界面132N-110N處可具有較低的熱力學穩定性,這可導致大量非Zr基過渡摻質從界面132N-110N擴散出去並擴散至nWFM矽化物層132N中。如此一來,如第2E圖所示,輪廓248的峰值摻質濃度可與界面132N-110N相距距離D1(例如,約0.1nm至約0.5nm),並且可在界面132N-110N處具有摻質濃度C2,上述摻質濃度C2小於峰值摻質濃度C1。
在一些實施例中,如第2E圖所示,當nWFM矽化物層132N的摻雜包括高溫退火製程時,非Zr基的摻質由於其在界面132N-110N處的較低的熱力學穩定性而可擴散更進去nWFM矽化物層132N中,並且可具有摻質濃度輪廓250。輪廓250的峰值摻質濃度可與界面132N-110N相距距離D2(例如,約0.2nm至約0.8nm),並且可在界面132N-110N處具有小於摻質濃度C2的摻質濃度C3,上述距離D2大於距離D1。由於在界面132N-110N處的摻質濃度與在界面132N-110N處的偶極濃度成正比,因此輪廓246之偶極層144中的偶極濃度可大於輪廓248及250的偶極層144中的偶極濃度,並且輪廓248之偶極層144中的偶極濃度可大於輪廓250的偶極層144中的偶極濃度。如此一來,輪廓246位於nWFM矽化物層132N及HD n型層110N之間的SBH可低於輪廓248及250的位於nWFM矽化物層132N及HD n型層110N之間的SBH,且輪廓248位於nWFM矽化物層132N及HD n型層110N之間的SBH可低於輪廓250的位於nWFM矽化物層132N及HD n型層110N之間的SBH。在一些實施例中,當nWFM矽化物層132N以Zr金屬及一種或多種非Zr基的過渡金屬的組合摻雜時,摻質濃度可具有沿著第2A圖及第2C圖之線E-E的輪廓246及248、或者可具有輪廓246及250。
參照第2A圖及第2C圖,接觸插塞134N可包括例如下列導電材料:鈷(cobalt, Co)、鎢(tungsten, W)、釕(ruthenium, Ru)、銥(iridium, Ir)、鎳(nickel, Ni)、鋨(osmium, Os)、銠(rhodium, Rh)、鋁(aluminum, Al)、鉬(molybdenum, Mo)、銅(copper, Cu)、鋯(zirconium, Zr)、錫(stannum, Sn)、銀(silver, Ag)、金(gold, Au)、鋅(zinc, Zn)、鎘(cadmium, Cd)及其組合。在一些實施例中,金屬基襯層的堆疊135N可包括第一襯層136N、第二襯層138N、及第三襯層140N。第一襯層136N可為如後文詳述的用於形成nWFM矽化物層132N之來源層的一部分,並且可包括nWFM矽化物層132N的金屬或者可包括nWFM矽化物層132N的金屬的氧化物。第二襯層138N可為如後文詳述的用於摻雜nWFM矽化物層132N之來源層的一部分,並且可包括位於nWFM矽化物層132N中之摻質的過渡金屬,或者可包括摻質的金屬的氧化物。第三襯層140N可為如後文詳述的用於形成pWFM矽化物層132P之來源層的一部分,並且可包括pWFM矽化物層132P的金屬或者可包括pWFM矽化物層132P的金屬的氧化物。在一些實施例中,第二及/或第三襯層138N-140N可不存在於金屬基襯層的堆疊135N中,或者金屬基襯層的堆疊135N可不存在於S/D接觸結構120N中(如第23A圖及第23C圖所示)。阻障層142N可包括氮化物材料,並且可減少或防止氧原子從ILD層118A-118B擴散至接觸插塞134N中,以防止接觸插塞134N的導電材料的氧化。
參照第2B圖及第2D圖,S/D接觸結構120P設置於S/D區108P上。在一些實施例中,S/D接觸結構120P可包括(i)設置於HD p型層110P上的pWFM矽化物層131;(ii)設置於pWFM矽化物層131上的nWFM矽化物層132P;(iii)設置於nWFM矽化物層132P上的接觸插塞134P;(iv)金屬基襯層的堆疊135P,具有第一襯層136P、第二襯層138P、及第三襯層140P設置於接觸插塞134P的側壁上;以及(v)設置於金屬基襯層的堆疊135P上的阻障層142P。除非另有說明,否則接觸插塞134N、阻障層142N、以及具有第一襯層、第二襯層、及第三襯層136N-140N之金屬基襯層的堆疊135N的討論分別適用於接觸插塞134P、阻障層142P、以及具有第一襯層、第二襯層、及第三襯層136P-140P之金屬基襯層的堆疊135P。在一些實施例中,第二襯層及/或第三襯層138P-140P可不存在於金屬基襯層的堆疊135P中,或者金屬基襯層的堆疊135P可不存在於S/D接觸結構120P中(如第24B圖及第24D圖所示)。
在一些實施例中,pWFM矽化物層131的頂表面可在S/D區108P的頂表面上方(如第2B圖及第2D圖所示),或者可與S/D區108P的頂表面實質上共平面(未繪示)。在一些實施例中,如第2D圖所示,pWFM矽化物層132N可與金屬基襯層的堆疊135P形成角度C及角度D。角度C及D可彼此相似或不同,並且可在約45度至約60度的範圍內。在一些實施例中,pWFM矽化物層131可包括具有功函數值比HD p型層110P之材料的導帶邊緣能量更接近價帶邊緣能量的金屬或金屬矽化物。舉例而言,金屬或金屬矽化物可具有大於4.5eV(例如,約4.5eV至約5.5eV)的功函數值,其相較於HD p型層110P的Si基或SiGe基材料的導帶能量(例如,Si的4.1eV或SiGe的3.8eV)而言,可更接近價帶能量(例如,Si的5.2eV或SiGe的4.8eV)。在一些實施例中,pWFM矽化物層131的金屬矽化物可包括例如下列:矽化鎳(nickel silicide, Nix
Siy
)、矽化鈷(cobalt silicide, Cox
Siy)、矽化錳(manganese silicide, Mnx
Siy
)、矽化鎢(tungsten silicide, Wx
Siy
)、矽化鐵(iron silicide, Fex
Siy
)、矽化銠(rhodium silicide, Rhx
Siy
)、矽化鈀(palladium silicide, Pdx
Siy
)、矽化釕(ruthenium silicide, Rux
Siy
)、矽化鉑(platinum silicide, Ptx
Siy
)、矽化銥(iridium silicide, Irx
Siy
)、矽化鋨(osmium silicide, Osx
Siy
)、或其組合。
pWFM矽化物層131的金屬矽化物不同於nWFM層132N-132P的金屬矽化物,並且可具有功函數值大於nWFM矽化物層132N-132P的功函數值。在一些實施例中,nWFM矽化物層132P可與nWFM矽化物層132N同時形成,並且可包括金屬矽化物及類似於nWFM矽化物層132N的摻質。一些摻質可擴散至pWFM矽化物層132中。如第2F圖所示,係根據各種實施例,nWFM矽化物層132P及pWFM矽化物層131上的摻質濃度類似於摻質濃度輪廓246-250,可具有沿著第2B圖及第2D圖之線F-F的輪廓252、254、及/或256。當在不包括高溫退火製程的摻雜製程中用過渡金屬(例如,Zr、Hf等)摻雜nWFM矽化物層132P時,摻質濃度在pWFM矽化物層131與nWFM矽化物層132P之間的界面(“界面131-132P”)處可具有峰值摻質濃度C4的輪廓252。當nWFM矽化物層132P在不包括高溫退火製程的摻雜製程中被非Zr基的過渡金屬(例如,Hf、Ce、Er等)摻雜時,摻質濃度可具有輪廓254。輪廓254的峰值摻質濃度可與界面131-132P相距距離D3(例如,約0.1nm至約0.5nm),並且可在界面131-132P處具有小於峰值摻質濃度C4的摻質濃度C5。
當在包括高溫退火製程的摻雜製程中,用非Zr基過渡金屬(例如,Hf、Ce、Er等)來摻雜nWFM矽化物層132P時,摻質濃度可具有輪廓256。輪廓256的峰值摻質濃度可與界面131-132P相距距離D4(例如,約0.2nm至約0.8nm),上述距離D4大於距離D3,並且可在界面131-132P處具有小於摻質濃度C5的摻質濃度C6。在一些實施例中,當nWFM矽化物層132P以Zr金屬及一種或多種非Zr基的過渡金屬的組合摻雜時,橫跨沿著第2B圖及第2D圖之線F-F的摻質濃度可具有輪廓252及254、或者可具有輪廓252及256。在一些實施例中,不同於nWFM矽化物層132N,nWFM矽化物層132P可為未摻雜的。為了有效降低接觸電阻,pWFM矽化物層131沿著Z軸的厚度可在約1nm至約3nm的範圍內,且nWFM矽化物層132N-132P沿著Z軸的厚度可在約2nm至約6nm的範圍內。
在一些實施例中,當在包括高溫退火製程的摻雜製程中用Zr金屬摻雜nWFM矽化物層132N-132P時,S/D接觸結構120N-120P可具有如第3A圖至第3D圖所示的剖面圖。參照第3A圖及第3C圖,S/D接觸結構120N可包括插在nWFM矽化物層132N及HD n型層110N之間的Zr基的三元化合物(Zr-based ternary compound, ZTC)層133。在高溫退火製程期間,nWFM矽化物層132N的Zr摻質可與HD n型層110N的Si原子及nWFM矽化物層132N的金屬原子交互作用,以形成ZTC層133。在一些實施例中,當nWFM矽化物層132N包括Tix
Siy
時,ZTC層133可包括矽化鋯鈦(zirconium titanium silicide, Zr3
Ti2
Si3
)。ZTC層133可在ZTC層133與HD n型層110N之間的界面(“界面133-110N”)處誘導(induce)偶極層145的形成。在一些實施例中,界面133-110N可位於S/D區108N內並且位於S/D區108N的頂表面下方。偶極層145可包括來自ZTC層133之Zr金屬離子以及來自HD n型層110N之矽離子的Zr-Si偶極。
類似於偶極層144,偶極層145在界面133-110N處產生的電場可使nWFM矽化物層132N及HD n型層110N之間的SBH降低約35%至約70%,並因此降低S/D接觸結構120N與S/D區108N之間的接觸電阻。ZTC層133中Zr原子的濃度可在約1原子百分比到約10原子百分比的範圍內。在一些實施例中,如第3E圖所示,Zr原子可具有沿著第3A圖及第3C圖之線G-G橫跨nWFM矽化物層132N、ZTC層133、及HD n型層110N的濃度輪廓358。
參照第3B圖及第3D圖,由於介於中間的pWFM矽化物層131可防止Zr摻質與HD p型層110P的Si原子交互作用,因此在高溫退火製程期間,nWFM矽化物層132P的Zr摻質並未在S/D接觸結構120P中形成ZTC層。Zr摻質可具有類似於第2F圖之輪廓252的濃度輪廓。
在一些實施例中,如第4A圖至第4D圖所示,S/D接觸結構120N-120P可包括相對應的氮化物蓋層146N-146P。可形成氮化物蓋層146N-146P,以在隨後的S/D接觸結構120N-120P的製程期間保護下方的層(例如,矽化物層131及132N-132P)。
在一些實施例中,對比於如第2A圖至第4A圖及第2C圖至第4C圖所示之界面132N-110N與位於p型蓋層111N及HD n型層110N之間的界面(“界面111N-110N”)實質上共平面,界面132N-110N可如第5A圖及第5C圖所示與界面111N-110N不共平面。當在nWFM矽化物層132N的形成中不使用p型蓋層111N的矽時,可發生非共平面性(non-coplanarity)。取而代之,在形成nWFM矽化物層132N的製程期間消耗了HD n型層110N的矽,且所得之nWFM矽化物層132N延伸至HD n型層110中。在後文中詳述形成具有及不具有p型蓋層111N的nWFM矽化物層132N。如第2B圖至第5B圖及第2D圖至第5D圖所示, 位於pWFM矽化物層131及HD p型層110N之間的界面可與位於n型蓋層111P及HD p型層110P之間的界面實質上共平面。
第6圖係根據一些實施例,係用於製造半導體裝置100的NFET 102N及PFET 102P的例示性方法600的流程圖。為了說明的目的,將參考用於製造如第7A圖至第23D圖所示之NFET 102N及PFET 102P的例示性製造製程來描述第6圖所示的操作。 第7A圖至第23A圖以及第7C圖至第23C圖係分別沿著第1圖及第7B圖至第23B圖之線A-A及C-C之NFET 102N的剖面圖,且第7D圖至第23D圖係根據一些實施例,係在製造的各個階段中沿著第1圖之相對應的線B-B及D-D的PFET 102P的剖面圖。可取決於特定的應用按照不同的順序進行操作或者可不進行操作。應注意的是,方法600可能不會產生完整的NFET 102N及PFET 102P。因此,應理解的是,可在方法600之前、期間、及之後提供額外的製程,且這裡可能僅簡要地描述一些其他製程。第7A圖至第23D圖中的元件具有與前文所述之第1圖及第2A圖至第5D圖中的元件相同的註解。
在操作605中,在位於基板上的鰭片結構上形成多晶矽結構以及n型及p型S/D區。舉例而言,如第7A圖至第7B圖所示,在形成於基板104上的鰭片結構106N-106P上形成多晶矽結構712N-712P及S/D區108N-108P。在隨後的製程期間,可在閘極替換製程中替換多晶矽結構712N-712P,以形成閘極結構112N-112P。在一些實施例中,S/D區108N-108P的形成可包括下列依序操作:(i)在不位於多晶矽結構712N-712P下方之鰭片結構106N-106P的部分中形成S/D開口(未繪示),( ii)將遮罩層(例如,光阻層;未繪示)圖案化以覆蓋鰭片結構106P中的S/D開口,(iii)在鰭片結構106N中的S/D開口內選擇性地磊晶成長Si層(未繪示),(iv)如第7A圖及第7C圖所示,用n型摻質(例如,磷)選擇性地摻雜Si層以形成LD及HD n型層109N-110N,(v)在HD n型層110N上選擇性地磊晶成長SiGe層(未繪示),(vi)如第7A圖及第7C圖所示,用p型摻質(例如,硼)選擇性地摻雜SiGe層以形成p型蓋層,(vii)從鰭片結構106P中的S/D開口移除遮罩層,(viii)將遮罩層圖案化以覆蓋S/D區108N,(ix)選擇性地磊晶成長SiGe層(未繪示)於鰭片結構106P中的S/D開口內,(x)如第7B圖及第7D圖所示,用p型摻質(例如,硼)選擇性地摻雜SiGe層,以形成LD及HD p型層109P-110P,(xi)在HD p型層110P上選擇性地磊晶成長Si層(未繪示),並且(xii)如第7B圖及第7D圖所示,用n型摻質(例如,磷)選擇性地摻雜Si層,以形成n型蓋層111P。在形成S/D區108N-108P之後,可形成ESL 117及ILD層118A以形成如第7A圖至第7D圖所示之結構。
參照第6圖,在操作610中,用閘極結構代替多晶矽結構。舉例而言,如第8A圖至第8B圖所示,用閘極結構112N-112P代替多晶矽結構712N-712P。在一些實施例中,如第9A圖至第9B圖所示,可回蝕閘極結構112N-112P以形成閘極蓋層130。在形成閘極蓋層130之後,可形成ILD層118B以形成如第9A圖至第9D圖所示之結構。
參照第6圖,在操作615中,第一接觸開口及第二接觸開口形成於n型及p型源S/D區上。舉例而言,如第10A圖至第10D圖所示,藉由蝕刻位於S/D區108N-108P上ESL 117及ILD層118A-118B的部分,於S/D區108N-108P上形成第一及第二接觸開口1020N-1020P。
參照第6圖,在操作620中,在第一接觸開口及第二接觸開口的側壁上選擇性地形成阻障層。舉例而言,如關於第11A圖至第12D圖所述,在第一及第二接觸開口1020N-1020P的側壁上選擇性地形成阻障層142N-142P。阻障層142N-142P的形成可包括下列依序操作:(i)在第10A圖至第10D圖的結構上沉積氮化物層142(例如,SiN),以形成第11A圖至第11D圖的結構,及(ii)進行等向性蝕刻製程,以從ILD層118A以及p型及n型蓋層111N-111P的頂表面移除氮化物層142的部分,以形成第12A圖至第12D圖的結構。
參照第6圖,在操作625中,在p型S/D區上選擇性地形成pWFM矽化物層。舉例而言,如第13A圖至第13D圖所示,在S/D區108P上選擇性地形成pWFM矽化物層131。pWFM矽化物層131的選擇性形成可包括在第12A圖及第12D圖的結構上沉積pWFM層140,其可啟始(initiate)n型蓋層111P與沉積在n型蓋層111N上之pWFM層140的底部(未繪示)之間的矽化反應(silicidation),以形成第13A圖至第13D圖的結構。在一些實施例中,pWFM層140可包括功函數值,其相較於S/D區108P之HD p型層110P的材料的導帶邊緣能量(conduction band-edge energy)而言更接近價帶邊緣能量(valence band-edge energy)。舉例而言,pWFM層140可包括具有大於4.5eV(例如,約4.5eV至約5.5eV)之功函數值的金屬,上述功函數值相較於HD p型層110P之Si的導帶能量4.1eV或SiGe的導帶能量3.8eV而言,可更接近HD p型層110P之Si的價帶能量5.2eV或SiGe的價帶能量4.8eV。在一些實施例中,pWFM層140可包括Ni、Co、Mn、W、Fe、Rh、Pd、Ru、Pt、Ir、Os、或其組合。
pWFM層140的沉積可包括在約160°C至約220℃的溫度範圍內及約5 Torr至約10 Torr的壓力下藉由化學氣相沉積(chemical vapor deposition, CVD)製程或原子層沉積(atomic layer deposition, ALD)製程沉積約0.5nm至約5nm厚的pWFM層。在一些實施例中,ALD製程可包括約300個循環至約800個循環,其中一個循環可包括下列依續週期:(i)金屬前驅物、反應物、及載氣混合物流(flow),以及(ii)約3秒至約15秒的氣體驅淨(gas purging)製程。在一些實施例中,反應物氣體可包括氨氣(ammonia, NH3
),載氣可包括氮氣或氬氣,而驅氣可包括稀有氣體。
在一些實施例中,金屬前驅物可包括金屬錯合物(metal complexes),例如雙(1,4-二叔丁基-1,3-二氮雜丁二烯基)M (Bis(1,4-di-t-butyl-1,3-diazabutadienyl)M))、
M(tBuNNCHCtBuO)2
、M(eBuNNCHCiPrO)2
、及
M(tBuNNCMeCMeO)2
,其中M可為Ni、Co、Mn、W、Fe、Rh、Pd、Ru、Pt、Ir、或Os。由於金屬錯合物對Si比對SiGe更高的親和力,因此pWFM層140沉積於包括Si的n型蓋層111P上,並且並未沉積於包括SiGe的p型蓋層111N上。SiGe的應變(strained)晶格結構抑制了金屬錯合物在p型蓋層111N上的粘附,結果防止了在NFET的p型蓋層111N上形成pWFM層140。因此,藉由消除用於在PFET 102P中選擇性地形成pWFM矽化物層131的光學微影及蝕刻製程的使用,將金屬錯合物用作pWFM層140的金屬前驅物減少了處理步驟的數量,因此降低了裝置製造成本。
在一些實施例中,可在沉積pWFM層140之前,在第12A圖至第12D圖的結構上進行清潔製程。清潔製程可包括氟基的乾式蝕刻製程,以從p型蓋層111N及n型蓋層111P的頂表面移除原生氧化物(native oxides)。
在一些實施例中,在形成pWFM矽化物層131之後,位於接觸開口1020N-1020P的側壁上之pWFM層140的部分可藉由濕式蝕刻製程來移除,以形成第14A圖至第14D圖的結構。在一些實施例中,可藉由濕式製程或乾式蝕刻製程從第13A圖及第13C圖的NFET結構或第14A圖及第14C圖的NFET結構選擇性地移除位於接觸開口1020N內的p型蓋層111N的露出部分,以形成第16A圖及第16C圖的NFET結構。
參照第6圖,在操作630中,在n型S/D區及pWFM矽化物層上形成摻雜的nWFM矽化物層。舉例而言,如第19A圖至第19D圖所示,分別在S/D區108N及pWFM矽化物層131上形成摻雜的nWFM矽化物層132N及132P。摻雜的nWFM矽化物層132N-132P的形成可包括下列依序操作:(i)在第13A圖至第13D圖的結構上進行清潔製程(例如,氟基的乾式蝕刻製程),以從p型蓋層111N及pWFM矽化物層131的頂表面移除原生氧化物,(ii)在第13A圖至第13D圖的清潔結構上沉積摻質來源層138,以形成第17A圖至第17D圖的結構,及(iii)在第17A圖至第17D圖的結構上沉積nWFM層136,以形成第19A圖至第19D圖的結構。
在nWFM層136的沉積期間,沉積溫度可使摻質來源層138的底部138b(如第17A圖至第17B圖所示)熱分解,並且熱分解的底部138b的原子擴散至上方的nWFM層136中作為摻質原子。參照第2A圖至第2F圖,摻質原子可誘發偶極層144的形成,並且可具有橫跨線E-E的濃度輪廓246或248及橫跨線F-F的濃度輪廓252或254。沉積溫度也可啟始下列部件之間的矽化反應:(i)位於接觸開口1020N內的nWFM層136的摻雜底部(未繪示)與p型蓋層111N之間的矽化反應,以形成如第19A圖及第19C圖所示之nWFM矽化物層132N,以及(ii)接觸開口1020P內的nWFM層136的摻雜底部與經由pWFM矽化物層131的HD p型層111P的矽化反應,以形成如第19B圖及第19D圖所示之nWFM矽化物層132P。在一些實施例中,如第18A圖至第18D圖所示,在沉積摻質來源層138之後,可選擇性地移除位於第17B圖及第17D圖之PFET結構上之摻質來源層138的部分,以形成未摻雜的nWFM矽化物層132P(未繪示)及摻雜的nWFM矽化物層132N。
在一些實施例中,摻質來源層138的沉積可包括在約300°C至約500°C之溫度範圍內使用CVD製程或ALD製程沉積過渡金屬,上述過渡金屬的電負值(electronegativity value)小於nWFM層136的金屬的電負值。在一些實施例中,摻質來源層138可包括例如下列過渡金屬:Zr、Hf、Yb、Y、Er、Ce、Sc、及其組合。為了有效及完全地熱分解摻質來源層138,可將摻質來源層138沉積為約0.05nm至約0.5nm範圍內的厚度。
在一些實施例中,nWFM層136的沉積可包括在約300℃至約500℃的溫度範圍內使用CVD製程或ALD製程來沉積金屬,上述金屬具有功函數值相較於S/D區108N之HD n型層111N之材料的價帶邊緣能量更接近導帶邊緣能量。舉例而言,nWFM層136可包括具有功函數值小於4.5eV(例如,約3.5eV至約4.4eV)的金屬,上述功函數值相較於HD n型層111N之Si的價帶能量5.2eV或SiGe的價帶能量4.8eV而言,更接近HD n型層111N之Si的的導帶能量4.1eV或SiGe的的導帶能量3.8eV。在一些實施例中,nWFM層136可包括Ti、Ta、Mo、Zr、Hf、Sc、Y、Ho、Tb、Gd、Lu、Dy、Er、Yb、或其組合。
在一些實施例中,摻雜的nWFM矽化物層132N-132P的形成可包括下列依序操作:(i)在第14A圖至第14D圖、第15A圖至第15D圖、或第16A圖至第16D圖而非第13A圖至第13D圖中的結構上進行清潔製程(例如,氟基的乾式蝕刻製程),(ii)在第14A圖至第14D圖、第15A圖至第15D圖、或第16A圖至第16D圖所示的清潔結構上沉積摻質來源層138,以及(iii)在摻質來源層138上沉積nWFM層136。在下列結構上進行這些製程:(i)在第14A圖至第14D圖的結構上進行這些製程,可導致形成S/D接觸結構120N-120P(如第2A圖至第4D圖所示)而沒有第三襯層140N-140P,(ii)在第15A圖至第15D圖的結構上進行這些製程,可導致形成沒有第三襯層140N-140P的S/D接觸結構120N-120P(如第5A圖至第5D圖所示),以及(iii)在第16A圖至第16D圖的結構上進行這些製程,可導致形成如第5A圖至第5D圖所示之S/D接觸結構120N至120P。
參照第6圖,在操作635中,進行高溫退火製程。舉例而言,可在約500℃至約800℃的溫度範圍內於N2
的環境中使用快速熱退火(rapid thermal annealing, RTA)製程、尖峰退火(spike annealing)製程或、雷射退火(laser annealing)製程長達約100奈秒至約100微秒,對第19A圖至第19D圖的結構進行熱退火製程。參照第2A圖至第2F圖,在熱退火製程之後,如果nWFM矽化物層132N-132P中的摻質原子包括非Zr基的過渡金屬,則摻質原子可具有橫跨線E-E的濃度輪廓250(第19A圖及第19C圖)及橫跨線F-F的濃度輪廓256(第19B圖及第19D圖)。另一方面,參照第3A圖至第3E圖,在對第19A圖至第19D圖的結構進行熱退火製程之後,如果摻雜原子包括Zr金屬,則第20A圖至第20D圖的結構可形成具有沿著線G-G之Zr濃度輪廓358。熱退火製程可提高nWFM矽化物層132N、pWFM矽化物層131、以及界面132N-110N及131-110P的品質(quality),結果降低了nWFM矽化物層132N與S/D區108N之間的接觸電阻以及pWFM矽化物層132P與S/D區108P之間的接觸電阻。
在一些實施例中,在形成nWFM矽化物層132N-132P之後並且在熱退火製程之前,氮化物蓋層(未繪示)可形成於第19A圖至第19D圖的結構上。如第4A圖至第4D圖所示,氮化物蓋層可在隨後的製程中形成氮化物蓋層146N-146P。氮化物蓋層的形成可包括在第19A圖至第19D圖的結構上沉積例如Ti或Ta的金屬層,並使用氨(ammonia, NH3
)氣體在金屬層上進行氮化(nitridation)製程。
參照第6圖,在操作640中,在第一接觸開口及第二接觸開口內形成接觸插塞。舉例而言,如第21A圖至第21D圖所示,在接觸導孔1020N-1020P內形成接觸插塞134N-134P。接觸插塞134N-134P的形成可包括用導電材料填充第19A圖至第19D圖的結構中的接觸開口1020N-1020P並進行CMP製程,以形成第21A圖至第21D圖的結構。CMP製程可使接觸結構120N-120P的頂表面與ILD層118B的頂表面實質上共平面。
在一些實施例中,可藉由填充第20A圖至第20D 圖而非第19A圖至第19D圖之結構中的接觸開口1020N-1020P來形成接觸插塞134N-134P,隨後進行CMP製程以形成第22A圖至第22B圖的結構。在一些實施例中,在用導電材料填充接觸開口1020N-1020P並進行CMP製程之前,可從第19A圖至第19D圖的結構中移除pWFM層140、摻質來源層138、及nWFM層136,以形成第23A圖至第23D圖的結構。
本公開提供具有具有彼此不同的源極/汲極(source/drain, S/D)接觸結構的NFETs(例如,NFET 102N)及PFETs(例如,PFET 102P)的例示性半導體裝置(例如,半導體裝置100)並提供在同一基板上形成這種NFETs及PFETs的例示性方法,具有在S/D區及S/D接觸結構之間減小的接觸電阻。例示性方法在NFETs及PFETs的鰭片結構上形成n型及p型S/D區的陣列。在一些實施例中,由於NFET及PFET S/D區(例如,S/D區108N-108P)是由各自的n型及p型材料所形成,所以NFET及PFET S/D接觸結構(例如,接觸結構 120N-120P)是由彼此不同的矽化物層所形成,以減小S/D接觸結構與S/D區之不同材料之間的接觸電阻。
在一些實施例中,NFET S/D接觸結構是由nWFM矽化物層(例如,nWFM矽化物層132N)所形成,上述nWFM矽化物層具有相較於n型S/D區之價帶能量而言更接近導帶能量的功函數值。相反地,PFET S/D接觸結構是由pWFM矽化物層(例如,pWFM矽化物層131)所形成,上述pWFM矽化物層131具有相較於p型S/D區的導帶能量而言更接近價帶能量的功函數值。在一些實施例中,偶極層(例如,偶極層144)可選擇性地形成於NFETs的S/D區與nWFM矽化物層之間的界面處,以進一步減小n型S/D區與S/D接觸結構之間的SBHs。可藉由用電負值低於nWFM矽化物層之金屬的金屬來摻雜nWFM矽化物層來形成偶極層。金屬摻質可誘發n型S/D區的金屬摻質與半導體元件之間形成偶極。相較於具有相同的NFET及PFET矽化物層且沒有偶極層的半導體裝置,這種選擇性形成位於半導體裝置中的矽化物層及偶極層可將半導體裝置的接觸電阻減小約50%至約70%,因此改善了半導體裝置的性能。
在一些實施例中,一種半導體裝置包括基板;第一鰭片結構及第二鰭片結構,設置於基板上;第一閘極結構及第二閘極結構,分別設置於第一鰭片結構及第二鰭片結構上;第一源極/汲極(source/drain, S/D)區及第二源極/汲極區,分別設置鄰近位於第一鰭片結構及第二鰭片結構上的第一第一閘極結構及第二閘極結構;第一接觸結構及第二接觸結構,分別設置於第一S/D區及第二S/D區上,其中第一接觸結構包括第一n型功函數金屬(n-type work function metal, nWFM)矽化物層及第一接觸插塞,第一nWFM矽化物層設置於第一S/D區上,第一接觸插塞設置於第一nWFM矽化物層上;及偶極層,設置於位於第一nWFM矽化物層及第一S/D區之間的界面處。其中第一接觸結構包括第一n型功函數金屬(n-type work function metal, nWFM)矽化物層及第一接觸插塞,第一nWFM矽化物層設置於第一S/D區上,第一接觸插塞設置於第一nWFM矽化物層上。其中第二接觸結構包括p型功函數金屬(p-type work function metal, pWFM)矽化物層、第二nWFM矽化物層、及第二接觸插塞,pWFM矽化物層設置於第二S/D區上,第二nWFM矽化物層設置於pWFM矽化物層上,第二接觸插塞設置於pWFM矽化物層上。
在一些實施例中,偶極層包括第一nWFM矽化物層的摻質原子及第一S/D區的半導體原子。在一些實施例中,第一nWFM矽化物層包括過渡金屬的多個摻質,且其中該些摻質的濃度輪廓在位於第一nWFM矽化物層與第一S/D區之間的界面處具有峰值濃度。在一些實施例中,第一nWFM矽化物層包括多個金屬摻質,該些金屬摻質的電負值小於位於第一nWFM矽化物層的金屬矽化物中金屬的電負值。在一些實施例中,第一nWFM矽化物層及第二nWFM矽化物層摻雜過渡金屬。在一些實施例中,第一nWFM矽化物層摻雜過渡金屬,且第二nWFM矽化物層為未摻雜的。在一些實施例中,第一接觸結構及第二接觸結構更包括第一襯層及第二襯層,分別沿著第一接觸插塞及第二接觸插塞的側壁,及其中第一襯層及第二襯層包括偶極層的金屬或金屬的氧化物。在一些實施例中,第一接觸結構及該第二接觸結構更包括第一襯層及第二襯層,分別沿著第一接觸插塞及第二接觸插塞的側壁,及其中第一襯層及第二襯層包括該第一nWFM矽化物層的金屬或金屬的氧化物。在一些實施例中,第一接觸結構及該第二接觸結構更包括第一襯層及第二襯層,分別沿著第一接觸插塞及第二接觸插塞的側壁,及其中第一襯層及該第二襯層包括pWFM矽化物層的金屬或金屬的氧化物。在一些實施例中,第一接觸結構及該第二接觸結構更包括第一蓋層及第二蓋層,分別設置於第一nWFM矽化物層及第二nWFM矽化物層上。
在一些實施例中,一種半導體裝置包括第一閘極結構及第二閘極結構,分別設置於第一鰭片結構及第二鰭片結構上;n型源極/汲極(source/drain, S/D)區及p型S/D區,分別設置於第一鰭片結構及第二鰭片結構上;第一接觸結構及第二接觸結構,分別設置於n型S/D區及p型S/D區上;及偶極層,設置於位於三元化合物層及n型S/D區之間的界面處。其中第一接觸結構包括三元化合物層、第一n型功函數金屬(n-type work function metal, nWFM)矽化物層、及第一接觸插塞,三元化合物層設置於n型S/D區上,第一nWFM矽化物層設置於三元化合物層上,第一接觸插塞設置於nWFM矽化物層上。其中第二接觸結構包括p型功函數金屬(p-type work function metal, pWFM)矽化物層、第二nWFM矽化物層、及第二接觸插塞,pWFM矽化物層設置於p型S/D區上,第二nWFM矽化物層設置於pWFM矽化物層上,第二接觸插塞設置於pWFM矽化物層上。
在一些實施例中,三元化合物層包括鋯基(zirconium-based)三元化合物。在一些實施例中,偶極層包括三元化合物層的金屬原子及n型S/D區的半導體原子。在一些實施例中,第一nWFM矽化物層及第二nWFM矽化物層摻雜過渡金屬。在一些實施例中,第一nWFM矽化物層摻雜過渡金屬,且第二nWFM矽化物層為未摻雜的。在一些實施例中,第一接觸結構及第二接觸結構更包括第一襯層及第二襯層,分別沿著第一接觸插塞及第二接觸插塞的側壁,及其中第一襯層及第二襯層包括偶極層、pWFM矽化物層、或第一nWFM矽化物層的金屬。
在一些實施例中,一種半導體裝置的形成方法包括:形成第一鰭片結構及第二鰭片結構於一基板上;分別形成第一源極/汲極(source/drain, S/D)區及第二源極/汲極區於第一鰭片結構及第二鰭片結構上;分別形成第一接觸開口及第二接觸開口於第一S/D區及第二S/D區上。選擇性地形成p型功函數金屬(p-type work function metal, pWFM)矽化物層於第二S/D區上;形成摻雜的n型功函數金屬矽化物層於pWFM矽化物層上及第一S/D區上;形成三元化合物層於摻雜的nWFM矽化物層及第一S/D區之間;及形成第一接觸插塞及第二接觸插塞於第一接觸開口及第二接觸開口內。
在一些實施例中,形成摻雜的nWFM矽化物層的步驟包括沉積摻質來源層於第一S/D區上及pWFM矽化物層上,及其中摻質來源層包括金屬,金屬的電負值小於位於摻雜的nWFM矽化物層的金屬矽化物中的金屬的電負值。在一些實施例中,形成三元化合物層的步驟包括:沉積鋯基(zirconium-based)摻質來源層於第一S/D區上及pWFM矽化物層上;沉積nWFM層於摻質來源層上;及進行退火製程。在一些實施例中,半導體裝置的形成方法更包括沉積氮化物蓋層於摻雜的nWFM矽化物層上。
以上概述數個實施例之特徵,以使本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解,可輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且可在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:半導體裝置
102N:NFET
102P:PFET
104:基板
106N:鰭片結構
106P:鰭片結構
108N:S/D區
108P:S/D區
109N:輕摻雜n型層
109P:輕摻雜p型層
110N:重摻雜n型層
110P:重摻雜p型層
111N:n型蓋層
111P:n型蓋層
112N:閘極結構
112P:閘極結構
114:閘極間隔物
116:淺溝槽隔離區
117:蝕刻停止層
118A:層間介電層
118B:層間介電層
120N:S/D接觸結構
120P:S/D接觸結構
122:界面氧化物層
124:高k閘極介電層
126:功函數金屬層
128:閘極金屬填充層
130:閘極蓋層
131:矽化物層
132N:矽化物層
132P:矽化物層
133:三元化合物層
134N:接觸插塞
134P:接觸插塞
135N:金屬基襯層
135P:金屬基襯層
136:nWFM層
136N:第一襯層
136P:第一襯層
138:摻質來源層
138b:底部
138N:第二襯層
138P:第二襯層
140:pWFM層
140N:第三襯層
140P:第三襯層
142:氮化物層
142N:阻障層
142P:阻障層
144:偶極層
145:偶極層
146N:氮化物蓋層
146P:氮化物蓋層
246:濃度輪廓
248:濃度輪廓
250:濃度輪廓
600:方法
605,610,615,620,625,630,635,640:操作
712N:多晶矽結構
712P:多晶矽結構
1020N:接觸開口
1020P:接觸開口
C1:摻質濃度
C2:摻質濃度
C3:摻質濃度
D1:距離
D2:距離
A-A:線
B-B:線
C-C:線
D-D:線
E-E:線
F-F:線
G-G:線
本揭露的各面向從以下詳細描述中配合附圖可最好地被理解。
第1圖係根據一些實施例,繪示出半導體裝置的等距視圖。
第2A圖至第2D圖、第3A圖至第3D圖、第4A圖至第4D圖、及第5A圖至第5D圖係根據一些實施例,繪示出具有不同接觸結構之半導體裝置的剖面圖。
第2E圖至第2F圖及第3E圖係根據一些實施例,繪示出具有不同接觸結構之半導體裝置的裝置特徵。
第6圖係根據一些實施例,係用於製造具有不同接觸結構之半導體裝置的方法的流程圖。
第7A圖至第7D圖、第8A圖至第8D圖、第9A圖至第9D圖、第10A圖至第10D圖、第11A圖至第11D圖、第12A圖至第12D圖、第13A圖至第13D圖、第14A圖至第14D圖、第15A圖至第15D圖、第16A圖至第16D圖、第17A圖至17D圖、第18A圖至第18D圖、第19A圖至第19D圖、第20A圖至第20D圖、第21A圖至第21D圖、第22A圖至第22D圖、第23A圖至第23D圖根據一些實施例,係在半導體裝置製造製程的各個階段中具有不同接觸結構之半導體裝置的剖面圖。
現在將參考附圖描述說明性實施例。在附圖中,相似的參考數值通常表示相同、功能相似、及/或結構相似的元件。
600:方法
605,610,615,620,625,630,635,640:操作
Claims (12)
- 一種半導體裝置,包括:一基板;一第一鰭片結構及一第二鰭片結構,設置於該基板上;一第一閘極結構及一第二閘極結構,分別設置於該第一鰭片結構及該第二鰭片結構上;一第一源極/汲極(source/drain,S/D)區及一第二源極/汲極區,分別設置鄰近位於該第一鰭片結構及該第二鰭片結構上的該第一閘極結構及該第二閘極結構;一第一接觸結構及一第二接觸結構,分別設置於該第一S/D區及該第二S/D區上,其中該第一接觸結構包括一第一n型功函數金屬(n-type work function metal,nWFM)矽化物層及一第一接觸插塞,該第一nWFM矽化物層設置於該第一S/D區上,該第一接觸插塞設置於該第一nWFM矽化物層上其中該第一nWFM矽化物層包括多個金屬摻質,該些金屬摻質的電負值小於位於該第一nWFM矽化物層的一金屬矽化物中之金屬的電負值,及其中該第二接觸結構包括一p型功函數金屬(p-type work function metal,pWFM)矽化物層、一第二nWFM矽化物層、及一第二接觸插塞,該pWFM矽化物層設置於該第二S/D區上,該第二nWFM矽化物層設置於該pWFM矽化物層上,該第二接觸插塞設置於該pWFM矽化物層上;及一偶極層,設置於位於該第一nWFM矽化物層及該第一S/D區之間的一界面處。
- 如請求項1所述之半導體裝置,其中該偶極層包括該第一nWFM矽化物層的一摻質原子及該第一S/D區的一半導體原子,其中該第一nWFM矽化物層包括多個過渡金屬摻質,且其中該些過渡金屬摻質的濃度輪廓在位於該第一nWFM矽化物層與該第一S/D區之間的界面處具有峰值濃度。
- 如請求項1所述之半導體裝置,其中該第一nWFM矽化物層摻雜過渡金屬,且該第二nWFM矽化物層摻雜過渡金屬或為未摻雜的。
- 如請求項1所述之半導體裝置,其中該第一接觸結構及該第二接觸結構更包括一第一襯層及一第二襯層,分別沿著該第一接觸插塞及該第二接觸插塞的側壁,及其中該第一襯層及該第二襯層包括該偶極層、該第一nWFM矽化物層、或該pWFM矽化物層的金屬或金屬的氧化物。
- 如請求項1至4中任一項所述之半導體裝置,其中該第一接觸結構及該第二接觸結構更包括一第一蓋層及一第二蓋層,分別設置於該第一nWFM矽化物層及該第二nWFM矽化物層上。
- 一種半導體裝置,包括:一第一閘極結構及一第二閘極結構,分別設置於一第一鰭片結構及一第二鰭片結構上;一n型源極/汲極(source/drain,S/D)區及一p型S/D區,分別設置於該第一鰭片結構及該第二鰭片結構上;一第一接觸結構及一第二接觸結構,分別設置於該n型S/D區及該p型S/D區上,其中該第一接觸結構包括一三元化合物層、一第一n型功函數金屬(n-type work function metal,nWFM)矽化物層、及一第一接觸插塞,該三元化合物層設置於該n型S/D區上,該第一nWFM矽化物層設置於該三元化合物層上,該第一接觸插塞設置於該nWFM矽化物層上,及其中該第二接觸結構包括一p型功函數金屬(p-type work function metal,pWFM)矽化物層、一第二nWFM矽化物層、及一第二接觸插塞,該pWFM矽化物層設置於該p型S/D區上,該第二nWFM矽化物層設置於該pWFM矽化物層上,該第二接觸插塞設置於該pWFM矽化物層上;及一偶極層,設置於位於該三元化合物層及該n型S/D區之間的一界面處。
- 如請求項6所述之半導體裝置,其中該三元化合物層包括一鋯基(zirconium-based)三元化合物,其中該偶極層包括該三元化合物層的一金屬原子及該n型S/D區的一半導體原子。
- 如請求項6至7中任一項所述之半導體裝置,其中該第一接觸結構及該第二接觸結構更包括一第一襯層及一第二襯層,分別沿著該第一接觸插塞及該第二接觸插塞的側壁,及其中該第一襯層及該第二襯層包括該偶極層、該pWFM矽化物層、或該第一nWFM矽化物層的金屬。
- 一種半導體裝置的形成方法,包括:形成一第一鰭片結構及一第二鰭片結構於一基板上;分別形成一第一源極/汲極(source/drain,S/D)區及一第二源極/汲極區於該第一鰭片結構及該第二鰭片結構上;分別形成一第一接觸開口及一第二接觸開口於該第一S/D區及該第二S/D區上; 選擇性地形成一p型功函數金屬(p-type work function metal,pWFM)矽化物層於該第二S/D區上;形成一摻雜的n型功函數金屬矽化物層於該pWFM矽化物層上及該第一S/D區上;形成一三元化合物層於該摻雜的nWFM矽化物層及該第一S/D區之間;及形成一第一接觸插塞及一第二接觸插塞於該第一接觸開口及該第二接觸開口內。
- 如請求項9所述之半導體裝置的形成方法,其中形成該摻雜的nWFM矽化物層的步驟包括沉積一摻質來源層於該第一S/D區上及該pWFM矽化物層上,及其中該摻質來源層包括一金屬,該金屬的電負值小於位於該摻雜的nWFM矽化物層的一金屬矽化物中的一金屬的電負值。
- 如請求項9所述之半導體裝置的形成方法,其中形成該三元化合物層的步驟包括:沉積一鋯基(zirconium-based)摻質來源層於該第一S/D區上及該pWFM矽化物層上;沉積一nWFM層於該摻質來源層上;及進行退火製程。
- 如請求項9至11中任一項所述之半導體裝置的形成方法,更包括沉積一氮化物蓋層於該摻雜的nWFM矽化物層上。
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