CN108074820A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN108074820A
CN108074820A CN201610990039.1A CN201610990039A CN108074820A CN 108074820 A CN108074820 A CN 108074820A CN 201610990039 A CN201610990039 A CN 201610990039A CN 108074820 A CN108074820 A CN 108074820A
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China
Prior art keywords
layer
source
metal
contact layer
substrate
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CN201610990039.1A
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English (en)
Inventor
李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201610990039.1A priority Critical patent/CN108074820A/zh
Priority to EP17200581.1A priority patent/EP3327753A1/en
Priority to US15/809,120 priority patent/US10121700B2/en
Publication of CN108074820A publication Critical patent/CN108074820A/zh
Pending legal-status Critical Current

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Abstract

一种半导体器件及其形成方法，包括：提供基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区；在所述源漏掺杂区上形成氧化层；在所述氧化层上形成金属层；对所述金属层进行反应退火处理，使得所述金属层与所述源漏掺杂区的材料相互扩散且发生化学反应，在所述源漏掺杂区上形成金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。本发明减小了金属接触层与源漏掺杂区之间的接触电阻，从而降低所述半导体器件的寄生外接电阻，改善形成的半导体器件的电学性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造技术领域，特别涉及一种半导体器件及其形成方法。
背景技术
随着半导体器件集成度不断增大，半导体器件相关的临界尺寸不断减小，相应的出现了很多问题，如器件漏源区的表面电阻和接触电阻相应增加，导致器件的响应速度降低，信号出现延迟。因此，低电阻率的互连结构成为制造高集成度半导体器件的一个关键要素。
为了降低器件漏源掺杂区的接触电阻，在所述源漏掺杂区上形成金属接触层，所述金属接触层的材料为金属硅化物。所述金属硅化物具有较低的电阻率，可以显著减小漏源极的接触电阻。金属硅化物和自对准金属硅化物及形成工艺已被广泛地用于降低器件源极和漏极的表面电阻和接触电阻，从而降低电阻电容延迟时间。
然而，现有技术形成的半导体器件的电学性能仍有待提高。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，改善形成的半导体器件的电学性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区；在所述源漏掺杂区上形成氧化层；在所述氧化层上形成金属层；对所述金属层进行反应退火处理，使得所述金属层与所述源漏掺杂区的材料相互扩散且发生化学反应，在所述源漏掺杂区上形成金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
可选的，形成所述氧化层的方法包括：对所述源漏掺杂区进行氧化处理，形成所述氧化层。
可选的，采用化学溶液浸润的方法，进行所述氧化处理。
可选的，所述氧化处理的工艺参数包括：采用硫酸和双氧水的混合溶液对所述源漏掺杂区进行浸润处理，硫酸和双氧水的体积比为1:1～1:5，混合溶液温度为120℃～180℃。
可选的，所述氧化处理的工艺参数包括：采用氨水和双氧水的混合溶液对所述源漏掺杂区进行浸润处理，氨水和双氧水的体积比为1:4～1:15，混合溶液温度为25℃～45℃。
可选的，所述氧化层的材料为氧化硅；所述氧化层的厚度为5埃～30埃。
可选的，所述金属层的材料为钛。
可选的，所述第一金属接触层的材料为硅化钛；所述金属含氧接触层的材料为硅氧化钛；所述第二金属接触层的材料为硅化钛。
可选的，在形成所述氧化层之前，还包括：在所述栅极结构露出的基底上以及栅极结构顶部上形成介质层；刻蚀所述介质层形成贯穿所述介质层的通孔，所述通孔底部露出源漏掺杂区部分表面或者全部表面；在形成所述氧化层的工艺步骤中，在所述通孔底部暴露出的源漏掺杂区上形成所述氧化层。
可选的，在形成所述金属层的工艺步骤中，还在所述通孔侧壁以及介质层顶部形成所述金属层；形成的所述金属接触层位于所述通孔露出的源漏掺杂区上。
可选的，在形成所述通孔之后，还包括：形成填充满所述通孔的导电插塞，所述导电插塞与所述金属接触层电连接。
可选的，在形成所述金属层之后、形成所述导电插塞之前，还包括：刻蚀所述介质层形成开口，所述开口底部露出栅极结构顶部。
可选的，在形成所述导电插塞的工艺步骤中，还形成填充满所述开口的栅极插塞，所述栅极插塞与所述栅极结构电连接。
可选的，所述介质层包括层间介质层以及位于所述层间介质层以及栅极结构顶部上的上层介质层，其中，所述层间介质层顶部与所述栅极结构顶部齐平或者低于栅极结构顶部；采用后栅工艺形成所述栅极结构，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述基底上形成伪栅以及位于所述伪栅侧壁上的侧墙；在所述伪栅两侧的基底内形成源漏掺杂区；在所述伪栅露出的基底上形成层间介质层，且所述层间介质层暴露出所述伪栅顶部；去除所述伪栅；在所述伪栅所在的位置处形成所述栅极结构。
可选的，采用先栅工艺形成所述栅极结构，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述基底上形成所述栅极结构以及位于栅极结构侧壁上的侧墙；在所述栅极结构两侧的基底内形成源漏掺杂区。
可选的，在进行所述反应退火处理之后，还包括：在所述栅极结构露出的基底上以及所述栅极结构顶部上形成介质层；刻蚀所述介质层形成贯穿所述介质层的通孔，所述通孔底部露出所述第二金属接触层表面；形成填充满所述通孔的导电插塞。
可选的，形成的所述半导体器件为NMOS器件、PMOS器件或者CMOS器件。
可选的，所述基底包括：衬底；位于所述衬底上的分立的鳍部；所述鳍部露出的衬底上的隔离结构，所述隔离结构覆盖鳍部的部分侧壁，且所述隔离结构顶部低于鳍部顶部。
可选的，所述基底为平面衬底。
本发明还提供一种半导体器件，包括：基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区；位于所述源漏掺杂区上的金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
可选的，所述第一金属接触层的材料为硅化钛；所述金属含氧接触层的材料为硅氧化钛；所述第二金属接触层的材料为硅化钛。
与现有技术相比，本发明的技术方案具有以下优点：
本发明提供的半导体器件的形成方法的技术方案中，在形成金属层之前，在源漏掺杂区上形成氧化层；在所述氧化层上形成金属层；对所述金属层进行反应退火处理，使得所述金属层与所述源漏掺杂区的材料相互扩散且发生化学反应，在所述源漏掺杂区上形成金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。在所述反应退火处理过程中，由于所述氧化层对所述金属层与源漏掺杂区的材料相互扩散起到一定的阻挡作用，使得形成金属接触层的速率较慢，从而提高了形成的金属接触层的厚度均匀性，有利于降低形成的金属接触层的电阻；同时，由于形成的金属接触层包括位于第一金属接触层以及第二金属接触层之间的金属含氧接触层，使得所述金属接触层中具有偶极子(dipole)，所述偶极子有利于降低所述金属接触层与源漏掺杂区之间的肖特基势垒高度，从而减小所述金属接触层与所述源漏掺杂区之间的接触电阻，进而降低形成的半导体器件的寄生外接电阻。因此，本发明改善了形成的半导体器件的电学性能。
可选方案中，采用化学溶液浸润的方法，对所述源漏掺杂区进行氧化处理，形成所述氧化层，使得形成的氧化层的厚度可控性好，且所述氧化层的致密性适中，后续在反应退火处理过程中，所述金属层与所述源漏掺杂区中的材料可以经由所述氧化层进行相互扩散且发生化学反应。
附图说明
图1至图8为本发明一实施例提供的半导体器件形成过程的剖面结构示意图。
具体实施方式
由背景技术可知，现有技术形成的半导体器件的电学性能有待提高。
寄生外接电阻(Rext，parasitic external resistance)大是影响半导体器件电学性能的主要原因之一，特别是对于FinFET器件而言，随着器件节点尺寸不断减小，寄生外接电阻造成的不良影响越来越显著。
经分析，寄生外接电阻的主要贡献来自与金属接触层与源漏掺杂区之间的接触电阻；且所述接触电阻与所述源漏掺杂区与金属接触层之间的肖特基势垒高度(SBH，Schottky Barrier Height)有关。当所述源漏掺杂区与金属接触层之间的肖特基势垒高度降低时，金属接触层与所述源漏掺杂区之间的接触电阻减小，相应的所述半导体器件的寄生外接电阻也将减小。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区；在所述源漏掺杂区上形成氧化层；在所述氧化层上形成金属层；对所述金属层进行反应退火处理，使得所述金属层与所述源漏掺杂区的材料相互扩散且发生化学反应，在所述源漏掺杂区上形成金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
本发明降低了金属接触层与所述源漏掺杂区之间的肖特基势垒高度，减小了金属接触层与所述源漏掺杂区之间的接触电阻，从而降低了半导体器件的寄生外接电阻，改善了形成的半导体器件的电学性能。为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图8为本发明一实施例提供的半导体器件形成过程的剖面结构示意图。
本实施例中，以采用后栅工艺(gate last)形成所述栅极结构作为示例进行详细说明。
参考图1，提供基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区。
本实施例中，以形成的半导体器件为FinFET器件为例，所述基底包括：衬底101；位于所述衬底101上的分立的鳍部102；位于所述鳍部102露出的衬底101上的隔离结构103，所述隔离结构103覆盖鳍部102的部分侧壁，且所述隔离结构103顶部低于鳍部102顶部。
在其他实施例中，所述半导体器件还可以为平面器件，所述基底为平面衬底。
所述衬底101的材料为硅、锗、锗化硅、碳化硅、砷化镓或镓化铟，所述衬底101还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底；所述鳍部102的材料包括硅、锗、锗化硅、碳化硅、砷化镓或镓化铟。本实施例中，所述衬底101为硅衬底，所述鳍部102的材料为硅。
所述隔离结构103起到电隔离相邻鳍部102的作用，所述隔离结构103的材料为绝缘材料，例如为氧化硅、氮化硅、氮氧化硅或碳氮氧化硅。本实施例中，所述隔离结构103的材料为氧化硅。
以形成的半导体器件为CMOS器件为例，所述衬底101包括NMOS区域I和PMOS区域II，所述NMOS区域I为形成NMOS管提供工艺平台，所述PMOS区域II为形成PMOS管提供工艺平台。在另一实施例中，所述衬底还能够仅包括PMOS区域或NMOS区域，相应形成的FinFET器件为PMOS管或NMOS管。
需要说明的是，在其他实施例中，形成的半导体器件还可以为NMOS器件或者PMOS器件。
所述栅极结构位于所述隔离结构103上且横跨所述鳍部102，且所述栅极结构覆盖鳍部102的部分顶部和侧壁。本实施例中，所述栅极结构包括：位于NMOS区域I的第一栅极结构以及位于PMOS区域II的第二栅极结构。
其中，所述第一栅极结构包括第一高k栅介质层111以及位于所述第一高k栅介质层111上的第一栅电极层113；所述第二栅极结构包括第二高k栅介质层121以及位于所述第二高k栅介质层121上的第二栅电极层123。
所述第一高k栅介质层111以及第二高k栅介质层121的材料为高k栅介质材料，其中，高k栅介质材料指的是，相对介电常数大于氧化硅相对介电常数的栅介质材料，所述高k栅介质材料为HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2或Al2O3。所述第一栅电极层113的材料为Cu、Al或W；所述第二栅电极层123的材料为Cu、Al或W。
需要说明的是，为了调节NMOS管和PMOS管的阈值电压，所述第一高k栅介质层111与所述第一栅电极层113之间还可以形成有N型功函数层112，所述第二高k栅介质层121与所述第二栅电极层123之间还可以形成有P型功函数层122。在所述第一高k栅介质层111与所述基底之间、以及所述第二高k栅介质层121与所述基底之间还可以形成有界面层，改善第一高k栅介质层111与所述基底之间、以及第二高k栅介质层121与所述基底之间的界面性能。所述界面层的材料为氧化硅。
所述侧墙200的材料为氮化硅、氧化硅或氮氧化硅。本实施例中，所述侧墙200的材料为氮化硅。
所述源漏掺杂区包括：位于第一栅极结构两侧的NMOS区域I基底内的第一源漏掺杂区211，其中，所述第一源漏掺杂区211位于所述NMOS区域I鳍部102内，所述第一源漏掺杂区211的掺杂离子为N型离子，例如为P、As或Sb；位于所述第二栅极结构两侧的PMOS区域II基底内的第二源漏掺杂区212，其中，所述第二源漏掺杂区212位于所述PMOS区域II鳍部102内，所述第二源漏掺杂区212的掺杂离子为P型离子，例如为B、Ga或In。
本实施例中，为了提高形成的半导体器件的运行速率，形成所述第一源漏掺杂区211的工艺步骤包括：刻蚀所述第一栅极结构两侧的部分厚度的鳍部102，在所述第一栅极结构两侧的鳍部102内形成第一凹槽；形成填充满所述第一凹槽的第一应力层，所述第一应力层的材料为SiC或SiCP；在形成所述第一应力层的工艺过程中，对所述第一应力层进行原位掺杂，形成所述第一源漏掺杂区211；或者，在形成所述第一应力层之后，对所述第一应力层进行掺杂处理，形成所述第一源漏掺杂区211。
形成所述第二源漏掺杂区212的工艺步骤包括：刻蚀所述第二栅极结构两侧的部分厚度的鳍部102，在所述第二栅极结构两侧的鳍部102内形成第二凹槽；形成填充满所述第二凹槽的第二应力层，所述第二应力层的材料为SiGe或SiGeB；在形成所述第二应力层的工艺过程中，对所述第二应力层进行原位掺杂，形成所述第二源漏掺杂区212；或者，在形成所述第二应力层之后，对所述第二应力层进行掺杂处理，形成所述第二源漏掺杂区212。
本实施例中，还在所述栅极结构露出的基底上形成层间介质层104，且所述层间介质层104露出所述栅极结构顶部。本实施例中，所述层间介质层104的材料为氧化硅。在其他实施例中，所述层间介质层的材料还可以为氮化硅或氮氧化硅。
具体地，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述NMOS区域I隔离结构103上形成横跨鳍部102的第一伪栅；在所述PMOS区域II隔离结构103上形成横跨鳍部102的第二伪栅；在所述第一伪栅侧壁以及第二伪栅侧壁上形成侧墙200；在所述第一伪栅两侧的NMOS区域I基底内形成所述第一源漏掺杂区211；在所述第二伪栅两侧的PMOS区域II基底内形成所述第二源漏掺杂区212；在所述第一伪栅以及第二伪栅露出的基底上形成层间介质层104，所述层间介质层104位于所述第一源漏掺杂区211以及第二源漏掺杂区212上，且所述层间介质层104露出所述第一伪栅顶部以及第二伪栅顶部；去除所述第一伪栅；在所述第一伪栅所在位置形成第一栅极结构；去除所述第二伪栅，在所述第二伪栅所在位置形成第二栅极结构。
需要说明的是，在其他实施例中，还可以采用先栅工艺(gate first)形成所述栅极结构。在形成所述源漏掺杂区之前，在所述基底上形成栅极结构、以及位于所述栅极结构侧壁上的侧墙；在所述栅极结构两侧的基底内形成所述源漏掺杂区。具体地，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述NMOS区域基底上形成第一栅极结构；在所述PMOS区域基底上形成第二栅极结构；在所述第一栅极结构侧壁以及第二栅极结构侧壁上形成侧墙；在所述第一栅极结构两侧的NMOS区域基底内形成第一源漏掺杂区；在所述第二栅极结构两侧的PMOS区域基底内形成第二源漏掺杂区。
后续的工艺步骤还包括：在栅极结构露出的基底上以及栅极结构顶部上形成介质层。采用先栅工艺形成栅极结构，且在形成所述源漏掺杂区以及栅极结构之后，直接在所述栅极结构露出的基底上以及栅极结构顶部上形成介质层，所述介质层为单层结构；所述介质层还可以为双层结构，包括位于基底上的层间介质层以及位于所述层间介质层上的上层介质层，所述层间介质层顶部与所述栅极结构顶部齐平，且所述层间介质层的材料致密度大于上层介质层的材料致密度。
参考图2及图3，在所述层间介质层104上以及栅极结构顶部上形成上层介质层105，所述层间介质层104以及位于所述层间介质层104上的上层介质层105构成介质层，所述介质层位于所述栅极结构露出的基底上以及所述栅极结构顶部上；刻蚀所述介质层形成贯穿所述介质层的通孔106，所述通孔106底部露出所述源漏掺杂区部分表面或者全部表面。
所述上层介质层105的材料为氧化硅、氮化硅或氮氧化硅；采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺，形成所述上层介质层105。
本实施例中，采用化学气相沉积工艺形成所述上层介质层105，所述上层介质层105的材料为氧化硅。
所述通孔106为后续形成与所述源漏掺杂区电连接的导电插塞提供工艺基础，此外，所述通孔106还为后续形成与所述源漏掺杂区电连接的金属接触层提供工艺基础。
所述通孔106暴露出第一源漏掺杂区211部分表面或全部表面，所述通孔106还暴露出第二源漏掺杂区212部分表面或全部表面。
本实施例中，为了避免形成的通孔106与所述第一栅极结构侧壁或者第二栅极结构侧壁发生电连接，所述通孔106暴露出所述源漏掺杂区的部分表面。具体地，所述通孔106暴露出部分第一源漏掺杂区211表面以及部分第二源漏掺杂区212表面。
在其他实施例中，所述通孔还可以暴露出所述源漏掺杂区的全部表面。
形成所述通孔106的工艺步骤包括：在所述上层介质层105上形成第一光刻胶层107，所述第一光刻胶层107定义出待形成的通孔106的位置和尺寸；以所述第一光刻胶层107为掩膜，刻蚀所述上层介质层105以及层间介质层104，形成贯穿所述介质层的通孔106，且所述通孔106底部露出所述第一源漏掺杂区211表面以及第二源漏掺杂区212表面。
本实施例中，为了保证所述通孔106暴露出所述源漏掺杂区表面，在刻蚀所述介质层的工艺步骤中，还对所述源漏掺杂区进行过刻蚀。
在形成所述通孔106之后，去除所述第一光刻胶层107。
参考图4，在所述上层介质层105中形成暴露出所述栅极结构顶部的开口108。
具体地，所述开口108暴露出所述第一栅极结构顶部，且暴露出所述第一栅极结构中的第一栅电极层113顶部；所述开口108还暴露出所述第二栅极结构顶部，且暴露出所述第二栅极结构中的第二栅电极层123顶部。
所述开口108为后续形成与所述栅极结构电连接的栅极插塞提供工艺基础。
形成所述开口108的工艺步骤包括：在所述上层介质层105上形成第二光刻胶层109，所述第二光刻胶层109定义出待形成的开口108的位置和尺寸；以所述第二光刻胶层109为掩膜刻蚀所述上层介质层105，形成贯穿所述上层介质层105的开口108，且所述开口108底部露出栅极结构顶部。
在形成所述开口108之后，去除所述第二光刻胶层109。
参考图5，在所述源漏掺杂区上形成氧化层201。
本实施例中，在所述通孔106底部露出的源漏掺杂区上形成所述氧化层201。具体地，在所述通孔106底部露出的第一源漏掺杂区211上、以及所述通孔106底部露出的第二源漏掺杂区212上形成所述氧化层201。
对所述源漏掺杂区进行氧化处理，形成所述氧化层201。其好处包括，采用氧化处理形成的氧化层201与所述源漏掺杂区之间的界面性能好，有利于提高后续形成的金属接触层的质量。
本实施例中，所述氧化层201的材料为氧化硅。
所述氧化层201的厚度不宜过薄，也不宜过厚。若所述氧化层201的厚度过薄，后续形成的金属含氧接触层厚度较薄，且所述金属含氧接触层中的氧含量少，对半导体器件的接触电阻的改善有限；若所述氧化层201的厚度过厚，后续在反应退火处理过程中，金属层与所述源漏掺杂区的材料相互扩散难度增加。
为此，本实施例中，所述氧化层201的厚度为5埃～30埃。
本实施例中，采用化学溶液浸润的方法，进行所述氧化处理，在所述源漏掺杂区上形成氧化层201，使得形成所述氧化层201工艺过程中的厚度可控性强。
本实施例中，所述氧化处理的工艺参数包括：采用硫酸和双氧水的混合溶液对所述源漏掺杂区进行浸润处理，硫酸和双氧水的体积比为1:1～1:5，混合溶液温度为120℃～180℃。
在其他实施例中，所述氧化处理的工艺参数还可以包括：采用氨水和双氧水的混合溶液对所述源漏掺杂区进行浸润处理，氨水和双氧水的体积比为1:4～1:15，混合溶液温度为25℃～45℃。
需要说明的是，在形成所述氧化层201的工艺步骤中，所述氧化处理对所述第一栅极结构顶部以及第二栅极结构顶部的氧化能力弱甚至可以忽略不计，因此避免了对所述第一栅电极层113顶部以及第二栅电极层123顶部造成不必要的氧化。
参考图6，在所述氧化层201上形成金属层202。
本实施例中，在形成所述金属层202的工艺步骤中，还在所述通孔106侧壁以及介质层顶部形成金属层202，且还在所述开口108顶部和侧壁上形成金属层202。
所述金属层202为后续形成第一金属接触层、金属含氧接触层以及第二金属接触层提供金属原子。
所述金属层202的材料为Ni、W、Ti、Ta、Pt或Co中的一种或多种；所述金属层202的形成工艺为物理气相沉积、金属溅射或者原子层沉积。
本实施例中，所述金属层202的材料为Ti，所述金属层202的厚度为50埃～200埃。
采用Ti作为所述金属层202的材料，在后续进行了反应退火处理之后，无需去除未发生化学反应的金属层202，因此金属层202可以保留在所述开口108底部和侧壁上，从而节约了工艺步骤；此外，位于所述开口108底部和侧壁上的金属层202还可以起到粘附层的作用；位于所述通孔106侧壁上的金属层202也可以起到粘附层的作用。
本实施例中，为了防止所述金属层202的材料为环境中的O2所氧化，在形成所述金属层202之后，还在所述金属层202上形成保护层20，所述保护层20使得所述金属层202与O2隔绝开；所述保护层20的材料为TiN或TaN。
在后续形成导电插塞的工艺步骤中，所述保护层20还可以起到粘附层的作用。
参考图7，对所述金属层202进行反应退火处理203，使得所述金属层202与所述源漏掺杂区的材料相互扩散且发生化学反应，在所述源漏掺杂区上形成金属接触层204，所述金属接触层204包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
本实施例中，所述金属接触层204用于降低所述半导体器件的接触电阻；所述第一金属接触层位于所述通孔106暴露出的源漏掺杂区上，具体的，所述第一金属层位于所述通孔106暴露出的第一源漏掺杂区211以及第二源漏掺杂区212上。
以所述金属层202的材料为Ti为例，在所述反应退火处理203过程中，所述金属层202中的Ti离子经由所述氧化层201扩散至所述源漏掺杂区内，所述源漏掺杂区内的Si离子与所述Ti离子发生反应形成TiSi；且所述源漏掺杂区中的Si离子经由所述氧化层201(参考图6)扩散至所述金属层202中，所述金属层202中的Ti离子与所述Si离子发生反应形成TiSi；同时，所述金属层202中的Ti离子以及所述源漏掺杂区中的Si离子扩散至所述氧化层201中，使得所述氧化层201转化为金属含氧接触层。
在所述反应退火处理过程中，由于所述氧化层201的阻挡作用，使得所述反应退火处理203过程中的化学反应速率减小，从而减小了形成金属接触层204的速率，使得形成的金属接触层204的厚度更为均匀，进而使得所述金属接触层204起到的降低半导体器件的接触电阻的效果更好。
本实施例中，形成的金属接触层204包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层，其中，所述第一金属接触层的材料为硅化钛，所述金属含氧接触层的材料为硅氧化钛，所述第二金属接触层的材料为硅化钛。在所述第一金属接触层与第二金属接触层之间形成有金属含氧接触层，使得形成的金属接触层中具有偶极子，所述偶极子有利于降低所述金属接触层与源漏掺杂区之间的肖特基势垒高度，从而减小所述金属接触层与所述源漏掺杂区之间的接触电阻，进而降低形成的半导体器件的寄生外接电阻。
此外，由于所述源漏掺杂区上形成有氧化层201，所述氧化层201起到阻止在所述源漏掺杂区上形成自然氧化物(native oxide)的作用，从而提高工艺余裕度，使得形成所述氧化层201的工艺与形成金属层202的工艺之间可以等待的工艺时长更长。
采用激光退火、尖峰退火或者毫秒退火进行所述反应退火处理。本实施例中，采用激光退火进行所述反应退火处理，所述反应退火处理的退火温度不宜过低，也不宜过高。如果所述反应退火处理的退火温度过低，则形成的金属接触层204的硅化程度较低，所述金属接触层204的电阻率高；如果所述反应退火处理的退火温度过高，则所述金属接触层204在高温下性能发生变化，形成的金属接触层204的质量差。
为此，本实施例中，采用激光退火工艺进行所述反应退火处理，退火温度为800℃～880℃，例如为800℃、850℃、880℃。
在所述反应退火处理203之后，位于所述通孔106侧壁上的金属层202以及保护层20被保留，在后续形成填充满所述通孔106的导电插塞时，位于所述通孔106侧壁上的金属层202以及保护层20起到提高导电插塞与介质层之间粘附性的作用。在所述反应退火处理203之后，位于所述开口108底部和侧壁上的金属层202以及保护层20也被保留，在后续形成填充满所述开口108的栅极插塞时，位于所述开口108侧壁上的金属层202以及保护层20起到提高栅极插塞与所述介质层之间的粘附性的作用。
参考图8，在进行所述反应退火处理203(参考图7)之后，在所述第二金属接触层上形成填充满所述通孔106(参考图7)的导电插塞205。
本实施例中，在形成所述导电插塞205的工艺步骤中，还形成填充满所述开口108(参考图7)的栅极插塞206，所述栅极插塞206与所述第一栅极结构电连接，所述栅极插塞206还与所述第二栅极结构电连接。
所述导电插塞205的材料包括铜、铝或钨。本实施例中，所述导电插塞205的材料为钨。
形成所述导电插塞205的工艺步骤包括：形成填充满所述通孔106以及开口108的导电膜，所述导电膜还位于所述介质层顶部上；采用平坦化工艺，去除高于所述介质层顶部的导电膜，形成填充满所述通孔106的导电插塞205以及填充满所述开口108的栅极插塞206。
在所述平坦化工艺过程中，还去除位于所述介质层顶部上的保护层20以及金属层203。
需要说明的是，本实施例中以后栅工艺形成栅极结构为例，在其他实施例中，还可以采用先栅工艺形成所述栅极结构，相应的，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述基底上形成栅极结构以及位于栅极结构侧壁上的侧墙；在所述栅极结构两侧的基底内形成源漏掺杂区。
还需要说明的是，本实施例中，在形成与所述源漏掺杂区电连接的通孔之后、形成所述氧化层以及金属层；在其他实施例中，还可以先形成所述氧化层以及金属层、后形成与所述源漏掺杂区电连接的通孔；具体的，在进行所述反应退火处理之后，还包括：在所述栅极结构露出的基底上以及所述栅极结构顶部上形成介质层；刻蚀所述介质层形成贯穿所述介质层的通孔，所述通孔底部露出所述第二金属接触层表面；形成填充满所述通孔的导电插塞。
相应的，本发明还提供一种半导体器件，参考图8，所述半导体器件包括：
基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙200，所述栅极结构两侧的基底内具有源漏掺杂区；
位于所述源漏掺杂区上的金属接触层204，所述金属接触层204包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
以下将结合附图对本发明实施例提供的半导体器件进行详细说明。
本实施例中，所述基底包括：衬底101；位于所述衬底101上的分立的鳍部102；位于所述鳍部102露出的衬底101上的隔离结构103，所述隔离结构103覆盖鳍部102的部分侧壁，且所述隔离结构103顶部低于鳍部102顶部。
所述栅极结构位于所述隔离结构103上且横跨所述鳍部102，且所述栅极结构覆盖鳍部102的部分顶部和侧壁。
以半导体器件为CMOS器件为例，所述基底包括NMOS区域I和PMOS区域II。相应的，所述栅极结构包括：位于NMOS区域I的第一栅极结构以及位于NPMOS区域II的第二栅极结构。
其中，所述第一栅极结构包括第一高k栅介质层111以及位于所述第一高k栅介质层111上的第一栅电极层113；所述第二栅极结构包括第二高k栅介质层121以及位于所述第二高k栅介质层121上的第二栅电极层123。
所述第一高k栅介质层111与所述第一栅电极层113之间还可以形成有N型功函数层112，所述第二高k栅介质层121与所述第二栅电极层123之间还可以形成有P型功函数层122。
所述源漏掺杂区包括：位于第一栅极结构两侧的NMOS区域I基底内的第一源漏掺杂区211，其中，所述第一源漏掺杂区211位于所述NMOS区域I鳍部102内；位于所述第二栅极结构两侧的PMOS区域II基底内的第二源漏掺杂区212，其中，所述第二源漏掺杂区212位于所述PMOS区域II鳍部102内。
本实施例中，所述半导体器件还包括：位于所述栅极结构露出的基底上的层间介质层104，且所述层间介质层104露出所述栅极结构顶部。
所述第一金属接触层的材料为硅化钛，所述金属含氧接触层的材料为硅氧化钛，所述第二金属接触层的材料为硅化钛。在所述第一金属接触层与第二金属接触层之间具有金属含氧接触层，使得金属接触层中具有偶极子，所述偶极子有利于降低所述金属接触层与源漏掺杂区之间的肖特基势垒高度，从而减小所述金属接触层与所述源漏掺杂区之间的接触电阻，进而降低半导体器件的寄生外接电阻。
本实施例中，所述半导体器件还包括：位于所述层间介质层104上以及栅极结构顶部上的上层介质层105；贯穿所述上层介质层105以及层间介质层104的导电插塞205，所述导电插塞205与所述金属接触层204电连接；贯穿所述上层介质层105的栅极插塞206，所述栅极插塞206与所述栅极结构电连接。虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区；
在所述源漏掺杂区上形成氧化层；
在所述氧化层上形成金属层；
对所述金属层进行反应退火处理，使得所述金属层与所述源漏掺杂区的材料相互扩散且发生化学反应，在所述源漏掺杂区上形成金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
2.如权利要求1所述的半导体器件的形成方法，其特征在于，形成所述氧化层的方法包括：对所述源漏掺杂区进行氧化处理，形成所述氧化层。
3.如权利要求2所述的半导体器件的形成方法，其特征在于，采用化学溶液浸润的方法，进行所述氧化处理。
4.如权利要求3所述的半导体器件的形成方法，其特征在于，所述氧化处理的工艺参数包括：采用硫酸和双氧水的混合溶液对所述源漏掺杂区进行浸润处理，硫酸和双氧水的体积比为1:1～1:5，混合溶液温度为120℃～180℃。
5.如权利要求3所述的半导体器件的形成方法，其特征在于，所述氧化处理的工艺参数包括：采用氨水和双氧水的混合溶液对所述源漏掺杂区进行浸润处理，氨水和双氧水的体积比为1:4～1:15，混合溶液温度为25℃～45℃。
6.如权利要求1所述的半导体器件的形成方法，其特征在于，所述氧化层的材料为氧化硅；所述氧化层的厚度为5埃～30埃。
7.如权利要求1所述的半导体器件的形成方法，其特征在于，所述金属层的材料为钛。
8.如权利要求7所述的半导体器件的形成方法，其特征在于，所述第一金属接触层的材料为硅化钛；所述金属含氧接触层的材料为硅氧化钛；所述第二金属接触层的材料为硅化钛。
9.如权利要求1所述的半导体器件的形成方法，其特征在于，在形成所述氧化层之前，还包括：在所述栅极结构露出的基底上以及栅极结构顶部上形成介质层；刻蚀所述介质层形成贯穿所述介质层的通孔，所述通孔底部露出源漏掺杂区部分表面或者全部表面；在形成所述氧化层的工艺步骤中，在所述通孔底部暴露出的源漏掺杂区上形成所述氧化层。
10.如权利要求9所述的半导体器件的形成方法，其特征在于，在形成所述金属层的工艺步骤中，还在所述通孔侧壁以及介质层顶部形成所述金属层；形成的所述金属接触层位于所述通孔露出的源漏掺杂区上。
11.如权利要求10所述的半导体器件的形成方法，其特征在于，在形成所述通孔之后，还包括：形成填充满所述通孔的导电插塞，所述导电插塞与所述金属接触层电连接。
12.如权利要求10所述的半导体器件的形成方法，其特征在于，在形成所述金属层之后、形成所述导电插塞之前，还包括，刻蚀所述介质层形成开口，所述开口底部露出栅极结构顶部；在形成所述导电插塞的工艺步骤中，还形成填充满所述开口的栅极插塞，所述栅极插塞与所述栅极结构电连接。
13.如权利要求9所述的半导体器件的形成方法，其特征在于，所述介质层包括层间介质层以及位于所述层间介质层以及栅极结构顶部上的上层介质层，其中，所述层间介质层顶部与所述栅极结构顶部齐平或者低于栅极结构顶部；
采用后栅工艺形成所述栅极结构，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述基底上形成伪栅以及位于所述伪栅侧壁上的侧墙；在所述伪栅两侧的基底内形成源漏掺杂区；在所述伪栅露出的基底上形成层间介质层，且所述层间介质层暴露出所述伪栅顶部；去除所述伪栅；在所述伪栅所在的位置处形成所述栅极结构。
14.如权利要求9所述的半导体器件的形成方法，其特征在于，采用先栅工艺形成所述栅极结构，形成所述栅极结构以及源漏掺杂区的工艺步骤包括：在所述基底上形成所述栅极结构以及位于栅极结构侧壁上的侧墙；在所述栅极结构两侧的基底内形成源漏掺杂区。
15.如权利要求1所述的半导体器件的形成方法，其特征在于，在进行所述反应退火处理之后，还包括：在所述栅极结构露出的基底上以及所述栅极结构顶部上形成介质层；刻蚀所述介质层形成贯穿所述介质层的通孔，所述通孔底部露出所述第二金属接触层表面；形成填充满所述通孔的导电插塞。
16.如权利要求1所述的半导体器件的形成方法，其特征在于，形成的所述半导体器件为NMOS器件、PMOS器件或者CMOS器件。
17.如权利要求1所述的半导体器件的形成方法，其特征在于，所述基底包括：衬底；位于所述衬底上的分立的鳍部；所述鳍部露出的衬底上的隔离结构，所述隔离结构覆盖鳍部的部分侧壁，且所述隔离结构顶部低于鳍部顶部。
18.如权利要求1所述的半导体器件的形成方法，其特征在于，所述基底为平面衬底。
19.一种半导体器件，其特征在于，包括：
基底，所述基底上具有栅极结构以及位于所述栅极结构侧壁上的侧墙，所述栅极结构两侧的基底内具有源漏掺杂区；
位于所述源漏掺杂区上的金属接触层，所述金属接触层包括第一金属接触层、位于所述第一金属接触层上的金属含氧接触层、以及位于所述金属含氧接触层上的第二金属接触层。
20.如权利要求19所述的半导体器件，其特征在于，所述第一金属接触层的材料为硅化钛；所述金属含氧接触层的材料为硅氧化钛；所述第二金属接触层的材料为硅化钛。
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