WO2017052610A1

WO2017052610A1 - Techniques for bottom-up filling of three-dimensional semiconductor device topographies

Info

Publication number: WO2017052610A1
Application number: PCT/US2015/052304
Authority: WO
Inventors: Grant M. Kloster; Florian Gstrein; Scott B. Clendenning; Rami HOURANI; Kent N. FRASURE
Original assignee: Intel Corporation
Priority date: 2015-09-25
Filing date: 2015-09-25
Publication date: 2017-03-30
Also published as: TWI697964B; TW201724273A

Abstract

Techniques are disclosed for bottom-up filling of semiconductor device topographies. In accordance with some embodiments, a seed layer may be formed over a bottom surface of a feature patterned in a dielectric layer. The seed layer may be, for example, a work function metal (WFM) layer or a barrier layer. In accordance with some embodiments, the fill metal may be, at least initially, selectively deposited over only the seed layer, and as deposition continues, the fill metal may grow to fill the feature from bottom to top, in some cases with no seam or void formed therein. Optional selective passivation of the sidewalls of the feature (or other layer therein) may inhibit fill metal deposition on those surfaces, facilitating selective deposition. In accordance with some embodiments, an etch and recess process that utilizes a sacrificial fill material may be used in forming the seed layer at the feature bottom.

Description

TECHNIQUES FOR BOTTOM-UP FILLING OF THREE-DIMENSIONAL

SEMICONDUCTOR DEVICE TOPOGRAPHIES

BACKGROUND

In typical three-dimensional transistor architectures, a three-dimensional silicon fin rises up vertically from an underlying silicon substrate. A metal gate is wrapped over the top and two sides of the fin, providing a so-called tri-gate transistor. In contrast, traditional two-dimensional planar transistors have only a single silicon surface over which the gate is provided. A gate dielectric is normally provided between the gate and the underlying silicon.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates conformal filling of a feature formed in an inter-layer dielectric (ILD).

Figure 2A is a cross-sectional view of an integrated circuit (IC) configured in accordance with an embodiment of the present disclosure.

Figure 2B is a cross-sectional view of IC of Figure 2A after forming a layer of fill material, in accordance with an embodiment of the present disclosure.

Figure 2C is a cross-sectional view of the IC of Figure 2B after partial removal of the fill material, a work function metal (WFM) layer, and a barrier layer, in accordance with an embodiment of the present disclosure.

Figure 2D is a cross-sectional view of the IC of Figure 2C after removal of the remainder of the fill material, in accordance with an embodiment of the present disclosure.

Figure 2E is a cross-sectional view of the IC of Figure 2D after forming a metal layer, in accordance with an embodiment of the present disclosure.

Figure 3A is a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.

Figure 3B is a cross-sectional view of the IC of Figure 3 A after forming a layer of fill material, in accordance with an embodiment of the present disclosure.

Figure 3C is a cross-sectional view of the IC of Figure 3B after partial removal of a second barrier layer and the fill material, in accordance with an embodiment of the present disclosure.

Figure 3D is a cross-sectional view of the IC of Figure 3C after removal of the remainder of the fill material, in accordance with an embodiment of the present disclosure.

Figure 3E is a cross-sectional view of the IC of Figure 3D after forming a metal layer, in accordance with an embodiment of the present disclosure. Figure 4 is a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.

Figure 5 is a cross-sectional view of an IC configured in accordance with another embodiment of the present disclosure.

Figure 6 is a cross-sectional view of a source/drain (S/D) contact configured in accordance with an embodiment of the present disclosure.

Figure 7 illustrates a computing system implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines, right angles, etc., and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. In short, the figures are provided merely to show example structures.

DETAILED DESCRIPTION

Techniques are disclosed for bottom-up filling of three-dimensional semiconductor device topographies. In accordance with some embodiments, a seed layer may be formed over a bottom surface of a trench, hole, or other patterned feature in a dielectric layer. The seed layer may be, for example, a work function metal (WFM) layer or a barrier layer. In either case, the fill metal may be, at least initially, selectively deposited over only the seed layer, in accordance with some embodiments. As deposition continues, the fill metal may grow to fill the feature from bottom to top, in some cases with no seam or void formed therein. In some instances, optional selective passivation of the sidewalls of the feature (or other layer therein) may inhibit deposition of the fill metal on those surfaces having passivant molecules disposed thereon, thereby facilitating selective formation of the fill metal within the feature. In accordance with some embodiments, an etch and recess process that utilizes a sacrificial fill material may be used in formation of the seed layer at the bottom portion of the feature. Numerous configurations and variations will be apparent in light of this disclosure. General Overview

As feature sizes shrink, it becomes increasingly difficult to fill topographies in three- dimensional transistor devices. Existing conformal filling techniques result in formation of seams or voids like those shown in Figure 1, which illustrates conformal filling of a feature formed in an inter-layer dielectric (ILD). Those seams or voids cause device reliability issues and normally cannot be healed without applying extreme thermal conditions. Some existing processes impart non-conformal fill due to a difference in deposition rate on the horizontal field compared to sidewalls perpendicular thereto. In addition, existing bottom-up fill processes that utilize surface modification by ion implantation are limited to patterns with low aspect ratios and unvarying size and pitch, and those that utilize electroless chemistries are notoriously difficult to keep in control for particle formation.

Thus, and in accordance with some embodiments of the present disclosure, techniques are disclosed for bottom-up filling of three-dimensional semiconductor device topographies. In accordance with some embodiments, a seed layer may be formed over a bottom surface of a trench, hole, or other patterned feature in a dielectric layer. The seed layer may be, for example, a work function metal (WFM) layer or a barrier layer. In either case, the fill metal may be, at least initially, selectively deposited over only the seed layer, in accordance with some embodiments. As deposition continues, the fill metal may grow to fill the feature from bottom to top, in some cases with no seam or void formed therein. In some instances, optional selective passivation of the sidewalls of the feature (or other layer therein) may inhibit deposition of the fill metal on those surfaces having passivant molecules disposed thereon, thereby facilitating selective formation of the fill metal within the feature. In accordance with some embodiments, an etch and recess process that utilizes a sacrificial fill material may be used in formation of the seed layer at the bottom portion of the feature.

In accordance with some embodiments, the disclosed techniques can be used, for example, in forming gate structures, as well as source/drain contact structures, in three- dimensional transistor architectures. The techniques disclosed herein may be utilized independent of feature size and pitch to provide seamless or gapless bottom-up fill with minimized (or otherwise reduced) presence of defects, in accordance with some embodiments. As will be appreciated in light of this disclosure, elimination or reduction of the presence of seams or gaps in the metal (e.g., gate metal; source/drain contact metal) may improve device reliability and yield, in some instances. Numerous suitable uses and applications will be apparent in light of this disclosure.

In accordance with some embodiments, use of the disclosed techniques may be detected, for example, by visual or other inspection (e.g., scanning electron microscope, or SEM, imaging; transmission electron microscope, or TEM, imaging) of a given integrated circuit or other device having a chemically distinct layer at the bottom of a feature and a seamless or otherwise gapless fill of that feature. In some cases, the presence of a void or seam in a region of the fill above a semiconductor fin may be indicative of use of the techniques disclosed herein.

Methodologies and Structures

Figures 2A-2E illustrate an integrated circuit (IC) fabrication process flow for forming an IC 100 A, in accordance with an embodiment of the present disclosure. The process flow of Figures 2A-2E may be used, for example, to provide bottom-up fill by selective deposition of fill material (e.g., gate material) in a three-dimensional p-type metal-oxide-semiconductor (PMOS) transistor device, in accordance with some embodiments. Other suitable uses of the process flow of Figures 2A-2E will be apparent in light of this disclosure.

The process may begin as in Figure 2A, which is a cross-sectional view of an integrated circuit (IC) 100A configured in accordance with an embodiment of the present disclosure. As can be seen, IC 100A may include a dielectric layer 102. Dielectric layer 102 can be formed from any suitable dielectric material(s), as will be apparent in light of this disclosure. For instance, in some cases, dielectric layer 102 may be formed from an oxide such as silicon dioxide (Si0₂). In some cases, dielectric layer 102 may be formed from a nitride such as silicon nitride (Si₃N₄), silicon oxynitride (SiON), silicon carbonitride (SiCN), or boron nitride (BN). In some cases, dielectric layer 102 may be formed from a carbide such as silicon carbide (SiC). In a more general sense, and in accordance with some embodiments, dielectric layer 102 may be formed from any one, or combination, of the aforementioned materials. In some instances, dielectric layer 102 may be a homogeneous dielectric structure (e.g., comprising only a single dielectric material). In some other instances, dielectric layer 102 may be a heterogeneous dielectric structure (e.g., comprising portions of different dielectric material composition). Dielectric layer 102 may be, for example, an inter-layer dielectric (ILD), in some embodiments.

Dielectric layer 102 may be patterned with a feature 106. Feature 106 may have, for example, one or more trench/hole portions 106a, in some instances. In some cases, feature 106 may have a bottom portion 106b and one or more sidewall portions 106c. The dimensions and geometry of dielectric layer 102, as well as feature 106, can be customized, as desired for a given target application or end-use. Patterning of feature 106 within dielectric layer 102 may be performed via any suitable standard, custom, or proprietary patterning technique(s), as will be apparent in light of this disclosure. Other suitable materials, dimensions, geometries, and formation techniques for dielectric layer 102 and feature 106 will depend on a given application and will be apparent in light of this disclosure. Also, as can be seen from Figure 2A, IC 100A may include a semiconductor body 104 disposed within dielectric layer 102 and protruding into feature 106, resulting in the presence of one or more trenches (or holes) 106a alongside semiconductor body 104 in dielectric layer 102. Semiconductor body 104 can be formed from any suitable semiconductor material(s), as will be apparent in light of this disclosure. For instance, in some cases, semiconductor body 104 may be formed from silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon germanium carbide (SiGeC), or silicon carbide (SiC). In some cases, semiconductor body 104 may be formed from a III-V compound semiconductor such as gallium nitride (GaN), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or indium gallium arsenide (InGaAs). In a more general sense, and in accordance with some embodiments, semiconductor body 104 may be formed from any one, or combination, of the aforementioned materials.

The dimensions and geometry of semiconductor body 104 can be customized, as desired for a given target application or end-use. In some cases, semiconductor body 104 may be configured as a fin or other fin-like prominence. In accordance with some embodiments, semiconductor body 104 can be utilized, for example, in forming a fin-based transistor device or other suitable fin-based semiconductor architecture, as will be apparent in light of this disclosure.

Formation of semiconductor body 104 may be performed via any suitable standard, custom, or proprietary patterning (e.g., finFET fabrication) technique(s), as will be apparent in light of this disclosure. In some instances, semiconductor body 104 may have one or more layers, such as a hardmask or other layer, formed between it (e.g., at an upper surface thereof) and any overlying layer(s), such as dielectric layer 108 (discussed below). Other suitable materials, dimensions, geometries, and formation techniques for semiconductor body 104 will depend on a given application and will be apparent in light of this disclosure.

As can be seen further from Figure 2A, IC 100A may include a dielectric layer 108. In accordance with an embodiment, dielectric layer 108 may be configured to serve as a gate dielectric layer. Dielectric layer 108 may be formed from any suitable high-κ dielectric material(s) (e.g., having a dielectric constant κ greater than or equal to that of silicon dioxide). For instance, in some cases, dielectric layer 108 may be formed from an oxide such as hafnium oxide (Hf0₂), aluminum oxide (A1₂0₃), zirconium dioxide (Zr0₂), tantalum pentoxide (Ta₂0₅), titanium dioxide (Ti0₂), lanthanum oxide (La₂0₃), or gadolinium oxide (Gd₂0₃). In some cases, dielectric layer 108 may be formed from a silicon-doped oxide such as, for example, hafnium silicate (HfSiOx), aluminum silicate (AlSiOx), zirconium silicate (ZrSiOx), tantalum silicate (TaSiOx), titanium silicate (TiSiOx), lanthanum silicate (LaSiOx), or gadolinium silicate (GdSiOx). Other suitable rare earth oxide and rate earth silicates will depend on a given target application and will be apparent in light of this disclosure. In a more general sense, and in accordance with some embodiments, dielectric layer 108 may be formed from any one, or combination, of the aforementioned materials. Dielectric layer 108 and dielectric layer 102 may be of different material composition, in accordance with some embodiments.

The dimensions and geometry of dielectric layer 108 can be customized, as desired for a given target application or end-use. In some cases, dielectric layer 108 may have an average thickness, for example, in the range of about 1-10 nm (e.g., about 1-5 nm, about 5-10 nm, or any other sub-range in the range of about 1-10 nm). In some cases, dielectric layer 108 may have an average thickness, for example, in the range of about 0.5-5 nm (e.g., about 0.5-2.5 nm, about 2.5-5 nm, or any other sub-range in the range of about 0.5-5 nm). In some cases, dielectric layer 108 may have an average thickness, for example, in the range of about 0.1-3 nm (e.g., about 0.1-1 nm, about 1-2 nm, about 2-3 nm, or any other sub-range in the range of about 0.1-3 nm). In some cases, dielectric layer 108 may have an average thickness, for example, of about 1 nm or less (e.g., about 0.5 nm or less, about 0.1 nm or less, etc.).

In some instances, dielectric layer 108 may have a substantially uniform thickness over the topography provided, for example, by underlying dielectric layer 102 (e.g., including feature 106 formed therein) and semiconductor body 104. In some instances, dielectric layer 108 may be provided as a substantially conformal layer over such topography. In other instances, dielectric layer 108 may be provided with a non -uniform or otherwise varying thickness over such topography. For example, in some cases a first portion of dielectric layer 108 may have a thickness within a first range, whereas a second portion thereof may have a thickness within a second, different range. In some instances, dielectric layer 108 may have first and second portions having average thicknesses that are different from one another by about 20% or less, about 15% or less, about 10%> or less, or about 5% or less. In some cases, dielectric layer 108 may extend from bottom portion 106b of feature 106 to the full height of sidewall portion 106c of feature 106. In some other cases, dielectric layer 108 may extend from bottom portion 106b of feature 106 to a height of sidewall portion 106c of feature 106 equal to the thickness of dielectric layer 108 (e.g., such as can be seen from Figures 4-5, discussed below).

Dielectric layer 108 can be formed using any suitable technique(s), as will be apparent in light of this disclosure. For instance, in some cases, dielectric layer 108 may be formed via any one, or combination, of a chemical vapor deposition (CVD) process such as plasma-enhanced CVD (PECVD) and an atomic layer deposition (ALD) process. Other suitable materials, dimensions, geometries, and formation techniques for dielectric layer 108 will depend on a given application and will be apparent in light of this disclosure.

In accordance with some embodiments, a barrier layer 110 may be formed over dielectric layer 108. In some cases, barrier layer 110 can be formed, for example, from a metal nitride such as any one, or combination, of titanium nitride (TiN), tantalum nitride (TaN), vanadium nitride (VN), niobium nitride (NbN), and zirconium nitride (ZrN). In a more general sense, and in accordance with some embodiments, barrier layer 110 may be formed from any suitable material(s) that may serve, at least in part, as a reliability layer for the host IC 100A (or other host IC configured as described herein). As will be appreciated in light of this disclosure, barrier layer 110 may be formed with any of the example dimensions, geometries, and techniques discussed above, for instance, with respect to dielectric layer 108, in accordance with some embodiments. In some cases, barrier layer 110 may be conformal to the topography of underlying dielectric layer 108. In some instances, barrier layer 110 may extend, at least initially, from bottom portion 106b of feature 106 to the full height of sidewall portion 106c of feature 106. In some instances, barrier layer 110 may extend from bottom portion 106b of feature 106 to less than the full height of sidewall portion 106c of feature 106. Other suitable materials, dimensions, geometries, and formation techniques for barrier layer 110 will depend on a given application and will be apparent in light of this disclosure.

In accordance with some embodiments, a work function metal (WFM) layer 112 may be formed over barrier layer 110. WFM layer 112 can be formed from any suitable work function metal, as will be apparent in light of this disclosure. For instance, in some cases, WFM layer 112 may be formed from any one, or combination, of tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), and zirconium nitride (ZrN). As will be appreciated in light of this disclosure, WFM layer 112 may be formed with any of the example dimensions, geometries, and techniques discussed above, for instance, with respect to dielectric layer 108, in accordance with some embodiments. In some cases, WFM layer 112 may be conformal to the topography of underlying barrier layer 110. In some instances, WFM layer 112 may extend, at least initially, from bottom portion 106b of feature 106 to the full height of sidewall portion 106c of feature 106. In some instances, WFM layer 112 may extend from bottom portion 106b of feature 106 to less than the full height of sidewall portion 106c of feature 106. In accordance with some embodiments, WFM layer 112 may serve, at least in part, as a seed layer, for example, for metal layer 116 (discussed below with respect to Figure 2E). Other suitable materials, dimensions, geometries, and formation techniques for WFM layer 112 will depend on a given application and will be apparent in light of this disclosure.

The process may continue as in Figure 2B, which is a cross-sectional view of the IC 100 A of Figure 2 A after forming a layer of fill material 114, in accordance with an embodiment of the present disclosure. As can be seen, fill material 114 may be disposed within feature 106 (e.g., within trenches/holes 106a alongside semiconductor body 104) over WFM layer 112, barrier layer 110, and dielectric layer 108. Fill material 114 can be any of a wide range of materials. For instance, in some cases, fill material 114 may be any one, or combination, of silicon dioxide (Si0₂), a carbon hardmask, and tungsten (W). In some cases, fill material 114 may be a dielectric or other insulating material on which a metal (e.g., such as metal layer 116, discussed below) may be selectively formed. In a more general sense, and in accordance with some embodiments, fill material 114 may be formed from any one, or combination, of the aforementioned materials. As will be appreciated in light of this disclosure, fill material 114 may be considered, in a general sense, a sacrificial fill material.

The dimensions and geometry of fill material 114 can be customized, as desired for a given target application or end-use, and in some instances may be depend, at least in part, on the dimensions and geometry of feature 106 and semiconductor body 104 therein. Fill material 114 can be deposited using any suitable technique(s), as will be apparent in light of this disclosure. For instance, in some cases, fill material 114 may be deposited using any one, or combination, of a chemical vapor deposition (CVD) process such as a plasma-enhanced CVD (PECVD) process, an atomic layer deposition (ALD) process, and a spin-on deposition (SOD) process. Any undesired excess of fill material 114 (e.g., overburden that may extend above an upper surface of IC 100A) may be removed using any one, or combination, of a chemical -mechanical planarization (CMP) process and an etch-and-clean process. Other suitable materials, dimensions, geometries, and formation techniques for fill material 114 will depend on a given application and will be apparent in light of this disclosure.

The process may continue as in Figure 2C, which is a cross-sectional view of the IC 100A of Figure 2B after partial removal of fill material 114, WFM layer 112, and barrier layer 110, in accordance with an embodiment of the present disclosure. Fill material 114, WFM layer 112, and barrier layer 110 may be partially removed from feature 106 using any suitable technique(s), as will be apparent in light of this disclosure. For instance, in some cases, fill material 114, WFM layer 112, and barrier layer 110 may be partially removed (e.g., recessed) using any one, or combination, of a wet etch process or a dry etch process, the etch chemistry of which can be customized as desired for a given target application or end-use, a polish or planarization process (e.g., CMP), and an ash process (e.g., which does not oxidize any metal present). Partial removal of fill material 114 may occur sequentially or concurrently with partial removal of WFM layer 112 and barrier layer 110, in accordance with some embodiments. As will be appreciated in light of this disclosure, if the same etchant(s) used to partially remove the fill material 114, WFM layer 112, and barrier layer 110 simultaneously are also used to remove the remainder of the fill material 114 subsequently (e.g., as discussed below with reference to Figure 2D), then it may be desirable to ensure proper process timing, as desired for a given target application or end-use. Upon removing a portion of each of fill material 114, WFM layer 112, and barrier layer 110 from feature 106, each of fill material 114, WFM layer 112, and barrier layer 110 may only partially remain, for example, in the bottom portion 106b of the feature 106, in accordance with an embodiment. In some instances, barrier layer 110 and WFM layer 112 each may extend from bottom portion 106b of feature 106 to less than the full height of sidewall portion 106c of feature 106.

The process may continue as in Figure 2D, which is a cross-sectional view of the IC 100A of Figure 2C after removal of the remainder of fill material 114, in accordance with an embodiment of the present disclosure. As will be appreciated in light of this disclosure, any of the techniques discussed above, for instance, with respect to Figure 2C and partial removal of fill material 114 may be used to that end, in accordance with some embodiments. Upon removal of the remainder of fill material 114, WFM layer 112 and barrier layer 110 still may only partially remain, for example, in the bottom portion 106b of the feature 106, in accordance with an embodiment. The portion of WFM layer 112 over bottom portion 106b may serve, at least in part, as a seed layer, for example, for metal layer 116 (discussed below).

The process may continue as in Figure 2E, which is a cross-sectional view of the IC 100A of Figure 2D after forming metal layer 116, in accordance with an embodiment of the present disclosure. Metal layer 116 can be formed from any suitable electrically conductive material(s), as will be apparent in light of this disclosure. For instance, in some cases, metal layer 116 may be formed from a metal such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), titanium (Ti), or tantalum (Ta). In some cases, metal layer 116 may be formed from a nitride such as titanium nitride (TiN) or tantalum nitride (TaN). In a more general sense, and in accordance with some embodiments, metal layer 116 may be formed from any one, or combination, of the aforementioned materials.

The dimensions and geometry of metal layer 116 can be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on the dimensions and geometry of feature 106 and semiconductor body 104 therein. In accordance with some embodiments, metal layer 116 may be selectively formed (e.g., selectively deposited or otherwise selectively grown) over the thin layer (e.g., seed layer) of WFM layer 112 over bottom portion 106b of feature 106. To that end, metal layer 116 can be formed using any suitable technique(s), as will be apparent in light of this disclosure. For instance, in some cases, metal layer 116 may be formed via any one, or combination, of an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, and an electroless deposition process. Other suitable materials, dimensions, geometries, and formation techniques for metal layer 116 will depend on a given application and will be apparent in light of this disclosure. In some cases, and in accordance with an embodiment, metal layer 116 initially may grow only on the thin layer (e.g., seed layer) of WFM layer 112, resulting in seamless, bottom-up filling of metal layer 116 within feature 106 around semiconductor body 104. As metal layer 116 reaches and clears the top of semiconductor body 104, growth of metal layer 116 may continue laterally within feature 106, in accordance with an embodiment. In some instances, a void or seam may form in region 118 of feature 106 as metal layer 116 clears the top of semiconductor body 104. As will be appreciated in light of this disclosure, it may be desirable, in some cases, to eliminate or otherwise reduce the presence of such a void or seam. To that end, any suitable metal reflow process may be used to reflow metal layer 116, as will be apparent in light of this disclosure. In other cases, however, such a void or seam may remain in region 118 with no or otherwise negligible or acceptable effect on IC 200A (or other host IC configured as described herein).

In accordance with some embodiments, after partial removal of fill material 114, WFM layer 112, and barrier layer 110 (e.g., as discussed above with respect to Figure 2C) or after removal of the remainder of fill material 114 (e.g., as discussed above with respect to Figure 2D), dielectric layer 108 optionally may undergo selective passivation of any exposed portion thereof. In some instances, and in accordance with an embodiment, passivation of the exposed surface of dielectric layer 108 may promote bottom-up filling of feature 106 with metal layer 116 (as discussed above with respect to Figure 2E).

Passivation of dielectric layer 108, in part or in whole, may be provided using any suitable passivation materials and techniques, as will be apparent in light of this disclosure. For instance, in some cases, dielectric layer 108 may be selectively passivated using one or more self-assembled monolayers (SAMs). As will be appreciated in light of this disclosure, selective passivation of dielectric layer 108 via a SAM may occur from the vapor phase or from molecules dissolved in solvent (or both). In some cases, dielectric layer 108 may be selectively passivated using one or more SAMs that attach preferentially to an oxide surface, such as phosphonic acids, thiols, carboxylic acids, and amines. Some suitable examples include octadecylphosphonic acid (ODPA), 1-octadecanethiol (ODT), and octadecanoic acid (ODCA; stearic acid). In some cases, dielectric layer 108 may be selectively passivated using one or more SAMs that attach preferentially to a dielectric surface, such as chloro-, alkoxy-, and amino-silanes with alkane chain length in the range of 1-20 carbons. Some suitable examples include organosilicon compounds such as octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS). In some instances, the passivant(s) may be selected so as not to react (or otherwise only negligibly react) with any or all of the WFM layer 112, dielectric layer 102, and dielectric layer 108. In a more general sense, and in accordance with some embodiments, selective passivation of dielectric layer 108 may be provided using any one, or combination, of the aforementioned materials and techniques. If the selectivity of the passivation material(s) is insufficient due to reactivity with any surrounding materials, then any undesired passivant material can be removed from the surfaces where passivation is not desired using any one, or combination, of thermal annealing, a wet etch process, and a dry etch process, in accordance with some embodiments.

Figures 3A-3E illustrate an IC fabrication process flow for forming an IC 100B, in accordance with another embodiment of the present disclosure. The process flow of Figures BASE may be used, for example, to provide bottom-up fill by selective deposition of fill material (e.g., gate material) in a three-dimensional n-type metal-oxide-semiconductor (NMOS) device transistor device, in accordance with some embodiments. Other suitable uses of the process flow of Figures 3A-3E will be apparent in light of this disclosure.

The process may begin as in Figure 3 A, which is a cross-sectional view of an IC 100B configured in accordance with another embodiment of the present disclosure. As can be seen, IC 100B may include a dielectric layer 102 patterned with a feature 106, as discussed above. Also, as can be seen from Figure 3 A, IC 100B may include a semiconductor body 104 disposed within dielectric layer 102 and protruding into feature 106, resulting in the presence of one or more trenches (or holes) 106a alongside semiconductor body 104 in dielectric layer 102, as discussed above. As can be seen further from Figure 3 A, IC 100B may include a dielectric layer 108, barrier layer 110, and WFM layer 112, as described above.

Unlike IC 100A discussed above, however, IC 100B further may include a barrier layer 113 formed over WFM layer 112, in accordance with some embodiments. Barrier layer 113 may be formed from any of a wide range of materials. For instance, in some cases, barrier layer 113 may be formed from a metal such as tantalum (Ta), titanium (Ti), or manganese (Mn). In some cases, barrier layer 113 may be formed from a nitride such as tantalum nitride (TaN), titanium nitride (TiN), or manganese nitride (MnN). In a more general sense, and in accordance with some embodiments, barrier layer 113 may be formed from any one, or combination, of the aforementioned materials.

As will be appreciated in light of this disclosure, barrier layer 113 may be formed with any of the example dimensions, geometries, and techniques discussed above, for instance, with respect to dielectric layer 108, in accordance with some embodiments. In some instances, barrier layer 113 may extend, at least initially, from bottom portion 106b of feature 106 to the full height of sidewall portion 106c of feature 106. In some instances, barrier layer 113 may extend from bottom portion 106b of feature 106 to less than the full height of sidewall portion 106c of feature 106. In accordance with some embodiments, barrier layer 113 may serve, at least in part, as a seed layer, for example, for metal layer 116 (discussed above, as well as below with respect to Figure 3E). Other suitable materials, dimensions, geometries, and formation techniques for barrier layer 113 will depend on a given application and will be apparent in light of this disclosure.

The process may continue as in Figure 3B, which is a cross-sectional view of the IC 100B of Figure 3 A after forming a layer of fill material 114, in accordance with an embodiment of the present disclosure. As can be seen, fill material 114 (discussed above) may be disposed within feature 106 (e.g., within trenches/holes 106a alongside semiconductor body 104) over barrier layer 113, WFM layer 112, barrier layer 1 10, and dielectric layer 108. As noted above, fill material 114 may be considered, in a general sense, a sacrificial fill material, in accordance with some embodiments. Any undesired excess of fill material 114 (e.g., overburden that may extend above an upper surface of IC 100B) may be removed using any one, or combination, of a CMP process and an etch-and-clean process, as discussed above.

The process may continue as in Figure 3C, which is a cross-sectional view of the IC 100B of Figure 3B after partial removal of barrier layer 113 and fill material 114, in accordance with an embodiment of the present disclosure. Fill material 114 and barrier layer 113 may be partially removed from feature 106 using any suitable technique(s), as will be apparent in light of this disclosure, including any of those example techniques discussed above, for instance, with respect to Figure 2C and partial removal of fill material 114, in accordance with some embodiments. Partial removal of fill material 114 may occur sequentially or concurrently with partial removal of barrier layer 113, in accordance with some embodiments. As will be appreciated in light of this disclosure, if the same etchant(s) used to partially remove the fill material 114 and barrier layer 113 simultaneously are also used to remove the remainder of the fill material 114 subsequently (e.g., as discussed below with reference to Figure 3D), then it may be desirable to ensure proper process timing, as desired for a given target application or end-use. Upon removing a portion of each of fill material 1 14 and barrier layer 113 from feature 106, each of fill material 114 and barrier layer 113 may only partially remain, for example, in the bottom portion 106b of the feature 106, in accordance with an embodiment. In some instances, barrier layer 113 may extend from bottom portion 106b of feature 106 to less than the full height of sidewall portion 106c of feature 106.

The process may continue as in Figure 3D, which is a cross-sectional view of the IC 100B of Figure 3C after removal of the remainder of fill material 114, in accordance with an embodiment of the present disclosure. As will be appreciated in light of this disclosure, any of the techniques discussed above, for instance, with respect to Figure 3C and partial removal of fill material 114 and barrier layer 113 may be used to that end, in accordance with some embodiments.

Upon removal of the remainder of fill material 114, barrier layer 113 still may only partially remain, for example, in the bottom portion 106b of the feature 106, in accordance with an embodiment. The portion of barrier layer 113 over bottom portion 106b may serve, at least in part, as a seed layer, for example, for metal layer 116 (discussed below). WFM layer 112 and barrier layer 110 may remain over bottom portion 106b of feature 106, as well as optionally over sidewall portion(s) 106c of feature 106.

The process may continue as in Figure 3E, which is a cross-sectional view of the IC 100B of Figure 3D after forming metal layer 116, in accordance with an embodiment of the present disclosure. Metal layer 116 (discussed above) may be selectively formed (e.g., selectively deposited or otherwise selectively grown) over the thin layer (e.g., seed layer) of barrier layer 113 over bottom portion 106b of feature 106. Metal layer 116 may be selectively formed in this manner without being formed on WFM layer 112, at least initially, in accordance with some embodiments. To that end, metal layer 116 can be formed using any suitable technique(s), as discussed above. In some cases, and in accordance with an embodiment, metal layer 116 initially may grow only on the thin layer (e.g., seed layer) of barrier layer 113, resulting in seamless, bottom-up filling of metal layer 116 within feature 106 around semiconductor body 104. As metal layer 116 reaches and clears the top of semiconductor body 104, growth of metal layer 116 may continue laterally within feature 106. In some cases, a void or seam may form in region 118 of feature 106 as metal layer 116 clears the top of semiconductor body 104, as discussed above. If desired, the presence of such a void or seam may be eliminated or otherwise reduced, as described above.

In accordance with some embodiments, after partial removal of fill material 114 and barrier layer 113 (e.g., as discussed above with respect to Figure 3C) or after removal of the remainder of fill material 114 (e.g., as discussed above with respect to Figure 3D), WFM layer 112 optionally may undergo selective passivation of any exposed surface thereof. In some instances, and in accordance with an embodiment, passivation of the exposed surface of WFM layer 112 may promote bottom-up filling of feature 106 with metal layer 116 (as discussed above with respect to Figure 3E). Passivation of WFM layer 112 may be provided using any of the example materials and techniques discussed above, for instance, with respect to optional passivation of dielectric layer 108, in accordance with some embodiments. In addition, any undesired passivant material can be removed from the surfaces where passivation is not desired using any one, or combination, of thermal annealing, a wet etch process, and a dry etch process, as described above, in accordance with some embodiments. In accordance with some embodiments, dielectric layer 108 may be formed selectively within feature 106. For instance, consider Figures 4-5, which are cross-sectional views of an IC 100A' and an IC 100B', respectively, configured in accordance some embodiments of the present disclosure. As can be seen here, dielectric layer 108 may be formed, for example, over semiconductor body 104, as well as a bottom portion 106b of feature 106, but not over sidewall portion(s) 106c of feature 106. In some instances, dielectric layer 108 may extend from bottom portion 106b of feature 106 to a height of sidewall portion 106c of feature 106 about equal to a thickness of dielectric layer 108.

To that end, in accordance with some embodiments, a sacrificial blocking layer (e.g., such as any of the SAM materials discussed above) may be formed over a given surface (e.g., a sidewall portion 106c) where no dielectric layer 108 is desired and a selective atomic layer deposition (ALD) process may be utilized in depositing the dielectric material(s) of dielectric layer 108. The molecules of the SAM material(s) applied may form a blanket monolayer that blocks deposition of dielectric layer 108, for instance, on sidewall portion(s) 106c (or any other desired portion) of feature 106. In accordance with some embodiments, the SAM material(s) applied may be subsequently removed, for example, via a thermal treatment. In some cases, a thermal treatment at a temperature in the range of about 200-400 °C (e.g., about 200-250 °C, about 250-300 °C, about 300-350 °C, about 350-400 °C, or any other sub-range in the range of about 200-400 °C) may be sufficient to remove any SAM material(s) applied. As will be appreciated in light of this disclosure, due to the low temperature at which a given SAM blocking layer will thermally decompose, it may be desirable to provide a sufficiently low- temperature formation of dielectric layer 108 to avoid premature degradation of that SAM layer. In some instances, and in accordance with some embodiments, a low-temperature ALD process for dielectric materials such as hafnium oxide (Hf0₂) or zirconium dioxide (Zr0₂) may be utilized. For example, tetrakis(dimethylamido)hafnium will react with water at about 250 °C in an ALD process to produce a Hf0₂ film in accordance with the following relationship:

ALD

Hf(NMe₂)+2H₂0→ Hf0₂+4NHMe₂.

As will be appreciated in light of this disclosure, the exposed sidewall portion(s) 106c of feature 106 in dielectric layer 102 (e.g., as in Figure 4) or of WFM layer 112 (e.g., as in Figure 5) optionally may be selectively passivated with any of the example passivation materials (e.g., SAMs) and techniques discussed above with respect to optional selective passivation of dielectric layer 108, in accordance with some embodiments.

As previously noted, the techniques disclosed herein can be used, for example, in the formation of gate structures, as well as source/drain contact structures, in accordance with some embodiments. For instance, consider Figure 6, which is a cross-sectional view of a source/drain (S/D) contact 200 configured in accordance with an embodiment of the present disclosure. As can be seen, S/D contact 200 may include a dielectric layer 102 and a semiconductor body 104 (both discussed above).

S/D contact 200 also may include a dielectric layer 103. As will be appreciated in light of this disclosure, dielectric layer 103 may be formed with any of the example materials, dimensions, geometries, and techniques discussed above, for instance, with respect to dielectric layer 102. In some cases, dielectric layer 103 may be of different material composition than dielectric layer 102.

As can be seen further from Figure 6, S/D contact 200 also may include an epitaxial semiconductor body 105 formed over semiconductor body 104. Epitaxial semiconductor body 105 may be, for example, a three-dimensional semiconductor structure. As will be appreciated in light of this disclosure, epitaxial semiconductor body 105 may be formed with any of the example materials discussed above, for instance, with respect to semiconductor body 104. Epitaxial semiconductor body 105 may be formed using any suitable technique(s), as will be apparent in light of this disclosure. For instance, in some cases, epitaxial semiconductor body 105 may be formed using any one, or combination, of an epitaxy process such as metalorganic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE), an atomic layer deposition (ALD) process, and a chemical vapor deposition (CVD) process. The dimensions and geometry of epitaxial semiconductor body 105 may be customized, as desired for a given target application or end-use. Other suitable materials, dimensions, geometries, and formation techniques for epitaxial semiconductor body 105 will depend on a given application and will be apparent in light of this disclosure.

In accordance with some embodiments, dielectric layer 103 may be etched back to reveal a top surface of epitaxial semiconductor body 105, and a contact metal layer 107 may be formed over the exposed top surface of epitaxial semiconductor body 105. Contact metal layer 107 may be formed from any suitable electrically conductive metal or metal silicide. For instance, in some cases, contact metal layer 107 may be formed from any one, or combination, of nickel silicide (NiSi_x) and cobalt silicide (CoSi_x). In some other cases, contact metal layer 107 may be formed from any of the example electrically conductive materials discussed above, for instance, with respect to metal layer 116.

Contact metal layer 107 may be formed using any suitable technique(s), as will be apparent in light of this disclosure. For instance, in some cases, contact metal layer 107 may be formed using any one, or combination, of a physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, and an atomic layer deposition (ALD) process. The dimensions and geometry of contact metal layer 107 may be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on the topography of underlying epitaxial semiconductor body 105. Other suitable materials, dimensions, geometries, and formation techniques for contact metal layer 107 will depend on a given application and will be apparent in light of this disclosure.

As can be seen further from Figure 6, S/D contact 200 also may include a dielectric layer 108, a barrier layer 110, and a WFM layer 112 (each discussed above) formed over topography provided by underlying contact metal layer 107 (and possibly dielectric layer 103). In accordance with some embodiments, a contact metal layer 120 may be formed over the underlying topography provided, for instance, by WFM layer 112. As will be appreciated in light of this disclosure, contact metal layer 120 may be formed with any of the example materials and techniques discussed above, for instance, with respect to metal layer 116, in accordance with some embodiments. The dimensions and geometry of contact metal layer 120 may be customized, as desired for a given target application or end-use, and in some cases may depend, at least in part, on the dimensions and geometry of recess 106. Other suitable materials, dimensions, geometries, and formation techniques for contact metal layer 120 will depend on a given application and will be apparent in light of this disclosure.

Example System

Figure 7 illustrates a computing system 1000 implemented with integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc. Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit including: a first dielectric layer having a feature patterned therein, the feature having a bottom portion and a sidewall portion, and a semiconductor body extending through the bottom portion of the feature; a second dielectric layer disposed within the feature over the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer is of higher dielectric constant than the first dielectric layer; a seed layer disposed within the feature over at least a portion of the second dielectric layer; and a metal layer disposed over the seed layer, wherein: the metal layer and the seed layer are of different material composition; and the metal layer is free of at least one of seams and voids alongside the semiconductor body.

Example 2 includes the subject matter of any of Examples 1, 3-5, 13-14, and 16-19, wherein the seed layer includes a work function metal (WFM) layer.

Example 3 includes the subject matter of Example 2, wherein the WFM layer: includes at least one of tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), and zirconium nitride (ZrN); and has an average thickness in the range of about 0.1-3 nm.

Example 4 includes the subject matter of Example 2, wherein the WFM layer extends from a bottom portion of the feature to less than a full height of a sidewall portion of the feature.

Example 5 includes the subject matter of any of Examples 1-4, 13-14, and 16-19, wherein at least a portion of the second dielectric layer is passivated with a self-assembled monolayer (SAM) including at least one of octadecylphosphonic acid (ODPA), 1- octadecanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS). Example 6 includes the subject matter of any of Examples 1, 7-13, and 15-19, wherein the seed layer includes a barrier layer.

Example 7 includes the subject matter of Example 6, wherein the barrier layer: includes at least one of tantalum (Ta), titanium (Ti), manganese (Mn), tantalum nitride (TaN), titanium nitride (TiN), and manganese nitride (MnN); and has an average thickness in the range of about 0.1-3 nm.

Example 8 includes the subject matter of Example 6, wherein the barrier layer extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature.

Example 9 includes the subject matter of Example 6 and further includes a WFM layer disposed within the feature over at least a portion of the second dielectric layer, between the second dielectric layer and the seed layer.

Example 10 includes the subject matter of Example 9, wherein the WFM layer: includes at least one of tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), and zirconium nitride (ZrN); and has an average thickness in the range of about 0.1-3 nm.

Example 11 includes the subject matter of Example 9, wherein the WFM layer extends from the bottom portion of the feature to a full height of the sidewall portion of the feature.

Example 12 includes the subject matter of Example 9, wherein at least a portion of the WFM layer is passivated with a self-assembled monolayer (SAM) including at least one of octadecylphosphonic acid (ODPA), 1 -octadecanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS) .

Example 13 includes the subject matter of any of Examples 1-12 and 14-19 and further includes a barrier layer disposed within the feature over at least a portion of the second dielectric layer, between the second dielectric layer and the seed layer.

Example 14 includes the subject matter of Example 13, wherein the barrier layer: extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature; and has an average thickness in the range of about 0.1-3 nm.

Example 15 includes the subject matter of Example 13, wherein the barrier layer: extends from the bottom portion of the feature to a full height of the sidewall portion of the feature; and has an average thickness in the range of about 0.1-3 nm.

Example 16 includes the subject matter of any of Examples 1-15 and 17-19, wherein the second dielectric layer: includes at least one of hafnium oxide (Hf0₂), aluminum oxide (A1₂0₃), zirconium dioxide (Zr0₂), tantalum pentoxide (Ta₂0₅), titanium dioxide (Ti0₂), lanthanum oxide (La₂0₃), gadolinium oxide (Gd₂0₃), hafnium silicate (HfSiOx), aluminum silicate (AlSiOx), zirconium silicate (ZrSiOx), tantalum silicate (TaSiOx), titanium silicate (TiSiOx), lanthanum silicate (LaSiOx), and gadolinium silicate (GdSiOx); and has an average thickness in the range of about 0.1-3 nm.

Example 17 includes the subject matter of any of Examples 1-16 and 18-19, wherein the second dielectric layer extends from the bottom portion of the feature to a height of the sidewall portion of the feature equal to a thickness of the second dielectric layer.

Example 18 includes the subject matter of any of Examples 1-17 and 19, wherein the second dielectric layer extends from the bottom portion of the feature to a full height of the sidewall portion of the feature.

Example 19 includes the subject matter of any of Examples 1-18, wherein a portion of the metal layer directly over the semiconductor body has at least one of a seam and a void therein.

Example 20 is a method of forming an integrated circuit, the method including: providing a first dielectric layer having a feature patterned therein, the feature having a bottom portion and a sidewall portion, and a semiconductor body extending through the bottom portion of the feature; forming a second dielectric layer over the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer is of higher dielectric constant than the first dielectric layer; forming a seed layer over the second dielectric layer; and forming a metal layer over the seed layer, wherein: the metal layer and the seed layer are of different material composition; and the metal layer is free of at least one of seams and voids alongside the semiconductor body.

Example 21 includes the subject matter of any of Examples 20, 22-25, 31-32, and 34- 37, wherein the seed layer includes a work function metal (WFM) layer, and the method further includes: depositing a fill material over the WFM layer within the feature, wherein the fill material includes at least one of silicon dioxide (Si0₂), tungsten (W), and a carbon hardmask.

Example 22 includes the subject matter of Example 21 and further includes: removing a portion of each of the fill material and the WFM layer from the feature, such that each of the fill material and the WFM layer partially remains in the bottom portion of the feature, wherein the WFM layer extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature.

Example 23 includes the subject matter of Example 22 and further includes: removing a remainder of the fill material from the feature.

Example 24 includes the subject matter of Example 23 and further includes: selectively depositing the metal layer initially over only the WFM layer; and growing the metal layer to fill the feature, wherein the metal layer is free of at least one of seams and voids alongside the semiconductor body.

Example 25 includes the subject matter of any of Examples 20-24, 31-32, and 34-37 and further includes: passivating at least a portion of the second dielectric layer with a self-assembled monolayer (SAM) including at least one of octadecylphosphonic acid (ODPA), 1- octadecanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS).

Example 26 includes the subject matter of any of Examples 20, 27-31, and 33-37, wherein the seed layer includes a barrier layer and the method further includes: forming a work function metal (WFM) layer over the second dielectric layer, between the second dielectric layer and the seed layer; and depositing a fill material over the barrier layer within the feature, wherein the fill material includes at least one of silicon dioxide (Si0₂), tungsten (W), and a carbon hardmask.

Example 27 includes the subject matter of Example 26 and further includes: removing a portion of each of the fill material and the barrier layer from the feature, such that each of the fill material and the barrier layer partially remains in the bottom portion of the feature, wherein the barrier layer extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature.

Example 28 includes the subject matter of Example 27 and further includes: removing a remainder of the fill material from the feature.

Example 29 includes the subject matter of Example 28 and further includes: selectively depositing the metal layer initially over only the barrier layer; and growing the metal layer to fill the feature, wherein the metal layer is free of at least one of seams and voids alongside the semiconductor body.

Example 30 includes the subject matter of Example 26 and further includes: passivating at least a portion of the WFM layer with a self-assembled monolayer (SAM) including at least one of octadecylphosphonic acid (ODPA), 1-octadecanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS) .

Example 31 includes the subject matter of any of Examples 20-30 and 32-37 and further includes: forming a barrier layer over the second dielectric layer, between the second dielectric layer and the seed layer.

Example 32 includes the subject matter of Example 31, wherein the barrier layer extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature. Example 33 includes the subject matter of Example 31, wherein the barrier layer extends from the bottom portion of the feature to a full height of the sidewall portion of the feature.

Example 34 includes the subject matter of any of Examples 20-33 and 35-37, wherein the second dielectric layer extends from the bottom portion of the feature to a height of the sidewall portion of the feature equal to a thickness of the second dielectric layer.

Example 35 includes the subject matter of any of Examples 20-34 and 36-37, the second dielectric layer extends from the bottom portion of the feature to a full height of the sidewall portion of the feature.

Example 36 includes the subject matter of any of Examples 20-35 and 37, wherein a portion of the metal layer directly over the semiconductor body has at least one of a seam and a void therein.

Example 37 is an integrated circuit formed via a method including the subject matter of any of Examples 20-36.

Example 38 is an integrated circuit including: a first dielectric layer having a semiconductor fin extending therethrough; a second dielectric layer disposed over the semiconductor fin, wherein the second dielectric layer is of higher dielectric constant than the first dielectric layer; a first barrier layer disposed over the second dielectric layer; a work function metal (WFM) layer disposed over the first barrier layer; and a first metal layer disposed over the WFM layer, wherein the first metal layer is free of at least one of seams and voids.

Example 39 includes the subject matter of any of Examples 38 and 40 and further includes a second barrier layer disposed over the WFM layer, wherein the first metal layer is disposed over the second barrier layer.

Example 40 includes the subject matter of any of Examples 38-39 and 41-43, wherein the first metal layer is free of at least one of seams and voids except for in a region of the first metal layer directly over the semiconductor fin, wherein that region has at least one of a seam and a void therein.

Example 41 includes the subject matter of any of Examples 38, 40, and 42-43 and further includes: an epitaxial semiconductor body disposed over the semiconductor fin; and a second metal layer disposed over the epitaxial semiconductor body; wherein the first metal layer is disposed over the epitaxial semiconductor body and the second metal layer and is configured to serve as a source/drain contact.

Example 42 includes the subject matter of Example 41, wherein the second metal layer includes at least one of nickel silicide (NiSi_x) and cobalt silicide (CoSi_x).

Example 43 includes the subject matter of Example 41 and further includes: a third dielectric layer in which the first dielectric layer is disposed, wherein: the first and third dielectric layers are of different material composition; and the second and third dielectric layers are of different material composition.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future-filed applications claiming priority to this application may claim the disclosed subject matter in a different manner and generally may include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising:

a first dielectric layer having a feature patterned therein, the feature having a bottom portion and a sidewall portion, and a semiconductor body extending through the bottom portion of the feature;

a second dielectric layer disposed within the feature over the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer is of higher dielectric constant than the first dielectric layer;

a seed layer disposed within the feature over at least a portion of the second dielectric layer; and

a metal layer disposed over the seed layer, wherein:

the metal layer and the seed layer are of different material composition; and the metal layer is free of at least one of seams and voids alongside the semiconductor body.

2. The integrated circuit of claim 1, wherein the seed layer comprises a work function metal (WFM) layer.

3. The integrated circuit of claim 2, wherein the WFM layer:

comprises at least one of tungsten (W), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), and zirconium nitride (ZrN);

has an average thickness in the range of about 0.1-3 nm; and

extends from a bottom portion of the feature to less than a full height of a sidewall portion of the feature.

4. The integrated circuit of claim 1, wherein at least a portion of the second dielectric layer is passivated with a self-assembled monolayer (SAM) comprising at least one of octadecylphosphonic acid (ODPA), 1 -octadecanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS) .

5. The integrated circuit of claim 1, wherein the seed layer comprises a barrier layer.

6. The integrated circuit of claim 5, wherein the barrier layer:

comprises at least one of tantalum (Ta), titanium (Ti), manganese (Mn), tantalum nitride

(TaN), titanium nitride (TiN), and manganese nitride (MnN);

has an average thickness in the range of about 0.1-3 nm; and

extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature.

7. The integrated circuit of claim 5 further comprising a WFM layer disposed within the feature over at least a portion of the second dielectric layer, between the second dielectric layer and the seed layer.

8. The integrated circuit of claim 7, wherein the WFM layer:

has an average thickness in the range of about 0.1-3 nm; and

extends from the bottom portion of the feature to a full height of the sidewall portion of the feature.

9. The integrated circuit of claim 7, wherein at least a portion of the WFM layer is passivated with a self-assembled monolayer (SAM) comprising at least one of octadecylphosphonic acid (ODPA), 1 -octadecanethiol (ODT), octadecanoic acid (ODCA), octadecyltrichlorosilane (ODTCS), octadecyltris(dimethylamino)silane (ODTAS), and octadecyltrimethoxysilane (ODTMS) .

10. The integrated circuit of claim 1 further comprising a barrier layer disposed within the feature over at least a portion of the second dielectric layer, between the second dielectric layer and the seed layer, wherein the barrier layer:

extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature; and

has an average thickness in the range of about 0.1-3 nm.

11. The integrated circuit of claim 1 further comprising a barrier layer disposed within the feature over at least a portion of the second dielectric layer, between the second dielectric layer and the seed layer, wherein the barrier layer:

extends from the bottom portion of the feature to a full height of the sidewall portion of the feature; and

has an average thickness in the range of about 0.1-3 nm.

12. The integrated circuit of claim 1, wherein the second dielectric layer:

comprises at least one of hafnium oxide (Hf0₂), aluminum oxide (A1₂0₃), zirconium dioxide (Zr0₂), tantalum pentoxide (Ta₂0₅), titanium dioxide (Ti0₂), lanthanum oxide (La₂0₃), gadolinium oxide (Gd₂0₃), hafnium silicate (HfSiOx), aluminum silicate (AlSiOx), zirconium silicate (ZrSiOx), tantalum silicate (TaSiOx), titanium silicate (TiSiOx), lanthanum silicate (LaSiOx), and gadolinium silicate (GdSiOx);

has an average thickness in the range of about 0.1-3 nm; and

extends from the bottom portion of the feature to a height of the sidewall portion of the feature equal to a thickness of the second dielectric layer.

13. The integrated circuit of claim 1, wherein the second dielectric layer:

has an average thickness in the range of about 0.1-3 nm; and

14. The integrated circuit of any of claims 1-13, wherein a portion of the metal layer directly over the semiconductor body has at least one of a seam and a void therein.

15. A method of forming an integrated circuit, the method comprising: providing a first dielectric layer having a feature patterned therein, the feature having a bottom portion and a sidewall portion, and a semiconductor body extending through the bottom portion of the feature;

forming a second dielectric layer over the semiconductor body and the bottom portion of the feature, wherein the second dielectric layer is of higher dielectric constant than the first dielectric layer;

forming a seed layer over the second dielectric layer; and

forming a metal layer over the seed layer, wherein:

16. The method of claim 15, wherein the seed layer comprises a work function metal (WFM) layer, and the method further comprises:

depositing a fill material over the WFM layer within the feature, wherein the fill material comprises at least one of silicon dioxide (Si0₂), tungsten (W), and a carbon hardmask.

17. The method of claim 16 further comprising:

removing a portion of each of the fill material and the WFM layer from the feature, such that each of the fill material and the WFM layer partially remains in the bottom portion of the feature, wherein the WFM layer extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature;

removing a remainder of the fill material from the feature;

selectively depositing the metal layer initially over only the WFM layer; and

growing the metal layer to fill the feature, wherein the metal layer is free of at least one of seams and voids alongside the semiconductor body.

18. The method of claim 15, wherein the seed layer comprises a barrier layer and the method further comprises:

forming a work function metal (WFM) layer over the second dielectric layer, between the second dielectric layer and the seed layer; and

depositing a fill material over the barrier layer within the feature, wherein the fill material comprises at least one of silicon dioxide (Si0₂), tungsten (W), and a carbon hardmask.

19. The method of claim 18 further comprising:

removing a portion of each of the fill material and the barrier layer from the feature, such that each of the fill material and the barrier layer partially remains in the bottom portion of the feature, wherein the barrier layer extends from the bottom portion of the feature to less than a full height of the sidewall portion of the feature;

removing a remainder of the fill material from the feature;

selectively depositing the metal layer initially over only the barrier layer; and

20. The method of claim 15 further comprising:

forming a barrier layer over the second dielectric layer, between the second dielectric layer and the seed layer.

21. An integrated circuit comprising:

a first dielectric layer having a semiconductor fin extending therethrough;

a second dielectric layer disposed over the semiconductor fin, wherein the second dielectric layer is of higher dielectric constant than the first dielectric layer;

a first barrier layer disposed over the second dielectric layer;

a work function metal (WFM) layer disposed over the first barrier layer; and

a first metal layer disposed over the WFM layer, wherein the first metal layer is free of at least one of seams and voids.

22. The integrated circuit of claim 21 further comprising a second barrier layer disposed over the WFM layer, wherein the first metal layer is disposed over the second barrier layer.

23. The integrated circuit of claim 21, wherein the first metal layer is free of at least one of seams and voids except for in a region of the first metal layer directly over the semiconductor fin, wherein that region has at least one of a seam and a void therein.

24. The integrated circuit of claim 21 further comprising:

an epitaxial semiconductor body disposed over the semiconductor fin; and a second metal layer disposed over the epitaxial semiconductor body, wherein the second metal layer comprises at least one of nickel silicide (NiSi_x) and cobalt silicide (CoSix);

wherein the first metal layer is disposed over the epitaxial semiconductor body and the second metal layer and is configured to serve as a source/drain contact.

25. The integrated circuit of claim 24 further comprising:

a third dielectric layer in which the first dielectric layer is disposed, wherein:

the first and third dielectric layers are of different material composition; and the second and third dielectric layers are of different material composition.