TWI788045B - 扇出型封裝結構及其製造方法 - Google Patents

扇出型封裝結構及其製造方法 Download PDF

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TWI788045B
TWI788045B TW110137625A TW110137625A TWI788045B TW I788045 B TWI788045 B TW I788045B TW 110137625 A TW110137625 A TW 110137625A TW 110137625 A TW110137625 A TW 110137625A TW I788045 B TWI788045 B TW I788045B
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Taiwan
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redistribution layer
upper redistribution
layer
die
fan
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TW110137625A
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TW202316595A (zh
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蔡佩君
徐宏欣
廖敬偉
張簡上煜
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力成科技股份有限公司
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Priority to TW110137625A priority Critical patent/TWI788045B/zh
Priority to CN202111419542.9A priority patent/CN115954329A/zh
Priority to US17/821,168 priority patent/US20230110079A1/en
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Publication of TWI788045B publication Critical patent/TWI788045B/zh
Publication of TW202316595A publication Critical patent/TW202316595A/zh

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Abstract

本申請提供一種扇出型封裝結構及其製造方法。扇出型封裝結構包括：上重佈線層、晶粒、被動元件和主動元件。上重佈線層包含第一面和相對該第一面之第二面。晶粒設置在該上重佈線層之該第一面上且與該上重佈線層電連接。被動元件設置在該上重佈線層之該第二面上且與該上重佈線層電連接。主動元件設置在該上重佈線層之該第二面上且與該上重佈線層電連接，其中該主動元件與該被動元件橫向地相鄰，以及該晶粒通過該上重佈線層與該主動元件和該被動元件電連接。

Description

扇出型封裝結構及其製造方法
本申請涉及一種半導體領域，特別是關於一種扇出型封裝結構及其製造方法。
隨著半導體技術的快速發展，對於封裝結構輕薄化的需求逐漸提升。目前，先進封裝主要有兩種發展方向，一是減少封裝面積，使其接近晶片大小，另一種則是將多個晶片整合在同一封裝內，增加封裝內部整合程度。因此，對於多晶片的封裝結構，如何在不增加封裝寬度的前提下實現多個元件之間的電連接，為目前產業界研究的焦點和需解決的技術問題。
有鑑於此，本申請提供一種扇出型封裝結構及其製造方法，以解決上述技術問題。
本申請提供一種扇出型封裝結構及其製造方法，在不增加封裝尺寸的前提下實現多個元件之間的電連接。
在一方面，本申請提供一種扇出型封裝結構，包括：一上重佈線層、一晶粒、一被動元件和一主動元件。上重佈線層包含一第一面和相對該第一面之一第二面。晶粒設置在該上重佈線層之該第一面上且與該上重佈線層電連接。被動元件設置在該上重佈線層之該第二面上且與該上重佈線層電連接。主動元件設置在該上重佈線層之該第二面上且與該上重佈線層電連接，其中該主動元件與該被動元件橫向地相鄰，以及該晶粒通過該上重佈線層與該主動元件和該被動元件電連接。
在一些實施例中，該主動元件在該上重佈線層上的正投影與該晶粒在該上重佈線層上的正投影部分重疊，以及該被動元件在該上重佈線層上的正投影與該晶粒在該上重佈線層上的該正投影重疊。
在一些實施例中，該上重佈線層包含：一第一連接墊、複數個第二連接墊、一第三連接墊、一第一導線和一第二導線。第一連接墊形成在該第一面，配置為與該晶粒連接。複數個第二連接墊形成在該第二面，配置為與該被動元件連接。第三連接墊形成在該第二面，配置為與該主動元件連接。第一導線形成在該上重佈線層內，配置為縱向連接該第一連接墊和該複數個第二連接墊的其中之一。第二導線形成在該上重佈線層內，配置為橫向連接該複數個第二連接墊的其中之一和該第三連接墊。
在一些實施例中，該扇出型封裝結構還包含：一第一絕緣層和一第二絕緣層。第一絕緣層設置該上重佈線層之該第二面上，配置為封裝該被動元件和該主動元件。第二絕緣層設置在該晶粒和該上重佈線層上，配置為封裝該晶粒，其中該第二絕緣層包含一開口，且該晶粒之一表面經由該開口曝露在外部。
在一些實施例中，該扇出型封裝結構還包含：一下重佈線層和一圖案化黏膠層。圖案化黏膠層設置在該下重佈線層上，其中該被動元件和該主動元件之一表面藉由該圖案化黏膠層與該下重佈線層黏接，以及該被動元件和該主動元件之另一表面與該上重佈線層電連接。
在一些實施例中，該扇出型封裝結構還包含：一第一導電柱、一第二導電柱、和一第三導電柱。第一導電柱連接該上重佈線層和該下重佈線層。第二導電柱連接該被動元件和該上重佈線層。第三導電柱連接該主動元件和該上重佈線層，其中該第一導電柱的間距大於或等於該第三導電柱的間距，且該第三導電柱的該間距大於或等於該第二導電柱的間距。
在一些實施例中，該扇出型封裝結構還包含一底膠層，設置在該上重佈線層和該晶粒之間。
在一些實施例中，該扇出型封裝結構還包含一保護環或一保護蓋，設置在該上重佈線層之該第一面上且環繞該晶粒。
在另一方面，本申請還提供一種扇出型封裝結構之製造方法，包含：提供一下重佈線層；形成一被動元件和一主動元件在該下重佈線層上；形成一上重佈線層在該被動元件和該主動元件上，其中該被動元件和該主動元件與該上重佈線層電連接，且該被動元件和該主動元件橫向地相鄰；形成一晶粒在該上重佈線層上，其中該晶粒通過該上重佈線層與該被動元件和該主動元件電連接。
在一些實施例中，在形成該晶粒在該上重佈線層上的步驟中，該晶粒設置為與該主動元件部分重疊以及與該被動元件重疊。
在本申請的扇出型封裝結構及其製造方法中，被動元件可為橋接晶片或者是整合有橋接功能的功能晶片。藉由被動元件可實現晶粒與主動元件之間的訊號傳遞，使得晶粒與主動元件的設置更加彈性和靈活，且不受限於兩者僅僅能採用特定的排列方式。舉例來說，藉由被動元件的設置，使得晶粒與主動元件可設置在不同的水平高度，並且從一俯視視角觀看時，晶粒與主動元件可設置為彼此重疊。因此，在本申請的扇出型封裝結構中，在符合封裝寬度的條件下，藉由被動元件實現了小型化且緊湊設計的多晶片的三維封裝，進而為本申請的扇出型封裝結構在高端產品的應用提供更多的設計靈活性和自由度。
現參考附圖更全面地描述示例實施方式。然而，示例實施方式能夠以多種形式實施，且不應被理解為限於在此闡述的範例。相反，提供這些實施方式使得本申請將更加全面和完整，並將示例實施方式的構思全面地傳達給本領域的技術人員。附圖僅為本申請的示意性圖解，並非一定是按比例繪製。圖中相同的附圖標記表示相同或類似的部分，因而將省略對它們的重複描述。
參照第1圖，其顯示根據本申請第一實施例之扇出型封裝結構之示意圖。扇出型封裝結構10包含下重佈線層(redistribution layer，RDL)110、圖案化黏膠層120、被動元件130、主動元件140、第一絕緣層150、上重佈線層160、晶粒170、底膠層180和第二絕緣層190。
如第1圖所示，下重佈線層110包含第一連接面111和第二連接面112，並且第一連接面111和第二連接面112上皆形成有複數個連接墊。下重佈線層110的第一連接面111通過其對應的連接墊與複數個第一導電柱101電連接，以及下重佈線層110的第二連接面112通過其對應的連接墊與複數個導電端子104電連接。在本實施例中，第一導電柱101的數量為兩個，惟不侷限於此。第一導電柱101可由銅、鋁、錫、金、銀或上述之組合所構成。再者，導電端子104可藉由使用植球製程、電鍍製程或其他合適的製程形成。在一些實施例中，導電端子104是藉由植球製程所形成的焊球，從而降低製造成本並提高製造效率。應當理解的是，根據設計要求，導電端子104可採用其他可能的材料和形狀，不侷限於此。可選地，藉由焊接製程和回焊製程以增強導電端子104和下重佈線層110的對應連接墊之間的接合力。
如第1圖所示，圖案化黏膠層120縱向地設置在下重佈線層110的第一連接面111上，以及被動元件130和主動元件140縱向地設置在圖案化黏膠層120上。被動元件130和主動元件140藉由圖案化黏膠層120與下重佈線層110黏接。具體來說，圖案化黏膠層120包含複數個黏膠單元，且該複數個黏膠單元排列在下重佈線層110的第一連接面111上。被動元件130與其中之一黏膠單元對應設置，以及主動元件140與另一黏膠單元對應設置。藉由圖案化黏膠層120將被動元件130和主動元件140黏接至下重佈線層110。較佳地，圖案化黏膠層120可採用晶片貼膜(die attach film，DAF)，圖案化黏膠層120可有效地增強被動元件130和主動元件140的穩定性，進而避免被動元件130和主動元件140在後續製程時發生位移或脫落。應當注意的是，被動元件130和主動元件140彼此橫向地相鄰，並且兩者設置在一相同或大致相同的水平高度上。此外，被動元件130在遠離圖案化黏膠層120的表面上形成有複數個連接墊和設置在複數個連接墊上的複數個第二導電柱102。相似地，主動元件140在遠離圖案化黏膠層120的表面上也形成有複數個連接墊和設置在複數個連接墊上的複數個第三導電柱103。第二導電柱102和第三導電柱103可由銅、鋁、錫、金、銀或上述之組合所構成。
如第1圖所示，第一絕緣層150縱向地設置在下重佈線層110的第一連接面111、被動元件130和主動元件140上。第一絕緣層150將下重佈線層110的第一連接面111和設置在其上的元件(第一導電柱101、被動元件130和主動元件140)包封，並僅僅曝露出第一導電柱101、第二導電柱102和第三導電柱103之一對應的表面，以用於與後續形成的元件電連接。
如第1圖所示，上重佈線層160縱向地設置在第一絕緣層150之遠離下重佈線層110的表面上。上重佈線層160包含第一面161和相對第一面161之第二面162。上重佈線層160的第一面161形成有複數個第一連接墊163，上重佈線層160的第二面162形成有複數個第二連接墊164和複數個第三連接墊165。上重佈線層160藉由複數個第二連接墊164與被動元件130的第二導電柱102電連接，以及上重佈線層160藉由複數個第三連接墊165與主動元件140的第三導電柱103電連接。再者，上重佈線層160還包含複數個第一導線166和至少一第二導線167。第一導線166和第二導線167皆形成在上重佈線層160的內部，其中第一導線166配置為縱向連接其中之一第一連接墊163和其中之一第二連接墊164，以及第二導線167配置為橫向連接其中之一第二連接墊164和其中之一第三連接墊165。此外，上重佈線層160的內部還設置有至少一第三導線168和一對第四導線169。第三導線168配置為縱向連接其中之一第一連接墊163和其中之一第三連接墊165。第四導線169通過對應的連接墊與第一導電柱101電連接。在本實施例中，透過第二導電柱102和第三導電柱103實現被動元件130和主動元件140與上重佈線層160的電連接，可避免因外部施加應力或製程內含應力，致使低介電係數(low-k)材料與被動元件130和主動元件140的接合界面破裂(cracking)，進而造成導線斷裂和可靠度低之問題。
如第1圖所示，晶粒170縱向地設置在上重佈線層160之第一面161上且與上重佈線層160電連接。晶粒170包含主動面171和相對主動面171的背面172。晶粒170的主動面171上設置有複數個第一凸塊173、複數個第二凸塊174和至少一第三凸塊175。第一凸塊173、第二凸塊174和第三凸塊175的材料可以是或可包括銅、金、鎳、金屬合金等。晶粒170執行覆晶接合以將第一凸塊173、第二凸塊174和第三凸塊175接合到上重佈線層160，以實現晶粒170與上重佈線層160的電連接。具體來說，上重佈線層160設置有突出於第一面161的連接件，且該些連接件與第一面161上的第一連接墊163對應設置。該些連接件亦與晶粒170的該些凸塊對應設置，並且可藉由焊接等技術將連接件與凸塊對應連接。在一些實施例中，上重佈線層160的連接件亦可被省略，以簡化製程和提高生產效率。
如第1圖所示，晶粒170藉由第一凸塊173通過上重佈線層160的第四導線169和第一導電柱101與下重佈線層110電連接。第一凸塊173、第四導線169和第一導電柱101共同形成的路徑作為晶粒170的電源路徑。又，晶粒170藉由第二凸塊174通過重佈線層160的第一導線166和第二導電柱102與被動元件130電連接。第二凸塊174、第一導線166和第二導電柱102共同形成的路徑P1作為晶粒170的主要訊號傳遞路徑。被動元件130藉由第二導電柱102通過上重佈線層160的第二導線167和第三導電柱103與主動元件140電連接。第二導電柱102、第二導線167和第三導電柱103共同形成的路徑P2作為主動元件140的主要訊號傳遞路徑。也就是說，晶粒170與主動元件140之間的主要訊號是藉由路徑P1和路徑P2來傳遞，並且被動元件130作為晶粒170與主動元件140之間的橋接元件。另一方面，晶粒170藉由第三凸塊175通過上重佈線層160的第三導線168和第三導電柱103與主動元件140電連接。第三凸塊175、第三導線168和第三導電柱103共同形成的路徑P3作為主動元件140的接地或是電源傳輸路徑。應當注意的是，路徑P3的數量少於路徑P1的數量。
如第1圖所示，第一凸塊173的間距相近於第一導電柱101的間距W1，第二凸塊174的間距相近於第二導電柱102的間距W2，以及第三凸塊175的間距相近於第三導電柱103的間距W3。對於用於連接不同元件的凸塊與導電柱具有不同的間距(pitch)。舉例來說，第一導電柱101的間距W1或等於第三導電柱103的間距W3，且第三導電柱103的間距W3大於或等於第二導電柱102的間距W2。藉由尺寸最大的第一導電柱101和第一凸塊173縱向地連接晶粒170、上重佈線層160、下重佈線層110，可以有效地降低阻抗、縮短電源路徑和降低功率衰退(power drop)，進而獲得良好的電源完整性能。中間尺寸的第三凸塊175和第三導電柱103為主動元件140提供良好的接地線路。較佳地，第二凸塊174、第二導電柱102、和上重佈線層160的第二連接墊164和第一導線166採用細間距技術來形成。採用細間距技術能使得對應連接的晶片體積縮小和晶片功能增加，以實現在小體積的晶片裡容納更多的I/O端子。在一些實施例中，第二導電柱102的間距W2(細間距)可介於45至50微米之間，或者是小於40微米。
如第1圖所示，底膠層180設置在上重佈線層160和晶粒170之間。具體來說，底膠層180可形成在晶粒170的主動面171和上重佈線層160的上表面161之間的間隙中，且橫向地覆蓋主動面171和上表面161的對應連接件，以增強晶粒170和上重佈線層160之間的接合力和增強接合的可靠性。在一些實施例中，底膠層180可被省略，以簡化製程和提高生產效率。
如第1圖所示，第二絕緣層190縱向地設置在晶粒170和上重佈線層160上，配置為封裝晶粒170。在本實施例中，第二絕緣層190包含一開口，且晶粒170之背面172經由該開口曝露在外部。藉此設計，可有效地提高晶粒170的散熱性能。
在本實施例中，晶粒170可為系統單晶片(system on a chip，SoC)。被動元件130可為橋接晶片或者是整合有橋接功能的功能晶片。主動元件140可為儲存器晶片等，例如非揮發性和/或揮發性儲存器。非揮發性儲存器可包括唯讀儲存器(read only memory，ROM)、可程式化ROM(PROM)、電可程式化ROM(EPROM)、電可擦除可程式化ROM(EEPROM)或快閃儲存器。揮發性儲存器可包括隨機存取儲存器(RAM)等。在本申請中，藉由被動元件130來實現晶粒170與主動元件140之間的訊號傳遞，使得晶粒170與主動元件140的設置更加彈性和靈活，且不受限於兩者僅僅能採用特定的排列方式，如傳統的封裝結構是將所有的主動元件並行地排列在同一層。舉例來說，在本實施例中，藉由被動元件130的設置，使得晶粒170與主動元件140可設置在不同的水平高度，並且從一俯視視角觀看時，晶粒170與主動元件140可設置為彼此重疊。具體來說，晶粒170與主動元件140分別設置在上重佈線層160的相對兩面。並且，主動元件140在上重佈線層160上的正投影141與晶粒170在上重佈線層160上的正投影176部分重疊。在一些實施例中，主動元件140在上重佈線層160上的正投影141亦可設計為與晶粒170在上重佈線層160上的正投影176重疊，即正投影141在正投影176的範圍內。因此，在本申請的扇出型封裝結構10中，在符合封裝寬度的條件下，藉由被動元件130實現了小型化且緊湊設計的多晶片的三維封裝，進而為本申請的扇出型封裝結構10在高端產品的應用提供更多的設計靈活性和自由度。另一方面，在本實施例中，被動元件130在上重佈線層160上的正投影131與晶粒170在上重佈線層160上的正投影176重疊，即正投影131在正投影176的範圍內。藉由被動元件130與晶粒170重疊的設計，可有效地縮短主要訊號的傳遞路徑P1。
在本實施例中，大尺寸的第一導電柱101、被動元件130和主動元件140採用內埋(embedded)式技術設置在扇出型封裝結構10內部，以最大限度地減少了扇出型封裝結構10的外形尺寸，進而保持封裝高度要求。內埋式技術的優點包括可提昇電性、降低雜訊、縮小產品寬度，以及降低成本等。再者，本申請藉由上重佈線層160的精細佈線作為多晶片之間的訊號傳遞路徑，可有效地提高訊號傳遞的速度和縮小佈線面積，進而確保了多晶片之間的電連接，和實現了高電路密度和細間距的設計。另一方面，在傳統的封裝結構，為了避免翹曲的問題，需要在與被動元件130和第一導電柱101相同的層中額外設置無功能之晶粒(dummy die)。相較於傳統的封裝結構，本申請藉由將主動元件140設置在與被動元件130和第一導電柱101相同的層中，可有效地減少無功能之晶粒的數量，並進一步減少第一絕緣層150的材料使用量，同時還解決了扇出型封裝結構10容易發生翹曲的問題。
參照第2A圖至第2L圖，其顯示一系列的剖面圖，用於闡明第1圖的扇出型封裝結構10的製造流程。
如第2A圖所示，提供一載板105，並且在載板105上縱向形成分離層106。分離層106配置為將後續形成的膜層從載板105的表面分離。此外，分離層106還可以為載板105和後續形成的膜層之間提供足夠的結合力(通過黏合和/或其他結合力)，使得後續的膜層可順利形成。
如第2B圖所示，在分離層106遠離載板105的表面上依序形成下重佈線層110和複數個第一導電柱101。下重佈線層110和複數個第一導電柱101的具體結構參照上述，在此不加以贅述。可選地，下重佈線層110可用光刻微影製程來形成，以及第一導電柱101可採用電鍍法來形成。
如第2C圖所示，在下重佈線層110遠離分離層106的表面上縱向形成圖案化黏膠層120，以及在圖案化黏膠層120遠離下重佈線層110的表面上縱向形成複數個被動元件130和複數個主動元件140。被動元件130和主動元件140藉由圖案化黏膠層120與下重佈線層110黏接(bonding)。具體來說，圖案化黏膠層120包含複數個黏膠單元，且該複數個黏膠單元排列在下重佈線層110上。每一被動元件130和每一主動元件140與其中之一黏膠單元對應設置。藉由圖案化黏膠層120將被動元件130和主動元件140黏接至下重佈線層110。較佳地，圖案化黏膠層120可採用晶片貼膜(die attach film，DAF)，圖案化黏膠層120可有效地增強被動元件130和主動元件140的穩定性，進而避免被動元件130和主動元件140在後續製程時發生位移或脫落。如第2C圖所示，在被動元件130和主動元件140遠離下重佈線層110的表面上形成有對應的第二導電柱102和第三導電柱103。被動元件130、主動元件140、第二導電柱102和第三導電柱103的具體結構參照上述，在此不加以贅述。
如第2D圖所示，在下重佈線層110、被動元件130和主動元件140遠離下重佈線層110的表面上縱向形成第一絕緣層150。在此步驟中，第一絕緣層150完全地覆蓋下重佈線層110的表面和被動元件130與主動元件140所有表面，以包封被動元件130和主動元件140。在一些實施例中，第一絕緣層150可以包括藉由模塑製程(molding process)所形成的模塑化合物(molding compound)。可選地，第一絕緣層150可以是由例如是環氧樹脂或其他適宜樹脂等絕緣材料所形成。
如第2E圖所示，對第一絕緣層150施加一薄化製程，以減少第一絕緣層150的厚度和曝露出第一導電柱101、被動元件130上的第二導電柱102和主動元件140上的第三導電柱103之一對應的表面，以用於與後續形成的元件電連接。可選地，薄化製程可藉由使用研磨機來實現。
如第2F圖所示，在第一絕緣層150遠離下重佈線層110的表面上縱向形成上重佈線層160。上重佈線層160包含第一面161和相對第一面161之第二面162。上重佈線層160的第一面161和第二面162形成有複數個連接墊。上重佈線層160藉由對應的連接墊與被動元件130的第二導電柱102和主動元件140的第三導電柱103電連接。再者，上重佈線層160內部形成有多條導線，配置為連接對應的連接墊。上重佈線層160的具體結構參照上述，在此不加以贅述。在本實施例中，上重佈線層160還形成有突出於第一面161的連接件107，且該些連接件107與第一面161上的連接墊對應設置。在一些實施例中，上重佈線層160的連接件107亦可被省略，以簡化製程和提高生產效率。可選地，上重佈線層160可用光刻微影製程來形成。
如第2G圖所示，在上重佈線層160的第一面161縱向形成複數個晶粒170。晶粒170的主動面上形成有複數個凸塊。凸塊的材料可以是或可包括銅、金、金屬合金等。晶粒170採用覆晶接合技術以將凸塊接合到上重佈線層160，以實現晶粒170與上重佈線層160的電連接。晶粒170的具體結構參照上述，在此不加以贅述。應當注意的是，在形成晶粒170在上重佈線層160上的步驟中，晶粒170設置為與對應的主動元件140部分重疊以及與對應的被動元件130重疊。在本實施例中，在上重佈線層160和晶粒170之間還設置有底膠層180。具體來說，底膠層180可形成在晶粒170的主動面和上重佈線層160的上表面161之間的間隙中，且橫向地覆蓋主動面和上表面161的對應連接件，以增強晶粒170和上重佈線層160之間的接合力和增強接合的可靠性。在一些實施例中，底膠層180可被省略，以簡化製程和提高生產效率。
如第2H圖所示，在上重佈線層160的第一面161和晶粒170上縱向形成第二絕緣層190。在此步驟中，第二絕緣層190完全地覆蓋上重佈線層160的第一面161和晶粒170的所有表面，以封裝晶粒170。在一些實施例中，第二絕緣層190可以包括藉由模塑製程(molding process)所形成的模塑化合物(molding compound)。可選地，第二絕緣層190可以是由例如是環氧樹脂或其他適宜樹脂等絕緣材料所形成。
如第2I圖所示，對第二絕緣層190施加一薄化製程，以減少第二絕緣層190的厚度和曝露出晶粒170之背面172。也就是說，在本實施例中，第二絕緣層190包含開口，且晶粒170之背面172經由該開口曝露在外部。藉此設計，可有效地提高晶粒170的散熱性能。可選地，薄化製程可藉由使用研磨機來實現。
如第2J圖所示，藉由分離層106將載板105與下重佈線層110分離。載板105可對其上方形成的元件提供良好的支撐性，以避免在第2A圖至第2I圖對應的步驟中結構發生形變的風險。並且，在第2J圖對應的步驟中將載板105分離，可有效地減少結構整體的厚度。
如第2K圖所示，在下重佈線層110遠離被動元件130和主動元件140的表面縱向形成複數個導電端子104。導電端子104可藉由使用植球製程、電鍍製程或其他合適的製程形成。在一些實施例中，導電端子104是藉由植球製程所形成的焊球，從而降低製造成本並提高製造效率。應當理解的是，根據設計要求，導電端子104可採用其他可能的材料和形狀，不侷限於此。可選地，藉由焊接製程和回焊製程以增強導電端子104和下重佈線層110的對應電接墊之間的接合力。
如第2L圖所示，將第2K圖對應的半成品沿著分離線108斷開，以形成多個獨立的扇出型封裝結構10。可選地，半成品的斷開可藉由切割機來實現。
應當注意的是，根據第2A圖至第2L圖對應的步驟所製造形成的扇出型封裝結構10中，晶粒170可為系統單晶片。被動元件130可為橋接晶片或者是整合有橋接功能的功能晶片。主動元件140可為儲存器晶片等。藉由被動元件130可實現晶粒170與主動元件140之間的訊號傳遞，使得晶粒170與主動元件140的設置更加彈性和靈活，且不受限於兩者僅僅能採用特定的排列方式，如傳統的並行排列。舉例來說，在本實施例中，藉由被動元件130的設置，使得晶粒170與主動元件140可設置在不同的水平高度，並且從一俯視視角觀看時，晶粒170與主動元件140可設置為彼此重疊。具體來說，晶粒170與主動元件140分別設置在上重佈線層160的相對兩面。並且，主動元件140在上重佈線層160上的正投影與晶粒170在上重佈線層160上的正投影部分重疊。在一些實施例中，主動元件140在上重佈線層160上的正投影亦可設計為與晶粒170在上重佈線層160上的正投影重疊，即主動元件140的正投影在晶粒170的正投影的範圍內。因此，在本申請的扇出型封裝結構10中，在符合封裝寬度的條件下，藉由被動元件130實現了小型化且緊湊設計的多晶片的三維封裝，進而為本申請的扇出型封裝結構10在高端產品的應用提供更多的設計靈活性和自由度。另一方面，在本實施例中，被動元件130在上重佈線層160上的正投影與晶粒170在上重佈線層160上的正投影重疊。藉由被動元件130與晶粒170重疊的設計，可有效地縮短主要訊號的傳遞路徑。
參照第3圖，其顯示根據本申請第二實施例之扇出型封裝結構20之示意圖。第二實施例之扇出型封裝結構20與第一實施例之扇出型封裝結構10的結構大致相同，兩者差別在於，第一實施例之底膠層180在第二實施例中被省略，以簡化製程和提高生產效率。再者，在第二實施例之扇出型封裝結構20中，第二絕緣層190形成在晶粒170的主動面和上重佈線層160的上表面之間的間隙中，且橫向地覆蓋晶粒170的主動面和上表面161的對應連接件。因此，藉由第二絕緣層190可實現晶粒170和上重佈線層160的封裝，並增強晶粒170和上重佈線層160之間的接合力和增強接合的可靠性。
參照第4圖，其顯示根據本申請第三實施例之扇出型封裝結構30之示意圖。第三實施例之扇出型封裝結構30與第一實施例之扇出型封裝結構10的結構大致相同，兩者差別在於，第一實施例之第二絕緣層190在第三實施例中被省略，以簡化製程和提高生產效率。再者，在第三實施例之扇出型封裝結構30中，藉由底膠層180可實現晶粒170和上重佈線層160的封裝，並增強晶粒170和上重佈線層160之間的接合力和增強接合的可靠性。在本實施例中，晶粒170的背面可暴露在外部，確保晶粒170具有良好的散熱性能。
參照第5圖，其顯示根據本申請第四實施例之扇出型封裝結構40之示意圖。第四實施例之扇出型封裝結構40與第一實施例之扇出型封裝結構10的結構大致相同，兩者差別在於，第一實施例之第二絕緣層190在第四實施例中被省略，以簡化製程和提高生產效率。並且，第四實施例之扇出型封裝結構40還包含保護蓋191。保護蓋191較佳地以金屬材料製成。保護蓋191縱向地覆蓋住上重佈線層160和晶粒170，以增強扇出型封裝結構40的穩定性，避免翹曲變形。
參照第6圖，其顯示根據本申請第五實施例之扇出型封裝結構50之示意圖。第五實施例之扇出型封裝結構50與第一實施例之扇出型封裝結構10的結構大致相同，兩者差別在於，第一實施例之第二絕緣層190在第四實施例中被省略，以簡化製程和提高生產效率。並且，第五實施例之扇出型封裝結構50還包含保護環192。保護環192較佳地以金屬材料製成。保護環192縱向地設置在上重佈線層160之第一面上且環繞晶粒170。可選地，保護環192沿著上重佈線層160之第一面的外周緣設置，以增強扇出型封裝結構40的穩定性，避免翹曲變形。另一方面，藉由保護環192的設計，使得晶粒170的背面可暴露在外部，確保晶粒170具有良好的散熱性能。
綜上所述，在本申請的扇出型封裝結構及其製造方法中，被動元件130可為橋接晶片或者是整合有橋接功能的功能晶片。藉由被動元件130可實現晶粒170與主動元件140之間的訊號傳遞，使得晶粒170與主動元件140的設置更加彈性和靈活，且不受限於兩者僅僅能採用特定的排列方式，如傳統的並行排列。舉例來說，藉由被動元件130的設置，使得晶粒170與主動元件140可設置在不同的水平高度，並且從一俯視視角觀看時，晶粒170與主動元件140可設置為彼此重疊。因此，在本申請的扇出型封裝結構中，在符合封裝寬度的條件下，藉由被動元件130實現了小型化且緊湊設計的多晶片的三維封裝。也就是說，在不增加封裝尺寸的前提下實現多個元件之間的電連接，進而為本申請的扇出型封裝結構在高端產品的應用提供更多的設計靈活性和自由度。
以上所述僅為本申請的具體實施方式，但本申請的保護範圍並不局限於此，任何所屬技術領域通常知識者在本申請揭露的技術範圍內，可輕易想到變化或替換，都應涵蓋在本申請的保護範圍之內。因此，本申請的保護範圍應以所述申請專利範圍的保護範圍為准。
10、20、30、40、50:扇出型封裝結構 101:第一導電柱 102:第二導電柱 103:第三導電柱 104:導電端子 105:載板 106:分離層 107:連接件 108:分離線 110:下重佈線層 111:第一連接面 112:第二連接面 120:圖案化黏膠層 130:被動元件 131:正投影 140:主動元件 141:正投影 150:第一絕緣層 160:上重佈線層 161:第一面 162:第二面 163:第一連接墊 164:第二連接墊 165:第三連接墊 166:第一導線 167:第二導線 168:第三導線 169:第四導線 170:晶粒 171:主動面 172:背面 173:第一凸塊 174:第二凸塊 175:第三凸塊 176:正投影 180:底膠層 190:第二絕緣層 P1、P2、P3:路徑 W1、W2、W3:間距
第1圖顯示根據本申請第一實施例之扇出型封裝結構之示意圖； 第2A圖至第2L圖顯示一系列的剖面圖，用於闡明第1圖的扇出型封裝結構的製造流程； 第3圖顯示根據本申請第二實施例之扇出型封裝結構之示意圖； 第4圖顯示根據本申請第三實施例之扇出型封裝結構之示意圖； 第5圖顯示根據本申請第四實施例之扇出型封裝結構之示意圖； 第6圖顯示根據本申請第五實施例之扇出型封裝結構之示意圖。
10:扇出型封裝結構
101:第一導電柱
102:第二導電柱
103:第三導電柱
104:導電端子
110:下重佈線層
111:第一連接面
112:第二連接面
120:圖案化黏膠層
130:被動元件
131:正投影
140:主動元件
141:正投影
150:第一絕緣層
160:上重佈線層
161:第一面
162:第二面
163:第一連接墊
164:第二連接墊
165:第三連接墊
166:第一導線
167:第二導線
168:第三導線
169:第四導線
170:晶粒
171:主動面
172:背面
173:第一凸塊
174:第二凸塊
175:第三凸塊
176:正投影
180:底膠層
190:第二絕緣層
P1、P2、P3:路徑
W1、W2、W3:間距

Claims (9)

  1. 一種扇出型封裝結構，包括：一上重佈線層，包含一第一面和相對該第一面之一第二面；一晶粒設置在該上重佈線層之該第一面上且與該上重佈線層電連接；一被動元件，設置在該上重佈線層之該第二面上且與該上重佈線層電連接；以及一主動元件，設置在該上重佈線層之該第二面上且與該上重佈線層電連接，其中該主動元件與該被動元件橫向相鄰，以及該晶粒通過該上重佈線層與該主動元件和該被動元件電連接；以及其中該上重佈線層包含：一第一連接墊，形成在該第一面，配置為與該晶粒連接；複數個第二連接墊，形成在該第二面，配置為與該被動元件連接；一第三連接墊，形成在該第二面，配置為與該主動元件連接；一第一導線，形成在該上重佈線層內，配置為縱向連接該第一連接墊和該複數個第二連接墊的其中之一；一第二導線，形成在該上重佈線層內，配置為橫向連接該複數個第二連接墊的其中之一和該第三連接墊。
  2. 如請求項1的扇出型封裝結構，其中該主動元件在該上重佈線層上的正投影與該晶粒在該上重佈線層上的正投影部分重疊，以及該被動元件在該上重佈線層上的正投影與該晶粒在該上重佈線層上的該正投影重疊。
  3. 如請求項1的扇出型封裝結構，還包含： 一第一絕緣層，設置該上重佈線層之該第二面上，配置為封裝該被動元件和該主動元件；以及一第二絕緣層，設置在該晶粒和該上重佈線層上，配置為封裝該晶粒，其中該第二絕緣層包含一開口，且該晶粒之一表面經由該開口曝露在外部。
  4. 如請求項1的扇出型封裝結構，還包含：一下重佈線層；以及一圖案化黏膠層，設置在該下重佈線層上，其中該被動元件和該主動元件之一表面藉由該圖案化黏膠層與該下重佈線層黏接，以及該被動元件和該主動元件之另一表面與該上重佈線層電連接。
  5. 如請求項4的扇出型封裝結構，還包含：一第一導電柱，連接該上重佈線層和該下重佈線層；一第二導電柱，連接該被動元件和該上重佈線層；以及一第三導電柱，連接該主動元件和該上重佈線層，其中該第一導電柱的間距大於或等於該第三導電柱的間距，且該第三導電柱的該間距大於或等於該第二導電柱的間距。
  6. 如請求項1的扇出型封裝結構，還包含一底膠層，設置在該上重佈線層和該晶粒之間。
  7. 如請求項1的扇出型封裝結構，還包含一保護環或一保護蓋，設置在該上重佈線層之該第一面上且環繞該晶粒。
  8. 一種扇出型封裝結構之製造方法，包含：提供一下重佈線層；形成一被動元件和一主動元件在該下重佈線層上； 形成一上重佈線層在該被動元件和該主動元件上，其中該被動元件和該主動元件與該上重佈線層電連接，且該被動元件和該主動元件橫向地相鄰；以及形成一晶粒在該上重佈線層上，其中該晶粒通過該上重佈線層與該被動元件和該主動元件電連接；以及其中在形成一上重佈線層在該被動元件和該主動元件上的步驟中，該上重佈線層包含一第一面和相對該第一面之一第二面，並且該上重佈線層包含：一第一連接墊，形成在該第一面，配置為與該晶粒連接；複數個第二連接墊，形成在該第二面，配置為與該被動元件連接；一第三連接墊，形成在該第二面，配置為與該主動元件連接；一第一導線，形成在該上重佈線層內，配置為縱向連接該第一連接墊和該複數個第二連接墊的其中之一；一第二導線，形成在該上重佈線層內，配置為橫向連接該複數個第二連接墊的其中之一和該第三連接墊。
  9. 如請求項8的扇出型封裝結構之製造方法，其中在形成該晶粒在該上重佈線層上的步驟中，該晶粒設置為與該主動元件部分重疊以及與該被動元件重疊。
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* Cited by examiner, † Cited by third party
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TW200950049A (en) * 2008-05-28 2009-12-01 Siliconware Precision Industries Co Ltd Semiconductor package device, semiconductor package structure, and method for fabricating the same
TW202105626A (zh) * 2019-07-17 2021-02-01 台灣積體電路製造股份有限公司 封裝結構及形成封裝結構的方法

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