200950049 九、發明說明： 【發明所屬之技術領域】 _· 科明係㈣於—種半導體封I裝置、半導體封裂，士 構及其製法，更詳而言之，係有關於—種具石夕通道⑽ 之半導體封裝裝置、半導體封裝結構及其製法。 【先前技術】 ' J遗Λ電子產T發展以及晶片整合度提高的需求，業 界广展出以&層姓刻技術為基礎的石夕通道技術 €^hr〇ugh-Sii icon Via，TSV)，相關之專利包 請參閱第2人线圖所==5/2,754綠 體裝置之製作流程示意囷如二為干=梦通道之半導 於該晶圓2〇之-表面形成晶圓2〇, 填充金屬材料21，同時於該金屬二：該開孔201中 並藉由黏著材…著於載金=== ❹晶圓2〇進行薄化，以使相對具有該銲墊22 材^另-表面外露出該金屬材料21，同時移除該黏著 該金屬;該載片24,再將半導體晶片30設置於外露出 電性連;^ 21之晶圓2〇表面上’以供該半導體晶片30 複數2至該晶^ 2G，再於該晶圓2G之銲塾22上植設 料凸塊31 ’以供後續電性連接至外界裝置。 有談束=衣法中，於植設辉料凸塊時’係將該晶圓20設 ^體晶片30之一側朝下’而將該晶圓2〇設有該鲜 側朝上’以於該鐸墊22上植設複數鮮料凸塊31， 110800 5 200950049 然而，此時由於該半導體晶片30之厚度大小不同，易使 該晶圓20置放不平整，而導致於進行銲料凸塊製程時造 -成銲料凸塊31植設位置偏移，以及後續欲將該晶圓2〇 進行切單作業時造成切割不易等問題。 因此，如何提出一種具矽通道之半導體封裝裝置及其 製法以克服先前技術之種種缺失，實已成爲目前亟待克服 - 之難題。 【發明内容】 © 鑑於上述習知技術之缺點，本發明之一目的在於提供 -種可提升晶圓置放平整度之半導體封裝裝置、半導體封 裝結構及其製法。 本發明之又-目的在於提供—種 之半導體封裝裝置、半導體封裝結構及其製法。 >本發明之復一目的在於提供一種可避免銲料凸塊植 設位置偏移之半導 导體封裝裝置、半導體封裝結構及其製 ❹ 法。 本發明之再-目的在於提供—種 之半導體封裝裝置、半導體封裝結構及其製法。 半導==一目的在於提供一種可提升散熱效能之 +導體封裝裝置及其製法。 > 述目的’本發明揭露一種半導體封裝裝置之製 法’其步驟係包括：提供一 表 C wafers 具有複數矽基板之晶圓 (wafer)該矽基板具有相對之第一表面及第二表 數矽通道；將複數半導體晶 一 々°又罝於該矽基板之第一表面 110800 6 200950049 上，且電性連接至該矽基板之矽通道；將具有複數開口之 ·*硬質框架設置於該矽基板之第一表面上，且令該半導體晶 *片容置於該開口中；形成封裝膠體於該矽基板之第一表面 上，並包覆該半導體晶片及該硬質框架；以及形成複數導 電元件於該矽基板之第二表面上，且電性連接至該矽通 道。後續製法復包括對該晶圓進行切單作業。 透過前述製法，本發明復揭示一種半導體封裝裝置， 係包括：矽基板，係具有相對之第一表面及第二表面與複 ❹數矽通道，半導體晶片，係設置於該石夕基板之第一表面 上，且電性連接至該矽通道；硬質框架，係具有開口，且 該硬貝框架设置於該石夕基板之第一表面上，以供該半導體 晶片容置於該硬質框架之開口中；封裝膠體，係形成於該 矽基板之第一表面上並包覆該硬質框架及半導體晶片；以 及多數導電元件，係設置於該矽基板之第二表面上，且電 性連接該碎通道。 鵪 另外，亦可揭露一種半導體封裝結構之製法，係包 括：提供一晶圓，該晶圓具有複數矽基板，且該矽基板具 有相對之第一及第二表面與複數矽通道；將半導體晶片接 置於該矽基板之第一表面上，且電性連接至該矽通道；將 具有複數開口之硬質框架設置於該矽基板之第一表面 上，且令該半導體晶片容置於該開口中；於該矽基板之第 表面上形成封裝膠體’以包覆該半導體晶片及該硬質框 架，於該石夕基板之第二表面上形成複數導電元件；以及將 承载件接置並電性連接該導電元件，以供與該半導體晶 110800 7 200950049 片電性連接。 透過剧述製法，本發明另可揭示一種半導體封裝結 -構，係包括：矽基板，係具有相對之第一及第二表面與矽 通道，半導體晶片，係設置於該矽基板之第一表面上，且 電性連接至該石夕通道；硬質框架，係具有開口，該硬質框 架設置於該石夕基板之第一表面上，且供該半導體晶片容置 於j硬質框架之開口中；封裝膠體，係形成於該矽基板之 第一表面上並包覆該硬質框架及該半導體晶片；導電元 ❹件係《λ置於該;^基板之第二表面上，並電性連接至該石夕 通I’以及承載件，係接置並電性連接該導電元件，以供 與該半導體晶片電性連接。 ，因此，本發明之半導體封裝裝置、半導體封裝結構及 其衣法主要係提供具有複數石夕基板之晶圓，該石夕基板具有 相對之第-表面及第二表面，且該梦基板藉由石夕通道技術 $成填充有導電材料之料道，接著，將複數半導體晶片 ❹-又置於該⑦基板之第—表面上且電性連接至财通道， ⑽具有複數開口之硬f框架設置於财基板之第一表 面上，使該半導體晶片容置於該硬質框架之開口中，並於 ^二基板之第—表面上形成包覆該半導體晶片及該硬質 封^膠再於該碎基板之第二表面上形成複數導 ^ 後復可對該晶圓進行切單作業’以分離各該矽 而形成複數具石夕道道之半導體封裝裝置，同時， 板^導綠t封裝裝置可透過該導電元件與可為基板、電路 線架的承载件電性連接，進而形成半導體封裝結 110800 8 200950049 構，亦即，該半導辦 ，植設導電元件時2裝置及半導體封裝結構係於進行 :整度，同時’於進行“ :晶圓置放之平 之支撐作用而平業7該曰曰圓可猎由該封裴膠體 術中因不平整;=置二7單載一 業切割不易蓉門％成钕電兀件植設困難以及於切單作 -晶片周圍，故^提供=，’該硬質框架係環設於該半導體 屬材質之硬質框架復;保護，且藉由金 何體封裝裝置散熱效能。 、*以下係藉由特定的具體實例說明本發明之實施方 沾悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實例加以施行或應用，本說明書中的各項細節亦可 基於不同觀點與應用，在不悖離本發明之精神下進行各種 修飾與變更。 請參閱第1A至1G圖，係顯示本發明之半導體封裝裝 置及其製法之示意圖。 如第1A圖所示’提供一晶圓（wafer)1〇，該晶圓1〇 具有複數矽基板100 ’且該矽基板100具有相對之第一表 面101及第二表面102,其中，該矽基板1〇〇藉由石夕通道 (Through-Silicon Via，TSV)技術形成複數填充有導電材 料之矽通道103，亦即，於該矽基板1〇〇之第二表面1〇2 形成至少一貫穿孔’並於該貫穿孔中填充如銅或錄/金之 導電材料，再藉由研磨作業（Grinding)將該矽基板1〇〇 110800 9 200950049 之第一表面101進行薄化製程，以外露填充於該貫穿孔中 :之導電材料，進而形成矽通道丨03。 接著，提供複數半導體晶片11，以將該半導體晶片 11設置於該矽基板100之第一表面1〇1上，並電性連接 至該矽通道103，而該矽基板1〇〇與該半導體晶片11間 可填充底部填膠111 ’藉以減少該晶圓10與該半導體晶 片11間之相對變形。 如1B及1C圖所示，提供一硬質框架12，該硬質框 〇架12由玻璃材料、金屬材料（如銅金屬等）、熱固性材料 (如聚亞醯胺樹脂（p〇lyimide Resin)、Βτ樹脂 (Bismaleimide Triazine Resin)、& FR_4)等材料所製 成，且該硬質框架12具有複數貫穿開口 121，俾將該$ 質框架12設置於該矽基板1〇〇之第一表面1〇1上且使 該半導體晶片11容置於該硬質框架12之開口 121中，該 半導體晶片11與該硬f框架12相隔有―適當距離之間隙 112 ’而使兩者不致接觸。 如第1D圖所示，於該矽基板丨〇〇之第一表面I"上 =成封裝膠體13,以包覆各該半導體晶片u及該硬質框 架12，同％填充於該半導體晶片11與該硬質框架12 之間隙112。 ” 曰 如第1E圖所示，於該矽基板1〇〇之第二表面IQ?上 形成複數如為録料凸塊之導電元件14’並使該些導電元 件14電性連接至該矽通道1〇3,其中，該晶圓^於進行 銲料凸塊製程時，係將設有該些半導體晶片〇及該硬質 110800 10 200950049 伯木α之矽基板100第一表面ι〇ι -之第二表面102朝上，以於第二表面〗n9 ^矽基板100 14,以#盥j曰~~ 】02上形成導電元件 - 供與该日日圓10電性連接之半導I# θ η n 些料道㈣導電元件14與外:導二片 可藉由該封裝膠體13提供该曰1、電十連接，同時， 风丨/、成日日圓1 〇之平萼疳 知鮮料凸塊製程中不平整之問題。 ；、客 辈，如f 1F圖所示’其後復可對該晶圓10進行切單作 導脚^離各5亥石夕基板100 ’進而形成複數具石夕通道之半 ❹框^ ，亦即，將上述具有半導體晶片η、硬質 封裝膠卿心士 / 使該晶圓10可藉由該 "^ 支撐作用而平穩地置放於該載具，以利於 切d而形成複數半導體封裝裝置。 再者’由於該硬質框架12係環設於該半導體晶片^ : 故可提供该半導體晶片U額外之保護且藉由金 屬^才質之硬質框架12復可提升半導體封裝裝置散熱效 月tl 0 ❹復請參閱第1E及1F圖所示，透過前述製法，本發明 亦揭不種半導體封裝裝置，係包括：石夕基板⑽該石夕 基板刪具有相對之第一及第二表面101，102及石夕通道 103;半導體晶片1卜係設置於該第-表面101上，且電 性連接至該石夕通道103 ;硬質框架12 ’係具有開口 12卜 f硬質框木12設置於該第—表面！ Q i上，且使該半導體 曰曰片11令置δ亥硬質框架丨2之開口 i 2丨中；封裝膠體】3， 係升v成於《亥第一表面！ 〇 j上並包覆該硬質框架^ 2及該半 π 1)0800 200950049 τ祖日日门11 ;以及冬童邋 :面102上。及夕數導電兀件14 ’係設置於該第二表 •:參閱第1G圖所示，係為本發 充本有實導:例大致與上述實施例相同，其差別= 數半導體之梦通道103的梦基板100上，將複 矽通道^， 置於該石夕基板100上並電性連接至該 質框架12且^於該石夕基板1〇0上設置硬質框_ 12，該硬 令功^ /、有開口 121用以容置該半導體晶片11，再於 ❹12之1板刚上形成包覆該半導體晶片11及該硬質框架 作^封裝㈣13,成複料電元件14後對進行切單 ，、錯以分離各該矽基板1〇〇以形成複數 5•各該半導體封裝裝置可透過該導電元件14與；= 導^生連接’進而與該半導體晶片11電性連接以形成半 封裝結構，該承載件15可為基板、電路板或導線架。 =過別述製法，本發明亦揭示—種半導體封裝結構， 二.石夕基板100 ’該石夕基S 1〇〇具有相對之第一及第 :2 101，102及矽通道103;半導體晶片11，係設置於 表面101上，且電性連接至該矽通道1〇3 ;硬質框 :，係具有開口 121，該硬質框架12設置於該 口 上’且使該半導體晶片u容置該硬質框架12之開 勺1中’·封裝膠體13，係形成於該第一表面1〇1上並 广覆讀硬質框架12及該半導體晶片11;多數導電元件 係设置於該第二表面102 ± ’·以及承載件15，係接 w電性連接該導電元件〗4，以供與該半導體晶片11電 η 0800 12 200950049 性連接。 :因此，本發明之半導體封裝裝置、半導體封裝結構及 八；法主要係提供具有複财基板之晶圓财基板具有 相對之第-表面及第二表面，且該石夕基板藉由石夕通道技術 =填充有導電材料之料道，接著，將複數半導體晶片 2置於财基板之第-表面上，且電性連接至㈣通道， •再將具有複數開口之硬質框架設置於料基板之第一表 使該半導體晶片容置於該硬質框架之開口中，並於 之第—表面上形成包覆該半導體晶片及該硬質 ^卞之封裝膠體，再於财基板之第二表面上 導 ^件，其錢可㈣㈣騎切料^分離各該石夕 二：束：而形成複數具石夕道道之半導體封裝裝置，同時， =導體封裝裝置可透過該導電元件與200950049 IX. Description of the invention: [Technical field to which the invention belongs] _· Keming Department (4) in a semiconductor sealing device, semiconductor sealing, and its method of manufacturing, more specifically, related to A semiconductor package device, a semiconductor package structure, and a method of fabricating the same. [Prior Art] 'The development of J's electronic product T and the need for increased wafer integration. The industry has exhibited the Shixi channel technology based on the & layer surname technology. ^^〇ugh-Sii icon Via,TSV) For the related patent package, please refer to the 2nd person line diagram == 5/2, 754 green body device production process is shown as two dry = the dream channel semi-guided on the wafer 2 - surface formation wafer 2 Filling the metal material 21 at the same time in the metal 2: the opening 201 and thinning by means of the adhesive material ... carrying the gold === ❹ wafer 2 以, so as to have the solder pad 22 Excluding the metal material 21 from the surface while removing the adhesion of the metal; the carrier 24, and then placing the semiconductor wafer 30 on the outer surface of the wafer; 30 Complex 2 to the crystal 2G, and then the material bump 31' is implanted on the soldering pad 22 of the wafer 2G for subsequent electrical connection to the external device. In the beaming method, when the solder bump is implanted, the wafer 20 is disposed on the side of the wafer 30 and the wafer 2 is provided with the fresh side facing up. A plurality of fresh bumps 31 are implanted on the mat 22, 110800 5 200950049. However, due to the different thickness of the semiconductor wafer 30, the wafer 20 is easily placed unevenly, resulting in solder bumps. During the manufacturing process, the solder bumps 31 are implanted with a positional offset, and the subsequent cutting of the wafer 2 is difficult to cut. Therefore, how to propose a semiconductor package device having a meandering channel and its manufacturing method to overcome various defects of the prior art has become a problem that needs to be overcome at present. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, it is an object of the present invention to provide a semiconductor package device, a semiconductor package structure and a method of fabricating the same that can improve wafer placement flatness. Still another object of the present invention is to provide a semiconductor package device, a semiconductor package structure, and a method of fabricating the same. A further object of the present invention is to provide a semiconductor package device, a semiconductor package structure and a method of manufacturing the same that can avoid the positional deviation of solder bump implantation. A further object of the present invention is to provide a semiconductor package device, a semiconductor package structure and a method of fabricating the same. The purpose of semi-conducting == one is to provide a +-conductor package device that can improve heat dissipation performance and a method of manufacturing the same. > The present invention discloses a method of fabricating a semiconductor package device. The steps of the method include: providing a wafer of wafers having a plurality of substrates, the substrate having a first surface and a second surface. a channel; a plurality of semiconductor crystals are further disposed on the first surface 110800 6 200950049 of the germanium substrate, and electrically connected to the germanium channel of the germanium substrate; and a hard frame having a plurality of openings is disposed on the germanium substrate Forming, on the first surface, the semiconductor wafer * in the opening; forming an encapsulant on the first surface of the germanium substrate, and covering the semiconductor wafer and the hard frame; and forming a plurality of conductive elements The second surface of the substrate is electrically connected to the channel. Subsequent methods include singulation of the wafer. Through the foregoing method, the present invention further discloses a semiconductor package device comprising: a germanium substrate having opposite first and second surfaces and a plurality of turns, and a semiconductor wafer disposed on the first substrate of the stone substrate Surfacely, and electrically connected to the channel; the rigid frame has an opening, and the hard shell frame is disposed on the first surface of the substrate for the semiconductor wafer to be received in the opening of the rigid frame The encapsulant is formed on the first surface of the germanium substrate and covers the hard frame and the semiconductor wafer; and a plurality of conductive elements are disposed on the second surface of the germanium substrate and electrically connected to the broken channel. In addition, a method for fabricating a semiconductor package structure can also be disclosed, comprising: providing a wafer having a plurality of germanium substrates, wherein the germanium substrate has opposite first and second surfaces and a plurality of germanium channels; Connected to the first surface of the substrate and electrically connected to the channel; a hard frame having a plurality of openings is disposed on the first surface of the substrate, and the semiconductor wafer is received in the opening Forming an encapsulant ' on the first surface of the substrate to cover the semiconductor wafer and the hard frame, forming a plurality of conductive elements on the second surface of the substrate; and connecting and electrically connecting the carrier a conductive element for electrically connecting to the semiconductor wafer 110800 7 200950049. The present invention further discloses a semiconductor package structure comprising: a germanium substrate having opposite first and second surfaces and a meandering channel, and a semiconductor wafer disposed on the first surface of the germanium substrate Upper and electrically connected to the stone channel; the rigid frame has an opening, the hard frame is disposed on the first surface of the stone substrate, and the semiconductor wafer is received in the opening of the j rigid frame; a colloid is formed on the first surface of the crucible substrate and covers the hard frame and the semiconductor wafer; the conductive element is placed on the second surface of the substrate and electrically connected to the stone The illuminating device is connected and electrically connected to the semiconductor device for electrical connection with the semiconductor device. Therefore, the semiconductor package device, the semiconductor package structure, and the clothing method thereof of the present invention mainly provide a wafer having a plurality of slab substrates having opposite first and second surfaces, and the dream substrate is The stone channel technology is filled with a track filled with a conductive material, and then a plurality of semiconductor wafers are placed on the first surface of the 7 substrate and electrically connected to the financial channel, (10) a hard f frame having a plurality of openings On the first surface of the substrate, the semiconductor wafer is received in the opening of the rigid frame, and the semiconductor wafer and the hard seal are formed on the first surface of the substrate and then the broken substrate Forming a plurality of leads on the second surface, and then performing a singulation operation on the wafer to separate the respective ridges to form a plurality of semiconductor package devices having a stone-like circuit, and at the same time, the green-encapsulated device can pass through the substrate The conductive component is electrically connected to the carrier of the substrate and the circuit frame, thereby forming a semiconductor package junction 110800 8 200950049, that is, the semiconductor device, the device and the semiconductor device are provided with 2 devices and a half The body package structure is carried out: the degree of uniformity, and at the same time 'in progress': the support of the flat placement of the wafer and the flat industry 7 the round can be hunted by the seal colloid due to unevenness; = set 2 7 It is difficult to set up a cutting in the industry, and it is difficult to set up the 兀 钕 以及 以及 以及 以及 以及 以及 - - - - - - - - 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 提供 晶片 提供 提供 提供 提供 提供 提供 提供 该 该 该 该 该 该 该 该Other advantages and effects of the present invention can be readily understood by those skilled in the art from this disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. 1G is a schematic view showing a semiconductor package device of the present invention and a method of manufacturing the same. As shown in FIG. 1A, a wafer is provided, which has a plurality of germanium substrates 100' and the germanium substrate 100 The first surface 101 and the second surface 102 are opposite to each other, wherein the 矽 substrate 1 形成 is formed by a Through-Silicon Via (TSV) technology to form a plurality of 矽 channels 103 filled with a conductive material, that is, The second surface 1〇2 of the germanium substrate 1 is formed into at least a uniform via hole and filled with a conductive material such as copper or gold/gold in the through hole, and the germanium substrate is rubbed by a grinding operation (Grinding). The first surface 101 of 110800 9 200950049 is subjected to a thinning process to expose the conductive material filled in the through hole, thereby forming the channel 丨 03. Next, a plurality of semiconductor wafers 11 are provided to set the semiconductor wafer 11 thereon. The first surface 〇1 of the NMOS substrate 100 is electrically connected to the 矽 channel 103, and the 填 substrate 1 〇〇 and the semiconductor wafer 11 can be filled with an underfill 111 ′ to reduce the wafer 10 and the Relative deformation between the semiconductor wafers 11. As shown in FIGS. 1B and 1C, a rigid frame 12 is provided. The rigid frame truss 12 is made of a glass material, a metal material (such as copper metal, etc.), and a thermosetting material (such as p〇lyimide Resin, Βτ). A material such as a resin (Bismaleimide Triazine Resin), & FR_4), and the hard frame 12 has a plurality of through openings 121, and the material frame 12 is disposed on the first surface of the substrate 1〇1〇1 The semiconductor wafer 11 is placed in the opening 121 of the hard frame 12, and the semiconductor wafer 11 is separated from the hard f frame 12 by a gap 112 of an appropriate distance so that the two are not in contact. As shown in FIG. 1D, on the first surface I" of the substrate substrate, the encapsulant 13 is encapsulated to cover each of the semiconductor wafers u and the hard frame 12, and the same is filled in the semiconductor wafer 11 and The gap 112 of the rigid frame 12. As shown in FIG. 1E, a plurality of conductive elements 14', such as recording bumps, are formed on the second surface IQ of the substrate 1A, and the conductive elements 14 are electrically connected to the germanium channel. 1〇3, wherein the wafer is to be provided with a solder bump process, and the semiconductor wafer raft and the first surface of the hard substrate 110800 10 200950049 The surface 102 faces upward, so that the second surface is n9 ^ 矽 the substrate 100 14 , and the conductive element is formed on the # 盥 j 曰 ~ 02 02 - the semi-conducting I# θ η n which is electrically connected to the Japanese yen 10 The material channel (4) conductive element 14 and the outer layer: the two sheets can be provided by the encapsulation colloid 13 to provide the crucible 1 and the electric ten connection, and at the same time, the air enthalpy/, the Japanese yen is 1 〇 萼疳 萼疳 萼疳 萼疳 萼疳 萼疳 凸 凸 凸The problem of unevenness.;, the guest generation, as shown in the figure of f 1F, can be used to sing the wafer 10 as a guide pin and then separate from each of the 5 slabs of the substrate 100' to form a plurality of stone eve channels. The half frame ^, that is, the semiconductor wafer η, the hard-package adhesive, or the wafer 10 can be smoothed by the support function The semiconductor device is mounted on the carrier to facilitate the formation of a plurality of semiconductor package devices. Further, since the rigid frame 12 is provided on the semiconductor wafer, the semiconductor wafer U can be additionally protected by the metal. The rigid frame 12 can improve the heat dissipation efficiency of the semiconductor package device. The first embodiment of the present invention also discloses a semiconductor package device, including: Shixi substrate (10), as shown in FIGS. 1E and 1F. The stone substrate has a first and second surface 101, 102 and a stone channel 103; the semiconductor wafer 1 is disposed on the first surface 101 and electrically connected to the stone channel 103; the rigid frame 12' has an opening 12, and the hard frame 12 is disposed on the first surface! Q i, and the semiconductor chip 11 is placed in the opening i 2 of the hard frame 丨 2; the encapsulant 3 , 升升成成于海第一第一! 〇j and covered the hard frame ^ 2 and the half π 1) 0800 200950049 τ祖日日11; and winter nursery rhyme: face 102. and eve Conductive element 14' is set in the second table.: See Figure 1G. The present invention is substantially the same as the above embodiment, and the difference is the same as the above embodiment, the difference is that the dream substrate 100 of the semiconductor dream channel 103 is placed on the stone substrate 100 and electrically Connected to the material frame 12 and provided with a hard frame _ 12 on the slab substrate 1 , 0, the hard-working device has an opening 121 for accommodating the semiconductor wafer 11 and then on the first 12 of the ❹12 Forming the semiconductor wafer 11 and the hard frame as a package (4) 13, forming a composite electrical component 14 and then performing singulation, and erroneously separating the 矽 substrate 1 〇〇 to form a plurality of 5 The semiconductor device 11 is electrically connected to the semiconductor wafer 11 through the conductive element 14 to form a semi-package structure. The carrier 15 can be a substrate, a circuit board or a lead frame. The method of the present invention also discloses a semiconductor package structure. 2. The stone substrate 100' has a first and a second: 101, 102 and a channel 103; a semiconductor wafer 11, the system is disposed on the surface 101 and electrically connected to the channel 1〇3; the rigid frame has an opening 121, the rigid frame 12 is disposed on the port and the semiconductor wafer u is received in the rigid frame The 'on-package colloid 13' is formed on the first surface 1〇1 and widely covers the hard frame 12 and the semiconductor wafer 11; a plurality of conductive elements are disposed on the second surface 102 ± '· And the carrier member 15 is electrically connected to the conductive member _4 for electrically connecting to the semiconductor wafer 11 η 0800 12 200950049. Therefore, the semiconductor package device, the semiconductor package structure, and the method of the present invention mainly provide a wafer substrate having a complex financial substrate having a first surface and a second surface, and the stone substrate is provided by the stone channel Technology = filled with a conductive material, then the plurality of semiconductor wafers 2 are placed on the first surface of the financial substrate, and electrically connected to the (four) channels, and the hard frame having the plurality of openings is placed on the substrate a semiconductor wafer is placed in the opening of the rigid frame, and a sealing gel covering the semiconductor wafer and the hard surface is formed on the first surface thereof, and then the second surface of the financial substrate is guided , the money can be (4) (4) riding the cutting material ^ separate each of the Xi Xi 2: bundle: and form a plurality of semiconductor packaging devices with Shi Xidao Road, at the same time, = conductor packaging device can pass through the conductive elements and
或導= 承載件電性連接’進而形成半導⑽ 構亦即，本案之半導體封萝_ s 、丄…* A 製法係於進行植設導電元件；* 封裝結構及其 參晶圓晉於夕巫故☆冑件 错由該封裝膠體提供該 " 、’正又，同時，於進行切單作業時該晶圓可藉 以膠體之支㈣用而平穩地置放於十刀單載具上，進 以解決習知技術中因不平整 以及於切置你誓+叫 成導電元件植設困難 設於該半導體Γ片刀二易等問題’再者’該硬質框架係環 1曰Λ 可提㈣㈣體w額外之保 濩’且糟由金屬材質之硬質框 ” 散熱效能。 午復了楗升+導體封裝裝置 上述實施例僅例示性說明本發明之原理及其功效，而 110800 13 200950049 非用於限制本發明。任何熟習此項技藝之人士均可在不違 :背本發明之精神及範訂，對上述實施例進行修倚與改 -變。因此，本發明之權利保護範圍，應如後述之申請 範圍所列。 【圖式簡單說明】 * 第1A至1F圖係為本發明之半導體封裝裝置及其製法 -之示意圖； 八衣/ 第1G圖所示，係為本發明之半導體封裝結構示音 ❹圖；以及 第2A至2E圖係為習知具矽通道之半導體裝置之掣作 /泉程示意圖。 【主要元件符號說明】 10晶圓 石夕基板 1〇1 第一表面 I 〇2 第二表面 !〇3 矽通道 II 半導體晶片 !11 底部填膠 112 間隙 硬質框架 121 開口 13 封裝膠體 14 導電元件 110800 14 200950049 15 承載件 20 晶圓 201 開孔 21 金屬材料 22 銲墊 23 黏著材料 24 載片 30 半導體晶片 〇31 銲料凸塊Or the conduction = the electrical connection of the carrier' to form a semi-conductive (10) structure, that is, the semiconductor encapsulation _ s, 丄 ... * A method of the present invention is used for planting conductive elements; * the package structure and its reference wafers Witch ☆ 胄 错 由 由 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该In order to solve the problem of the irregularity in the conventional technology and the difficulty in planting your oath + called the conductive component, the problem is set in the semiconductor cymbal knives and the other is the 'harder' of the hard frame ring 1 曰Λ can mention (4) (4) The body w is additionally protected and the hard frame made of metal is used for heat dissipation. The midnight recovery + conductor package device The above embodiment only exemplifies the principle and function of the present invention, and 110800 13 200950049 is not used. The present invention is not limited by the spirit and scope of the present invention, and the scope of protection of the present invention should be as described later. The scope of application is listed. BRIEF DESCRIPTION OF THE DRAWINGS * FIGS. 1A to 1F are schematic views of a semiconductor package device and a method of manufacturing the same according to the present invention; and FIG. 1G is a schematic diagram of a semiconductor package structure of the present invention; and 2A to The 2E diagram is a schematic diagram of the fabrication/spring path of a conventional semiconductor device with a channel. [Main component symbol description] 10 wafer lithography substrate 1 〇 1 first surface I 〇 2 second surface! 〇 3 矽 channel II Semiconductor wafer! 11 underfill 112 gap hard frame 121 opening 13 encapsulant 14 conductive element 110800 14 200950049 15 carrier 20 wafer 201 opening 21 metal material 22 pad 23 adhesive material 24 carrier 30 semiconductor wafer 〇 31 solder bump Piece