TWI785590B - 積體電路裝置及其製造方法 - Google Patents

積體電路裝置及其製造方法 Download PDF

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TWI785590B
TWI785590B TW110115993A TW110115993A TWI785590B TW I785590 B TWI785590 B TW I785590B TW 110115993 A TW110115993 A TW 110115993A TW 110115993 A TW110115993 A TW 110115993A TW I785590 B TWI785590 B TW I785590B
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silicon
metal
integrated circuit
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TW202145366A (zh
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蔡昕翰
吳仲強
洪正隆
張文
志安 徐
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台灣積體電路製造股份有限公司
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Abstract

一種積體電路裝置的製造方法，包括形成閘極介電質於半導體區，沉積功函數層於閘極介電質上方，沉積矽層於功函數層上方，以及沉積膠層於矽層上方。功函數層、矽層以及膠層皆為原位沉積。此方法更包括沉積填充金屬於膠層上方；以及執行平坦化處理，其中膠層、矽層以及功函數層之剩餘部分形成閘極電極之部分。

Description

積體電路裝置及其製造方法
本發明實施例是關於半導體製造技術，特別是關於一種金屬閘極調變器之原位形成方法。
金屬氧化物半導體(Metal Oxide Semiconductor；MOS)裝置通常包含金屬閘極，而金屬閘極是為了解決常出現於多晶矽閘極中的多晶空乏效應(poly-depletion effect)。多晶空乏效應發生在施加的電場從閘極區將載子帶往閘極介電質並形成空乏層。在n摻雜的多晶矽層中，空乏層包含離子化後不可移的施子點，而在p摻雜的多晶矽層中，空乏層包含離子化後不可移的受子點。空乏效應將導致有效閘極介電質厚度的增加，使在半導體表面生成反轉層變得更加困難。
金屬閘極可包含多個膜層，從而滿足NMOS裝置與PMOS裝置的不同需求。金屬閘極的形成通常涉及移除堆疊的虛置閘極以形成溝槽，沉積多個延伸到溝槽中的金屬層，形成填充其餘溝槽部分的金屬區，接著執行化學機械拋光(Chemical Mechanical Polish；CMP)處理去除多餘的金屬層部分。剩餘的金屬層與金屬區便形成金屬閘極。
本發明實施例提供一種積體電路裝置的製造方法，包括：形成第一閘極介電質於第一半導體區；沉積第一功函數層於第一閘極介電質上方；沉積第一矽層於第一功函數層上方；沉積第一膠層於第一矽層上方，其中第一功函數層、第一矽層以及第一膠層為原位沉積；沉積第一填充金屬於第一膠層上方；以及執行平坦化處理，其中第一膠層、第一矽層以及第一功函數層之剩餘部分形成閘極電極之部分。
本發明實施例提供一種積體電路裝置，包括：半導體區；閘極介電質，於半導體區上方；功函數層，於閘極介電質上方；矽層，於功函數層上方；膠層，於矽層上方並接觸矽層；以及填充金屬區，於膠層上方並接觸膠層。
本發明實施例提供一種積體電路裝置，包括：半導體鰭片；高介電常數介電質，在半導體鰭片之上；功函數層，於高介電常數介電質上方；第一氮化鈦層，於功函數層上方；矽層，於第一氮化鈦層上方；第二氮化鈦層，於矽層上方，其中在矽層與第二氮化鈦層之間的界面不含氧；以及填充金屬區，於第二氮化鈦層上方並接觸第二氮化鈦層。
10:晶圓
20:基板
22:井區
24:淺溝槽隔離區
24A:淺溝槽隔離區的頂表面
24’/124’/224’/324’:凸出的半導體鰭片
26:半導體條
28:墊氧化層
30:硬遮罩層
36:鰭片
38/138/238/338:虛置閘極堆疊
40/140/240/340:虛置閘極介電質
42/142/242/342:虛置閘電極
44/144/244/344:硬遮罩層
46/146/246/346:閘極間隔物
50:凹槽
54/154/254/354:磊晶區
56:孔洞
58:接觸蝕刻停止層
60:層間介電質
61/161/261/361:閘極介電質
62/162/262/362:溝槽
64/164/264/364:界面層
66/166/266/366:高介電常數介電層
68/168/268/368:第一含金屬層
70/170/370:第一蝕刻遮罩
72/172/272/372:第二含金屬層
74/174/274:第二蝕刻遮罩
76/176/276/376:功函數層
78/178/278/378:蓋層
80/180/280/380:矽層
82/182/282/382:膠層
83/183/283/383:填充金屬區
84/184/284/384:閘極堆疊
86/186/286/386:閘電極
88/188/288/388:自對準硬遮罩
94/194/294/394:閘極接觸插塞
95/195/295/395:矽化物區
96/196/296/396:源極/汲極接觸插塞
98/198/298/398:鰭式場效電晶體
100/200/300:裝置區
由以下的詳細敘述配合所附圖式，可最好地理解本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用於說明。事實上，可任意地放大或縮小各種元件的尺寸，以清楚地表現出本發明實施例之特徵。
第1-6圖、第7A圖、第7B圖、第8A圖、第8B圖、第9-18圖、第19A圖和第19B 圖是根據本發明的一些實施例，繪示出形成鰭式場效電晶體(Fin Field-Effect Transistors；FinFETs)中間過程的透視示意圖與剖面示意圖。
第20圖是根據一些實施例繪示形成閘極堆疊後的依時性介電質崩潰(Time-Dependent Dielectric Breakdown；TDDB)數據。
第21圖是根據一些實施例的閘極堆疊繪示一些元素的範例分佈輪廓。
第22圖是根據一些實施例繪示形成鰭式場效電晶體的方法流程圖。
應理解的是，以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，元件的尺寸不限於所揭露的範圍或數值，而可依製程情況及/或所欲的裝置特性而定。此外，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。為了簡單和清楚起見，可按不同比例任意繪製各種部件。
再者，其中可能用到與空間相對用詞，例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
以下提供具有改善電晶體可靠度的金屬閘極形成方法的一些實施例。這些實施例中說明了形成電晶體的中間過程。也討論了實施例的一些變化型。在各種視圖和例示性實施例中，相似的元件符號用來表示相似的元件。在一些實施例中，鰭式場效電晶體的形成用來作為解釋本揭露概念的範例。其他類型的電晶體，諸如平面電晶體(planar transistors)、全繞式閘極(Gate-All-Around；GAA)電晶體或其他類似的電晶體，同樣也可採用本揭露的概念來形成。本說明書所討論的實施例是為了作為範例以進行或使用本揭露的主題，並且在本技術領域之通常知識者將容易理解可進行的修改，而仍保持在不同實施例的預期範圍內。儘管所討論的一些實施例以特定順序的步驟執行，這些步驟仍可以另一合乎邏輯的順序執行。
根據一些實施例，帶有功函數層的金屬閘極被用於形成電晶體。並且會在功函數層的頂部上添加蓋層和矽層以減少功函數層的氧化。由於當矽層暴露在空氣中時很可能會被氧化，因此功函數層、蓋層、矽層和在矽層上方的膠層皆為原位形成，即在形成的過程間沒有破真空，從而減少或消除了矽層的氧化。閘極的接觸電阻便因此降低。此外，在功函數層下方的閘極介電質，其可靠度也因而被改善。
第1-6圖、第7A圖、第7B圖、第8A圖、第8B圖、第9-18圖、第19A圖和第19B圖說明了根據本揭露內容之一些實施例形成鰭式場效電晶體中間過程的剖面示意圖和透視示意圖。這些圖所展示的過程同樣地也對應到第22圖的方法流程圖400中。
在第1圖中提供了基板20。基板20可以是半導體基板，例如塊體半導體(bulk semiconductor)基板、絕緣體上覆半導體 (Semiconductor-On-Insulator；SOI)基板或其他類似的基板，並且可被摻雜(例如用p型或n型摻質)或無摻雜。半導體基板20可以是晶圓10的一部分。一般來說，絕緣體上覆半導體基板是一層形成在絕緣層上的半導體材料。絕緣層可以是埋藏氧化物(Buried Oxide；BOX)層、氧化矽層或其他類似材料。絕緣層通常設置在矽或玻璃基板上。其他也可使用像是多層(multi-layered)或梯度(gradient)基板。在一些實施例中，半導體基板20的半導體材料可包括矽；鍺；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦的化合物半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半導體；或上述之組合。
進一步參見第1圖，井區22形成在基板20中。在第22圖所繪示的方法流程圖400中，相對應的流程為402。根據一些實施例，井區22是透過佈植硼、銦或其他p型雜質到基板20中形成p型井區。根據其他實施例，井區22是透過佈植磷、砷、銻或其他n型雜質到基板20中形成n型井區。所得的井區22可延伸到基板20的頂表面。n型或p型的摻雜濃度可小於等於1018cm-3，例如摻雜濃度範圍為約1017cm-3至約1018cm-3。
參見第2圖，隔離區24從基板20的頂表面延伸形成到基板20中。在下文中，隔離區24也被稱為淺溝槽隔離(Shallow Trench Isolation；STI)區。在第22圖所繪示的方法流程圖400中，相對應的流程為404。基板20在淺溝槽隔離區24之間相鄰的部分被稱為半導體條(semiconductor strips)26。為了形成淺溝槽隔離區24，形成墊氧化層28和硬遮罩層30於半導體基板20上，並對其進行圖案化。墊氧化層28可以是由氧化矽形成的薄膜。根據一些實施例，利用熱氧化製程將半導體基板20的頂表面層氧化形成墊氧化層28。墊氧化層28可當作半 導體基板20與硬遮罩層30之間的附著層。墊氧化層28也可當作蝕刻硬遮罩層30的蝕刻停止層。根據一些實施例，硬遮罩層30是由氮化矽形成，其使用例如低壓化學氣相沉積(Low-Pressure Chemical Vapor Deposition；LPCVD)的製程。根據其他實施例，硬遮罩層30是使用電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition；PECVD)的製程。在硬遮罩層30上形成光阻(未繪示)並進行圖案化。利用圖案化後的光阻作為硬遮罩層30的蝕刻遮罩以形成如第2圖所繪示的硬遮罩層30。
接著，利用圖案化後的硬遮罩層30作為墊氧化層28和基板20的蝕刻遮罩，隨後用介電材料填充基板20中蝕刻形成的溝槽。執行諸如化學機械拋光或機械研磨(mechanical grinding)之類的平坦化處理以去除多餘的介電材料部分，剩餘的介電材料部分便成為淺溝槽隔離區24。淺溝槽隔離區24可包含透過熱氧化基板20的表面層而形成的熱氧化物襯(liner)介電質(未繪示)。襯介電質也可以是沉積的氧化矽層、氮化矽層、或使用例如原子層沉積(Atomic Layer Deposition；ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition；HDPCVD)、化學氣相沉積(Chemical Vapor Deposition；CVD)或其他類似方法形成的介電質。淺溝槽隔離區24還包括在襯氧化物上方的介電質材料，像是利用可流動化學氣相沉積(Flowable Chemical Vapor Deposition；FCVD)、旋塗或其他類似方法形成的介電質材料。在一些實施例中，襯介電質上的介電質材料可包括氧化矽。
硬遮罩層30的頂表面和淺溝槽隔離區24的頂表面大致上彼此齊平。半導體條26位在相鄰的淺溝槽隔離區24之間。根據一些實施例，半導體條26是原始基板20的一部分，因此半導體條26與基板20的材料相同。在替代實施 例中，半導體條26的形成是透過蝕刻淺溝槽隔離區24之間的基板20部分以形成凹槽，並且在凹槽中進行磊晶生長其他半導體材料。因此，半導體條26便會由不同於基板20的半導體材料形成。根據一些實施例，半導體條26由矽鍺、碳化矽或III-V族化合物半導體材料形成。
參見第3圖，淺溝槽隔離區24被凹蝕，於是比淺溝槽隔離區24其餘部分的頂表面24A高的半導體條26的頂表面部分便形成突出鰭片36。在第22圖所繪示的方法流程圖400中，相對應的流程為406。此處的蝕刻可使用乾式蝕刻製程進行，例如將HF3和NH3用作蝕刻氣體。在蝕刻過程中，可產生電漿。也可包括氬氣。根據替代實施例，淺溝槽隔離區24的凹槽是利用濕式蝕刻製程進行。蝕刻化學品例如可包含HF。
一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距更小的圖案。例如，在一實施例中，在基板上方形成犧牲層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。之後去除犧牲層，然後可以使用剩餘的間隔物或心軸作為遮罩以圖案化鰭片。
參見第4圖，虛置閘極堆疊38延伸形成在凸出鰭片36的頂表面與側壁上。在第22圖所繪示的方法流程圖400中，相對應的流程為408。虛置閘極堆疊38可包括虛置閘極介電質40與在虛置閘極介電質40上方的虛置閘電極42。虛置閘電極42可使用例如多晶矽或是其他材料形成。每個虛置閘極堆疊38還可包括在虛置閘電極42上方的一個(或多個)硬遮罩層44。硬遮罩層44可由單層氮化矽、氧化矽、碳氮化矽或其多層形成。虛置閘極堆疊38可跨過單個或多個突出鰭片36和/或淺溝槽隔離區24。虛置閘極堆疊38的縱長方向還與突出鰭片36 的縱長方向相互垂直。
接下來，在虛置閘極堆疊38的側壁上形成閘極間隔物46。在第22圖所繪示的方法流程圖400中，相對應的流程為408。根據一些實施例，形成閘極間隔物46的介電材料可以是氮化矽、碳氮化矽或其他類似材料，並且可以是包括多個介電層的單層或多層結構。
接著對突出鰭片36進行蝕刻製程以蝕刻未被虛置閘極堆疊38和閘極間隔物46覆蓋的部分，如第5圖的結構所繪示。在第22圖所繪示的方法流程圖400中，相對應的流程為410。由於凹蝕可以是非等向性，位於虛置閘極堆疊38和閘極間隔物46正下方的鰭片36部分便能受到保護，不會被蝕刻。根據一些實施例，凹蝕後半導體條26的頂表面可低於淺溝槽隔離區24的頂表面24A。因而形成了凹槽50。凹槽50包括的部分有位於虛置閘極堆疊38另一側的部份以及位於突出鰭片36之間的剩餘部分。
接下來，在凹槽50中選擇性生長(透過磊晶方式)半導體材料來形成磊晶區(源極/汲極區)54，如第6圖的結構所繪示。在第22圖所繪示的方法流程圖400中，相對應的流程為412。在磊晶的進行過程中，可以原位摻雜p型或n型雜質，並根據摻雜的雜質來決定是p型還是n型的鰭式場效電晶體。例如，當所得的是p型鰭式場效電晶體時，可以生長矽鍺硼(SiGeB)、矽硼(SiB)或其他p型雜質。相反的，當所得的是n型鰭式場效電晶體時，可以生長矽磷(SiP)、矽碳磷(SiCP)或其他n型雜質。根據替代實施例，磊晶區54包括III-V族的化合物半導體，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、及上述之單層或多層的組合。在凹槽50被磊晶區54填滿之後，磊晶區54還會進一步磊晶生長造成磊晶區54的水平擴展，並形成刻面。磊晶區54的進一 步生長可引起相鄰磊晶區54的彼此合併。產生孔洞(氣隙)56。根據一些實施例，磊晶區54可以選擇在磊晶區54的頂表面仍然是波浪形時，或當合併後磊晶區54的頂表面已經變得平坦時停止生長，如第6圖所繪示之磊晶區54的進一步生長。
在磊晶製程之後，便進一步向磊晶區54佈植p型或n型雜質以形成源極區和汲極區，元件符號54也可表示源極區和汲極區。根據替代實施例，若在磊晶期間磊晶區54已原位摻雜p型或n型雜質，可跳過此佈植步驟。
第7A圖繪示出形成接觸蝕刻停止層(Contact Etch Stop Layer；CESL)58和層間介電質(Inter-Layer Dielectric；ILD)60後的結構透視示意圖。在第22圖所繪示的方法流程圖400中，相對應的流程為414。接觸蝕刻停止層58的形成可以由氧化矽、氮化矽、碳氮化矽或其他類似材料，並使用化學氣相沉積、原子層沉積或其他類似方法形成。層間介電質60可以是由可流動化學氣相沉積、旋塗、化學氣相沉積或其他類似方法形成的介電材料。層間介電質60可由含氧的介電材料形成，其可以是以氧化矽為主的材料，例如氧化矽、磷矽玻璃(Phospho-Silicate Glass；PSG)、硼矽玻璃(Boro-Silicate Glass；BSG)、硼磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)或其他類似材料。可加入諸如化學機械拋光或機械研磨之類的平坦化處理，以使層間介電質60、虛置閘極堆疊38和閘極間隔物46的頂表面能彼此齊平。
第7B圖繪示出在同一基板20上形成的第一、第二和第三鰭式場效電晶體(第19A圖中的198、298和398)中間過程的結構剖面示意圖。此處僅以鰭式場效電晶體為範例，其他類型的電晶體，例如奈米片(nano-sheet)電晶體、奈米線(nano-wire)電晶體、平面電晶體、全繞式閘極電晶體或其他類似 電晶體，也可透過應用本揭露的概念來形成。根據一些實施例，第一、第二和第三鰭式場效電晶體分別形成在裝置區100、200和300中。根據一些實施例，此處的三個鰭式場效電晶體範例為n型鰭式場效電晶體。根據替代實施例，三個鰭式場效電晶體為p型鰭式場效電晶體。又根據其他實施例，三個鰭式場效電晶體為包含任何組合的n型和p型鰭式場效電晶體之混合。第一、第二和第三鰭式場效電晶體中的任一個剖面示意圖可對應第7A圖中包含7B-7B線的垂直平面。
為了區分第一、第二和第三鰭式場效電晶體中的部件，在裝置區100中的部件可用第7A圖中對應部件的附圖標記加上數字100來表示，在第7B圖中裝置區200中的部件可用第7A圖中對應部件的附圖標記加上數字200來表示。同樣地，在裝置區300中第三鰭式場效電晶體的部件可用第7A圖中對應部件的附圖標記加上數字300來表示。例如，第7B圖中的源極/汲極區154、254和354對應第7A圖中的源極/汲極區54，而第7B圖中的閘極間隔物146、246和346對應第7A圖中的閘極間隔物46。裝置區100、200和300中的對應部件可透過共同製程來形成，其中一些示範製程會在稍後的段落討論，或者由分開的製程形成。
在形成第7A圖和第7B圖所繪示的結構之後，第7B圖中的虛置閘極堆疊138、238和338被替換為金屬閘極和替代的閘極介電質如第8A圖、第8B圖和第9-18圖所繪示。在這些附圖中，繪示出淺溝槽隔離區24的頂表面24A，且突出的半導體鰭片124'、224'和324'皆各自高於相鄰淺溝槽隔離區24的頂表面24A。
為了形成替換的閘極，首先移除如第7A圖和第7B圖所繪示的硬遮罩層144、244和344、虛置閘電極142、242和342以及虛置閘極介電質140、240和340，並形成如第8A圖所繪示的溝槽62。在第22圖所繪示的方法流程圖400中， 相對應的流程為416。如第8B圖所繪示，第8A圖中的溝槽62對應於裝置區100中的溝槽162、裝置區200中的溝槽262和裝置區300中的溝槽362。突出鰭片124’、224’和324’的頂表面和側壁分別暴露於溝槽162、262和362中。
接著參見第9圖，形成閘極介電質161、261和361，其分別延伸至溝槽162、262和362中。在第22圖所繪示的方法流程圖400中，相對應的流程為418。根據一些實施例，閘極介電質包括界面層(Interfacial Layers；ILs)164、264和364，各別形成在突出鰭片124'、224'和324'的暴露表面上。每個界面層164、264和364中可包括諸如氧化矽層的氧化物層，其可透過熱氧化突出鰭片124'、224'和324'、化學氧化製程或沉積製程形成。閘極介電質還可包括在對應的界面層164、264和364上方的高介電常數介電層166、266和366。每一個高介電常數介電層166、266和366可由氧化鑭、氧化鉿、氧化鋁、氧化鋯或其他類似材料形成。高介電常數介電質材料的介電常數(k值)高於3.9，且可高於約7.0。高介電常數介電層166、266和366覆蓋並可接觸相應下方的界面層164、264和364。高介電常數介電層166、266和366作為保形層，並且分別延伸至突出鰭片124'、224'和324'的側壁以及閘極間隔物146、246和346的頂表面和側壁。根據一些實施例，高介電常數介電層166、266和366使用原子層沉積或化學氣相沉積形成。高介電常數介電層166、266和366可以是相同介電層的一部分，且同時使用相同的材料形成並具有相同的厚度，或分開使用不同的材料和/或不同的厚度來形成。
第9圖進一步說明第一含金屬層168、268和368的形成，其可在共同的沉積製程(且可以是同一毯覆層的多個部分)或單獨的沉積製程中形成。在第22圖所繪示的方法流程圖400中，相對應的流程為420。覆蓋層延伸到p型鰭式場效電晶體區中的部分可作為p型鰭式場效電晶體的功函數層。根據一些實施 例，含金屬層168、268和368包括氮化鈦、氮化鉭或其類似物。含金屬層168、268和368可使用諸如原子層沉積、化學氣相沉積或其他保形(conformal)沉積方法來形成。含金屬層168、268和368的厚度T1厚度範圍為約5埃至約50埃。
第10圖展示了第一蝕刻遮罩的形成，包括分別在裝置區100和300中的蝕刻遮罩(部分)170和370。在第22圖所繪示的方法流程圖400中，相對應的流程為422。根據一些實施例，蝕刻遮罩170和370包含底部抗反射塗層(Bottom Anti-Reflective Coatings；BARCs)和在底部抗反射塗層上的光阻層。硬遮罩(未繪示)可以在或不在底部抗反射塗層的下方形成。根據一些實施例，在金屬氧化物層上方的硬遮罩可包括金屬氧化物層諸如氧化鋁層，以及金屬氮化物層諸如氮化鈦層。含金屬層268經由蝕刻遮罩露出。
經過蝕刻製程去除暴露的含金屬層268，且蝕刻後暴露出高介電常數介電層266。在第22圖所繪示的方法流程圖400中，相對應的流程為424。蝕刻後的結構如第11圖所繪示。根據一些實施例，此處為利用濕式蝕刻製程執行含金屬層268的蝕刻，而此處也可以使用乾式蝕刻製程。
接下來，移除蝕刻遮罩170和370。移除的結構如第12圖所繪示。根據一些實施例，可透過灰化或使用包括氫氣(H2)和氮氣(N2)的蝕刻氣體來去除光阻。硬遮罩(如果有)的移除可使用蝕刻化學品，其可包含氫氧化銨、過氧化氫鹽酸、碳酸或其類似物。
第13圖至第15圖分別繪示在電晶體區100和200中形成第二含金屬層172和272。參見第13圖，例如利用共同沉積製程形成的含金屬層172、272和372。在第22圖所繪示的方法流程圖400中，相對應的流程為426。第二含金屬層172、272和372所使用的材料可與第一含金屬層168相同。第二含金屬層172、 272和372的厚度T2可與第一含金屬層168相同。厚度T2可大於、等於或小於第一含金屬層168的厚度T1，取決於裝置區100和200中想要調整的電晶體臨界電壓大小。例如根據一些實施例，厚度比T1/T2的範圍為約0.5至約2.0。
第14圖繪示了第二蝕刻遮罩的形成，包括分別在裝置區100和200中的蝕刻遮罩174和274，並皆以共同的沉積製程與共同的微影製程形成。在第22圖所繪示的方法流程圖400中，相對應的流程為428。蝕刻遮罩174和274的材料、結構和形成方法可從蝕刻遮罩170和370(第10圖)的候選材料、結構和形成方法中來選擇。在隨後的製程中，含金屬層372和368會透過蝕刻製程去除。在第22圖所繪示的方法流程圖400中，相對應的流程為430。在蝕刻製程期間，蝕刻遮罩174和274被用來保護裝置區100中的含金屬層168和172以及裝置區200中的含金屬層272。蝕刻遮罩174和274隨後被移除，移除後的結構如第15圖所繪示。含金屬層372和368的蝕刻製程類似於含金屬層268的蝕刻製程(第10圖和第11圖)，此處不再贅述。
如先前進行的圖案化製程所繪示，第一含金屬層368的蝕刻將用與第二含金屬層372相同的蝕刻製程(第15圖)來進行，而不是用蝕刻第一含金屬層268的製程(第11圖)。這具有使高介電常數介電層366暴露於蝕刻化學品的次數從兩次降至一次的有利特徵。這將減少高介電常數介電層366因含金屬層的過度蝕刻而受到的損害。高介電常數介電層366因而被暴露，如第15圖所繪示。
接下來，將沉積多個膜層以填充溝槽162、262和362，所得的結構如第16圖所繪示。多個堆疊的膜層包括功函數層76、蓋層78、矽層80以及膠層82。在第22圖所繪示的方法流程圖400中，相對應的流程為432。堆疊的膜層76、78、80和82為在相同的生產設備中進行原位沉積，其間沒有破真空。換句 話說，從第一時間開始沉積功函數層76一直到第二時間完成沉積膠層82的整段期間，晶圓10一直處於真空環境中而沒有破真空。此外，在第一時間和第二時間的整段期間，晶圓10並沒有暴露在諸如O2、O3或其他含氧氣體中，也不暴露於水蒸氣中。另一方面，堆疊膜層與第二含金屬層172和272可以是異位形成，即在它們之間存在著破真空。功函數層76、蓋層78、矽層80和膠層82的每一個都包括了裝置區100、200和300中的部分。功函數層76包括176、276和376部分。蓋層78包括178、278和378部分。矽層80包括180、280和380部分。膠層82包括182、282和382部分。
根據一些實施例，功函數層76，包括分別在裝置區100、200和300中的176、276和376部分，是使用原子層沉積、化學氣相沉積或其他類似方法沉積。使用的材料可包括以鋁為主的層，可由作為n型功函數的材料包括TiAl、TiAlN、TiAlC、TaAlN、TaAlC或其他類似材料形成。根據一些實施例，功函數層76的厚度範圍為約15埃至約50埃。
根據一些實施例，蓋層78，包括分別在裝置區100、200和300中的178、278和378部分，被沉積在功函數層76上方。蓋層78可由包括TiN、TaN或其他類似材料形成，可使用諸如原子層沉積、化學氣相沉積或其他類似方法沉積。蓋層78的厚度可小於約10埃。
接著，矽層80，包括分別在裝置區100、200和300中的180、280和380部分，被沉積在蓋層78上方。根據一些實施例，執行矽層的沉積引入了以矽為主的前驅物製程氣體諸如矽烷(SiH4)、乙矽烷(Si2H6)或它們的組合到各自的生產設備中。諸如Ar、He、N2或其他類似氣體也可加到製程氣體中。此段製程包括了熱浸，其中熱浸的溫度範圍為約300℃至約500℃。熱浸製程的持 續時間範圍為約0.5分鐘至約3分鐘。在熱浸製程中，以矽為主的前驅物之分壓範圍為約10托至約35托。所得的矽層80厚度可小於約12埃，且厚度範圍為約5埃至約12埃。初沉積的矽層80可包括沒有與其他元素形成化合物的元素態矽原子，且矽層80中矽原子的原子百分比可大於約90%，或者原子百分比的範圍為約95%至約100%。
接下來，在矽層80形成後且沒有破真空的情況下，繼續形成膠層82。根據一些實施例，膠層82包括TiN、TaN或其他類似材料。形成的製程可包括原子層沉積、化學氣相沉積或其他類似方法。膠層82的厚度可小於25埃，也可小於約20埃。根據一些實施例，膠層82的厚度範圍為約8埃至約20埃。形成膠層82的製程中並未使用含氧的製程氣體。
第17圖繪示了填充金屬區183、283和383的沉積。在第22圖所繪示的方法流程圖400中，相對應的流程為434。在膠層82與填充金屬區183、283和383的形成間可能會或不會破真空。根據一些實施例，填充金屬區183、283和383是由鎢、鈷或其他類似材料形成，可使用原子層沉積、化學氣相沉積或其他類似方法來沉積。根據一些實施例，填充金屬區183、283和383由鎢(W)或包含鎢(W)的材料形成。形成填充金屬區183、283和383的前驅物可包括WF6和諸如H2的還原劑。根據一些實施例，填充金屬區183、283和383是使用原子層沉積形成，原子層沉積製程可包括多個原子層沉積的循環，每個循環包括導入WF6、排出WF6、導入H2和排出H2。沉積製程為在高溫下執行的熱處理，例如溫度範圍為約250℃至約400℃。根據替代實施例，填充金屬區183、283和383的沉積是利用化學氣相沉積，使用例如WF6和H2作為製程氣體。根據一些實施例，填充金屬區183、283和383都分別延伸至各個溝槽162、262和362(第16圖)的未 填充部分中。根據替代實施例，在形成蓋層82之後，溝槽162或者溝槽162和262都被完全填充，因此填充金屬區183或者填充金屬區183和283完全在相應的溝槽162和262之外。
在溝槽被完全填充之後，會執行平坦化處理以去除數個膜層的多餘部分，從而形成如第18圖所繪示的閘極堆疊184、284和384。在第22圖所繪示的方法流程圖400中，相對應的流程為436。閘極堆疊184、284和384分別包含閘電極186、286和386。
根據一些實施例，第19A圖繪示了自對準硬遮罩188、288和388的形成，其包括執行蝕刻製程以將閘極堆疊184、284和384凹蝕形成凹槽。接著用介電質材料填充凹槽，並進行平坦化處理以去除介電質材料的多餘部分，其餘的介電質材料便形成硬遮罩188、288和388。硬遮罩188、288和388可由氮化矽、氮氧化矽、氮碳氧化矽或其類似材料形成。
進一步參見第19A圖，形成矽化物區195、295和395以及源極/汲極接觸插塞196、296和396以分別電性連接到源極/汲極區154、254和354。形成閘極接觸插塞194、294和394以分別電性連接到閘電極186、286和386。因此鰭式場效電晶體198、298和398便分別在裝置區100、200和300中形成。
第19B圖繪示了鰭式場效電晶體98的透視示意圖，可代表第19A圖所繪示的鰭式場效電晶體198、298和398。此處也繪示了閘極接觸插塞94(在第19A圖為194、294和394)、源極/汲極矽化物區95(在第19A圖為195、295和395)和源極/汲極接觸插塞96(在第19A圖為196、296和396)。
電晶體198、298和398能具有不同的臨界電壓，可歸因於下層相應的功函數層所引起的調諧效應(tuning effect)。例如，當電晶體198、298和 398是n型電晶體時，電晶體198在相應的功函數層176下方具有膜層168和172，電晶體298在相應的功函數層276下方具有膜層272，而電晶體398在功函數層376和高介電常數介電層366之間不具有任何膜層。因此，電晶體198、298和398的臨界電壓彼此都不同。當電晶體198、298和398是n型電晶體時，電晶體198的臨界電壓在三者中會最低，且電晶體398的臨界電壓在三者中會最高。
如第16圖所繪示，功函數層76、蓋層78、矽層80和膠層82為原位形成且在製程中沒有任何破真空。因此，蓋層78和矽層80可有效地保護功函數層76，不讓其暴露在空氣內的氧氣、水或其他類似氣體之中，避免功函數層76不利的氧化。此外，由於膠層82在發生破真空之前就沉積在矽層80上，所以矽層80不會被氧化。如發生破真空，導致矽層80被氧化，則閘極電阻將增加，並導致電晶體的性能下降。值得注意的是，矽層的氧化物並不是將其下方到上方的部分完全地電性地絕緣。而是使閘極電阻(gate resistance；Rg)增加。在本實施例中，透過防止矽層80被氧化，可將閘極電阻減少高達約22%。
另外，如果矽層80遭到氧化，則膠層82必須形成得更厚，以便有效地執行將上覆的填充金屬區183、283和383黏合到各自對應的下方矽層180、280和380上的功能。例如，膠層82的厚度需要大於約25埃。否則，可能會在矽層180、280和380與各自對應的上覆填充金屬區183、283和383之間發生剝離。然而在本實施例中，由於矽層80沒有被氧化，因此膠層82的厚度可顯著的減少，例如減少厚度範圍到約8埃至約20埃，且不會犧牲其黏合功能。
減少膠層82厚度的另一有利特徵是，透過減少膠層82的厚度，填充金屬區183、283和383與下方各自對應的高介電常數介電層166、266和366之間的距離也減少了。因此，在填充金屬區183、283和383中的氟可更多地擴散到 高介電常數介電層中。實驗結果顯示，透過採用本實施例，在晶圓樣本中擴散到高介電常數閘極介電質166、266和366中的氟的量可增加約15.9%。這可顯著提高裝置的可靠度。例如，第20圖說明了高介電常數閘極介電質的依時性介電質崩潰(TDDB)Vmax(Y軸)與電流Igi(流過高介電常數閘極介電質的漏電流，X軸)間的關係。對應的實驗在125℃下進行。結果顯示，當膠層厚度為20埃(點90)時，依時性介電質崩潰Vmax為0.99伏。當採用本實施例，且膠層的厚度減少到12埃，則依時性介電質崩潰Vmax增加約80毫伏(點92)，顯示高介電常數閘極介電質的可靠度增加。
第21圖根據一些實施例繪示了閘電極386(第19A圖)中一些元素的範例分佈輪廓。X軸顯示閘極堆疊的位置，Y軸顯示元素的信號強度。此圖說明了高介電常數介電層366、功函數層376、(TiN)蓋層378、矽層380、(TiN)膠層382和填充金屬區383中元素鉿、氧、矽、鋁和鈦的分佈。結果顯示，由於使用原位沉積，在矽層380和膠層382(TiN)之間的界面中並沒有氧。
本實施例具有一些有利特徵。透過在功函數層上方原位形成含金屬蓋層，且在含金屬層上方原位形成矽層，可保護功函數層免於被氧化。另一方面，由於矽層也容易被氧化，因此在矽層上方原位形成膠層，以確保矽層不被氧化。進而使膠層形成得更薄，使電晶體介電質的依時性介電質崩潰相關可靠度得到改善。
根據一些實施例，有一種方法包括在第一半導體區上形成第一閘極介電質；在第一閘極介電質上方沉積第一功函數層；在第一功函數層上方沉積第一矽層；在第一矽層上方沉積第一膠層，其中第一功函數層、第一矽層和第一膠層為原位沉積；在第一膠層上沉積第一填充金屬；以及執行平坦化處理， 其中所述的第一膠層、第一矽層和第一功函數層之其餘部分形成閘電極的一部分。在一個實施例中，此方法還包括在第一功函數層上方沉積含金屬蓋層，其中第一矽層在含金屬蓋層的上方，且第一功函數層、含金屬蓋層、第一矽層和第一膠層為原位執行。在一個實施例中，第一膠層包括氮化鈦，且第一膠層與第一矽層為物理性接觸。在一個實施例中，第一矽層為利用熱浸一包括第一功函數層之晶圓於以矽為主的前驅物中來形成。在一個實施例中，此方法還包括在第二半導體區上形成第二閘極介電質；在第二閘極介電質上方沉積含金屬層；在含金屬層上方沉積第二功函數層，其中含金屬層和第二功函數層由不同的材料形成；在第二功函數層上方沉積第二矽層；在第二矽層上方沉積第二膠層，其中第二功函數層、第二矽層和第二膠層是原位執行；在第二膠層上方沉積第二填充金屬。在一個實施例中，含金屬層和第二功函數層是異位執行，其間存在破真空。在一個實施例中，第一膠層的厚度小於25埃。在一個實施例中，沉積第一功函數層、第一矽層和第一膠層的整個原位沉積製程期間，沒有使用氧(O2)。
根據一些實施例，有一種積體電路裝置包括半導體區；半導體區上方的閘極介電質；閘極介電質上的功函數層；功函數層上的矽層；在矽層上方並與之接觸的膠層；在膠層上方並與膠層接觸的填充金屬區。在一個實施例中，膠層的厚度小於25埃。在一個實施例中，矽層包括元素態的矽原子，且元素態矽原子與膠層有物理性接觸。在一個實施例中，膠層包括氮化鈦。在一個實施例中，積體電路裝置更包括在功函數層和矽層之間的氮化鈦層。在一個實施例中，功函數層是n型功函數層。在一個實施例中，矽層的厚度小於約10埃。
根據一些實施例，有一種裝置包括半導體鰭片；半導體鰭片上的 高介電常數介電質；高介電常數介電質上的功函數層；功函數層上方的第一氮化鈦層；在第一氮化鈦層上方的矽層；在矽層上方的第二氮化鈦層，其中矽層與第二氮化鈦層之間的界面不含氧。在第二氮化鈦層上方並與之接觸的填充金屬區。在一個實施例中，第一氮化鈦層與功函數層有物理性接觸。在一個實施例中，第二氮化鈦層的厚度小於25埃。在一個實施例中，第二氮化鈦層的厚度範圍為約8埃至約20埃。在一個實施例中，矽層的厚度小於約10埃。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。
10:晶圓
20:基板
24A:淺溝槽隔離區的頂表面
124’/224’/324’:凸出的半導體鰭片
146/246/346:閘極間隔物
154/254/354:磊晶區
58:接觸蝕刻停止層
60:層間介電質
161/261/361:閘極介電質
164/264/364:界面層
166/266/366:高介電常數介電層
168:第一含金屬層
172/272:第二含金屬層
76/176/276/376:功函數層
78/178/278/378:蓋層
80/180/280/380:矽層
82/182/282/382:膠層
183/283/383:填充金屬區
184/284/384:閘極堆疊
186/286/386:閘電極
188/288/388:自對準硬遮罩
194/294/394:閘極接觸插塞
195/295/395:矽化物區
196/296/396:源極/汲極接觸插塞
198/298/398:鰭式場效電晶體
100/200/300:裝置區

Claims (15)

  1. 一種積體電路裝置的製造方法，包括：形成一第一閘極介電質於一第一半導體區；沉積一第一功函數層於該第一閘極介電質上方；沉積一第一矽層於該第一功函數層上方；沉積一第一膠層於該第一矽層上方，其中該第一功函數層、該第一矽層以及該第一膠層為原位沉積；沉積一第一填充金屬於該第一膠層上方；以及執行一平坦化處理，其中該第一膠層、該第一矽層以及該第一功函數層之剩餘部分形成一閘極電極之部分。
  2. 如請求項1之積體電路裝置的製造方法，更包括沉積一含金屬蓋層於該第一功函數層上方，其中該第一矽層更位於該含金屬蓋層上方，以及其中該第一功函數層、該含金屬蓋層、該第一矽層以及該第一膠層為原位執行。
  3. 如請求項1或2之積體電路裝置的製造方法，其中該第一膠層包括氮化鈦，且該第一膠層與該第一矽層為物理性接觸。
  4. 如請求項1或2之積體電路裝置的製造方法，其中該第一矽層為利用熱浸一包括該第一功函數層之晶圓於一以矽為主的前驅物中形成。
  5. 如請求項1或2之積體電路裝置的製造方法，更包括：形成一第二閘極介電質於一第二半導體區；沉積一含金屬層於該第二閘極介電質上方；沉積一第二功函數層於該含金屬層上方，其中該含金屬層以及該第二功函數層為不同材料形成，且該含金屬層以及該第二功函數層為異位執行，其間經過 破真空；沉積一第二矽層於該第二功函數層上方；沉積一第二膠層於該第二矽層上方，其中該第二功函數層、該第二矽層以及該第二膠層為原位執行；以及沉積一第二填充金屬於該第二膠層上方。
  6. 如請求項1或2之積體電路裝置的製造方法，其中該第一膠層厚度小於25埃。
  7. 如請求項1或2之積體電路裝置的製造方法，其中沉積該第一功函數層、該第一矽層以及該第一膠層之整個原位沉積過程中，並未使用氧。
  8. 一種積體電路裝置，包括：一半導體區；一閘極介電質，於該半導體區上方；一功函數層，於該閘極介電質上方；一蓋層，於該功函數層上方；一矽層，於該蓋層上方；一膠層，於該矽層上方並接觸該矽層；以及一填充金屬區，於該膠層上方並接觸該膠層。
  9. 如請求項8之積體電路裝置，其中該矽層包括元素態的(elemental)矽原子。
  10. 如請求項8之積體電路裝置，更包括一氮化鈦層位於該功函數層與該矽層之間。
  11. 如請求項8之積體電路裝置，其中該功函數層為一n型功函數 層。
  12. 如請求項8之積體電路裝置，其中該矽層厚度小於10埃。
  13. 一種積體電路裝置，包括：一半導體鰭片；一高介電常數介電質，在該半導體鰭片之上；一功函數層，於該高介電常數介電質上方；一第一氮化鈦層，於該功函數層上方；一矽層，於該第一氮化鈦層上方；一第二氮化鈦層，於該矽層上方，其中在該矽層與該第二氮化鈦層之間的一界面不含氧；以及一填充金屬區，於該第二氮化鈦層上方並接觸該第二氮化鈦層。
  14. 如請求項13之積體電路裝置，其中該第一氮化鈦層與該功函數層為物理性接觸。
  15. 如請求項13之積體電路裝置，其中該第二氮化鈦層厚度控制在8埃至20埃之間。
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