201128713 ； 六、發明說明： " .【發明所屬之技術領域】 - 本發明大體上係關於半導體裝置和製造半導體裝置之 - 方法，而尤係關於具有經摻雜之含矽蓋層（下文中亦稱「摻 雜含矽蓋層」）的金氧半導體裝置及製造此種金氧半導體裝 置之方法。 【先前技術】 多數的現今積體電路（ic)藉由使用複數個互相連接 之場效電晶體（FET)(亦稱之為金氧半場效電晶體（M〇SFET 或M0S電晶體））來施行。一般使用p通道和n通道FET二 者來形成1C ’於此種情況1C稱之為互補M0S或者CMOS。 有持續的傾向加入更多更複雜之電路於單一 1C晶片上。為 了持續此種傾向，各新的技術世代係減少於電路中各個別 裝置之尺寸和裝置元件之間之間隔、或者間距（pitch；)。 當關鍵尺寸微‘時，裝置組件（C0mp〇nerit)(譬如閘極 長度和閘極絕緣層之厚度）係以實質上等比例於各世代之 方式被微縮。對於65nm技術世代而言，習知的閘極絕緣體 材料（譬如像是熱生長二氧化矽（Si〇2)或者沉積之氮氧化 矽（SiON))當單獨使用時，開始呈現過量的漏電流並且因此 只能在電晶體之閘極電極與下方通道之間提供勉強充分的 電性隔離。因此，具有介電常數大於約7(本文中稱之為高 k介電質）之替代性材料已經考慮使用於先進的裝置，包含 先進的CMOS裴置。由高k介電質製成之閘極絕緣體能夠製 成較用Si〇2或SiON所製成的閘極絕緣體更厚，而不會犧 94831 201128713 牲電容’並因此提供了明顯減少漏 料包含過渡金屬氧化物、矽酸鹽、 铪、梦酸給、和氧It化給。 然而’結合高k介電絕緣體與傳統的客曰 Ζ, Λ 夕曰曰石夕閘極雷:Κ 時，對於包含45nm世代者之先進的裝置而言，常導電極 體具有較最佳臨限電壓為高之臨限電壓（Vt)、吊致電晶 率和驅動電流為不合意的低。研究人員已經提#出通道移動 的高Vt係相關於在高k/多晶矽介面處之缺 ·所造成 提出：.通道移動率之減少主要係導因於表面光子 已、！-(scattering)於高k介電材料中之主要的月、 又、、，〇禾。欲克服 不相雜’從如氮化鈦⑽）之金㈣造之_電極層被插 置於高性能電晶體之閘極堆疊中之高k絕緣體與多晶石夕電 極之fB卜此種金相極有效減緩於通道區域中由高让介電 質所引起的光子散射，而導致驅動電流改善。金屬閑極由 此克服關聯於將高k介電質用作為閘極絕緣體之問題，並 且因此可以藉由使料些材料所提供之时的優越絕緣性 而進一步微縮至較小的關鍵尺寸。 努力最佳化多晶石夕/金屬複合物閘極電極裝置已經導 致對此種閘極電極之金I组件之組成和Μ之工作函數 (〇rk funtion)的研究。舉例而言，已經證明使用具有最 佳化組成和工作函數之金屬閘極能夠獲致於所希望之〜或 者接近所希望之Vt進行操作之電晶體。再者，當將金屬層 加到多晶♦電極時’當操作於直流（DC)模式時，因為此種. 閘極之低f阻’故能夠改進譬如通道驅動電流之裝置性能 94831 4 ,201128713201128713; VI. Description of the invention: " . TECHNICAL FIELD OF THE INVENTION - The present invention relates generally to semiconductor devices and methods of fabricating semiconductor devices, and more particularly to having a doped capping layer (hereinafter Also known as a "gold-doped semiconductor device doped with a capping layer" and a method of fabricating such a gold-oxide semiconductor device. [Prior Art] Most of today's integrated circuits (ic) use a plurality of interconnected field effect transistors (FETs) (also known as metal oxide half field effect transistors (M〇SFETs or MOS transistors)). Implementation. Both p-channel and n-channel FET are typically used to form 1C'. In this case, 1C is referred to as a complementary MOS or CMOS. There is a continuing tendency to add more complex circuits to a single 1C die. In order to continue this tendency, each new generation of technology is reduced by the size of the individual devices in the circuit and the spacing, or pitch, between the device components. When the critical dimension is micro, the device components (such as the gate length and the thickness of the gate insulating layer) are shrunk in a manner that is substantially proportional to each generation. For the 65 nm technology generation, conventional gate insulator materials (such as, for example, thermally grown cerium oxide (Si〇2) or deposited cerium oxynitride (SiON)) begin to exhibit excessive leakage current when used alone and Therefore, it is only possible to provide a strong and sufficient electrical isolation between the gate electrode of the transistor and the lower channel. Thus, alternative materials having dielectric constants greater than about 7 (referred to herein as high k dielectrics) have been considered for use in advanced devices, including advanced CMOS devices. A gate insulator made of a high-k dielectric can be made thicker than a gate insulator made of Si〇2 or SiON without sacrificing the capacitance of 94831 201128713 and thus providing a significant reduction in leakage inclusion. Transition metal oxides, citrates, hydrazines, dream acid, and oxygen are given. However, when combined with high-k dielectric insulators and traditional customers, the 导 曰曰 夕 夕 夕 Κ Κ Κ Κ Κ , , , , , , , , , , , , , , 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进 先进The threshold voltage (Vt), lift cell rate, and drive current at which the voltage is high are undesirably low. Researchers have already mentioned that the high Vt system moving out of the channel is related to the lack of high-k/polysilicon interface. The proposed reduction in channel mobility is mainly due to surface photons. - (scattering) the main month, again, and, in the high-k dielectric material. To overcome the incompatibility of the gold electrode (such as titanium nitride (10)), the electrode layer is inserted into the high-k dielectric gate stack of the high-k insulator and the polycrystalline stone electrode fB such gold The phase is effectively slowed down by photon scattering caused by high dielectric properties in the channel region, resulting in improved drive current. The metal idler thus overcomes the problem associated with the use of high-k dielectrics as gate insulators, and thus can be further reduced to smaller critical dimensions by providing superior insulation properties when materials are provided. Efforts to optimize the polylithic/metal composite gate electrode device have led to the study of the composition of the gold I component of this gate electrode and the work function of Μrk funtion. For example, it has been demonstrated that the use of a metal gate having an optimum composition and work function can achieve a transistor that is desired to operate at or near the desired Vt. Furthermore, when a metal layer is applied to a polycrystalline Δ electrode, when operating in a direct current (DC) mode, because of the low resistance of the gate, it is possible to improve the performance of a device such as a channel drive current. 94831 4 , 201128713
特性。然而，當操作於交流（AC)模式時，此種裝置之ACcharacteristic. However, when operating in alternating current (AC) mode, the AC of such a device
V 閘極阻抗已經顯示為不可接受之高。已經提出：高閘極阻 ' 抗也許是肇因於在閘極電極内於金屬/多晶矽介面處之缺 • 陷。高AC閘極阻抗會由於劣化切換速度而不利地影響裝置 性能，而因此不利地影響可以操作電晶體裝置之頻率。 因此，希望提供一種半導體裝置，其具有經摻雜之含 矽蓋層插置於複合閘極電極之金屬與多晶矽層之間，以減 少此種閘極之AC阻抗。而且亦希望提供製造此種半導體裝 置之方法。再者，由本發明之後續的詳細說明，和所附的 申請專利範圍，結合所附圖式和本發明之此先前技術，則 本發明之其他所希望之特徵和特性將變得清楚。 【發明内容】 本發明提供用來形成包括半導體基板之半導體裝置· 之方法。依照一個實施例，該方法包括下列步驟：形成高 k介電層以覆蓋該半導體基板；浪成含金屬閘極層以覆蓋 該高k介電層；形成經摻雜之含矽蓋層以覆蓋該含金屬閘 .極層；以及沉積含矽閘極層以覆蓋該經摻雜之含矽蓋層。 依照另一個範例實施例，提供用來於具有第一區域和 第二區域之半導體基板上製造半導體裝置之其他方法。該 方法包括下列步驟：.形成通道層，該通道層包括覆蓋該半 導體基板之該第二區域之受壓縮應力之半導體材料，形成 高k介電層以覆蓋該半導體基板之該第一區域和該通道 層；沉積含金屬閘極層以覆蓋該高k介電層；形成經摻雜 之梦蓋層以覆蓋該含金屬閘極層；形成含梦閘極層以覆蓋 5 94831 201128713 該經播雜之矽蓋層；以及加熱該基板。 提供一種具有覆蓋半導體基板之閘極堆疊的半導體 裝置。依照另一個範例實施例，該閘極堆疊包括：高k介 電層’配置成覆蓋該半導體基板；含金屬閘極層，配置成 覆蓋該高k介電.層；經摻雜之含矽蓋層，配置成覆蓋該含 金屬閘極層；以及含矽閘極層，覆蓋該經摻雜之含矽蓋層。 【實施方式] 本發明之下列詳細說明本質上僅僅為範例，並不打算 用來限制本發明或者本發明之應用和使用。再者，並不欲 父則面之先前技術（background of the invention)或下列 貫施方式（detail description of the invention)中所 表現之任何理論之限制。 本土明之各種實施例說明用以製造具有下述閘極電 極之NM0S和PM0S電晶體（剛或pFET)的方法，其中，該 7極具有經摻雜之碎或者摻雜之金屬碎化物 2置中之，阻抗。於這些實施例中，這些方= 3矽盍層插置於複合電晶體閘極堆疊之金屬*多 Γ旧石夕閘極電極之間。松 '、夕 層（conductivetrarJti石蓋層係提供一個導電性過渡 成不希望之高閘極阻抗^layer)其可減少咸信是造 些該等實施例中，經摻雜^原因之此介面之缺陷 。於-. 蓋層而使用，其中，^金=蓋層結合梦化物形成用金屬 多晶石夕閘極層之間^ 層插置於峰雜之發蓋層與 熱時，經播雜之石夕蓋;^反於後續的製程過程中被 充分加 夕化物形成用金屬蓋層反應以形 94831 6 .201128713 ； 成金屬矽化物層。此種金屬矽化物層亦減少界面的缺陷並 且進一步增加閘極電極的導電率。金屬石夕化物蓋層結構因 ' 此可以進一步將閘極阻抗減少至低於單獨使用摻雜之矽蓋 ’ 層所能得到之水準。 第1至9圖示意地顯示依照本發明之範例實施例半導 體M0S電晶體裝置1〇之一部分之剖面圖和用來製造此種半 導體裝置方法。本文中所述之該實施例適用於N.通道 MOS(NMOS)和P通道MOS(PMOS)電晶體，除非其特別說明實 施例僅適用於其中一種電晶體。雖'然第1至9圖中顯示製 造了一個M0S電晶體，但是應該了解到能夠使用所描述之 方法製造任何數目之此種電晶體。製造M0S組件之各種步 驟已為眾所熟知，因此，為了簡便起見，本文中對於許多 習知的步驟僅簡單提及，或者將其整個省略而不提供已熟 知製程之細節。 參照第1圖’本方法一開始先提供後續將在其上或其 内形成半導體裝置10之半導體基板14。半導體基板14能 夠是石夕、錯、譬如神化鎵之III-V族之材料、或其他的半 導體材料。下文中為了方便，但非有限制之意，將半導體 基板14稱之為梦基板。本文中所用的術語“妙基板，，包含 典型使用於半導體工業之相當純的矽以及與其他的元素 (譬如鍺、石炭等）混合之石夕。石夕基板可以是塊體石夕晶圓（bu 1匕 silicon wafer)，或者如所例示’可以是絕緣層a上之薄 矽層16(通常已知為絕緣體上覆矽），該絕緣層12依次由 載體晶圓11支撐。矽基板14之至少表面部分被換雜雜質， 7 94831 201128713 例如，藉由形成N型井區域和p型井區域而 分別製造P通道（臓）電晶私N通道（_s)電晶體。 將間極絕緣層22形成為覆蓋⑪基板14。典型的情況 是，閘極絕緣層22能夠是熱生長於薄石夕層16之表面耵 上之二氧化石夕（SW)之層。或可取而代之，以及針對盆他 類型之半導體基板，問極絕緣層22可以是氧化石夕⑸⑹ (此處X為大於G之數）、氮切、或氮氧切之沉積層。 氮化朴氣氧化梦之沉積薄财以是化學計量的組成 .化學計量的組成，但是於其任一情況，為了方便起見此種 薄膜下文中將分別稱之為Si3N4和Si〇N。能夠藉由例如化 學氣相沉積（CVD)、低壓化學氣相沉積⑽仰）' 或者電聚 增強化學氣相沉積（PECVD)製程來沉積閘極絕緣層。閉極絕 緣層22較佳由經覆蓋性地沉積（blanket_dep〇sited)之 .SiON層形成，並且具有從大約〇 8奈来（nm)至大約12随 之範圍的厚度，而最佳為大約0 8nm厚。 仍參照第1圖，在形成閘極絕緣層22後，將高k間 極絕緣層24覆蓋性地沉積而覆蓋在閘極絕緣層以上。較 佳的情況是’尚k閘極絕鍊層24由經沉積之高介電常數（高 k)絕緣材料（譬如铪之氧化物，包含氧化矽姶（HfSix〇j、 氧化銓（Hf〇2)、和氮氧化铪（Hf0xNy)、或氮氧化矽铪 -CHfSixOyNz)(此處X、y、z為大於〇)、氧化鋅（Zn〇2)等）形 成，而最佳由Hf 〇2形成。可以藉由例如cvd、LPCVD、PECVD、 物理氣相沉積（PVD)、或原子層沉積（ALD)沉積高k閘極絕 、’彖層24。選擇用於尚k閘極絕緣層24之材料具有大於約. 94831 8 201128713 _ 7. 0之介電常數，而較佳為至少大約12。高卞閘極絕緣層 24具有從大約l.4nm至大約2.4nm之厚度，而較佳為大約 1. 7nm 厚0 .然後將含金屬閘極電極層48沉積而覆蓋在高k閘極 絕緣層24上。含金屬閘極電極層48可以由鑭㈤或鑭合 金、銘（A1)或紹合金、鎂（Mg)或鎮合金、譬如氮化欽（工⑻ 或氮化紐（TiAlN)之鈦㈤基·、譬如氮德（TaN)、 氮化触（TaAIN)、或碳德（Ta2G)之㉟㈤基材料、氣化 鶴（WN)等形成’而較佳為，。可以使用或⑽製程 實施含金屬閉極電極層48之沉積。含金屬閘極電極層48 ff具有從大約2._至大約^之厚度，而最佳為大約 3. 5nm 厚。 含金==性地沉積經摻雜之發蓋層52而覆蓋 。==:因為不希望讓原生氧化物― de)形成於3金屬閘極電極 板較佳保持在實質的無氣環境中(譬如,:=:1 .蓋層52之_。二::製積=’直到經摻雜: 素於原位摻雜經摻雜切蓋$ 52 用P_N型 包含硼⑻，而N型摻雜匈、曰V以使用之？型摻雜1 於-個實施例中，經=包含糊、慨)、或糊 至大約咖範圍之^巧蓋層52具有從大約㈣〇 實施例中，層52之摻雜\ =較佳為大約8nm厚。於另一 1.0xl0^^7atTc^ 94831 9 201128713 仍參照第1圖，形成含⑦閘極電極層6Q n覆蓋經捧 二52。用於含矽閘極電極層60之材料可以包括 拳m3夕a“夕，而較佳包括多晶#。含㈣極電極層60 严佳為經沉積為未摻雜之多晶 續地摻雜雜暂1、 立稭由離于植入後 ::。可以使用之雜質摻雜劑包含B、As、P、及 、〜可藉由例如由矽烧（SiH4)之氫還原而進行之LpCVJ) <積含矽閘極電極層6〇。 敏極電極層6G之沉積後，可以依於所使用之 」U王而形成額外的層。這些層包含硬遮罩層μ，其被 ^盘性地沉積成覆蓋含石夕閘極電極層⑼。硬遮罩層64具The V gate impedance has been shown to be unacceptably high. It has been suggested that the high gate resistance may be due to the absence of a metal/polysilicon interface in the gate electrode. The high AC gate impedance can adversely affect device performance due to degraded switching speeds, thus adversely affecting the frequency at which the transistor device can be operated. Accordingly, it is desirable to provide a semiconductor device having a doped cap layer interposed between a metal and a polysilicon layer of a composite gate electrode to reduce the AC impedance of such a gate. It is also desirable to provide a method of making such a semiconductor device. Further, other desirable features and characteristics of the present invention will become apparent from the Detailed Description of the appended claims. SUMMARY OF THE INVENTION The present invention provides a method for forming a semiconductor device including a semiconductor substrate. In accordance with an embodiment, the method includes the steps of: forming a high-k dielectric layer to cover the semiconductor substrate; forming a metal-containing gate layer to cover the high-k dielectric layer; forming a doped capping layer to cover The metal-containing gate layer; and a germanium-containing gate layer is deposited to cover the doped germanium-containing cap layer. In accordance with another exemplary embodiment, other methods for fabricating a semiconductor device on a semiconductor substrate having a first region and a second region are provided. The method includes the steps of: forming a channel layer comprising a compressively stressed semiconductor material overlying the second region of the semiconductor substrate, forming a high-k dielectric layer to cover the first region of the semiconductor substrate and the a channel layer; depositing a metal-containing gate layer to cover the high-k dielectric layer; forming a doped dream cap layer to cover the metal-containing gate layer; forming a dream-containing gate layer to cover 5 94831 201128713 a cap layer; and heating the substrate. A semiconductor device having a gate stack covering a semiconductor substrate is provided. In accordance with another exemplary embodiment, the gate stack includes: a high-k dielectric layer 'configured to cover the semiconductor substrate; a metal-containing gate layer configured to cover the high-k dielectric layer; the doped germanium cap a layer configured to cover the metal-containing gate layer; and a germanium-containing gate layer covering the doped germanium-containing cap layer. The following detailed description of the invention is merely exemplary in nature and is not intended to Furthermore, there is no limitation to any theory expressed in the background of the invention or in the detail description of the invention. Various embodiments of the invention illustrate a method for fabricating a NMOS and PMOS transistor (rigid or pFET) having a gate electrode with a doped mashed or doped metal fragment 2 centered It is impedance. In these embodiments, the square = 3 turns are interposed between the metal * multi-turned gate electrodes of the composite transistor gate stack. The loose layer, the eve layer (the conductivetrarJti stone cap layer provides a conductive transition into an undesirably high gate impedance ^layer) which can reduce the salty letter is the defect of the interface which is doped in these embodiments. . Used in the cover layer, wherein, ^ gold = cap layer combined with the metallization of the metallization of the dream compound formation layer between the layers of the gate layer and the heat of the capping layer and the heat夕盖; ^ In the subsequent process, it is fully formed with a metal cap layer to form a shape of 94831 6 .201128713; into a metal telluride layer. This metal telluride layer also reduces interface defects and further increases the conductivity of the gate electrode. The metal-lithium capping structure can further reduce the gate impedance to a level lower than that obtained by using the doped cap layer alone. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 9 are schematic views showing a cross-sectional view of a portion of a semiconductor MOS transistor device 1 according to an exemplary embodiment of the present invention and a method for fabricating such a semiconductor device. This embodiment described herein is applicable to N. channel MOS (NMOS) and P channel MOS (PMOS) transistors unless it is specifically described that the embodiment is applicable to only one of the transistors. Although it is shown in Figures 1 through 9 that a MOS transistor has been fabricated, it should be understood that any number of such transistors can be fabricated using the methods described. The various steps of fabricating the MOS assembly are well known, and therefore, for the sake of brevity, many of the well-known steps are simply mentioned herein or omitted entirely without providing details of well-known processes. Referring to Fig. 1, the method first provides a semiconductor substrate 14 on which semiconductor devices 10 are to be formed later or in the first step. The semiconductor substrate 14 can be a material of the III-V group of the sacred, erroneous, or deuterated gallium, or other semiconductor material. Hereinafter, the semiconductor substrate 14 will be referred to as a dream substrate for convenience, but without limitation. As used herein, the term "miao substrate" includes a relatively pure germanium that is typically used in the semiconductor industry and is mixed with other elements (such as germanium, charcoal, etc.). The stone substrate can be a bulk silicon wafer ( Bu 1匕silicon wafer), or as exemplified 'may be a thin layer 16 on the insulating layer a (generally known as an overlying insulator), which is in turn supported by the carrier wafer 11. The substrate 14 At least the surface portion is replaced with impurities, 7 94831 201128713 For example, a P-channel (臓) electro-crystal private N-channel (_s) transistor is separately fabricated by forming an N-type well region and a p-type well region. Formed to cover the 11 substrate 14. Typically, the gate insulating layer 22 can be a layer of SiO2 (SW) thermally grown on the surface of the thin layer 16, or alternatively, and for potting The type of semiconductor substrate, the polarity insulating layer 22 may be a deposit of oxidized stone (5) (6) (where X is greater than G), nitrogen cut, or oxynitride. Composition of stoichiometry. composition of stoichiometry However, in any case, for convenience, such films will hereinafter be referred to as Si3N4 and Si〇N, respectively, and can be, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (10), or An electro-convex-enhanced chemical vapor deposition (PECVD) process for depositing a gate insulating layer. The closed-pole insulating layer 22 is preferably formed by a blanket-deposited SiON layer and has a thickness of about 〇8 (nm) to a thickness of about 12 in the range, and preferably about 0.8 nm. Still referring to Fig. 1, after forming the gate insulating layer 22, the high-k interlayer insulating layer 24 is covered and covered. Above the gate insulating layer. It is preferable that the 'sink-gate gate chain 24 consists of a deposited high dielectric constant (high-k) insulating material (such as an oxide of cerium, including cerium oxide (HfSix〇j) , yttrium oxide (Hf〇2), and yttrium oxynitride (Hf0xNy), or yttrium oxynitride-CHfSixOyNz) (where X, y, z are greater than 〇), zinc oxide (Zn 〇 2), etc. Optimally formed by Hf 〇 2. Can be by, for example, cvd, LPCVD, PECVD, physical vapor deposition (PVD), or Layer deposition (ALD) deposition of high-k gates, 'layers 24. The material selected for the gate insulating layer 24 has a dielectric constant greater than about 94.83 201128713 _ 7. 0, and preferably at least Approximately 12. The high germanium gate insulating layer 24 has a thickness of from about 1.4 nm to about 2.4 nm, and preferably about 1. 7 nm thick. 0. The metal gate electrode layer 48 is then deposited to cover the high k gate. On the pole insulating layer 24. The metal-containing gate electrode layer 48 may be made of bismuth (five) or bismuth alloy, ing (A1) or sinter alloy, magnesium (Mg) or a town alloy, such as nitriding (8) or nitriding (TiAlN). Preferably, titanium (f) base, such as TaN, TaAIN, or Ta(G) (35) material, gasification crane (WN), etc. are formed. The deposition of the metal-containing closed electrode layer 48 can be carried out using or (10) a process. The metal-containing gate electrode layer 48 ff has a thickness of from about 2._ to about φ, and most preferably about 3.4 nm. Gold-containing == deposits the doped capping layer 52 to cover. ==: Since it is not desirable to form the primary oxide - de) in the 3 metal gate electrode plate, it is preferably kept in a substantially airless environment (for example, :=:1. Cap layer 52 _. 2:: Producing = 'un-doped: the in-situ doped doped dicing $ 52 contains boron (8) in the P_N type, and the N-type doped yttrium, yttrium V uses the doping 1 in one embodiment The cover layer 52 of the layer 52 has from about (four) 〇 embodiment, the doping of layer 52 is preferably about 8 nm thick. Still referring to Fig. 1 on another 1.0xl0^^7atTc^ 94831 9 201128713, a 7-th gate electrode layer 6Q n is formed to cover the second layer 52. The material for the germanium-containing gate electrode layer 60 may include a boxing m3, and preferably includes polycrystalline #. The (four)-electrode layer 60 is preferably deposited as an undoped polycrystal. After the implantation, the impurity can be used. The impurity dopants which can be used include B, As, P, and , and can be carried out by, for example, hydrogen reduction by simmering (SiH4). <Inclusion of the gate electrode layer 6〇. After the deposition of the gate electrode layer 6G, an additional layer can be formed depending on the "U" used. These layers comprise a hard mask layer [mu] which is deposited discrimetrically to cover the layer containing the gate electrode (9). Hard mask layer 64
乂ίΐ用作為硬遮罩之組成和厚度，以钱刻覆蓋基板U 佳二可二用作為硬遮罩層64之範例材料包含TiN和較 访地包含SisN4或Si〇x。 ㈣適的光學微影姊各向雜的_製輕 64 =離子_(卿製程序列）岐化硬遮罩層 Μ ’以形成硬遮罩68，如第2崮 用為用於钱刻層22、.24、48.、5圖斤；；。硬遮罩68接著使 隨同任何餘留的光阻被去除 的綱遮罩，然後 得到的是包括閑極絕緣體74種钱刻和去除之後，所 柯極電極86、經摻雜之㈣^閘極絕緣體％、含金屬 堆疊70，如第3圖所示,、和矽閘極電極92之閘極 依照另一個實施例，於形人 沉積石夕化物形成用金屬蓋層％/夕祕電極層60之前， 如第4圖所示。矽化物形成：2蓋經摻雜之矽蓋層52’ 屬蓋層56可以包括任何能 94831 10 .201128713 ) 夠與矽反應以形成金屬矽化物的金屬’譬如’像是鎳（Ni)、 鉑（Pt)、錄（Co)、或鈦（Ti)，或者它們的任何組合。於一 ' 個實施例中，矽化物形成用金屬蓋層56包括Ni和包含大 約5至15原子百分比（atomic%)之Pt，而較佳包含大約5 至10原子百分比之Pt。此種組成之NiPt薄膜能夠藉由使 用具有所希望之組成之標靶而適用於PVD系統中。沉積矽 化物形成用金屬蓋層56至從大約4nm至大約12nm之厚 度，而較佳為大約5nm至l〇nm之間之厚度。於形成石夕化物 形成用金屬蓋層56後，可以接著沉積含矽閘極電極層60 和硬遮罩層64，如以上所述。 依照另一.個實施例中（其在當裝置10被製造為PFET 裝置時特別有效），於形成閘極絕緣層22之前，將包含單 晶材料之通道層18選擇性磊晶生長於石夕表面21之一部分 上而得’到第5圖中所示之結構。對於PFET裝置而言，通道 層18可以包括適合用作為PFET通道之任何的受壓縮應力 之半導體材料，譬如像是鍺化矽（SiGe)、鍺（Ge)、或磷化 銦（InP)，較佳為包括siGe。若裝置1〇將為WET裝置， 則可取而代之選擇性地磊晶生長受拉張應力之單晶半導體. 材料。受壓縮應力之S i Ge層能夠例如藉由在將Ge添加到 矽烷（SiHO或二氯甲矽烷（SiH2C1〇下之這些反應劑的還原 作用而被磊晶生長。如有需要，可以藉由將氫氣酸（HC1) 引入到磊晶製程而控制生長選擇性以防止SiGe薄膜形成 於非石夕表面（未顯示）。添加入通道層18之^@濃度為從 大約20%至大約35%之範圍，而較佳為大約23%(^。然後本 94831 11 201128713 方法以如顯示於第1至3圖或第1至4圖者及參考該等圖 所說明者而繼續。 又依照另一個實施例，在第1圖中所例示之形成閘極 絕緣層22和高k閘極絕緣體24之後（不論具有或者不具有 第5圖中所例示之通道層18)，如前面之說明，沉積額外 之含金屬層以覆蓋高k閘極絕緣層24，如第6圖例示。能 夠使用任何適當的金屬沉積製程（包含例如電漿氣相沉積 (PVD)或者ALD)沉積這些含金屬層，而這些含金屬層可以 由La或鑭合金、A1或銘合金、Mg或鎮合金、譬如TiN成 TiAIN之鈦基材料、譬如TaN、TaAlN、或Ta2C.之组基材料、 或WN等’或它們的組合來形成。此等含金屬層於pFET農 置會特別有用，其可調整性能參數，譬如設定用於裝置1〇 之乂1於傳導帶邊緣（conduction band edge)或搂近傳導帶 邊緣。舉例而言，參照第6圖，於一個範例實施例中，較 佳包括TiN之含金屬層32被沉積成覆蓋在高k閘極絕緣層 24上"T以使用PVD或ALD况積含金屬層32’而該含金屬 廣32具有從大約i.5nm至大約2.5nm的厚度，而較佳為大 約2. Onm厚。然後本方法可以如上述顯示和說明者繼續。 依照另一個實施例，額外的含金屬層36和/或4〇可 以依序地沉積以覆蓋含金屬層32，如第6圖中所示。含金 屬層36和40亦可以包括上文所揭示之用於形成含金屬層 32的金屬之任何其中一個或其組合，並且較佳地分別包括 A1和TiN。於一個實施例中，含金屬層36具有從大約〇.丨咖 至大約0.8nm範圍的厚度，而較佳為大約〇.8nm厚。含金 94831 12 .201128713 ^ 屬層40具有從大約1. Onm至大約2. 5nm範圍的厚度，而較 佳為大約1.5nm厚。含金屬層32、36和/或40可以單獨或 ' 結合使用，以設定用於PFET裝置之Vt至所希望之位準。 ' 在形成含金屬層32、36和/或40後，本方法繼續形 成含金屬閘極電極層48、矽蓋層52、矽化物形成用金屬蓋 層56(如果需要）、含矽閘極電極層60、和硬遮罩層64， 如前面的圖示和說明。能夠將硬遮罩層64圖案化為硬遮 罩，並於之後使用來蝕刻這些各層連同通道層18、閘極絕 緣層22、和高k閘極絕緣層24。於該等钮刻製程和去除硬 遮罩層64後，便形成閘極堆疊95,該閘極堆疊,95包含PFET 通道72、閘極絕緣體74和高k閘極絕緣體76、視需要選 用之含金屬層78、80、.和82、含金屬閘極電極86、經摻 雜之矽蓋88、視需要選用之矽化物形成用金屬蓋90、和矽 閘極電極92，如第7圖所示。 依照又另一個實施例，當將裝置10製造為NFE：T裝置 -時’執行上述說明和圖示之方法步驟，惟於形成高k閘極 絕緣層24：後接著沉積金屬氧化物閘極蓋層44，如第8圖 , . . · · 所示。金屬氧化物閘極蓋層44可以使用來將用於NFET裝 置之Vt設定於傳導帶邊緣或接近傳導帶邊緣，並且可以包 括包含下述者之金屬氧化物和/或金屬氮氧化物之任何其 中一種或其組合：La、氧化鑭（La〇x)和氮氧化鑭（La〇爲）、 氧化銓（Hf〇x)和氣氧化铪（Hf〇xNy)、氧化錘（ZrO〇和氮氧化 錯（ZrOJy)、氧化鎮（Mg〇x)和氮氧化鎮（Mg〇xNy)、氧化紹 (Al〇x)和氮氧化鋁（Al〇xNy)、氧化鈦（Ti〇x)和氮氧化鈦 94831 13 201128713 (TiOxNy)、氧化鈕（7&0*)和氮氧化鈕（了8〇爲）、和氧化釔（丫〇5；) 和氮氧化紀（Y〇xNy)，其中x和y為大於0之數，而較佳為 La。可以使用任何適合的沉積技術，譬如像是PVD製程（例 如蒸發或濺鍍）、CVD、PECVD、LPCVD、ALD，來沉積金屬 氧化物閘極蓋層44，而較佳為藉由ALD形成。層44亦可 • · , 以使用適合用於此種沉積之化學化合物形成為自身組合或 經自身組合之單層（self-assembiedmon〇iayer，SAM)。此 種化合物一般包括經適當地功能化為用於黏著性吸附或者 接合至基板表面之分子位置之分子結構，但是缺少形成超 過單層厚度之薄膜之傾向。可以使用例如自旋塗覆或浸泡 製程而從適當的溶劑進行洗鑄而沉積SAM化合物。金屬氧 化物間極蓋層44之厚度為從大約o.lnm至大約0.8mn範 園，而較佳為大約〇 4nm厚。. 〜在形成金屬氧化物閘極蓋層44後，本方法依照上述 Γ/Γ日1不之任何實施例繼續進行。可以圖案化硬遮罩層 k閘極絕^^用為㈣料以去除包含閘極絕緣層22、高 \ 二4、和金屬氧化物閘極蓋層44之該等層之— 4刀。在這些蝕刻和硬遮罜 98’該閘極堆疊98 、曰4之去除後，形成閘極堆叠 76、金屬氧化物閘極蓋人緣體74和高k閑極絕緣體 之石夕蓋88、視需要選用^化=屬閑極電極託、經摻雜 極電極92，如第q圖於 形成用金屬蓋90、和矽閘 - 步y圖所示。 在形成閘極堆疊7〇( -者後，裝置10可以經 、95(第7圖）、或98任 ’工又額.卜的製程，該額外製程可涉及 94831 14 201128713 暴露至升高的溫度，譬如像是那些通常用來活化源極和汲 極摻雜劑或反應性地將石夕閘極電極92以及後續所沉積的 ，屬層轉變成為金屬魏物間極電極接觸點者^在閘極堆 立中使用有、&換雜之;^蓋88但沒有石夕化物形成用金屬蓋 90的If形中’則二個可能的結果之其中之一可能會發生。 第一個可能的結果為’若⑪閘極電極92其自身完全轉變成 為梦化物’敎摻雜之残⑽也許會轉變成經摻雜之金屬 夕化物第一個可此的結果為，若石夕問極電極Μ未完全轉 ^為=化物，譬如像衫Μ極電極92對減種完全的 _摻雜切蓋88可以保持為在含金屬間 極電極86與矽閘極電極9 的摻雜石夕層。於此情形中^間之未反應、導電的、過渡 报忐用厶鹿# η 了粑發生之第三個結果是矽化物 形成用金屬蓋90被包含於 及充分暴露於時叫溫度(2堆疊之情況。糾情況，涉 者達大於約5秒）之後續=如’像是大約_°c或者較高 屬蓋90與鄰接之經摻雜將引时化物形成用金 物形成用金屬之經摻雜之矽盍88反應以形成包括該矽化 之一部分亦可以與來自_^的層。魏物形成用金屬 應，以形成金屬矽化物。若矽閘極鼋極92之多晶矽反 學計量計超過矽化物形成用自蓋狀之摻雜矽存在有以化 可以保持未被反應，或者於f之量，則摻雜矽之一部分 化物閱極接觸點之製程過程I矽閘極電極92成為金屬矽 矽化物區。插置於含金屬門中可以被轉變成經摻雜之金屬 間之包括摻雜矽或者較佳^極電極86與矽閘極電極92之 包括經摻雜之金屬矽化物之層 94831 15 201128713 業經實驗發現可降低閘極堆疊之Ac阻抗，並且由此提升裝 置之整體AC性能。 第10至2 2圖依照本發明範例實施例示意地顯示具有 包含經摻雜之矽蓋層之P通道MOS(PMOS)和N通道 MOS(NMOS)電晶體之半導體裝置1〇〇之一部分之剖面圖和 用來形成此種半導體裝置之方法。雖然顯示了一個NM〇s 和一個PM0S之部分之製造，但是應該了解到描述於第1〇 .至22圖之本方法能夠用來製造任何數目之此種電晶體。如 前面之方法，於製造M0S組件之各種步驟已為眾所熟知， 因此為了簡便起見，許多習知的步驟將僅簡短提及或者將 被省略。 參照第10圖，依照範例實施例，本方法一開始先提 供半導體基板110。半導體基板11〇相似於上述之半導體 基板14，但是另外包括隔離區域丨18，該隔離區域1丨8延 伸穿過薄矽層16至絕緣層12。隔離區域us較佳由已熟 知的淺溝槽隔離（STI)技術形成，其中溝槽被蝕刻入薄矽層 .16，且該等溝槽被譬如沉積二氧化矽之介電材料所填滿， 並且藉由化學機械平坦化（CMP)去除過量的二氧化矽。隔離 區域118用來電性隔離NFET區域180和pfeT區域200， 而用於NFE1T和PFET電晶體之閘極堆疊係接著分別形成在 该NFET區域180和PFET區域200上。例如，藉由在pFET 區域200中形成N形井區域和在NFET區域18〇中形成p 形井區域，而將雜質摻雜於矽基板11〇之至少表面區域 108，以分別製造PFET和NFET電晶體。 94831 16 .201128713 ~ 其次，形成硬遮罩層122以覆蓋NFET和PFET區域180 和200，如第11圖中所示。硬遮罩層122可以包括熱生長 ' Si〇2，或者取而代之，可以包括經沉積之Si〇x、Si3N4、或 • SiON、或者於後續磊晶生長製程過程中適合用來提供遮罩 保護之另一種材料。當使用沉積製程時，可以例如藉由 CVD、LPCVD或PECVD覆蓋性地沉積硬遮罩層122。硬遮罩 層122較宜為熱生長Si〇2形成在薄矽層16之表面，如所 示’並且具有從大約7nm至大約15mn範圍之厚度，而較佳 為大約8nm厚。 然後使用適合的光學微影術和rIE製程序列從pFET 區域200去除硬遮罩層122，如第12圖中所示。所使用之 RIE製程化學作用係依於所選擇用於硬遮罩層122之材料 而疋’並且可以為根據例如CHF3、CF4或SFb.者，以用於氧 化石夕/_氧化發、或者氮化硬'然後將包括單晶半導體材料 之PFET通道層134蟲晶生長於區域·中之薄石夕層 1。6之縣面13Q’如第13圖中所示。選擇性地實施蠢晶製 程至石夕表面而使得不會發生於非石夕表面（譬如硬遮罩層 °pfet通道層134可以包括前面說明過之用於 u<任何受.壓縮應力之半導體材料和組成範圍，並 可、吏用相同的蟲晶製程來形成。較佳的情況是，PFet 通道層134包括具有大約咖之 剛=對於PFET通道層134選擇性去除硬遮罩、層吏= ”人*第14圖中所示，將閘極絕緣層138覆性 地沉積以覆蓋半導妒萝罟 Γ 亍等骽衮置1〇〇 ’包含於NFET區 94831 17 201128713 薄石夕層16和於PFET區域200中之PFET通道層134。閘極 絕緣層138包括沉積絕緣材料，譬如Si〇x、SM4、或SiON , 而較佳的是SiON。可以例如藉由CVD、LPCVD、或PECVD 製程施行沉積。閘極絕緣層138具有大約0. 8nm至大約' 1.2nm之厚度’而較佳為大約〇.gnm厚。 仍參照第14圖，在形成閘極絕緣層138後，將高k 閘極絕緣層HO覆蓋性地沉積以覆蓋.NFET和PFET區域18〇 和200 °較佳為，由經沉積之高k絕緣材料（譬如铪之氧化 物’ ·包含 HfSix〇y、Hf〇2、Hf〇xNy、和 HfSixOyNz(此處 X、y、 z分別大於0)、Zn〇2等’而較佳為Hf〇2)形成高k閘極絕緣 廣 140。可以例如藉由 CVD、LPCVD、PECVD、PVD、或 ALD 沉積局k閘極絕緣層140。選擇用於高k閘極絕緣層140 之材料具有大於大約7.0之介電常數，而較佳至少大約 12. 0 °高k閘極絕緣層140具有從大約lnm至大約ι〇ηπι 之厚度，.而較佳為大約h 7nm厚。 其次’於各種範例實施例中，額外的含金屬層經沉積 而覆蓋高k閑極絕緣層140,並且用來建立於PFET區域200 中待製造之PFET裝置之yt。此等層可以後續地從NFET區 域180去除，如下文中將作進一步之說明。參照第14圖， 於個貝施例中，含金屬層142被覆蓋性地沉積以覆蓋高 k閘極絕緣層UG於NFET和PFET區域⑽和⑽兩者。 可以使用任何適當的金屬沉積製程（包含PVD 或ALD)沉積 含金屬層14=’並且該含金屬層142具有從大約i 5nm至 大、力2. 5nm範圍之厚度.，而較佳為大約2. Onm厚。含金屬 94831 18 .201128713 層142可以由La或鑭合金、A1或紹合金、处或鎮合金、 如ΤιΝ或ΤιΑΙΝ之欽基材料、譬如Τ&Ν、以⑽、或 之組基材料、或Μ等，或者它們的組合形成，而The thickness and thickness of the hard mask are used to cover the substrate. (4) Appropriate optical lithography 姊 的 轻 light 64 = ion _ (clear program column) 岐 hard mask layer Μ 'to form a hard mask 68, such as the second 为 for the money layer 22 , .24, 48., 5 jin;; The hard mask 68 then causes the mask to be removed along with any remaining photoresist, and then the resulting electrode includes the idle insulator 74 and is removed and removed, the gate electrode 86, the doped (four) gate The insulator %, the metal-containing stack 70, as shown in FIG. 3, and the gate of the gate electrode 92 are in accordance with another embodiment, and the metal cap layer/metal electrode layer 60 is formed in the form of a human body. Previously, as shown in Figure 4. Telluride formation: 2 capped doped cap layer 52' cap layer 56 may comprise any metal capable of reacting with barium to form a metal telluride such as nickel (Ni), platinum (Pt), recorded (Co), or titanium (Ti), or any combination thereof. In one embodiment, the metallization layer 56 for telluride formation comprises Ni and a Pt comprising from about 5 to 15 atomic percent, and preferably from about 5 to 10 atomic percent of Pt. Such a composition of NiPt film can be applied to a PVD system by using a target having a desired composition. The metal cap layer 56 for forming a telluride is deposited to a thickness of from about 4 nm to about 12 nm, and preferably between about 5 nm and 10 nm. After forming the metal cap layer 56 for the formation of the lithium, the ruthenium-containing gate electrode layer 60 and the hard mask layer 64 may be deposited, as described above. According to another embodiment (which is particularly effective when the device 10 is fabricated as a PFET device), the channel layer 18 comprising the single crystal material is selectively epitaxially grown on the stone eve before the gate insulating layer 22 is formed. One of the surfaces 21 is partially formed to the structure shown in Fig. 5. For a PFET device, the channel layer 18 can comprise any compressively stressed semiconductor material suitable for use as a PFET channel, such as germanium telluride (SiGe), germanium (Ge), or indium phosphide (InP). Jiawei includes siGe. If the device 1 will be a WET device, a single crystal semiconductor material that is subjected to tensile stress can be selectively epitaxially grown. The compressively stressed S i Ge layer can be epitaxially grown, for example, by adding Ge to decane (SiHO or methylene chloride (the reduction of these reactants under SiH2C1). If necessary, Hydrogen acid (HC1) is introduced into the epitaxial process to control the growth selectivity to prevent the SiGe film from forming on the non-stone surface (not shown). The concentration added to the channel layer 18 ranges from about 20% to about 35%. And preferably about 23% (^. Then the method of 94831 11 201128713 continues as illustrated in Figures 1 to 3 or Figures 1 to 4 and as described with reference to the figures. Further according to another embodiment After forming the gate insulating layer 22 and the high-k gate insulator 24 illustrated in FIG. 1 (with or without the channel layer 18 illustrated in FIG. 5), as described above, deposition is additionally included. A metal layer overlies the high-k gate insulating layer 24, as illustrated in Figure 6. These metal-containing layers can be deposited using any suitable metal deposition process, including, for example, plasma vapor deposition (PVD) or ALD, and these metal-containing layers The layer can be made of La or tantalum alloy, A1 or alloy Mg or a master alloy, such as a titanium-based material in which TiN is TiAIN, a group-based material such as TaN, TaAlN, or Ta2C., or WN or the like, or a combination thereof. These metal-containing layers are particularly useful in pFET farming. The adjustable performance parameter, for example, is set for the device 1〇 to the conduction band edge or the conduction band edge. For example, referring to FIG. 6, in an exemplary embodiment, Preferably, the metal-containing layer 32 comprising TiN is deposited over the high-k gate insulating layer 24 to "tread the metal-containing layer 32' using PVD or ALD and the metal-containing layer 32 has a thickness of from about i.5 nm to about The thickness of 2.5 nm, and preferably about 2. Onm thickness. The method can then be continued as shown and described above. According to another embodiment, additional metal containing layers 36 and/or 4 can be deposited sequentially The metal containing layer 32 is covered, as shown in Figure 6. The metal containing layers 36 and 40 may also comprise any one or combination of the metals disclosed above for forming the metal containing layer 32, and preferably separately Including A1 and TiN. In one embodiment, metal-containing The thickness of the layer 40 has a thickness ranging from about 1. Onm to about 2. 5 nm. The thickness of the layer 40 is from about 1. Onm to about 2. 5 nm. Preferably, it is about 1.5 nm thick. The metal containing layers 32, 36 and/or 40 can be used alone or in combination to set the Vt for the PFET device to the desired level. After 36 and/or 40, the method continues to form a metal-containing gate electrode layer 48, a cap layer 52, a metallization layer 56 for telluride formation (if needed), a germanium-containing gate electrode layer 60, and a hard mask layer. 64, as shown and described above. The hard mask layer 64 can be patterned into a hard mask and used thereafter to etch the layers together with the channel layer 18, the gate insulating layer 22, and the high-k gate insulating layer 24. After the engraving process and removal of the hard mask layer 64, a gate stack 95 is formed. The gate stack 95 includes a PFET channel 72, a gate insulator 74, and a high-k gate insulator 76, optionally included Metal layers 78, 80, . and 82, metal-containing gate electrode 86, doped lid 88, optionally metallization forming metal lid 90, and tantalum gate electrode 92, as shown in FIG. . In accordance with yet another embodiment, when the device 10 is fabricated as an NFE:T device - the method steps of the above description and illustration are performed, except that the high-k gate insulating layer 24 is formed: followed by deposition of a metal oxide gate cap Layer 44, as shown in Figure 8, is shown. A metal oxide gate cap layer 44 can be used to set the Vt for the NFET device to or near the edge of the conductive strip, and can include any of the metal oxides and/or metal oxynitrides comprising: One or a combination thereof: La, lanthanum oxide (La〇x) and lanthanum oxynitride (La〇), lanthanum oxide (Hf〇x) and cerium oxide (Hf〇xNy), oxidized hammer (ZrO〇 and nitrogen oxidation error ( ZrOJy), oxidized town (Mg〇x) and oxynitride (Mg〇xNy), oxidized (Al〇x) and aluminum oxynitride (Al〇xNy), titanium oxide (Ti〇x) and titanium oxynitride 94831 13 201128713 (TiOxNy), oxidation button (7 & 0*) and nitrogen oxide button (8 〇), and yttrium oxide (丫〇5;) and nitrous oxide (Y〇xNy), where x and y are greater than 0 The number, and preferably La. The metal oxide gate cap layer 44 can be deposited using any suitable deposition technique, such as a PVD process (e.g., evaporation or sputtering), CVD, PECVD, LPCVD, ALD. Preferably formed by ALD. Layer 44 can also be formed into a self-combination using chemical compounds suitable for such deposition or Self-assembedmonium (SAM). This compound generally includes a molecular structure that is suitably functionalized for adhesive adsorption or bonding to the molecular surface of the substrate surface, but lacks formation beyond the thickness of the single layer. The tendency of the film. The SAM compound can be deposited by washing with a suitable solvent using, for example, a spin coating or dipping process. The thickness of the metal oxide cap layer 44 is from about 0.1 nm to about 0.8 nm. Preferably, the thickness is about 〇4 nm. 〜 After forming the metal oxide gate cap layer 44, the method continues according to any of the above embodiments. The hard mask layer k gate can be patterned. It is used as (4) material to remove the layer of the layer including the gate insulating layer 22, the high/two 4, and the metal oxide gate cap layer 44. In these etching and hard concealing 98' After the gate stacks 98 and 曰4 are removed, the gate stack 76, the metal oxide gate cap body 74 and the high-k idler insulator are formed, and the anode electrode is used as needed. Doped electrode 92, as shown in Figure q for formation The metal cover 90, and the gate-step y are shown. After forming the gate stack 7〇 (the device 10 can pass, 95 (Fig. 7), or 98, the process of the work, the amount of work, The additional process may involve exposure to elevated temperatures at 94831 14 201128713, such as those typically used to activate source and drain dopants or reactively deposited as the gate electrode 92 and subsequently deposited. Transformed into a contact point between the electrode and the electrode of the metal object. ^Used in the gate stack, and replaced with a ^88 but without the formation of a metal cover 90 in the If-shape of the metal cover 90. One of the results may happen. The first possible result is that if the 11 gate electrode 92 itself completely transforms into a dream compound, the doping of the doping (10) may be converted into a doped metal compound. The first result is that if the stone If the electrode electrode Μ is not completely converted to a compound, for example, the ruthenium electrode 92 of the rug-like electrode can be maintained as a doping of the inter-metal electrode 86 and the 矽 gate electrode 9 . Shi Xi layer. In this case, the unreacted, electrically conductive, transitional report of the embers # 粑 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第In the case of the situation, the situation is greater than about 5 seconds) followed by = such as 'like about _ ° c or higher is the cover 90 and the adjacent doping will lead the formation of metal for gold formation The reaction of the heteroquinone 88 to form a layer including the deuteration may also be with a layer derived from _^. The material is formed by a metal to form a metal halide. If the polysilicon counter-meter of the gate bungee 92 exceeds the doping of the telluride for the formation of the telluride, the doping may be left unreacted, or the amount of f may be a part of the doped The process of the contact point I 矽 the gate electrode 92 becomes a metal telluride region. Inserted in a metal-containing gate can be converted into a doped germanium or a preferred electrode 86 and a germanium gate electrode 92 comprising a doped metal germanide layer 94831 15 201128713 It has been found experimentally that the Ac impedance of the gate stack can be reduced and thereby the overall AC performance of the device can be improved. 10 to 22 are schematic cross-sectional views showing a portion of a semiconductor device 1 having a P-channel MOS (PMOS) and an N-channel MOS (NMOS) transistor including a doped cap layer, in accordance with an exemplary embodiment of the present invention. And methods for forming such semiconductor devices. Although the fabrication of a portion of NM〇s and a PMOS is shown, it should be understood that the method described in Figures 1 through 22 can be used to fabricate any number of such transistors. As in the previous method, various steps in the manufacture of the MOS assembly are well known, and thus many conventional steps will be briefly mentioned or will be omitted for the sake of brevity. Referring to Fig. 10, in accordance with an exemplary embodiment, the method first provides a semiconductor substrate 110. The semiconductor substrate 11 is similar to the above-described semiconductor substrate 14, but additionally includes an isolation region 丨18 which extends through the thin layer 16 to the insulating layer 12. The isolation region us is preferably formed by the well-known shallow trench isolation (STI) technique in which the trenches are etched into the thin germanium layer 16. and the trenches are filled with a dielectric material such as germanium dioxide deposited. And excess cerium oxide is removed by chemical mechanical planarization (CMP). Isolation region 118 is used to electrically isolate NFET region 180 and pfeT region 200, while gate stacks for NFE1T and PFET transistors are then formed on NFET region 180 and PFET region 200, respectively. For example, by forming an N-well region in the pFET region 200 and forming a p-well region in the NFET region 18, impurities are doped into at least the surface region 108 of the germanium substrate 11 to fabricate PFET and NFET, respectively. Crystal. 94831 16 .201128713 ~ Next, a hard mask layer 122 is formed to cover the NFET and PFET regions 180 and 200 as shown in FIG. The hard mask layer 122 may include thermal growth 'Si〇2, or alternatively, may include deposited Si〇x, Si3N4, or SiON, or may be used to provide mask protection during subsequent epitaxial growth processes. A material. When a deposition process is used, the hard mask layer 122 can be overlaid, for example, by CVD, LPCVD, or PECVD. Preferably, the hard mask layer 122 is formed by thermally growing Si〇2 on the surface of the thin layer 16, as shown and having a thickness ranging from about 7 nm to about 15 nm, and preferably about 8 nm thick. The hard mask layer 122 is then removed from the pFET region 200 using a suitable optical lithography and rIE program sequence, as shown in FIG. The RIE process chemistry used is based on the material selected for the hard mask layer 122 and may be based on, for example, CHF3, CF4 or SFb. for oxidized oxidized or oxidized or nitrogen. The hard surface of the PFET channel layer 134 including the single crystal semiconductor material is then grown in the area of the thin layer of the thin layer 1. The county face 13Q' of Fig. 13 is as shown in Fig. 13. Optionally performing a stupid process to the surface of the stone to prevent it from occurring on a non-stone surface (such as a hard mask layer). The pfet channel layer 134 may include any of the semiconductor materials described above for use in u<. And the composition range, and can be formed by the same insect crystal process. Preferably, the PFet channel layer 134 includes approximately kPa = selective removal of the hard mask for the PFET channel layer 134, layer 吏 = ” As shown in Fig. 14, the gate insulating layer 138 is deposited to cover the semi-conducting dill, etc., which is included in the NFET region 94831 17 201128713. PFET channel layer 134 in PFET region 200. Gate insulating layer 138 includes a deposition insulating material such as Si〇x, SM4, or SiON, and preferably SiON. Deposition can be performed, for example, by CVD, LPCVD, or PECVD processes. The gate insulating layer 138 has a thickness of about 0.8 nm to about '1.2 nm' and preferably about 〇.gnm. Still referring to FIG. 14, after forming the gate insulating layer 138, the high-k gate is insulated. Layer HO is overlaid to cover the .NFET and PFET regions 18 and 2 00 ° is preferably formed by a deposited high-k insulating material (such as an oxide of lanthanum), including HfSix〇y, Hf〇2, Hf〇xNy, and HfSixOyNz (where X, y, and z are each greater than 0, respectively). Zn〇2, etc., and preferably Hf〇2) forms a high-k gate insulating width 140. The local gate insulating layer 140 can be deposited, for example, by CVD, LPCVD, PECVD, PVD, or ALD. Selected for high k The material of the gate insulating layer 140 has a dielectric constant greater than about 7.0, and preferably at least about 12. 0 ° high-k gate insulating layer 140 has a thickness of from about 1 nm to about ιηηπι, and preferably about h 7 nm thick. Secondly, in various exemplary embodiments, an additional metal containing layer is deposited to cover the high k idler insulating layer 140 and is used to establish the yt of the PFET device to be fabricated in the PFET region 200. It can be subsequently removed from the NFET region 180, as will be further explained below. Referring to Figure 14, in a preferred embodiment, the metal containing layer 142 is overlaid to cover the high-k gate insulating layer UG to the NFET and Both PFET regions (10) and (10). Any suitable metal deposition process (including PVD or AL) can be used. D) depositing a metal containing layer 14 = ' and the metal containing layer 142 has a thickness ranging from about i 5 nm to large, a force of 2.5 nm, and preferably about 2. Onm thick. Metal containing 94831 18 .201128713 layer 142 It may be formed of La or bismuth alloy, A1 or sinter alloy, place or town alloy, such as 钦ιΝ or ΤιΑΙΝ, such as Τ & Ν, with (10), or a group of base materials, or ruthenium, or the like, or a combination thereof, and
TiN形成。 ^田 依照其他的實施例，含金屬閘極層146和/或150係 後續地被覆蓋性地沉積以覆蓋含金屬閘極層142於㈣了 矛PFET區域180和200兩者。含金屬閘極層146和150 可以包括上文中參照含金屬閘極層142所說明過之任何的 材料’並可由上文中參照含金屬問極層142所說明過之任 何製程所沉積。含金屬層146較佳核，並且具有從大約 O.lnm至大約〇.8nm範圍之厚度，而較佳為大約ο』⑽厚。 含金屬閘極们50較佳為則，具有從大約lnm至大約 2.5nm範圍之厚度，而較佳/為大約，l.5nm厚。 然後使用適當的圖案化製程分別將所使用之任何含 金屬層142、146和150從NFET區域18〇去除。此製程較 佳土含形成硬遮罩154,如第15圖所示，該形成製程使用 先前針對硬遮罩層說明過之適#的沉積、光學微影術、和. 乾侧製程順序 接著’使用硬遮罩154作為飿刻遮罩， 將含金屬層142、146、和150從NFET區域18〇去除，如 第16圖中所不。選擇性地實施蝕刻製程以便不會腐蝕於 區域180中之咼k閘極絕緣層140。所使用之钱刻化 學作用將部分地依據在含金屬層142、146、和15〇中待蝕 刻之材料組成而定，並且也許根據例如用於τ丨N之c 12 / h B『 化學作用、用於之Ch/CF4化學作用、或用於籠之 94831 19 201128713 SFe/CM2化學作用。在此鞋刻後，可以使用適當的濕钱刻 或乾钱刻製程去除硬遮罩層154，其中，紐刻製程不會 從PFET區域200腐ϋ掉含金屬層142、146、和/或15〇(如 果有使用），或從NFET區域180腐轉高k閘極絕緣層14〇。 在該去除硬遮罩層154後，本方法接著覆蓋性地沉積 金屬氧化物閘極蓋層162以覆蓋贿和ρ·區域⑽和 200 ’如第η圖中所示。如上文參照金屬氧化物閘極蓋層. 44所揭示’金屬氧化物閘極蓋層162可以使用來設定用於 待形成於購Τ區域18G中之_Τ裝置之Vt。金屬氧化物 閘極蓋層162可以包括下述金屬氧化物和/或金屬氮氧化 物之任何其中一種或其組合，包含u、—、和、 隱和HfO具、Zr0x和Zr〇爲、_〇和_爲、咖和 A10爲、Tl0x和 Ti0眞、Ta〇x和眞、γ〇χ和 γ〇爲， 和y為大於0之數，而較佳是La。可以使用任何適合、χ ，術沉積金屬氧化物閘極蓋層162，且該金屬 ;儿 厚度範圍係如前面參照金屬氧化物_ 接者’形成含金屬閘極層166以覆蓋金屬間 162。含金屬閘極層166可以由u或鑭合金、 日TiN is formed. According to other embodiments, the metal-containing gate layer 146 and/or 150 is subsequently overlaid to cover the metal-containing gate layer 142 to (4) both the spear PFET regions 180 and 200. The metal-containing gate layers 146 and 150 may comprise any of the materials described above with reference to the metal-containing gate layer 142 and may be deposited by any of the processes described above with reference to the metal-containing gate layer 142. Metal-containing layer 146 is preferably core and has a thickness ranging from about 0.1 nm to about 0.8 nm, and preferably about ο" (10) thick. The metal-containing gates 50 are preferably of a thickness ranging from about 1 nm to about 2.5 nm, and more preferably about 1.5 nm thick. Any metal containing layers 142, 146 and 150 used are then removed from the NFET region 18, respectively, using a suitable patterning process. Preferably, the process comprises forming a hard mask 154, as shown in Fig. 15, which is formed using a deposition, optical lithography, and dry side process sequence previously described for the hard mask layer. Using the hard mask 154 as an etch mask, the metal containing layers 142, 146, and 150 are removed from the NFET region 18, as shown in FIG. The etching process is selectively performed so as not to corrode the 闸k gate insulating layer 140 in the region 180. The chemistry used will depend, in part, on the composition of the material to be etched in the metal containing layers 142, 146, and 15 , and may be based, for example, on c 12 / h B chemistry for τ丨N, For the Ch/CF4 chemistry, or for the cage 94831 19 201128713 SFe/CM2 chemistry. After this shoe is engraved, the hard mask layer 154 can be removed using a suitable wet or dry engraving process in which the germanium process does not erode the metal containing layer 142, 146, and/or 15 from the PFET region 200. 〇 (if used), or rot the high-k gate insulating layer 14〇 from the NFET region 180. After the hard mask layer 154 is removed, the method then overlays the metal oxide gate cap layer 162 to cover the brittle and p regions (10) and 200' as shown in FIG. Referring to the metal oxide gate cap layer as described above, the metal oxide gate cap layer 162 can be used to set the Vt for the Τ device to be formed in the sourcing region 18G. The metal oxide gate cap layer 162 may comprise any one or combination of the following metal oxides and/or metal oxynitrides, including u, —, and, and HfO, Zr0x and Zr〇, _〇 And _, 咖, and A10 are, Tl0x and Ti0眞, Ta〇x and 眞, γ〇χ and γ〇 are, and y is a number greater than 0, and preferably La. Any suitable, germanium, deposited metal oxide gate cap layer 162 may be used and the metal thickness range is such that a metal-containing gate layer 166 is formed to cover the intermetal 162 as previously described with reference to the metal oxide. The metal-containing gate layer 166 may be made of u or tantalum alloy, day
Mg或鎮合金、譬* TiN或miN之鈦基材料、譬口金、 TaAIN或Ta2C之叙基材料、等形成，而較佳；、 可以使用PVD或CVD製程實施含金屬閑極層i66二lN。 含金屬雜層166較佳具有從大約2.5n ’儿積。 度，而較佳為大約3. 5nm厚。 大，力7⑽之厚 94831 20 201128713 在沉積含金屬閘極層166後，將半導體裝置100維持 於真空下（若使用於層166之沉積）或者於另一種型式之實 質無氧環境中以避免原生氧化物形成於含金屬閘極層166 之表面168上。接著’使用例如LPCVD製程而將包含摻雜 石夕之經捧雜之發蓋層Π0覆蓋性地沉積以覆蓋NFET和 =ΕΤ區域180和2〇〇中之含金屬閘極層166。經摻雜之矽. 蓋層170包括與於沉積製程過程中於原位加入於薄膜中之 雜質摻雜劑混合之石夕。此種摻雜劑元素可以包括譬如蝴⑻ 之Ρ垔凡素，或者·包括譬如磷（Ρ)、砷（As) '或銻（Sb)之Ν 里兀素。於一個實施例中，經摻雜之矽蓋層170具有從大 大約1〇nm範圍之厚度，而較佳為大約8咖厚。於 另一個貫施例中，經摻雜之㈣層⑺具有從大 『 滅10至大約Ux，at/cm3的摻雜濃度。，·〇Χΐ° no 圖中所不。切閘極電極層17 晶石夕或較佳之多㈣，並且可以使用前面 L括非 極電極層60之製程和摻雜劑元素來沉精^於含石夕閘 在沉積含㈣極電極層178後，可依於^雜植入。 希望之應用和所使用之整體製程，而形成額外f置100所 層包含被覆蓋性地沉積之硬遮罩声 ' 9層。這些 極層178，使用適當的光學微巧9 以覆蓋含矽閘極電 該硬遮罩請，以形成硬 和贿區域18〇和2〇〇，如第μ圖今別覆蓋於 186和190被各使用為蝕刻遮罩， 。硬遮罩 除覆意區域180和 94831 21 201128713 200之層之部分，以分別形成閘極堆疊2〇4和2〇8，如第 20圖—中所示。當此種钱刻和去除（包含去除硬遮罩186和 1J0)凡成時’閘極堆疊204包含NFET閘極絕緣體222、NFET 高k閘極絕緣體226、NFn金屬氧化物閘極蓋23〇、ΝρΕτ 含金屬閘極電極234、NFET摻雜矽蓋238、和肿肘矽閘極 電極250。閘極堆疊208包含PFET通道254、PFET閘極絕 緣體258、.PFET高k閘極絕緣體262、視需要選擇使用之 PFET含金屬層266、27Q、和274、pFET金屬氧化物閘極蓋 278、PFET含金屬閘極電極282、PFET摻雜矽蓋286、和 PFET石夕閘極電極294。 於另一個實施例中，在將含矽閘極電極層178形成於 區域丨別和200兩者之前，先沉積矽化物形成用金屬蓋層 ,174以覆蓋摻雜矽蓋層170，如第21圖中所示。矽化物形 成用金屬蓋層174可以包括上述參照矽化物形成用金屬蓋 層56所說明之任何的金屬或該等金屬之任何纟且合。於另一 個實施例中，矽化物形成用金屬蓋層174包括Ni並且包含 大約5至15.原子百分比之Pt，而較佳包含大約5至1〇原 子百分比之pt。沉積矽化物形成用金屬蓋層至從大約 4nm至木約12nm之厚度，而較佳為大約5nm至1 〇nm之間 的厚度。在形成矽化物形成用金屬蓋層174後，執行前面 所述和顯示於第18和19圖中之製程步驟，包含形成含石夕 閘極電極層178、硬遮罩層182、和硬遮罩18&和19〇。然 後將這些硬遮罩使用為蝕刻遮罩，用來分別形成問極堆疊 210和220而覆蓋區域180和.200，如第22圖中所示。 94831 22 201128713 在此蝕刻和去除硬遮罩186和190後，閘極堆疊210 包含NFET閘極絕緣體222、NFET高k閘極絕緣體226、NFET ' 金屬氧化物閘極蓋230、NFET含金屬閘極電極234、NFET , 摻雜矽蓋238、NFET矽化物形成用金屬蓋242、和NFE：T碎 閘極電極250。閘極堆疊220包含PFET通道254、PFET問 極絕緣體258、PFET高k閘極絕緣體沆2、視需要選擇使 用之PFET含金屬層266、270、和274、PFET金屬氧化物 閘極蓋278、PFET含金屬閘極電極282、PFET摻雜石夕蓋 286、PFET矽化物形成用金屬蓋290、和PFET矽閘極電極 294。 如前述關於裝置10之上下文的說明中，於後續的製 程期間’裝置100也許將經歷熱處理，其涉及升高的溫<度 經過預先特定的時間間隔。這些製程通常將包含進行二二 以反應性地分別結合後續沉積金屬層（未顯示）與 PFET矽閘極電極250和294，以形成用於閘極堆疊之相關 聯之金屬矽化物閘極電極接觸點。若未使用譬如由第如 圖中之閘極堆疊204、2〇8所示之NFET石夕化物形成〇 蓋，則二種可能結果之其中—種可能會發生。贿雜· 石夕蓋238和PF.ET摻雜石夕蓋286可能與後續形成的金】思之 應以形成經摻雜之金屬矽化物層。若覆蓋之矽曰反 250和294被完全反應地轉變成石夕化物，則此\電極 發生。若㈣極電極未全部被轉變，譬如像θ二^許會 太厚，則NFET摻雜矽蓋238和pFET摻雜矽蓋電極 它們的各自的閘極堆疊維持為未經反應之雷也許在 等電性摻雜矽 94831 23 201128713 層。若於閘極堆叠210和220中包含石夕化物形成用金屬蓋 242和290,譬如第22圖中所示，則第三種結果可能發生。 於此情況’當後續的熱處理包含暴露於溫度超過大約彻 艺經過大約5秒鐘或更久，則NFET摻雜矽蓋2祁和ρρΕτ 摻雜石夕蓋286將分別與石夕化物形成用.金屬t 242、29〇反應 以形成關聯之金屬碎化物。若來自這些蓋層之石夕以化學計 量計存在有超過來自鄰接之梦化物形成用金屬蓋層之金屬 物種，、則摻_蓋之—部分也許會保㈣未反應之播雜 矽。或者是，如此過量之矽於將矽閘極電極25〇和烈4轉 變為金屬石夕化物閘極接觸點之製程過程中也許會被消耗和 轉變成經摻雜之金屬梦化物區。以化學計量計超過來自各 個摻雜石夕蓋之石夕的來自梦化物形成用金屬蓋242和29〇之 金屬物種’則很可能將與來自石夕閘極電極和之矽 反應並且轉變成金屬石夕化物。包括分別被插置於含金屬閑 極電極234 # 282與石夕閘極電極250和m之間之摻雜硬 或者較佳之摻雜金屬石夕化物之層業經實驗發現可降低閑極 堆疊之AC阻抗。 因此，本文中說明之實施例提供新穎的方法用來製造 +導體裝置，該半導體裝豈具有經摻雜之含石夕蓋層插置於 電晶體，極堆疊之金屬與多晶石夕間極電極層之間。摻雜矽 :可以單獨使用或者與插置於摻雜％蓋層與多晶碎間極層 之石夕化物形成用金属蓋層結合使用。當於後續的製程 過程中破充分加熱時，摻雜石夕層可以保持未反應，或者可 以藉由與石夕化物形成用金屬蓋層（如果有使用）反應、或者 94831 24 201128713 、藉由與用來形成源極/汲極/閘極矽化物接觸點之後續衫成 之金屬層反應之任何-種情況，而後續地形成經接^金 屬矽化物。所導致的經摻雜之矽化物或者經摻雜之金屬矽 ，化物蓋層係橋接金屬與多晶矽閘極層之間之介面，有效地 增加此區域之導電率並且減少咸信為造成不希望之高閤槌 阻抗之原因之介面缺陷。藉由減少或者消除此種介面異 常，能夠更有效地使用具有其固有的性能優點之金屬閉極 材料，而結合多晶矽閘極以提供進一步之性能改善。造歧 優點包含相容的加入高1^介電閘極絕緣體、連同^們固有 的優越絕緣性質於閘極堆疊中。因此，可以結合使用這婆 方法製造CMOS裝置上之PFET和NFET電晶體，或者製造個 別的PFH和NFET裝置，並且能夠整合至習知的製造順序 中以提供改善之裝置性能。 雖然於本發明之上述詳細說明中呈現了至少一個實 施範例，.但是應該了解到存在有許多之變化。亦應該了解 到實施範例或諸實施範例僅是作實例用’而並不欲限制本 發明之範圍、應用、或架構於任何方式。而是，以上之詳 細說明將供提熟悉此項技術者施行本發明之實施範例之方 便的路途指引將了解到在例示之實施範例中所說明之功 能和元件的配置可以作各種之改變而仍不脫離本發明提出 於所附申請專利範圍中及其合法均等之範圍。 【圖式簡單說明】 上文中結合下列之圖式而說明本發明，其中相同之元 件付號表示相同之元件，且其中： 94831 25 201128713 第1至9圖示意地顯示依照本發明之範例實施例具有 經摻雜之含矽蓋層的半導體裝置之部分之剖面圖和用來製 造此種半導體裝置方法；以及 第10至22圖示意地顯示依照另一個範例實施例經摻 雜之含矽蓋層的半導體裝置之部分之剖面圖和用來製造此 種半導體裝置之方法。 【主要元件符號說明】 10、100 半導體M0S電晶體裝置（半導體裝置） 11 .載體晶圓’ 12 絕緣層 14、110 半導體基板（矽基板）。 16 薄石夕層 18、134 通道層 21 砍表面 2 2、13 8 閘極絕緣層 24、1.40 高k閘極絕緣層（高k介電層） 32、36、40 含金屬層 44、16.2 金屬氧化物閘極蓋層 48、142、146、150、166含金屬閘極電極層（含金屬閘極層） 50 外表面 52、170 含矽蓋層（摻雜之石夕蓋層） 56、174、242、290 矽化物形成用金屬蓋層 60 ' 178 含梦閘極電極層（含麥閘極層） 64、122、182 硬遮罩層 68、154、186、190 硬遮罩 70、95、98、204、208、210、220 閘極堆疊 72 PFET 74 閘極絕緣體 76 高k閘極絕緣體 26 94831 201128713 Λ 78 ' 86 80、82 含金屬層 84、162 含金屬閘極電極 金屬氧化物閘極蓋層 - 88 摻雜之矽蓋 90 矽化物形成用金屬蓋 92 梦閘極電極 108 表面區域 118 隔離區域 130 砍表面 180 NFET區域 200 PFET區域 222 NFET閘極絕緣體 226 NFET高k閘極絕緣體 230 NFE：T金屬氧化物閘極蓋 234 NFET含金屬閘極電極 238 NFET摻雜之矽蓋 242 NFET矽化物形成用金屬蓋 250 NFE1T矽閘極電極 254 PFET 通道 258 PFE1T閘極絕緣體 262 PFET高k閘極絕緣體 266、270、274 PFET 含金屬層 278 PFE1T金屬氧化物閘極蓋 282 PFET含金屬閘極電極 286 PFE1T摻雜之矽蓋 290 PFE1T矽化物形成用金屬蓋 294 PFE：T矽閘極電極 27 94831It is preferable to form a titanium-based material of Mg or a master alloy, a titanium-based material of 譬*TiN or miN, a gold base material of TaAIN or Ta2C, or the like; and a metal-containing idle layer i662N can be implemented by a PVD or CVD process. The metal-containing impurity layer 166 preferably has a product of from about 2.5 n'. 5纳米厚。 The degree, and preferably about 3. 5nm thick. Large, force 7 (10) thickness 94831 20 201128713 After deposition of the metal-containing gate layer 166, the semiconductor device 100 is maintained under vacuum (if used for deposition of layer 166) or in another type of substantial oxygen-free environment to avoid native An oxide is formed on surface 168 of metal-containing gate layer 166. The capping layer 包含0 containing doping is then overlaid to cover the metal-containing gate layer 166 in the NFET and =ΕΤ regions 180 and 2, using, for example, an LPCVD process. The doped layer 170 includes a mixture of impurity dopants that are added to the film in situ during the deposition process. Such dopant elements may include, for example, bismuth (8), or include ruthenium such as phosphorus (arsenic), arsenic (As) or bismuth (Sb). In one embodiment, the doped cap layer 170 has a thickness ranging from about 1 〇 nm, and preferably about 8 咖. In another embodiment, the doped (four) layer (7) has a doping concentration from a large "off 10" to about Ux, at/cm3. ,·〇Χΐ° no No in the picture. The gate electrode layer 17 is etched or preferably (4), and the process of the front electrode L and the dopant element may be used to deposit the quaternary electrode layer 178. After that, it can be implanted according to the miscellaneous. The desired application and the overall process used are formed to form an additional layer of 100 layers comprising a hard masking layer 9 layer that is deposited. These pole layers 178, using appropriate optical widgets 9 to cover the hard masks containing the 矽 gates, to form hard and bribe areas 18〇 and 2〇〇, such as the μth map now covered by 186 and 190 Each is used as an etch mask. The hard mask is divided into portions of the layers 180 and 94831 21 201128713 200 to form gate stacks 2〇4 and 2〇8, respectively, as shown in Fig. 20. When such money is removed and removed (including removal of hard masks 186 and 1J0), gate stack 204 includes NFET gate insulator 222, NFET high-k gate insulator 226, NFn metal oxide gate cap 23, ΝρΕτ includes a metal gate electrode 234, an NFET-doped cap 238, and a swollen elbow gate electrode 250. Gate stack 208 includes PFET channel 254, PFET gate insulator 258, .PFET high-k gate insulator 262, PFET metal-containing layers 266, 27Q, and 274, optionally used, pFET metal oxide gate cap 278, PFET A metal gate electrode 282, a PFET doped cap 286, and a PFET gate electrode 294. In another embodiment, a germanium formation metal cap layer 174 is deposited to cover the doped capping layer 170, such as the 21st, before the germanium-containing gate electrode layer 178 is formed between the region discrimination and the 200. Shown in the figure. The metallization layer 174 for telluride formation may include any of the metals described above with reference to the metallization layer 56 for telluride formation or any combination of the metals. In another embodiment, the metallization layer 174 for telluride formation comprises Ni and comprises from about 5 to about 15. atomic percent of Pt, and preferably comprises from about 5 to about 1 atomic percent of pt. The metallization layer for depositing the telluride is deposited to a thickness of from about 4 nm to about 12 nm of wood, and preferably between about 5 nm and 1 〇 nm. After the formation of the metallization layer 174 for telluride formation, the process steps described above and shown in FIGS. 18 and 19 are performed, including forming a stone-containing gate electrode layer 178, a hard mask layer 182, and a hard mask. 18& and 19〇. These hard masks are then used as etch masks to form the interstitial stacks 210 and 220, respectively, to cover regions 180 and .200, as shown in FIG. 94831 22 201128713 After etching and removing hard masks 186 and 190, gate stack 210 includes NFET gate insulator 222, NFET high-k gate insulator 226, NFET 'metal oxide gate cap 230, NFET metal gate The electrode 234, the NFET, the doped crucible cover 238, the NFET telluride forming metal cap 242, and the NFE:T broken gate electrode 250. Gate stack 220 includes PFET channel 254, PFET gate insulator 258, PFET high-k gate insulator 沆 2, PFET metal-containing layers 266, 270, and 274, optionally used, PFET metal oxide gate cap 278, PFET A metal-containing gate electrode 282, a PFET doped cover 286, a PFET telluride-forming metal cap 290, and a PFET-turn gate electrode 294. As previously described with respect to the context of device 10, device 100 may undergo a heat treatment during subsequent processing, which involves elevated temperatures & degrees through a predetermined time interval. These processes will typically involve performing two or two reactive combinations of subsequent deposited metal layers (not shown) with PFET gate electrodes 250 and 294 to form associated metal telluride gate electrode contacts for gate stacking. point. If a NFET is used, such as the NFET as shown in the gate stacks 204, 2, 8 in the figure, one of the two possible outcomes may occur. Brittle·Shi Xigai 238 and PF.ET doped Shixi cover 286 may be formed with the subsequent formation of a doped metal telluride layer. If the overlays 250 and 294 are completely reacted to become lithiates, then the \electrode occurs. If the (four) pole electrodes are not all converted, such as if θ is too thick, then the NFET-doped cap 238 and the pFET-doped cap electrode are maintained in their respective gate stacks as unreacted thunder, perhaps in isoelectricity. Doped 矽94831 23 201128713 layer. If the metal lids 242 and 290 for forming the ceramsite are included in the gate stacks 210 and 220, as shown in Fig. 22, a third result may occur. In this case, when the subsequent heat treatment involves exposure to a temperature of more than about 15 seconds or more, the NFET-doped lid 2祁 and ρρΕτ doped Shixi cover 286 will be formed separately from the Li Xi compound. Metals t 242, 29 are reacted to form associated metal fragments. If there is a metal species from the caps on the chemical scale that exceeds the metal cap layer from the adjacent dream compound formation, then the portion of the cap may be protected (4) unreacted solutes. Alternatively, such an excess may be consumed and converted into a doped metal dreaming zone during the process of converting the gate electrodes 25 〇 and 烈 4 into the metal lithium gate contact. It is likely that the metal species from the metallization caps 242 and 29 of the dream compound formation from the respective doped stones will be reacted with the samarium electrode and the ruthenium and converted into metal. Shi Xitian. The layer comprising the doped hard or better doped metal cerium compound respectively interposed between the metal-containing idle electrode 234 # 282 and the shi-shi gate electrode 250 and m has been experimentally found to reduce the AC of the idle-stack stack. impedance. Accordingly, the embodiments described herein provide a novel method for fabricating a +conductor device having a doped tarpaulin layer interposed in a transistor, a stack of metal and a polycrystalline intergranular pole Between the electrode layers. Doping 矽: It can be used alone or in combination with a metal cap layer for forming a yttrium-forming cap layer and a polycrystalline inter-layer electrode layer. The doped layer may remain unreacted during the subsequent process, or may be reacted by a metal cap layer (if used) with the formation of the stone, or 94831 24 201128713 by Any of the conditions of the metal layer reaction used to form the source/drain/gate telluride contact points, followed by the formation of the metallization. The resulting doped telluride or doped metal germanium, the capping layer bridges the interface between the metal and the polysilicon gate layer, effectively increasing the conductivity of the region and reducing the saltiness is undesirable. Interface defects due to high impedance. By reducing or eliminating such interface anomalies, metal closed-pole materials with inherent performance advantages can be used more efficiently, combined with polysilicon gates to provide further performance improvements. The advantages of the inclusion include the compatibility of the high dielectric gate insulators, together with the inherent superior insulating properties of the gate stack. Thus, PFET and NFET transistors on CMOS devices can be fabricated in conjunction with this method, or individual PFH and NFET devices can be fabricated and integrated into conventional fabrication sequences to provide improved device performance. Although at least one embodiment has been presented in the foregoing detailed description of the invention, it should be understood that there are many variations. It should also be understood that the examples or embodiments are merely illustrative and are not intended to limit the scope, application, or architecture of the invention. Rather, the above detailed description will provide a convenient way of carrying out the embodiments of the present invention. It will be appreciated that the configuration of the functions and components illustrated in the illustrated embodiments can be varied. The scope of the appended claims is intended to be within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The invention is described above in conjunction with the following drawings, wherein like reference numerals indicate like elements, and wherein::::::::::::::::::::::::::::::::: A cross-sectional view of a portion of a semiconductor device having a doped cap layer and a method for fabricating such a device; and FIGS. 10 through 22 schematically show a doped cap layer in accordance with another exemplary embodiment A cross-sectional view of a portion of a semiconductor device and a method for fabricating such a semiconductor device. [Description of main component symbols] 10, 100 Semiconductor MOS transistor device (semiconductor device) 11. Carrier wafer '12 Insulation layer 14, 110 Semiconductor substrate (矽 substrate). 16 Thin stone layer 18, 134 Channel layer 21 Cut surface 2 2, 13 8 Gate insulation layer 24, 1.40 High-k gate insulation layer (high-k dielectric layer) 32, 36, 40 Metal layer 44, 16.2 Metal The oxide gate cap layer 48, 142, 146, 150, 166 comprises a metal gate electrode layer (including a metal gate layer) 50. The outer surface 52, 170 comprises a capping layer (doped stone cap layer) 56, 174 242, 290 metallization layer 60' 178 for telluride formation, including dream gate electrode layer (including wheat gate layer) 64, 122, 182 hard mask layer 68, 154, 186, 190 hard mask 70, 95, 98, 204, 208, 210, 220 Gate Stack 72 PFET 74 Gate Insulator 76 High-k Gate Insulator 26 94831 201128713 Λ 78 ' 86 80, 82 Metal-containing layer 84, 162 Metal gate electrode with metal gate Cladding - 88 doped crucible cover 90 Deuterated metal forming cap 92 Dream gate electrode 108 Surface region 118 Isolation region 130 Chopping surface 180 NFET region 200 PFET region 222 NFET gate insulator 226 NFET high k gate insulator 230 NFE :T metal oxide gate cap 234 NFET metal gate electrode 238 NFET doped cap 242 NFET telluride forming metal cap 250 NFE1T 矽 gate electrode 254 PFET channel 258 PFE1T gate insulator 262 PFET high-k gate insulator 266, 270, 274 PFET metal-containing layer 278 PFE1T metal oxide gate cap 282 PFET metal gate Electrode electrode 286 PFE1T doped cap 290 PFE1T Telluride forming metal cap 294 PFE: T矽 gate electrode 27 94831