TWI785052B - 包括穿透孔洞貫孔的組件基板及其製作方法 - Google Patents
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Abstract
各種實施例係關於基板,具有一或更多井結構和從井結構底部延伸穿過基板的梯形柱形穿透孔洞貫孔。
Description
本申請案主張西元2017年6月1日申請的美國臨時專利申請案第62/513718號的優先權權益,本申請案依賴該臨時申請案全文內容且該臨時申請案全文內容以引用方式併入本文中。
各種實施例係關於基板,具有一或更多井結構和從井結構底部延伸穿過基板的梯形柱形穿透孔洞貫孔。
LED顯示器、LED顯示器部件和陣列式LED裝置包括大量二極體放置在顯示器或裝置表面各處的預定位置。射流組裝可用於相對基板組裝二極體。組裝通常係隨機製程,藉以將LED裝置置入基板的井內。將LED裝置置入井的問題為當懸浮液中的LED裝置流通過先前放置的裝置時傾向位移出井。此會導致無法充分插裝(populate)顯示器。
故至少基於上述原因,本領域需要用於製造組件基板的先進系統和方法。
各種實施例係關於基板,具有一或更多井結構和從井結構底部延伸穿過基板的梯形柱形穿透孔洞貫孔。
「發明內容」僅提供本發明的一些實施例概述。「在一實施例中」、「根據一實施例」、「在不同實施例中」、「在一或更多實施例中」、「在特定實施例中」等用語大體意指接在用語後的特定特徵、結構或特性係包括在本發明至少一實施例內,且可包括在本發明超過一個實施例內。重要的是,該等用語不必然指稱同一實施例。本發明的許多其他實施例在參閱以下詳細實施方式說明、後附申請專利範圍和附圖後將變得更清楚易懂。
各種實施例係關於基板,具有一或更多井結構和從井結構底部延伸穿過基板的梯形柱形穿透孔洞貫孔。
一些實施例提供組件基板,組件基板包括基板和組件結構層。基板具有第一表面和第二表面,且組件結構層置於基板的第一表面上面。組件結構層包括複數個開口,各自露出基板的部分第一表面。至少一穿透孔洞貫孔從基板的第二表面延伸到基板的第一表面,其中穿透孔洞貫孔的第一末端可於基板的第一表面進入並在複數個開口之一內,且穿透孔洞貫孔的第二末端可於基板的第二表面進入。在穿透孔洞貫孔的第二末端平行基板的第二表面的截面積大於在穿透孔洞貫孔的第一末端平行基板的第二表面的截面積。
在上述實施例的一些情況下,穿透孔洞貫孔的形狀係梯形柱。在上述實施例的不同情況下,複數個開口至少包括各具第一形狀的第一支組和各具第二形狀的第二支組。在一些情況下,其中至少一穿透孔洞貫孔係從第一支組所含開口延伸的第一穿透孔洞貫孔,組件基板進一步包括從第二支組所含開口延伸的第二穿透孔洞貫孔。第二穿透孔洞貫孔展露不同於第一穿透孔洞貫孔的尺度特性,例如不同尺寸及/或形狀。
在不同例子中,穿透孔洞貫孔完全填滿導電材料。在其他例子中,穿透孔洞貫孔共形填充導電材料。在一或更多例子中,電觸點形成於複數個開口之一的底部靠近穿透孔洞貫孔的第一開口,且導電材料形成於穿透孔洞貫孔,使之接觸電觸點。
在上述實施例的一些情況下,基板由玻璃形成。在一些實施例中,基板由第一種玻璃形成,且組件結構層由第二種玻璃形成。在上述實施例的不同情況下,至少一穿透孔洞貫孔係從複數個開口之一延伸的第一穿透孔洞貫孔,且組件基板進一步包括從基板的第一表面延伸到基板的第二表面的第二穿透孔洞貫孔。在此情況下,第一穿透孔洞貫孔呈梯形柱形,且第二穿透孔洞貫孔呈直筒形。
其他實施例提供形成組件基板的方法。方法包括:提供具第一表面和第二表面的基板;形成至少一穿透孔洞貫孔從基板的第二表面延伸到基板的第一表面;及形成組件結構層至基板的第一表面上面。穿透孔洞貫孔的第一末端位於基板的第一表面,且穿透孔洞貫孔的第二末端位於基板的第二表面,且穿透孔洞貫孔在第二表面的截面積大於穿透孔洞貫孔在第一表面的截面積。組件結構層包括至少一開口,開口露出基板的部分第一表面,此為穿透孔洞貫孔的第一末端所在。
在上述實施例的一些情況下,穿透孔洞貫孔的形狀係梯形柱。在上述實施例的不同情況下,形成至少一穿透孔洞貫孔包括:於基板的第一表面上待形成穿透孔洞貫孔的位置雷射鑽孔基板,以形成孔洞延伸穿過基板而至基板的第二表面;用抗蝕材料遮蔽基板的第一表面,抗蝕材料覆蓋在基板的第一表面的孔洞開口;及蝕刻基板,使在基板的第二表面的孔洞開口變得比在基板的第一表面的孔洞開口大。在一些情況下,形成至少一穿透孔洞貫孔進一步包括:移除覆蓋在基板的第一表面的孔洞開口的抗蝕材料;及再蝕刻基板,使在基板的第一表面的孔洞開口與在基板的第二表面的孔洞開口均增大。
在上述實施例的一或更多情況下,方法進一步包括用導電材料填充穿透孔洞貫孔。在一些情況下,方法包括用導電材料完全填滿穿透孔洞貫孔。在其他情況下,方法包括用導電材料共形塗覆穿透孔洞貫孔,使穿透孔洞貫孔僅部分填滿。
參照第1a圖,根據本發明一或更多實施例,所示射流組裝系統100能相對基板140表面頂上的組件結構層190移動由載體液體115與複數個實體物件130組成的懸浮液110。雖然第1a圖至第1b圖所述相關實例聚焦在射流放置實體物件,但包括組件結構層190的基板亦可用於其他組裝法。例如,基板140與組件結構層190結合可用於取放(pick-n-place)或其他製程。實體物件130可包括、但不限於電子元件、二極體、微發光二極體(microLED)及/或其他物件。
組件結構層190可利用本領域已知任何製程來形成射流結構至基板140上面而形成。形成組件結構層190可在一或更多基板140和組件結構層190上形成電子電路前或後完成。在一些例子中,基板140與組件結構層190的結合係固定的,在其他例子中,結合係靈活的。在一實例中,基板140與組件結構層190結合可用於製造大面積射流組裝板,以容納大量微LED並各自置入各井142而形成顯示面板。基板140與組件結構層190的其他可用結合實例包括、但不限於大面積照明與招牌和射頻識別標籤。
在一些實施例中,用於形成基板140的材料為玻璃,用於形成組件結構層190的材料係無機材料。然本發明的其他實施例當可使用不同材料組合或複合材料。例如,基板140亦可為玻璃陶瓷或陶瓷材料。基板140和層190可為光學透明、不透明或半透明。在一些例子中,當接觸高於攝氏六百度(600℃)的處理溫度時,用於形成基板140和組件結構層190的一或更多材料乃選擇呈機械相容。在其他例子中,材料相容於各種其他處理溫度。在一些例子中,材料相容於高於攝氏五百度(500℃)的處理溫度。在其他例子中,材料相容於高於攝氏四百度(400℃)的處理溫度。在另些例子中,材料相容於高於攝氏三百度(300℃)的處理溫度。此處理溫度尤其適合薄膜電晶體製造、焊料回流和共熔接合製程。
參照第1b圖,該圖圖示基板140的示例性表面上視圖199,其中井142(如圓圈所示)的陣列延伸到組件結構層190內且各具相應穿透孔洞貫孔143的開口(如內圈所示)從井142的底部延伸。每一井142具有直徑192和深度194。應注意雖然井142的截面圖示為圓形,但不同相關實施例可使用其他形狀。例如,本發明的不同實施例可採用其他形狀,例如方形、梯形或其他任意形狀。在不同例子中,直徑192大於五(5)微米。在其他例子中,直徑192大於十(10)微米。在另些不同例子中,直徑192大於二十(20)微米。在附加例子中,直徑192大於三十(30)微米。在一或更多例子中,深度194大於十(10)奈米。在其他例子中,深度194大於一百(100)奈米。在另些例子中,深度194大於一(1)微米。在一些特定實施例中,直徑192為四十(40)微米或以上並形成於組件結構層190,位移193為五百(500)微米或以下,且深度194為大於三(3)微米。在一些例子中,組件結構層190的厚度(即深度194)實質等於實體物件130的高度。在其他例子中,組件結構層190的厚度大於實體物件130的厚度,其中井142待整個形成於組件結構層190內。在其他例子中,組件結構層190的厚度小於實體物件130的厚度。注意各種不同尺寸、形狀、厚度及組合的實體物件可組裝到包括組件結構層190的基板上。井142的入口開口大於實體物件130的寬度,如此只有一個實體物件130可置入任一給定井142內。應注意雖然實施例描述將實體物件130置入井142內,根據本發明不同實施例也可放置其他裝置或物件。另應注意在一些特定應用中,未存有層190,圖案化表面特徵結構直接在基板140進行。
穿透孔洞貫孔143形成以從井142的底部延伸穿過基板140。穿透孔洞貫孔143的形狀為梯形柱,其中在基板140的底表面的開口大於在各井142的底部的開口。穿透孔洞貫孔143容許吸力施加至基板140底側,以經由各穿透孔洞貫孔143拉出一些載體液體115,直到實體物件130之一置入井142內,穿透孔洞貫孔143由此延伸。隨著實體物件130置入井142內,施加至基板130底側的吸力將操作使置入的實體物件130保持在井142內適當位置。
放置裝置150將懸浮液110放置到射流組件層190和基板140的表面上面。懸浮液110由壩結構側邊120頂在頂部。在一些實施例中,放置裝置150係泵且可進入懸浮液110的貯槽。懸浮液移動裝置160攪動置於基板140上的懸浮液110,使實體物件130相對基板140的表面移動。當實體物件130相對基板140的表面移動時,便置入井142內。同樣地,如前所述,施加至基板140底側的吸力促使實體物件130置入井142內,且相同吸力會促使置入的實體物件保持在井142內。在一些實施例中,懸浮液移動裝置160係朝三維移動的刷子。基於所述內容,本領域一般技術人士將明白各種裝置可用於執行懸浮液移動裝置160的功能,包括、但不限於泵。如所述,包括射流製程或除射流製程外的替代方法可用於相對貫孔定位實體物件。另行或替代射流製程來相對貫孔定位實體物件,僅一種附加方法可使用取放方法。在此實例中,實體物件不置入表面井結構本身,而是相對貫孔位於其他預定座標。
擷取裝置170包括伸進懸浮液110的入口,且能回收部分懸浮液110,包括部分載體液體115與未置入實體物件130,及送回回收材料再利用。在一些實施例中,擷取裝置170係泵。在一些例子中,基板140與組件結構層190的結合形成類似第3圖、第6圖、第6圖及第8圖所述相關實施例;及/或利用第5圖、第7圖及第9圖所述一或更多相關製程。
基板140與組件結構層190結合不僅展現實體特徵結構,例如所示射流組裝系統100的井142、流道或其他實體表面結構,還展現機械特性,例如上述剛性或撓性,亦可選擇或形成呈現特定光學性質。例如,在光學性質方面,基板140與無機組件結構層190結合可保持實質透明、具有不透明區來阻擋或隔絕光、具有特定光學吸收區或具有控制光學散射區。圖案化基板140與無機組件結構層190結合可只在所示射流組裝系統100的頂表面、或頂與底表面進行。實體特徵結構的二維形狀可利用適當光罩控制,儘管第1a圖圖示為完全垂直,實體結構的垂直側壁角可傾斜或塑形。上述圖案化可利用濕蝕刻、電漿蝕刻、剝除或其他圖案化製程或圖案化製程組合完成。
參照第2a圖至第2b圖,第2a圖至第2b圖圖示根據本發明一些實施例,部分組件基板的上視圖200和對應側視圖250,包括井結構240和對應穿透孔洞貫孔結構280。如所示,井結構240延伸入組件結構層210而至基板220的頂表面225。井結構240具有寬度230和深度270。應注意在一些例子中,井結構240不一直延伸穿過組件結構層210,在此情況下,基板220在井結構240底部的頂表面225未露出。井結構240的側壁245界定井240的外圍。
如所示,穿透孔洞貫孔結構280實質塑形成梯形柱並於基板220的頂表面225具小開口(圖示為直徑284)且於基板220的底表面290具大開口(圖示為直徑284)。梯形柱形穿透孔洞貫孔可藉由如在待形成穿透孔洞貫孔處雷射鑽孔穿透基板220而製造。雷射鑽孔會產生實質直筒開口延伸穿過基板。與欲形成最終穿透孔洞貫孔的寬度相比,開口寬度較小。施用雷射鑽孔的基板側接著用抗蝕膜遮蔽,及用第一高悌勒(Thiele)模量(Φ1
)蝕刻材料來蝕刻基板,計第一時間(t1
)。藉由僅從一側蝕刻基板,雷射鑽孔所形成實質直筒開口的開口一側打得比另一側更開,從而形成梯形柱形開口。接著自基板移除抗蝕膜,而留下露出梯形柱形開口的兩端,再用第二高悌勒模量(Φ2
)蝕刻材料來蝕刻基板,計第二時間(t2
)。藉由從兩端蝕刻現有梯形柱形開口,可增大開口尺寸,同時維持梯形柱形。
應注意不同尺寸的穿透孔洞貫孔可藉由用抗蝕膜遮蔽一些梯形柱形穿透孔洞貫孔兩側,及再蝕刻基板來進一步增大梯形柱形穿透孔洞貫孔支組尺寸而形成。另外,在初始蝕刻期間不遮蔽雷射鑽孔孔洞支組,使未遮蔽貫孔形狀保持為實質直筒,可於基板形成一些直形貫孔。基於所述內容,本領域一般技術人士將明白各種穿透孔洞貫孔尺寸與形狀組合可根據不同實施例形成穿過基板。又,多種穿透孔洞尺寸和形狀可存於同一基板。此可包括穿透孔洞與盲孔組合。
參照第3圖,該圖圖示具多個穿透孔洞貫孔與井組合的部分組件基板300,其中各組合根據本發明不同實施例設計成容納不同尺寸與形狀的實體物件。特別地,組件基板300包括置於基板340上面的組件結構層390。組件結構層390繪示為具有各自延伸到基板340的頂表面的三個不同井結構342、344、346,及延伸穿過基板340的對應穿透孔洞貫孔343、345、347。第3圖圖示在基板340中的多個穿透孔洞貫孔組合。此外,可於同一基板形成結合穿透孔洞的盲孔。
井結構346比井結構344或井結構342窄,以只讓較小實體物件336得插入於內。當部分實體物件332或實體物件334插入井結構346時,相應實體物件大部分實質在組件結構層390的頂表面上方延伸,而於射流組裝期間接觸材料流,此可能造成實體物件位移出井346。相較於井結構344的側壁,井結構346的側壁實質為錐形,以促進實體物件336朝所示位向置於井結構346內。如所示,實體物件336部分插入穿透孔洞貫孔347,穿透孔洞貫孔347的寬度擴展得比穿透孔洞貫孔343和穿透孔洞貫孔345大。穿透孔洞貫孔345擴大可藉由實行附加蝕刻基板340、同時用抗蝕膜覆蓋穿透孔洞貫孔343、345來達成。將部分實體物件336插入穿透孔洞貫孔347時,在進行射流組裝期間,實體物件336可能保持固定於井結構346。在基板340的底表面附近施加吸力可強化實體物件336於井結構346內的穩定性。在除第3圖所示以外的任何位向上,在進行射流組裝期間,實體物件336更不可能留在井結構346。
井結構342比井結構344窄,但比井結構346寬,是以容許插入實體物件332或實體物件336、而非實體物件334。然由於穿透孔洞貫孔343比穿透孔洞貫孔347窄,較小實體物件336無法插入穿透孔洞貫孔343。在未插入穿透孔洞貫孔343的情況下,實體物件的高度實質在組件結構層390的頂表面上方延伸,而於射流組裝期間接觸材料流,此可能造成實體物件位移出井342。反之,實體物件332包括當適當插入井結構342時能插入穿透孔洞貫孔343的小延伸區。將部分實體物件332插入穿透孔洞貫孔343時,在進行射流組裝期間,實體物件332可能保持固定於井結構342。在基板340的底表面附近施加吸力可強化實體物件332於井結構342內的穩定性。在除第3圖所示以外的任何位向上,在進行射流組裝期間,實體物件332更不可能留在井結構342。
井結構344乃夠寬以讓實體物件332、實體物件334或實體物件336插入於內。然當置於井結構344時,實體物件332和實體物件336的總高度將導致相應實體物件大部分實質在組件結構層390的頂表面上方延伸,而於射流組裝期間接觸材料流,此可能造成實體物件位移出井344。穿透孔洞貫孔345實質小於穿透孔洞貫孔343時尤其如是,實體物件332設計成插入穿透孔洞貫孔343的延伸部太大,以致無法實質插入穿透孔洞貫孔345。又,小尺寸的穿透孔洞貫孔345可藉由用抗蝕膜覆蓋穿透孔洞貫孔345、同時使基板340接觸蝕刻以相對穿透孔洞貫孔345增大穿透孔洞貫孔343及/或穿透孔洞貫孔347的尺寸來達成。對照將實體物件332或實體物件336插入井結構344,插入井結構344時,實體物件334未明顯在組件結構層390的頂表面上方延伸,實體物件334的側壁為實質垂直,此匹配井結構344的側壁。上述因素結合易致使實體物件334在進行射流組裝期間留在井結構344內。在基板340的底表面附近施加吸力可強化實體物件334於井結構344內的穩定性。
參照第4圖,該圖圖示具多個穿透孔洞貫孔446與井441組合的部分組件基板400,其中各組合具有相同尺寸與形狀,其中穿透孔洞貫孔446根據本發明一或更多實施例填充導電材料445。如圖所示,組件基板400包括置於基板440上面的組件結構層490。組件結構層490繪示為具有各自延伸到基板440的頂表面的三個相同井結構441,及延伸穿過基板440的對應穿透孔洞貫孔446。
井441由只讓單一實體物件430置於給定井441內的形狀與尺寸構成。實體物件430置入相應井441前,於各井441底部形成底部電觸點。在井441底部形成底部電觸點可在組件結構層490形成於基板440上面前或後施行。將實體物件430置入相應井441期間,穿透孔洞貫孔446打開而容許吸力施加至組件基板400底側,以助於捕集井441內的實體物件430。一旦實體物件430位於井441中,頂部電觸點452即可連接各實體物件430頂部與置於組件結構層490上面的相應連接結構454。此外,穿透孔洞貫孔446填充導電材料445,且底部基板電觸點462連接穿透孔洞貫孔446內的導電材料445與置於組件基板400下面的相應連接結構464、466。
參照第5圖,流程圖500顯示根據本發明一些實施例的方法,用於製造類似上述第4圖所示組件基板。依循流程圖500,形成基板440(方塊505)。在一些例子中,基板440為透明玻璃基板。在特定實施例中,透明玻璃基板係以本領域已知製程形成的Corning Eagle XG®纖薄玻璃基板。在特例中,透明玻璃基板為七百(700)微米厚。基於所述內容,本領域一般技術人士將明白本發明相關不同實施例可使用其他基板材料和厚度。
在基板440待形成穿透孔洞貫孔446的位置進行雷射鑽孔(方塊510)。雷射鑽孔會產生延伸穿過基板的實質直筒開口。與欲形成最終穿透孔洞貫孔的寬度相比,開口寬度較小。用抗蝕膜遮蔽施行雷射鑽孔的基板側(方塊515)。或者,遮蔽施行雷射鑽孔的對側。接著用第一高悌勒模量(Φ1
)蝕刻材料蝕刻基板440,計第一時間(t1
)(方塊520)。藉由僅從一側蝕刻基板440,雷射鑽孔所形成實質直筒開口的開口一側打得比另一側更開,從而形成梯形柱形開口。然後自基板440移除抗蝕膜,以露出梯形柱形開口的兩端(方塊525)。此時,接著用第二高悌勒模量(Φ2
)蝕刻材料蝕刻基板440,計第二時間(t2
)(方塊530)。藉由從兩端蝕刻現有梯形柱形開口,可增大開口尺寸,同時維持梯形柱形。此時,基板440中的穿透孔洞貫孔446已完成且可用於電子裝置製造,無需繼續進行方塊535。
組件結構層490形成於基板上面(方塊535)。組件結構層490包括井441形成於內,井441位於穿透孔洞貫孔446的至少一支組上方。組件結構層可任意結合層形成、然後遮蔽及蝕刻以界定井而形成,或可由附加製程形成,其中圖案形成於待存有井處,再形成組件結構層圍繞圖案,隨後移除圖案,以於組件結構層490中留下開井。基於所述內容,本領域一般技術人士將明白各種形成組件結構層的方式。
電觸點形成於井441的底部,此將當作置入組件結構層490的井441內的實體物件430的底部觸點(方塊540)。可利用本領域已知任何製程來沉積或形成導電材料至井441的底部。將實體物件430組裝到井441中(方塊545)。組裝可利用任何製程完成,包括、但不限於第1a圖至第1b圖所述射流組裝。在一些例子中,吸力施加至基板440的底部,促使實體物件430適當置入井441。
頂部觸點452形成以連接各實體物件430的頂側與相應連接結構454(方塊550)。可利用本領域已知任何製程來沉積或形成導電材料至實體物件430和組件結構上面。此外,穿透孔洞貫孔446填充導電材料445(方塊555),且底部觸點462形成以電氣連接實體物件430的底側與相應連接結構464、466(方塊560)。在此例中,填充堵在頂表面的穿透孔洞貫孔係盲孔填充程序。可利用本領域已知任何製程來用導電材料445填充穿透孔洞貫孔446及/或用於沉積或形成導電材料基板440以形成底部觸點462。
參照第6圖,該圖圖示具多個穿透孔洞貫孔646與井641組合的部分組件基板600,其中各組合具有相同尺寸與形狀,且其中穿透孔洞貫孔646根據本發明一或更多實施例共形塗覆導電材料645。如圖所示,組件基板600包括置於基板640上面的組件結構層690。組件結構層690繪示為具有各自延伸到基板640的頂表面的三個相同井結構641,及延伸穿過基板640的對應穿透孔洞貫孔646。
井641由只讓單一實體物件630置於給定井641內的形狀與尺寸構成。實體物件630置入相應井641前,於各井641底部形成底部電觸點。在井641底部形成底部電觸點可在組件結構層690形成於基板640上面前或後施行。將實體物件630置入相應井641期間,穿透孔洞貫孔646打開而容許吸力施加至組件基板600底側,以助於捕集井641內的實體物件630。一旦實體物件630位於井641中,頂部電觸點652即可連接各實體物件630頂部與置於組件結構層690上面的相應連接結構654。此外,穿透孔洞貫孔646共形塗覆導電材料645,且底部基板電觸點662沿穿透孔洞貫孔646的壁面電氣連接導電材料645與置於組件基板600下面的相應連接結構664、666。
參照第7圖,流程圖700顯示根據本發明一些實施例的方法,用於製造類似上述第6圖所示組件基板。依循流程圖700,形成基板640(方塊705)。在一些例子中,基板640為透明玻璃基板。在特定實施例中,透明玻璃基板係以本領域已知製程形成的Corning Eagle XG®纖薄玻璃基板。在特例中,透明玻璃基板為七百(700)微米厚。基於所述內容,本領域一般技術人士將明白本發明相關不同實施例可使用其他基板材料和厚度。
在基板640待形成穿透孔洞貫孔646的位置進行雷射鑽孔(方塊710)。雷射鑽孔會產生延伸穿過基板640的實質直筒開口。與欲形成最終穿透孔洞貫孔的寬度相比,開口寬度較小。用抗蝕膜遮蔽施行雷射鑽孔的基板640一側(方塊715)。或者,遮蔽施行雷射鑽孔的對側。接著用第一高悌勒模量(Φ1
)蝕刻材料蝕刻基板640,計第一時間(t1
)(方塊720)。藉由僅從一側蝕刻基板640,雷射鑽孔所形成實質直筒開口的開口一側打得比另一側更開,從而形成梯形柱形開口。然後自基板640移除抗蝕膜,以露出梯形柱形開口的兩端(方塊725)。此時,接著用第二高悌勒模量(Φ2
)蝕刻材料蝕刻基板640,計第二時間(t2
)(方塊730)。藉由從兩端蝕刻現有梯形柱形開口,可增大開口尺寸,同時維持梯形柱形。此時,基板640中的穿透孔洞貫孔646已完成且可用於電子裝置製造,無需繼續進行方塊735。
組件結構層690形成於基板640上面(方塊735)。組件結構層690包括井641形成於內,井641位於穿透孔洞貫孔646的至少一支組上方。組件結構層可任意結合層形成、然後遮蔽及蝕刻以界定井而形成,或可由附加製程形成,其中圖案形成於待存有井處,再形成組件結構層圍繞圖案,隨後移除圖案,以於組件結構層690中留下開井。基於所述內容,本領域一般技術人士將明白各種形成組件結構層的方式。
電觸點形成於井641的底部,此將當作置入組件結構層690的井641內的實體物件630的底部觸點(方塊740)。可利用本領域已知任何製程來沉積或形成導電材料至井641的底部。將實體物件630組裝到井641中(方塊745)。組裝可利用任何製程完成,包括、但不限於第1a圖至第1b圖所述射流組裝。在一些例子中,吸力施加至基板640的底部,促使實體物件630適當置入井641。
頂部觸點652形成以連接各實體物件630的頂側與相應連接結構654(方塊750)。可利用本領域已知任何製程來沉積或形成導電材料至實體物件630和組件結構上面。此外,穿透孔洞貫孔646填充導電材料645(方塊755),且底部觸點462形成以電氣連接實體物件630的底側與相應連接結構664、666(方塊760)。在此例中,填充堵在頂表面的穿透孔洞貫孔係盲孔填充程序。可利用本領域已知任何製程來用導電材料645填充穿透孔洞貫孔646及/或用於沉積或形成導電材料基板640以形成底部觸點662。
參照第8圖,該圖圖示具多個穿透孔洞貫孔846與井841組合的部分組件基板800,其中一些組合具有不同形狀及/或尺寸。如圖所示,組件基板800繪示為具有梯形柱形穿透貫孔846從置於基板840上面的組件結構層890中的井841的至少一支組延伸;至少一直筒形穿透孔洞貫孔870從組件結構層890的頂表面延伸到基板840的底表面。
井841由只讓單一實體物件830置於給定井841內的形狀與尺寸構成。實體物件830置入相應井841前,於各井841底部形成底部電觸點。在井841底部形成底部電觸點可在組件結構層890形成於基板840上面前或後施行。將實體物件830置入相應井841期間,穿透孔洞貫孔846打開而容許吸力施加至組件基板800底側,以助於捕集井841內的實體物件830。一旦實體物件830位於井841中,頂部電觸點852即可連接各實體物件830頂部與置於組件結構層890上面的相應連接結構854。此外,穿透孔洞貫孔846填充導電材料845,且底部基板電觸點862電氣連接穿透孔洞貫孔846內的導電材料845與置於組件基板800下面的相應連接結構864、866。此外,穿透孔洞貫孔870填充導電材料872,上觸點853電氣連接導電材料872與連接結構854b,且下觸點876電氣連接導電材料872與連接結構874。
參照第9圖,流程圖900顯示根據本發明一些實施例的方法,用於製造類似上述第8圖所示組件基板。依循流程圖900,形成基板840(方塊905)。在一些例子中,基板840為透明玻璃基板。在特定實施例中,透明玻璃基板係以本領域已知製程形成的Corning Eagle XG®玻璃基板。在特例中,透明玻璃基板為七百(700)微米厚。基於所述內容,本領域一般技術人士將明白本發明相關不同實施例可使用其他基板材料和厚度。
在基板840待形成穿透孔洞貫孔846和穿透孔洞貫孔870的位置進行雷射鑽孔(方塊910)。雷射鑽孔會產生延伸穿過基板的實質直筒開口。與欲形成最終穿透孔洞貫孔的寬度相比,開口寬度較小。用抗蝕膜遮蔽對穿透孔洞貫孔846和穿透孔洞貫孔870的位置施行雷射鑽孔的基板側(方塊915),及遮蔽基板840的部分對側,以覆蓋對應穿透孔洞貫孔870的位置(方塊920)。或者,遮蔽施行雷射鑽孔的對側。
接著用第一高悌勒模量(Φ1
)蝕刻材料蝕刻基板840,計第一時間(t1
)(方塊925)。藉由僅從一側蝕刻基板840,雷射鑽孔所形成實質直筒開口在對應穿透孔洞貫孔846位置的開口一側打得比另一側更開,從而形成梯形柱形開口。然後自基板840移除抗蝕膜,以露出梯形柱形開口的兩端及留下對應穿透孔洞貫孔870的雷射鑽孔孔洞兩端(方塊930)。此時,接著用第二高悌勒模量(Φ2
)蝕刻材料蝕刻基板840,計第二時間(t2
)(方塊935)。藉由從兩端蝕刻對應穿透孔洞貫孔846的位置處的現有梯形柱形開口,可增大開口尺寸,同時維持梯形柱形。同樣地,藉由從兩端蝕刻對應穿透孔洞貫孔870的位置的現有雷射鑽孔直開口,可增大開口尺寸,同時維持直筒形。此時,基板840中的穿透孔洞貫孔846已完成且可用於電子裝置製造,無需繼續進行方塊940。
組件結構層890形成於基板上面(方塊940)。組件結構層890包括井841形成於內,井841位於穿透孔洞貫孔846的至少一支組上方,且較窄的井881操作做為穿透孔洞貫孔870的延伸部。組件結構層可使用任意結合層形成、然後遮蔽及蝕刻以界定井而形成,或可由附加製程形成,其中圖案形成於待存有井處,再形成組件結構層圍繞圖案,隨後移除圖案,以於組件結構層890中留下開井。基於所述內容,本領域一般技術人士將明白各種形成組件結構層的方式。
電觸點形成於井841的底部,此將當作置入組件結構層890的井841內的實體物件830的底部觸點(方塊945)。可利用本領域已知任何製程來沉積或形成導電材料至井841的底部。將實體物件830組裝到井841中(方塊950)。組裝可利用任何製程完成,包括、但不限於第1a圖至第1b圖所述射流組裝。在一些例子中,吸力施加至基板840的底部,促使實體物件830適當置入井841。
頂部觸點852和頂部觸點853形成以連接各實體物件830的頂側與相應連接結構854(方塊955)。可利用本領域已知任何製程來沉積或形成導電材料至實體物件830和組件結構上面。此外,穿透孔洞貫孔846填充導電材料845,且穿透孔洞貫孔870填充導電材料872(方塊960),且底部觸點862、876形成以電氣連接實體物件830的底側與相應連接結構864、866和導電材料872與連接結構874(方塊960)。可利用本領域已知任何製程來用導電材料填充穿透孔洞貫孔846和穿透孔洞貫孔870。
總之,本發明提供新穎系統、裝置、方法和配置,用以在基板內形成結構。儘管本發明的一或更多實施例已詳述如上,但在不脫離本發明的精神下,熟諳此技術者當明白各種更動、潤飾和均等物。因此,以上敘述不應視為限定本發明的範圍,本發明範圍以後附申請專利範圍所界定者為準。
100‧‧‧射流組裝系統110‧‧‧懸浮液115‧‧‧載體液體120‧‧‧側130‧‧‧實體物件140‧‧‧基板142‧‧‧井143‧‧‧穿透孔洞貫孔150‧‧‧放置裝置160‧‧‧懸浮液移動裝置170‧‧‧擷取裝置190‧‧‧組件結構層192‧‧‧直徑193‧‧‧位移194‧‧‧深度199‧‧‧上視圖200‧‧‧上視圖210‧‧‧組件結構層220‧‧‧基板225‧‧‧頂表面230‧‧‧寬度240‧‧‧井(結構)245‧‧‧側壁250‧‧‧側視圖270‧‧‧深度280‧‧‧穿透孔洞貫孔結構282、284‧‧‧直徑290‧‧‧底表面300‧‧‧組件基板332、334、336‧‧‧實體物件340‧‧‧基板342、344、346‧‧‧井結構343、345、347‧‧‧穿透孔洞貫孔390‧‧‧組件結構層400‧‧‧組件基板430‧‧‧實體物件440‧‧‧基板441‧‧‧井(結構)445‧‧‧導電材料446‧‧‧穿透孔洞貫孔452、462‧‧‧電觸點454、464、466‧‧‧導電結構490‧‧‧組件結構層500‧‧‧流程圖505、510、515、520、525、530、535、540、545、550、555、560‧‧‧方塊600‧‧‧組件基板630‧‧‧實體物件640‧‧‧基板641‧‧‧井(結構)645‧‧‧導電材料646‧‧‧穿透孔洞貫孔652、662‧‧‧電觸點654、664、666‧‧‧導電結構690‧‧‧組件結構層700‧‧‧流程圖705、710、715、720、725、730、735、740、745、750、755、760‧‧‧方塊800‧‧‧組件基板830‧‧‧實體物件840‧‧‧基板841、881‧‧‧井845、872‧‧‧導電材料846、870‧‧‧穿透孔洞貫孔852、853、862、876‧‧‧電觸點854、854b、864、866、874‧‧‧導電結構900‧‧‧流程圖905、910、915、920、925、930、935、940、945、950、955、960、965‧‧‧方塊
藉由參照描述於說明書其餘部分的圖式可進一步理解本發明的各種實施例。在附圖中,各圖以相同的元件符號指稱類似的部件。在一些情況下,小寫字母組成下標聯結元件符號代表多個類似部件之一。當提及無指定現行下標的元件符號時,擬指所有此類多個類似部件。
第1a圖至第1b圖圖示根據本發明一或更多實施例的射流組裝系統,系統能相對包括一些穿透孔洞貫孔從井底部延伸穿過基板的組件基板移動由載體液體與複數個實體物件組成的懸浮液;
第2a圖至第2b圖圖示根據本發明一些實施例的穿透孔洞貫孔和井結構;
第3圖圖示具多個穿透孔洞貫孔與井組合的部分組件基板,各組合根據本發明不同實施例設計成容納不同尺寸與形狀的實體物件;
第4圖圖示根據本發明一或更多實施例,具多個穿透孔洞貫孔與井組合的部分組件基板,各組合具有相同尺寸與形狀,其中電觸點已用導電材料填充穿透孔洞貫孔而形成;
第5圖係圖示根據本發明一些實施例的方法流程圖,用於製造類似第6圖所示組件基板;
第6圖圖示根據本發明一或更多實施例,具多個穿透孔洞貫孔與井組合的部分組件基板,各組合具有相同尺寸與形狀,其中電觸點已用導電材料共形塗覆穿透孔洞貫孔而形成;
第7圖係圖示根據本發明一些實施例的方法流程圖,用於製造類似第6圖所示組件基板;
第8圖圖示根據本發明不同實施例,具多個穿透孔洞貫孔與井組合的部分組件基板,各組合具有梯形穿透孔洞貫孔從井延伸,另有直形穿透孔洞貫孔可用於電氣連接;及
第9圖係圖示根據本發明一些實施例的方法流程圖,用於製造類似第8圖所示組件基板。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
300‧‧‧組件基板
332、334、336‧‧‧實體物件
340‧‧‧基板
342、344、346‧‧‧井結構
343、345、347‧‧‧穿透孔洞貫孔
390‧‧‧組件結構層
Claims (18)
- 一種組件基板,該組件基板包含:一基板,具有一第一表面和一第二表面;一組件結構層,置於該基板的該第一表面上面,其中該組件結構層包括複數個開口,各自露出該基板一部分的該第一表面;及其中至少一穿透孔洞貫孔從該基板的該第二表面延伸到該基板的該第一表面,其中該穿透孔洞貫孔的一第一末端可於該基板的該第一表面進入並在該複數個開口中的一開口內,其中該穿透孔洞貫孔的一第二末端可於該基板的該第二表面進入,其中在該穿透孔洞貫孔的該第二末端平行該基板的該第二表面的一截面積大於在該穿透孔洞貫孔的該第一末端平行該基板的該第二表面的一截面積,其中該複數個開口至少包括各具一第一形狀的一第一支組和各具一第二形狀的一第二支組。
- 如請求項1所述之組件基板,其中該穿透孔洞貫孔的形狀係一梯形柱。
- 如請求項1所述之組件基板,其中該至少一穿透孔洞貫孔係從該第一支組所含的一開口延伸的一第一穿透孔洞貫孔,且其中該組件基板進一步包括從該第二支組所含的一開口延伸的一第二穿透孔洞貫孔, 其中該第二穿透孔洞貫孔展露不同於該第一穿透孔洞貫孔的一尺度特性,且其中該不同尺度特性選自由尺寸和形狀所組成的一群組。
- 如請求項1所述之組件基板,其中該穿透孔洞貫孔由一導電材料所完全填滿。
- 如請求項1所述之組件基板,其中該穿透孔洞貫孔由一導電材料所共形填充。
- 如請求項1所述之組件基板,其中一電觸點形成於該複數個開口之一的底部靠近該穿透孔洞貫孔的該第一開口,且其中一導電材料形成於該穿透孔洞貫孔中,使得該導電材料接觸該電觸點。
- 如請求項1所述之組件基板,其中該基板由一玻璃形成。
- 如請求項7所述之組件基板,其中該玻璃係一第一種玻璃,且其中該組件結構層係由一第二種玻璃形成。
- 如請求項1所述之組件基板,其中該至少一穿透孔洞貫孔係從該複數個開口之一延伸的一第一穿透孔洞貫孔,且其中該組件基板進一步包括從該基板的該第一表面延伸到該基板的該第二表面的一第二穿透孔洞貫孔,其中該第一穿透孔洞貫孔呈一梯形柱形,且該第二穿透孔洞貫孔呈一直筒形。
- 一種形成一組件基板的方法,該方法包含以下步驟:提供一基板,該基板具有一第一表面和一第二表面;形成至少一穿透孔洞貫孔,該至少一穿透孔洞貫孔從該基板的該第二表面延伸到該基板的該第一表面,其中該穿透孔洞貫孔的一第一末端位於該基板的該第一表面,且該穿透孔洞貫孔的一第二末端位於該基板的該第二表面,且其中該穿透孔洞貫孔在該第二表面的一截面積大於該穿透孔洞貫孔在該第一表面的一截面積;及形成一組件結構層至該基板的該第一表面上面,其中該組件結構層包括複數個開口,該複數個開口露出該穿透孔洞貫孔的該第一末端所在的該基板一部分的該第一表面,其中該複數個開口至少包括各具一第一形狀的一第一支組和各具一第二形狀的一第二支組。
- 如請求項10所述之方法,其中該穿透孔洞貫孔的形狀係一梯形柱。
- 如請求項10所述之方法,其中形成該至少一穿透孔洞貫孔包括:於該基板的該第一表面上待形成該穿透孔洞貫孔的 一位置雷射鑽孔該基板,以形成延伸穿過該基板而至該基板的該第二表面的一孔洞;用一抗蝕材料遮蔽該基板的該第一表面,該抗蝕材料覆蓋該孔洞於該基板的該第一表面的一開口;及蝕刻該基板,使該孔洞於該基板的該第二表面的一開口變得比該孔洞於該基板的該第一表面的該開口大。
- 如請求項12所述之方法,其中形成該至少一穿透孔洞貫孔進一步包括:移除覆蓋該孔洞於該基板的該第一表面的該開口的該抗蝕材料;及再蝕刻該基板,使該孔洞於該基板的該第一表面的該開口與該孔洞於該基板的該第二表面的該開口均增大。
- 如請求項10所述之方法,該方法進一步包含:用一導電材料填充該穿透孔洞貫孔。
- 如請求項14所述之方法,其中填充該穿透孔洞貫孔包括用該導電材料完全填滿該穿透孔洞貫孔。
- 如請求項14所述之方法,其中填充該穿透孔洞貫孔包括用該導電材料共形塗覆該穿透孔洞貫孔, 使該穿透孔洞貫孔僅部分填滿。
- 一種組件基板,該組件基板包含:一基板,具有一第一表面和一第二表面;一組件結構層,置於該基板的該第一表面上面,其中該組件結構層包括複數個開口,各自露出該基板一部分的該第一表面;及複數個穿透孔洞貫孔,在該複數個開口中的一相應開口內各自從該基板的該第一表面的一第一開口延伸到該基板的該第二表面的一第二開口,其中該複數個穿透孔洞貫孔各自的該第二開口大於該穿透孔洞貫孔各自的該第一開口,其中該複數個開口至少包括各具一第一形狀的一第一支組和各具一第二形狀的一第二支組。
- 如請求項17所述之組件基板,其中該至少一穿透孔洞貫孔係從該第一支組所含的一開口延伸的一第一穿透孔洞貫孔,且其中該組件基板進一步包括從該第二支組所含的一開口延伸的一第二穿透孔洞貫孔,其中該第二穿透孔洞貫孔展露不同於該第一穿透孔洞貫孔的一尺度特性,且其中該不同尺度特性選自由尺寸和形狀所組成的一群組。
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Also Published As
Publication number | Publication date |
---|---|
JP2020522884A (ja) | 2020-07-30 |
KR20200003942A (ko) | 2020-01-10 |
EP3622562A4 (en) | 2021-02-17 |
JP7312705B2 (ja) | 2023-07-21 |
KR102543621B1 (ko) | 2023-06-14 |
US20200118931A1 (en) | 2020-04-16 |
CN110692142A (zh) | 2020-01-14 |
TW201907552A (zh) | 2019-02-16 |
US10879182B2 (en) | 2020-12-29 |
EP3622562A1 (en) | 2020-03-18 |
WO2018222940A1 (en) | 2018-12-06 |
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