JP7312705B2 - 貫通ビアを含むアセンブリ基板および製造方法 - Google Patents
貫通ビアを含むアセンブリ基板および製造方法 Download PDFInfo
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- JP7312705B2 JP7312705B2 JP2019565555A JP2019565555A JP7312705B2 JP 7312705 B2 JP7312705 B2 JP 7312705B2 JP 2019565555 A JP2019565555 A JP 2019565555A JP 2019565555 A JP2019565555 A JP 2019565555A JP 7312705 B2 JP7312705 B2 JP 7312705B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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Description
アセンブリ基板において、
第1の表面および第2の表面を有する基板と、
前記基板の前記第1の表面の上に配置されて、該基板の該第1の表面の一部を各々が露出させる複数の開口部を含むアセンブリ構造層と
を含み、
少なくとも1つの貫通ビアが、前記基板の前記第2の表面から該基板の前記第1の表面に延伸し、前記貫通ビアの第1の端部は、該基板の該第1の表面でアクセス可能で、前記複数の開口部の1つの中に位置し、該貫通ビアの第2の端部は、該基板の該第2の表面でアクセス可能で、該貫通ビアの前記第2の端部での該基板の該第2の表面に平行な断面積は、該貫通ビアの前記第1の端部での該基板の該第2の表面に平行な断面積より広いものであるアセンブリ基板。
前記貫通ビアの形状が円錐台である、実施形態1に記載のアセンブリ基板。
前記複数の開口部は、各開口部が第1の形状を有する第1の部分集合、および、各開口部が第2の形状を有する第2の部分集合を、少なくとも含むものである、実施形態1に記載のアセンブリ基板。
前記少なくとも1つの貫通ビアは、前記第1の部分集合に含まれる開口部から延伸する第1の貫通ビアであり、
前記アセンブリ基板は、
前記第2の部分集合に含まれる開口部から延伸し、前記第1の貫通ビアとは異なる寸法特性を示す第2の貫通ビアを、
更に含み、
前記異なる寸法特性は、サイズおよび形状からなる群から選択されたものである、実施形態3に記載のアセンブリ基板。
前記貫通ビアは、導電材料で完全に充填されたものである、実施形態1に記載のアセンブリ基板。
前記貫通ビアは、導電材料で、コンフォーマルに充填されたものである、実施形態1に記載のアセンブリ基板。
電気接触部が、前記貫通ビアの前記第1の端部の近くで、前記複数の開口部の前記1つの開口部の底部に形成され、導電材料が、前記電気接触部に接触するように、該貫通ビア内に形成されるものである、実施形態1に記載のアセンブリ基板。
前記基板は、ガラスから形成されたものである、実施形態1に記載のアセンブリ基板。
前記ガラスは、第1の種類のガラスであり、前記アセンブリ構造層は、第2の種類のガラスから形成されたものである、実施形態8に記載のアセンブリ基板。
前記少なくとも1つの貫通ビアは、前記複数の開口部の1つから延伸する第1の貫通ビアであり、
前記アセンブリ基板は、
前記基板の前記第1の表面から該基板の前記第2の表面に延伸する第2の貫通ビアを、
更に含み、
前記第1の貫通ビアは、円錐台形状を示し、前記第2の貫通ビアは、直線的円筒形状を示すものである、実施形態1に記載のアセンブリ基板。
アセンブリ基板の形成方法において、
第1の表面および第2の表面を有する基板を提供する工程と、
前記基板の前記第2の表面から該基板の前記第1の表面に延伸する少なくとも1つの貫通ビアを形成する工程であって、前記貫通ビアの第1の端部は、該基板の該第1の表面に位置し、該貫通ビアの第2の端部は、該基板の該第2の表面に位置し、該貫通ビアの該第2の表面での断面積は、該貫通ビアの該第1の表面での断面積より広いものである工程と、
前記貫通ビアの前記第1の端部が位置する前記基板の前記第1の表面の一部を露出させる少なくとも1つの開口部を含むアセンブリ構造層を、該基板の該第1の表面の上に形成する工程と
を含む方法。
前記貫通ビアの形状が円錐台である、実施形態11に記載の方法。
前記少なくとも1つの貫通ビアを形成する工程は、
前記基板を、前記貫通ビアが形成されるべき該基板の前記第1の表面の位置で、レーザで穴あけして、該基板の前記第2の表面に該基板を通って延伸する孔を形成する工程と、
前記基板の前記第1の表面を、該基板の該第1の表面での前記孔の開口部を覆う耐エッチング剤で、遮蔽する工程と、
前記基板を、該基板の前記第2の表面での前記孔の開口部が、該基板の前記第1の表面での該孔の開口部より大きく拡大されるように、エッチングする工程と
を含むものである、実施形態11に記載の方法。
前記少なくとも1つの貫通ビアを形成する工程は、
前記基板の前記第1の表面で前記孔の開口部を覆う前記耐エッチング剤を除去する工程と、
前記基板を、該基板の前記第1の表面での前記孔の前記開口部と、該基板の前記第2の表面での該孔の前記開口部の両方が拡大されるように、再びエッチングする工程と
を更に含むものである、実施形態13に記載の方法。
前記貫通ビアを、導電材料で充填する工程を、
更に含む、実施形態11に記載の方法。
前記貫通ビアを充填する工程は、該貫通ビアを前記導電材料で完全に充填する工程を含むものである、実施形態15に記載の方法。
前記貫通ビアを充填する工程は、該貫通ビアを前記導電材料でコンフォーマルに被覆して、該貫通ビアが部分的にのみ充填されるようにする工程を含むものである、実施形態15に記載の方法。
アセンブリ基板において、
第1の表面および第2の表面を有する基板と、
前記基板の前記第1の表面の上に配置されて、該基板の該第1の表面の一部を各々が露出させる複数の開口部を含むアセンブリ構造層と、
複数の貫通ビアであって、各前記貫通ビアが、前記複数の開口部の各開口部内の前記基板の前記第1の表面の第1の開口部から、該基板の前記第2の表面の第2の開口部に延伸するものである複数の貫通ビアと
を含み、
各前記複数の貫通ビアの前記第2の開口部は、各該貫通ビアの前記第1の開口部より大きいものであるアセンブリ基板。
前記複数の開口部は、各開口部が第1の形状を有する第1の部分集合、および、各開口部が第2の形状を有する第2の部分集合を少なくとも含むものである、実施形態18に記載のアセンブリ基板。
少なくとも1つの前記貫通ビアは、前記第1の部分集合に含まれる開口部から延伸する第1の貫通ビアであり、
前記アセンブリ基板は、
前記第2の部分集合に含まれる開口部から延伸し、前記第1の貫通ビアとは異なる寸法特性を示す第2の貫通ビアを、
更に含み、
前記異なる寸法特性は、サイズおよび形状からなる群から選択されたものである、実施形態19に記載のアセンブリ基板。
140、220、440、640、840 基板
142 ウエル
190、210、390、490、890 アセンブリ構造層
240 ウエル構造物
280 貫通ビア構造部
300、400、600、800 アセンブリ基板
342、344、346 ウエル構造物
343、345、347 貫通ビア
845、872 導電材料
874 接続構造物
Claims (8)
- アセンブリ基板において、
第1の表面および第2の表面を有する基板と、
前記基板の前記第1の表面の上に配置されて、該基板の該第1の表面の一部を各々が露出させる複数の開口部を含むアセンブリ構造層と
を含み、
少なくとも1つの貫通ビアが、前記基板の前記第2の表面から該基板の前記第1の表面に延伸し、前記貫通ビアの第1の端部は、該基板の該第1の表面でアクセス可能で、前記複数の開口部の1つの中に位置し、該貫通ビアの第2の端部は、該基板の該第2の表面でアクセス可能で、該貫通ビアの前記第2の端部での該基板の該第2の表面に平行な断面積は、該貫通ビアの前記第1の端部での該基板の該第2の表面に平行な断面積より広いものであり、
前記複数の開口部は、各開口部が第1の形状を有する第1の部分集合、および、各開口部が第2の形状を有する第2の部分集合を、少なくとも含むものであり、
前記少なくとも1つの貫通ビアは、前記第1の部分集合に含まれる開口部から延伸する第1の貫通ビアであり、
前記アセンブリ基板は、前記第2の部分集合に含まれる開口部から延伸し、前記第1の貫通ビアとは異なる寸法特性を示す第2の貫通ビアを、更に含み、
前記異なる寸法特性は、サイズおよび形状からなる群から選択されたものである、アセンブリ基板。 - 前記貫通ビアの形状が円錐台である、請求項1に記載のアセンブリ基板。
- 前記貫通ビアは、導電材料で完全に充填されたものである、請求項1に記載のアセンブリ基板。
- 前記貫通ビアは、導電材料で、コンフォーマルに充填されたものである、請求項1に記載のアセンブリ基板。
- 電気接触部が、前記貫通ビアの前記第1の端部の近くで、前記複数の開口部の1つの底部に形成され、導電材料が、前記電気接触部に接触するように、該貫通ビア内に形成されるものである、請求項1に記載のアセンブリ基板。
- 前記基板は、ガラスから形成されたものである、請求項1に記載のアセンブリ基板。
- 前記ガラスは、第1の種類のガラスであり、前記アセンブリ構造層は、第2の種類のガラスから形成されたものである、請求項6に記載のアセンブリ基板。
- 前記少なくとも1つの貫通ビアは、前記複数の開口部の1つから延伸する第1の貫通ビアであり、
前記アセンブリ基板は、
前記基板の前記第1の表面から該基板の前記第2の表面に延伸する第2の貫通ビアを、
更に含み、
前記第1の貫通ビアは、円錐台形状を示し、前記第2の貫通ビアは、直線的円筒形状を示すものである、請求項1に記載のアセンブリ基板。
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Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109888067B (zh) * | 2019-04-19 | 2020-04-14 | 业成科技(成都)有限公司 | 发光显示器的制作方法 |
KR20200026673A (ko) * | 2019-06-11 | 2020-03-11 | 엘지전자 주식회사 | 디스플레이 장치의 제조방법 및 디스플레이 장치 제조를 위한 기판 |
KR102186922B1 (ko) * | 2019-10-01 | 2020-12-04 | 윤치영 | 버티컬 타입 초소형 엘이디의 수직 정렬방법 및 이를 이용한 엘이디 어셈블리 제조방법 |
KR102251195B1 (ko) | 2019-10-01 | 2021-05-12 | 윤치영 | 수직 정렬된 버티컬 타입 초소형 엘이디를 구비한 엘이디 어셈블리 |
KR102512547B1 (ko) * | 2019-10-01 | 2023-03-29 | 윤치영 | 수직 정렬된 버티컬 타입 초소형 엘이디를 구비한 엘이디 어셈블리 |
CN114868261A (zh) * | 2020-01-09 | 2022-08-05 | 苏州晶湛半导体有限公司 | 半导体结构及其衬底、半导体结构及其衬底的制作方法 |
KR20210149290A (ko) * | 2020-06-01 | 2021-12-09 | 삼성디스플레이 주식회사 | 표시 장치 및 그의 제조 방법 |
KR20230011974A (ko) * | 2020-06-26 | 2023-01-25 | 엘지전자 주식회사 | 디스플레이 장치 제조용 기판 및 이를 이용한 디스플레이 장치의 제조방법 |
US11764095B2 (en) * | 2020-07-10 | 2023-09-19 | Samsung Electronics Co., Ltd. | Wet alignment method for micro-semiconductor chip and display transfer structure |
TWI752707B (zh) | 2020-11-03 | 2022-01-11 | 財團法人工業技術研究院 | 具有通孔的基板及其製造方法 |
EP4012755A1 (en) * | 2020-12-11 | 2022-06-15 | Samsung Electronics Co., Ltd. | Micro-semiconductor chip wetting align apparatus |
US20220189931A1 (en) * | 2020-12-15 | 2022-06-16 | Samsung Electronics Co., Ltd. | Display transferring structure and display device including the same |
KR20230128460A (ko) * | 2021-01-06 | 2023-09-05 | 엘지전자 주식회사 | 반도체 발광소자를 이용한 디스플레이 장치 |
US20220285188A1 (en) * | 2021-03-02 | 2022-09-08 | Samsung Electronics Co., Ltd. | Display transfer structure including light emitting elements and transferring method of light emitting elements |
WO2022196019A1 (ja) | 2021-03-15 | 2022-09-22 | 日本電気硝子株式会社 | ガラス基板、貫通孔形成用ガラス原板及びガラス基板の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030169575A1 (en) | 2002-02-26 | 2003-09-11 | Kyocera Corporation | High frequency module |
CN103703874A (zh) | 2011-07-13 | 2014-04-02 | 揖斐电株式会社 | 电子部件内置电路板及其制造方法 |
JP2015135940A (ja) | 2013-12-16 | 2015-07-27 | 味の素株式会社 | 部品内蔵基板の製造方法および半導体装置 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5545291A (en) * | 1993-12-17 | 1996-08-13 | The Regents Of The University Of California | Method for fabricating self-assembling microstructures |
JPH11264991A (ja) * | 1998-01-13 | 1999-09-28 | Matsushita Electric Ind Co Ltd | 液晶表示素子の製造方法 |
US6469256B1 (en) | 2000-02-01 | 2002-10-22 | International Business Machines Corporation | Structure for high speed printed wiring boards with multiple differential impedance-controlled layers |
KR100444588B1 (ko) | 2002-11-12 | 2004-08-16 | 삼성전자주식회사 | 글래스 웨이퍼의 비아홀 형성방법 |
JP4138529B2 (ja) * | 2003-02-24 | 2008-08-27 | 浜松ホトニクス株式会社 | 半導体装置、及びそれを用いた放射線検出器 |
JP2004272014A (ja) * | 2003-03-10 | 2004-09-30 | Seiko Epson Corp | 光通信モジュールの製造方法、光通信モジュール、及び電子機器 |
JP3978189B2 (ja) * | 2004-01-23 | 2007-09-19 | 松下電器産業株式会社 | 半導体装置の製造方法及びその製造装置 |
US7629026B2 (en) * | 2004-09-03 | 2009-12-08 | Eastman Kodak Company | Thermally controlled fluidic self-assembly |
WO2010087483A1 (ja) * | 2009-02-02 | 2010-08-05 | 旭硝子株式会社 | 半導体デバイス部材用ガラス基板および半導体デバイス部材用ガラス基板の製造方法 |
US20100326716A1 (en) * | 2009-06-26 | 2010-12-30 | Zhichao Zhang | Core via for chip package and interconnect |
JP5447316B2 (ja) | 2010-09-21 | 2014-03-19 | 株式会社大真空 | 電子部品パッケージ用封止部材、及び電子部品パッケージ |
US10115862B2 (en) | 2011-12-27 | 2018-10-30 | eLux Inc. | Fluidic assembly top-contact LED disk |
US8648328B2 (en) * | 2011-12-27 | 2014-02-11 | Sharp Laboratories Of America, Inc. | Light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces |
CN104185799B (zh) * | 2012-02-03 | 2017-06-30 | 梅卡雷斯系统有限责任公司 | 补偿线路板上的光学传感器 |
US9034754B2 (en) * | 2012-05-25 | 2015-05-19 | LuxVue Technology Corporation | Method of forming a micro device transfer head with silicon electrode |
JP2014127701A (ja) * | 2012-12-27 | 2014-07-07 | Ibiden Co Ltd | 配線板及びその製造方法 |
US20140256231A1 (en) * | 2013-03-07 | 2014-09-11 | Dow Global Technologies Llc | Multilayer Chemical Mechanical Polishing Pad With Broad Spectrum, Endpoint Detection Window |
WO2014193978A1 (en) * | 2013-05-28 | 2014-12-04 | Georgia Tech Research Corporation | Glass-polymer optical interposer |
US9296646B2 (en) * | 2013-08-29 | 2016-03-29 | Corning Incorporated | Methods for forming vias in glass substrates |
US9722145B2 (en) * | 2015-06-24 | 2017-08-01 | Sharp Laboratories Of America, Inc. | Light emitting device and fluidic manufacture thereof |
US9892944B2 (en) * | 2016-06-23 | 2018-02-13 | Sharp Kabushiki Kaisha | Diodes offering asymmetric stability during fluidic assembly |
US9755110B1 (en) * | 2016-07-27 | 2017-09-05 | Sharp Laboratories Of America, Inc. | Substrate with topological features for steering fluidic assembly LED disks |
US9917226B1 (en) * | 2016-09-15 | 2018-03-13 | Sharp Kabushiki Kaisha | Substrate features for enhanced fluidic assembly of electronic devices |
US10535640B2 (en) * | 2014-10-31 | 2020-01-14 | eLux Inc. | System and method for the fluidic assembly of micro-LEDs utilizing negative pressure |
US10593562B2 (en) * | 2015-04-02 | 2020-03-17 | Samtec, Inc. | Method for creating through-connected vias and conductors on a substrate |
US9851056B2 (en) * | 2015-10-16 | 2017-12-26 | Seoul Viosys Co., Ltd. | Compact light emitting diode chip and light emitting device having a slim structure with secured durability |
CN205863156U (zh) * | 2016-07-05 | 2017-01-04 | 安徽三安光电有限公司 | 一种晶片减薄用载盘及上片机 |
US9837390B1 (en) * | 2016-11-07 | 2017-12-05 | Corning Incorporated | Systems and methods for creating fluidic assembly structures on a substrate |
CN106681069A (zh) * | 2017-01-03 | 2017-05-17 | 京东方科技集团股份有限公司 | 一种显示基板及其制备方法、显示装置 |
US10062674B1 (en) * | 2017-04-28 | 2018-08-28 | Corning Incorporated | Systems and methods for display formation using photo-machinable material substrate layers |
US10580725B2 (en) * | 2017-05-25 | 2020-03-03 | Corning Incorporated | Articles having vias with geometry attributes and methods for fabricating the same |
-
2018
- 2018-05-24 TW TW107117677A patent/TWI785052B/zh active
- 2018-05-31 EP EP18810470.7A patent/EP3622562A4/en not_active Withdrawn
- 2018-05-31 US US16/618,673 patent/US10879182B2/en active Active
- 2018-05-31 KR KR1020197038936A patent/KR102543621B1/ko active IP Right Grant
- 2018-05-31 CN CN201880036567.0A patent/CN110692142A/zh active Pending
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030169575A1 (en) | 2002-02-26 | 2003-09-11 | Kyocera Corporation | High frequency module |
CN103703874A (zh) | 2011-07-13 | 2014-04-02 | 揖斐电株式会社 | 电子部件内置电路板及其制造方法 |
JP2015135940A (ja) | 2013-12-16 | 2015-07-27 | 味の素株式会社 | 部品内蔵基板の製造方法および半導体装置 |
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JP2020522884A (ja) | 2020-07-30 |
US10879182B2 (en) | 2020-12-29 |
TWI785052B (zh) | 2022-12-01 |
KR20200003942A (ko) | 2020-01-10 |
WO2018222940A1 (en) | 2018-12-06 |
US20200118931A1 (en) | 2020-04-16 |
EP3622562A1 (en) | 2020-03-18 |
KR102543621B1 (ko) | 2023-06-14 |
CN110692142A (zh) | 2020-01-14 |
EP3622562A4 (en) | 2021-02-17 |
TW201907552A (zh) | 2019-02-16 |
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