TWI743595B - 具緊密解耦合結構的電路系統 - Google Patents

具緊密解耦合結構的電路系統 Download PDF

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TWI743595B
TWI743595B TW108142172A TW108142172A TWI743595B TW I743595 B TWI743595 B TW I743595B TW 108142172 A TW108142172 A TW 108142172A TW 108142172 A TW108142172 A TW 108142172A TW I743595 B TWI743595 B TW I743595B
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decoupling
die
substrate
circuit
unit
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TW108142172A
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TW202007245A (zh
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原口大
藤石義隆
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愛普科技股份有限公司
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一種具有緊密解耦合結構的電路系統，包括：母板; 至少一個電路單元，每個電路單元具有基板，邏輯電路晶粒，多個第一金屬觸點和多個第二金屬觸點，所述基板具有第一表面和第二表面，所述第一金屬觸點形成在 所述第一表面並焊接到所述母板上，所述第二金屬觸點形成在所述邏輯電路晶粒上並焊接到所述第二表面上以形成倒裝晶粒柱，並且所述倒裝芯柱確定所述晶粒之間的間隙的高度 和基板; 以及至少一個解耦合單元，用於為所述至少一個電路單元提供交流信號解耦合功能; 其中，所述至少一個解耦合單元中的每一個被放置在一個所述電路單元的間隙中，並且包括母晶粒和至少一個堆疊型集成電容元件晶粒。

Description

具緊密解耦合結構的電路系統
本發明係有關一種交流信號解耦合結構，尤其是關於一種具有緊密的交流信號解耦合結構的電路系統。
為了保護供電電路系統免受來自電源電路的雜訊或交流信號的干擾，在實際電路設計中通常採用解耦合裝置。
請參考圖1，其繪示具有一習知解耦合結構的電路系統的橫截面圖。 如圖1所示，該電路系統包括一母板10、一電路單元11及一解耦合電容器12。
母板10係用於承載電路單元11和解耦合電容器12。
電路單元11具有一基板11a、一晶粒11b和多個金屬觸點11c，晶粒11b係形成在基板11a的上表面上，以及所述多個金屬觸點11c係形成在基板11a的下表面上且被焊接到母板10上。
解耦合電容器12係放置在基板11a的頂表面上且位於晶粒11b旁邊以提供一AC信號解耦合功能。
對於另一種解耦合結構，請參考圖2，其繪示具有另一習知解耦合結構的電路系統的橫截面圖。如圖2所示，該電路系統包括一母板10、一電路單元11及一解耦合電容器12。
母板10係用於承載電路單元11和解耦合電容器12。
電路單元11具有一基板11a、一晶粒11b和多個金屬觸點11c，晶粒11b係形成在基板11a的上表面上，以及所述多個金屬觸點11c係形成在基板11a的下表面上且被焊接到母板10上。
解耦合電容器12係放置在母板10上且位於電路單元11旁邊以提供一AC信號解耦合功能。
為了最小化一電路系統的尺寸，金屬觸點11c可以是BGA（ball grid array；球柵陣列）觸點。 然而，由於解耦合電容器12需要具有大電容以提供AC信號解耦合功能，所以解耦合電容器12的尺寸將會非常大而妨害到圖1和圖2的兩個電路系統的薄型化。 此外，由於在解耦合電容器12和晶粒11b之間存在一定長度的導電連接走線，所以會產生寄生電阻值和寄生電感值來損害所述的AC信號解耦合效應。具體而言，所述寄生電感和解耦合電容器12的組合會將一LC諧振頻率引入到電路單元11中。
為了解決上述問題，本領域亟需一種用於一電路系統之新穎的解耦合結構。
本發明之一目的在於公開一種具有緊密的解耦合結構以提供超薄型的電路系統。
本發明之另一目的在於公開一種具有緊密解耦合結構的電路系統，其可降低寄生電阻值和低寄生電感值以優化AC信號解耦合功能。
為了實現上述目的，一種具有緊密的解耦合結構的電路系統乃被提出，其包括：
一母板；
至少一個電路單元，各所述電路單元具有一基板、一邏輯電路晶粒、多個第一金屬觸點以及多個第二金屬觸點，其中所述基板具有第一表面及與所述第一表面相對的第二表面，所述多個第一金屬觸點係形成在該第一表面上且被焊接到該母板上，所述多個第二金屬觸點係形成在該邏輯電路晶粒上且被焊接到該基板的所述第二表面上以形成多個覆晶柱，且所述多個覆晶柱決定了該邏輯電路晶粒和該基板間之一間隙的高度；以及
至少一個解耦合單元，用以為所述至少一個電路單元提供一AC信號解耦合功能；
其中，各所述解耦合單元均放置在一所述電路單元的所述間隙中，且均包括一母晶粒(mother die)、至少一堆疊型集成電容元件晶粒(stack-type integrated-passive-device die)和多個第三金屬觸點，所述多個第三金屬觸點係形成在該母晶粒上且被焊接到所述的邏輯電路晶粒上，各所述堆疊型集成電容元件晶粒均具有形成在其上的多個第四金屬觸點，且所述多個第四金屬觸點均被焊接到該母晶粒上。
在一實施例中，所述第二金屬觸點是可控塌陷晶粒連接凸塊(controlled-collapse-chip-connection bumps；C4 bumps)。
在一實施例中，所述第三金屬觸點是可控塌陷晶粒連接凸塊。
在一個實施例中，所述第四金屬觸點是具有焊錫帽的銅柱凸塊。
在一實施例中，所述至少一堆疊式集成被動元件晶粒包括至少一個解耦合電容器。
在一實施例中，所述解耦合電容器是堆疊型電容器。
在一實施例中，所述第一金屬觸點是BGA觸點。
為了實現上述目的，另一具有緊密解耦合結構的電路系統乃被提出，其包括：
一母板；
至少一個電路單元，各所述電路均具有一基板、至少一個晶粒和多個金屬觸點，所述基板具有一第一表面及與所述第一表面相對的一第二表面，所述至少一個晶粒形成在所述第一表面上，所述多個金屬觸點係形成於所述第二表面上並被焊接至所述母板上，所述基板與所述母板之間形成有一間隙，且所述間隙的高度小於50微米；以及
至少一個解耦合單元，放置在該間隙中且被焊接到該基板上，以為所述至少一個電路單元提供一解耦合功能。
在一實施例中，所述解耦合單元包括一高度小於30微米的分離電容器。
在一實施例中，所述分離電容器是堆疊型電容器。
在一實施例中，所述金屬觸點是BGA（ball grid array；球柵陣列）觸點。
為了實現上述目的，又一種具有緊密解耦合結構的電路系統乃被提出，包括：
一母板； 至少一電路單元，各所述電路單元均具有一基板、至少一第一晶粒、至少一第二晶粒及多個金屬觸點，所述基板具有一第一表面及與所述第一表面相對的一第二表面，所述基板和所述母板之間形成有一間隙且該間隙具有小於50微米的高度，所述至少一第一晶粒係形成在所述第一表面上，所述至少一第二晶粒係嵌入在所述基板的一內部區域中，所述內部區域具有小於50微米的高度，且所述多個金屬觸點係形成在所述第二表面上並被焊接到該母板上；以及
至少一解耦合單元，放置在該內部區域中並且與所述至少一第二晶粒非常接近地電連接，或者放置在該間隙中並被焊接到該基板上，以為所述至少一個電路單元提供一AC信號解耦合功能。
在一實施例中，所述解耦合單元包括一高度小於30微米的分離電容器。
在一實施例中，所述分離電容器是堆疊型電容器。
在一實施例中，所述金屬觸點是BGA觸點。
為使　貴審查委員能進一步瞭解本發明之結構、特徵及其目的，茲附以圖式及較佳具體實施例之詳細說明如後。
請參考圖3，其繪示根據本發明的一個實施例的具有緊密解耦合結構的電路系統的橫截面圖。 如圖3所示，所述具有緊密解耦合結構的電路系統包括一母板100、至少一電路單元110和至少一解耦合單元120。
母板100係用於承載至少一電路單元110和至少一解耦合單元120。
各電路單元110均具有一基板111、至少一晶粒112以及多個第一金屬觸點113。
基板111具有第一表面111a和與第一表面111a相對的第二表面111b。
所述至少一晶粒112（其可以是邏輯電路晶粒）具有多個第二金屬觸點113a。第二金屬觸點113a可以是形成在晶粒112上且被焊接到第二表面111b上以形成覆晶柱的C4（controlled-collapse-chip-connection；可控塌陷晶粒連接）凸塊，並且由此決定晶粒112和基板111間之一間隙的高度，其中該間隙係用以容納解耦合單元120。
第一金屬觸點113可為BGA觸點且係形成在第一表面111a上並被焊接到母板100上。
解耦合單元120係被放置在所述間隙中且被焊接到晶粒112上，用以為電路單元110提供一交流信號解耦合功能。解耦合單元120包括一母晶粒120a、至少一堆疊型集成電容元件晶粒120b、多個第三金屬觸點120c以及多個第四金屬觸點120d堆疊型集成電容元件。
第三金屬觸點120c，可為C4凸塊且係形成在母晶粒120a上並被焊接到晶粒112上，且各所述堆疊型集成电容元件晶粒120b具有第四金屬觸點120d，第四金屬觸點120d可以是形成在所述堆疊型集成电容元件晶粒120b上並被焊接到母晶粒120a上的C2（Cu-pillar-with-solder-cap ；具有焊錫帽的銅柱）凸塊。
在一較佳實施例中，所述至少一堆疊型集成電容元件晶粒120b包括至少一個解耦合電容器，且所述解耦合電容器較佳為堆疊式電容器以提供高電容密度。此外，堆疊式電容器可以具有多個堆疊在小體積中的MIM（金屬-絕緣體-金屬）夾層，以提供用於AC信號解耦合功能的足夠電容值。
依上述的設計，圖3的電路系統乃可具有緊密的解耦合結構以提供超薄厚度。 此外，藉由堆疊型電容器的高電容密度以及解耦合單元120與晶粒112的緊密接近，本發明的緊密解耦合結構乃可提供低寄生電阻和低寄生電感以優化AC信號解耦合功能。
請參照圖4，其繪示本發明具有緊密解耦合結構的電路系統的另一實施例剖面圖。 如圖4所示，所述具有緊密的解耦合結構的電路系統包括一母板100，至少一個電路單元110和至少一個解耦合單元120。
母板100係用於承載至少一個電路單元110和至少一個解耦合單元120。
每個電路單元110均具有一基板111、至少一個晶粒112和多個金屬觸點113，基板111具有第一表面111a和與第一表面111a相對的第二表面111b，至少一個晶粒112形成在第一表面111a上，且金屬觸點件113形成在第二表面111b上並且被焊接到母板100上。在基板111和母板100之間形成一間隙且該間隙具有小於50微米的高度。在一個可能的實施例中，金屬觸點是BGA（ball grid array；球柵陣列）觸點。
至少一個解耦合單元120係置於該間隙中並被焊接到基板111上以為至少一個電路單元110提供一AC信號解耦合功能。
在一較佳實施例中，解耦合單元120包括一高度小於30微米的分離電容器，且該分離電容器較佳為堆疊型電容器以提供高電容密度。所述堆疊式電容器可以具有以小體積堆疊的多個MIM夾層，以提供用於AC信號解耦合功能的足夠電容。
依上述的設計，圖4的電路系統乃可具有緊密的解耦合結構以提供超薄厚度。 此外，藉由堆疊型電容器的高電容密度以及解耦合單元120與電路單元110的緊密接近，本發明的緊密解耦合結構乃可提供低寄生電阻和低寄生電感以優化AC信號解耦合功能。
請參照圖5，其繪示本發明具有緊密解耦合結構的電路系統的又一實施例剖面圖。 如圖5所示，所述具有緊密的解耦合結構的電路系統包括一母板100、至少一個電路單元110和至少一個解耦合單元120。
母板100係用於承載至少一個電路單元110和至少一個解耦合單元120。
每個電路單元110均具有一基板111、至少一個第一晶粒112a、至少一個第二晶粒112b和多個金屬觸點113，基板111具有第一表面111a和與第一表面111a相對的第二表面111b。
至少一個第一晶粒112a形成在第一表面111a上，且至少一個第二晶粒112b嵌入在基板111的一內部區域1111中，該內部區域1111具有小於50微米的高度。
金屬觸點件113形成在第二表面111b上並且被焊接到母板100上，且基板111和母板100之間形成有一間隙，該間隙具有小於50微米的高度。在一個可能的實施例中，金屬觸點113是BGA觸點。
至少一個解耦合單元120被放置在內部區域1111中並且與至少一個第二晶粒112b緊密接近地電連接，或者被放置在該間隙中並被焊接到基板111上，以為所述至少一個電路單元110提供一AC信號解耦合功能。
在一較佳實施例中，解耦合單元120包括一高度小於30微米的分離電容器，且該分離電容器較佳為堆疊型電容器以提供高電容密度。堆疊式電容器可以具有以小體積堆疊的多個MIM夾層，以提供用於AC信號解耦合功能的足夠電容。
依上述的設計，圖5的電路系統乃可具有緊密的解耦合結構以提供超薄厚度。 此外，藉由堆疊型電容器的高電容密度以及解耦合單元120與電路單元110的緊密接近，本發明的緊密解耦合結構乃可提供低寄生電阻和低寄生電感以優化AC信號解耦合功能。
由於上述設計，本發明乃可提供以下優點：
1.本發明具有的緊密解耦合結構的電路系統可以提供超薄厚度。
2.本發明具有緊密解耦合結構的電路系統可提供低寄生電阻和低寄生電感，以優化交流信號解耦合功能。
本案所揭示者，乃較佳實施例，舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者，俱不脫本案之專利權範疇。
綜上所陳，本案無論就目的、手段與功效，在在顯示其迥異於習知之技術特徵，且其首先發明合於實用，亦在在符合發明之專利要件，懇請　貴審查委員明察，並祈早日賜予專利，俾嘉惠社會，實感德便。
10‧‧‧母板 11‧‧‧電路單元 11a‧‧‧基板 11b‧‧‧晶粒 11c‧‧‧觸點 12‧‧‧解耦合電容器 100‧‧‧母板 110‧‧‧電路單元 111‧‧‧基板 111a‧‧‧第一表面 111b‧‧‧第二表面 112‧‧‧晶粒 112a‧‧‧第一晶粒 112b‧‧‧第二晶粒 113‧‧‧第一金屬觸點 113a‧‧‧第二金屬觸點 120‧‧‧解耦合單元 120a‧‧‧母晶粒 120b‧‧‧堆疊型集成電容元件晶粒 120c‧‧‧第三金屬觸點 120d‧‧‧第四金屬觸點 1111‧‧‧內部區域
圖1繪示具有一習知解耦合結構的電路系統的橫截面圖。 圖2繪示具有另一習知解耦合結構的電路系統的橫截面圖。 圖3繪示根據本發明的一個實施例的具有緊密的解耦合結構的電路系統的橫截面圖。 圖4繪示根據本發明另一實施例的具有緊密解耦合結構的電路系統的橫截面圖。 圖5繪示根據本發明又一實施例的具有緊密解耦合結構的電路系統的橫截面圖。
100‧‧‧母板
110‧‧‧電路單元
111‧‧‧基板
111a‧‧‧第一表面
111b‧‧‧第二表面
112‧‧‧晶粒
113‧‧‧第一金屬觸點
113a‧‧‧第二金屬觸點
120‧‧‧解耦合單元
120a‧‧‧母晶粒
120b‧‧‧堆疊型集成電容元件晶粒
120c‧‧‧第三金屬觸點
120d‧‧‧第四金屬觸點

Claims (8)

  1. 一種具有緊密解耦合結構的電路系統，包括：一母板；至少一個電路單元，各所述電路單元均具有一基板、至少一個晶粒和多個金屬觸點，所述基板具有一第一表面及與所述第一表面相對的一第二表面，所述至少一個晶粒形成在所述第一表面上，所述多個金屬觸點係形成於所述第二表面上並被焊接至所述母板上，所述基板與所述母板之間形成有一間隙，且所述間隙的高度小於50微米；以及至少一個解耦合單元，放置在該間隙中且所述至少一個解耦合單元具有一第一表面及一第二表面，所述至少一個解耦合單元的所述第一表面被焊接到該基板上以及所述至少一個解耦合單元的所述第二表面與所述母板相接觸，以為所述至少一個電路單元提供一解耦合功能。
  2. 根據申請專利範圍第1項所述的具有緊密解耦合結構的電路系統，其中所述解耦合單元包括一高度小於30微米的分離電容器。
  3. 如申請專利範圍第2項所述的具有緊密的解耦合結構的電路系統，其中所述分離電容器是堆疊型電容器。
  4. 如申請專利範圍第1項所述的具有緊密的解耦合結構的電路系統，其中所述金屬觸點是BGA觸點。
  5. 一種具有緊密解耦合結構的電路系統，包括：一母板；至少一電路單元，各所述電路單元均具有一基板、至少一第一晶粒、至少一第二晶粒及多個金屬觸點，所述基板具有一第一表面及與所述第一表面相對的一第二表面，所述基板和所述母板之間形成有一間隙且該間隙具有小於50微米的高度，所述至少一第一晶粒係形成在所述第一表面上，所述至少一第二晶粒係嵌入在所述基板的一內部區域中，所述內部區域具有小於50微米的高度，且所述多個金屬觸點係形成在所述第二表面上並被焊接到該母板上；以及 至少一解耦合單元，放置在所述至少一第二晶粒所崁入的該內部區域中並且與所述至少一第二晶粒在該內部區域內非常接近地電連接，以為所述至少一個電路單元提供一AC信號解耦合功能。
  6. 如申請專利範圍第5項所述的具有緊密解耦合結構的電路系統，其中所述解耦合單元包括一高度小於30微米的分離電容器。
  7. 如申請專利範圍第6項所述的具有緊密解耦合結構的電路系統，其中所述分離電容器是堆疊型電容器。
  8. 如申請專利範圍第5項所述的具有緊密的解耦合結構的電路系統，其中所述金屬觸點是BGA觸點。
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