TWI735814B - 用於接觸表面之接合之方法 - Google Patents

用於接觸表面之接合之方法 Download PDF

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TWI735814B
TWI735814B TW107139009A TW107139009A TWI735814B TW I735814 B TWI735814 B TW I735814B TW 107139009 A TW107139009 A TW 107139009A TW 107139009 A TW107139009 A TW 107139009A TW I735814 B TWI735814 B TW I735814B
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Taiwan
Prior art keywords
bonding
sacrificial layer
substrate
layer
preferably less
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TW107139009A
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TW201921519A (zh
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瑞柏翰柏赫德
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奧地利商Ev集團E塔那有限公司
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Abstract

本發明係關於用於用以下步驟尤其以下進程將一第一基板之一第一至少部分地為金屬的接觸表面接合至一第二基板之一第二至少部分地金屬接觸表面之方法： -將至少部分地尤其主要可溶於該等接觸表面中之至少一者之材料中之一犧牲層施加至該等接觸表面中之至少一者， -藉助該等接觸表面中之至少一者中之該犧牲層之至少部分溶液接合該等接觸表面。

Description

用於接觸表面之接合之方法
本發明係關於一種用於將一第一基板之一第一接觸表面接合至一第二基板之一第二接觸表面之方法。
所謂的接合技術已在半導體工業中使用達數年。接合技術允許通常彼此極精確地對準之兩個或兩個以上基板之接合。在大多數情形中，此接合永久地(因此不可逆地)發生，此意指在無基板之破壞或至少基板之部分地破壞之情況下不再可能在該接合程序之後分離該兩個基板。當接合該等基板時，展示存在致使一永久連接之不同化學及物理機構。非金屬表面係尤其令人關注的。在非金屬表面中，一所謂的預接合之形成藉由進行純接觸而發生。
將經由表面效應引起之此自發地形成之該兩個基板之可逆連接稱作一預接合，以便區分其與稍後實際接合，該實際接合不再可分離(因此係不可逆)且藉由一額外熱處理引起。已以此方式產生之預接合仍由不應低估之一強度表徵。儘管已以此方式彼此接合之晶圓必須仍在較高溫度下經熱處理以用於一永久接合，但預接合之強度足以固定兩個基板直至下一程序步驟為止。預接合係用於主要在一對準程序之 後兩個基板之初步固定之一種極有用手段，此乃因在對準程序之後兩個基板不應再朝向彼此移動。預接合應主要基於因基板之表面上之永久及感應偶極而存在之凡德瓦(van der Waals)力。由於凡德瓦力係極弱的，因此一相應高接觸面積係必要的以使得一顯著黏合作用發生在該等基板之間。然而，未拋光固體表面不在相應高粗糙度下進行最佳接觸。在純固體接觸之情形中，預接合因此主要在極平坦拋光基板表面之間出現。在室溫下，在特定情況下甚至在無溫度及/或力至基板之額外施加之情況下亦可在基板表面之間形成已分離共價鍵。然而，在室溫下已形成之共價鍵之數目應係小到可忽略。
主要地，液體之使用可增大基板之間的一相應黏合作用。另一方面，液體均衡基板之表面上之不均勻性且自身較佳地形成甚至永久偶極。一明顯預接合能力主要建立在非金屬表面上。經拋光且極平坦之諸如矽、陶瓷之半導體(此處主要為氧化物、金屬氧化物)在進行接觸後旋即展示一相應行為。
對於非金屬表面、因此展示一主要共價鍵特徵之表面(例如Si、SiO2等)而言，一先前施加液體膜可甚至有助於藉由在熱處理期間出現之共價鍵來強化永久接合。非金屬表面在一預接合之後經歷熱處理。熱活化在表面之間產生共價鍵且因此產生一不可逆連接。因此單晶、高精確切割且磨碎矽晶圓主要藉由在矽原子之間形成共價鍵而彼此焊接。若一種矽氧化物係在一矽晶圓上，則主要地共價矽氧化物鍵及/或氧化物-氧化物鍵形成。已展示，極薄液體層(通常為水)之使用致使或至少改良表面之間的共價鍵之形成。液體層係僅數奈米厚或甚至僅由一單個液體單層構成。液體層因此不必僅改良預接合行為，而亦顯著促進共價連接之形成。在水之情形中，原因主要在於使得有效 氧作為彼此待接合之基板表面之原子之間的一連接原子。一水分子之氫與氧之間的鍵合能係足夠低以用所施加能量破壞。則氧之新反應物主要係基板表面之原子。在任何情形中應提及，存在其中在基板表面之永久接合程序中液體之原子直接參與之此等程序不需要必須發生之表面。
用於純金屬表面之接合程序極不同地進行。由於金屬因其金屬接合性質而在化學上及物理上表現得完全不同，因此需要一完全不同接合策略。金屬主要在較高溫度下且通常在極高壓力下彼此接合。高溫導致沿著表面及/或晶粒邊界及/或體積之增強擴散。由於原子之增大行動性，不同物理及化學效應發生，此導致兩個表面之一焊接。此等金屬接合之缺點因此主要在於極高溫度及壓力之使用以確保兩個基板之完全之一接合。在絕大多數情形中，將不會預先找到純金屬表面。除諸如Pt、Au及Ag之極惰性金屬之外之幾乎所有金屬在大氣中塗覆有一氧化物層(即使僅極薄)。此氧化物層足以甚至在以一極薄氧化物層覆蓋之金屬表面之間產生一預接合。在任何情形中，若意欲使兩種金屬彼此直接接合以(舉例而言)使兩個導電觸點彼此接合，則此氧化物層繼而係不期望的。
基板之熱處理規定相應長加熱及冷卻時間。此外，高溫可導致諸如(舉例而言)微晶片之功能單元及主要地記憶體晶片之破壞且可將其損壞到不可用之程度。
此外，具有相應表面之基板可在實際接合步驟之前彼此對準。此對準一旦經實施便不應再被破壞直至最終(因此永久)接合程序為止。在任何情形中，主要在較高溫度下，由於不同材料之不同熱膨脹係數及所得熱應力，通常基板之不同組件區之彼此之一位移發生。在 最糟糕情形中，彼此待接合之兩個基板由具有不同熱膨脹係數之兩種不同材料構成。此等位移越大，不同材料之熱膨脹係數之差別亦越大。
本發明之目的係構想一種對於材料之低溫度及/或低壓力接合儘可能高效之方法。
以技術方案1之特徵達成此目的。在隨附申請專利範圍中給定本發明之有利開發。說明書、申請專利範圍及/或圖中所給定之特徵中之至少兩個特徵之所有組合亦歸屬於本發明之範疇內。在給定值範圍內，所指示限制內之值亦將被視為揭示為邊界值且將以任何組合主張。
本發明係基於將至少一個超薄犧牲層沈積於待接合之基板之接觸表面中之至少一者上之思想，該層在如本發明中所主張之接合步驟期間溶解於環繞其之材料中或在界面上消耗。本發明之另一態樣在於，藉由用一材料(尤其至少主要地一液體，較佳地至少主要地水)作為犧牲層之一先前潤濕程序之金屬表面之接合尤其用於在基板之間產生一預接合。亦可聯想到彼此上下之數個犧牲層之一組合，尤其較佳地一固體犧牲層及已沈積於其上之一液體犧牲層之沈積。因此，通常亦可彼此上下地施加數個犧牲層。
儘管所揭示本發明根本上適合於滿足必要先決條件之所有種類之材料，但主要地金屬適合於如本發明中所主張之實施例。在進一步揭示內容中，藉由關於金屬表面之實例之方式圖解說明如本發明中所主張之實施例。
基板尤其由矽構成，一尤其金屬接合層較佳地由至少施加於基板上之接合區中之Cu構成。在接合層不覆蓋整個基板之情況下，接 合區較佳地由尤其基板之塊體材料環繞，且聯合地形成尤其平面接觸表面。
根據本發明之另一尤其獨立態樣，彼此待接合之接合區塗佈有一犧牲層，該犧牲層另一方面能夠產生一預接合，其原子另一方面在預接合之後在溫度處理中藉由接合區之材料/在接合區之材料中儘可能少地溶解。材料層較佳地由決不達到犧牲層之材料之溶解性限制之一材料構成。如本發明中所主張，犧牲層之材料完全地崩解於接觸表面中之至少一者上(較佳地兩個接觸表面上)之材料層中。濃度較佳地給定為以原子百分比為單位(%)。如本發明中所主張，接觸表面中之至少一者之尤其金屬材料中之犧牲層之材料之溶解性係介於0%與10%之間，較佳地介於0%與1%之間，更佳地介於0%與0.1%之間，最佳地介於0%與0.01%之間，特佳地介於0%與0.001%之間，絕佳地介於0%與0.0001%之間。
如本發明中所主張之犧牲層之厚度小於1000nm，較佳地小於100nm，更佳地小於10nm，最佳地小於1nm。犧牲層之厚度對基板(尤其基板之接合區)之厚度之比率小於1，較佳地小於10-2，較佳地小於10-4，更佳地小於10-6，仍更佳地小於10-8。
該犧牲層可藉由任何沈積方法施加至接觸表面中之至少一者。產生紋理儘量粗糙及/或至少主要單晶之一犧牲層之沈積方法係較佳的。如本發明中所主張可聯想到之沈積方法係尤其如下：-原子層沈積，-電化學沈積，-物理汽相沈積(PVD)，-化學汽相沈積(CVD)， -藉由冷凝及/或再昇華之汽相沈積來沈積，例如水在一表面上自水蒸汽之直接沈積，-電漿沈積，-潤濕化學沈積方法，-濺鍍及/或-分子束磊晶。
如本發明中所主張，若犧牲層(尤其Si)與接合層(尤其Cu)原位聯合地施加於基板上，則係有利的。此防止氧化物在接合層上之形成。
犧牲層如本發明中所主張尤其由適合於一預接合之形成且在彼此將進行接觸之基板中之至少一者之接觸表面上之接合區及/或塊體區中具有一溶解性之一材料構成。該犧牲層尤其至少部分地(較佳地主要地)由以下材料或物質中之至少一者構成：-金屬，尤其-Cu、Ag、Au、Al、Fe、Ni、Co、Pt、W、Cr、Pb、Ti、Te、Sn及/或Zn，-合金，-半導體(具有相應摻雜)，尤其-元素半導體，較佳地-Si、Ge、Se、Te、B及/或(α)-Sn，-化合物半導體，較佳地-GaAs、GaN、InP、InxGE1-xN、InSb、InAs、GaSb、AlN、InN、GaP、BeTe、ZnO、CuInGaSe2、ZnS、ZnSe、ZnTe、CdS、CdSe、CdTe、Hg(1-x)Cd(x)Te、BeSe、HgS、AlxGa1-xAs、GaS、GaSe、GaTe、InS、InSe、InTe、 CuInSe2、CuInS2、CuInGaS2、SiC及/或SiGe，-有機半導體，較佳地-黃烷士酮、紫環酮、Alq3、紫環酮、稠四苯、辛吖啶酮、稠五苯、酞青素、聚噻吩、PTCDA、MePTCDI、吖啶酮及/或陰丹士林。
-液體，尤其-水，-醇，-醛，-酮，-醚，-酸，-鹼基。
在如本發明中所主張之一第一實施例中，該接合區係在基板之整個接觸表面上方延伸之一層。該接合區之表面之粗糙度尤其藉由已知方法減小。較佳地使用一化學-機械拋光程序(CMP)。因此，該整個接合區表面用如本發明中所主張之犧牲層覆蓋。該犧牲層以一方式施加或在施加之後以一方式經處理使得平均粗糙度小於1μm、較佳地小於500nm、更佳地小於100nm、仍更佳地小於10nm、最佳地小於1nm。
在如本發明中所主張之一第二實施例中，存在分佈於整個接觸表面上方之數個接合區。該等接合區形成尤其在基板中之至少一者之接觸表面上方突出、因此突出超過其表面之一形貌。較佳地該等接合區由任何塊體材料環繞。塊體材料之表面及接合區表面形成尤其一共 同平面E。由導電區構成之表面及由非導電區環繞之表面亦稱為混合表面。非導電區由一介電質構成且與導電區絕緣。可想像到之最簡單實施例將係藉由用於電荷傳輸之介電質絕緣之接觸位點。藉由接合此等混合表面，基板之間的一導電連接可經由所接合接觸位點達成。
因此，犧牲層如本發明中所主張以一毯覆方式沈積於接觸表面上，既在塊體材料表面上亦又在接合區表面上。該等局部接合區尤其係用於封裝之銅墊、金屬接點或金屬框架。Cu墊尤其在不同層系統中用於功能單元之間的電連接。金屬接點可尤其係透過矽導通體(TSV)。一金屬框架可(舉例而言)進行微封裝以用於一MEMS裝置。為清晰起見，此等功能單元未展示於圖式中。
在如本發明中所主張之一第三實施例中，存在在直接在基板內之整個接觸表面上方分佈之數個接合區，基板係首先藉由蝕刻技術經結構化且然後填充有相應接合區材料且接著由犧牲材料覆蓋。
在如本發明中所主張之一接合步驟中，製作為任何層系統之兩個基板被致使互相接近以使得已施加至接觸表面之犧牲層彼此接觸且形成一預接合。犧牲層表面之粗糙度可藉由化學及/或機械方法在很大程度上減小(較佳地消除)。在特定層系統中，層系統可在預接合之前在一對準器中彼此對準。
在預接合之前，犧牲層表面可如本發明中所主張用一液體(較佳地水)潤濕。較佳地所施加液體層薄於100nm，更佳地薄於10nm，最佳地薄於1nm，特佳地僅一單層。對於親水表面，足以將基板曝露至周圍大氣。表面接著藉由來自大氣之水蒸汽來潤濕。
該液體可如本發明中所主張尤其藉由冷凝施加。在一項特殊實施例中，將經塗覆之基板(較佳地在冷卻狀態中)放置於具有一飽和蒸 汽大氣之一加熱空間中。該液體由於基板之低溫突然冷凝於基板表面上。
在本發明之一個替代版本中，藉由一自旋抗蝕劑施加程序將犧牲層之材料尤其作為一液體施加。
在本發明之另一替代版本中，藉由一噴塗抗蝕劑施加單元將犧牲層之材料尤其作為一液體噴塗至基板中之至少一者之接觸表面上。
在特殊實施例中，水藉由一起泡器引入至其中基板所位於之反應室中。為完成此，例如氬氣、氦氣及氮氣之惰性氣體透過一水浴驅動。惰性氣體在蒸鍍期間支援水且藉助水蒸汽使反應室飽和。水冷凝於基板之表面上且形成一極薄水膜。使基板冷卻可支援水之冷凝。
在另一特殊實施例中，水在一簡單汽化器中經汽化且投送至基板之表面上。與起泡器相比，不必使用一惰性氣體，但使水溫儘可能接近於沸點以便增大水之動能且因此加速汽化。藉由抽空反應室，沸點可因此降低，且程序因此經最佳化。
考量可建構可精確地沈積如本發明中所主張之犧牲層之特殊反應室，因此，如本發明中所主張之後文中稱作反應室之一單元亦出現。
該預接合較佳地在接觸表面之一個接觸點處起始且在整個表面上方藉由一接合波擴展。兩個犧牲層表面之接觸可尤其藉由使兩個基板中之一者彎曲之一接針產生以使得此基板之接觸表面中凸地變形且與第二基板之(特定而言)平坦地位於一接收表面上之犧牲層表面進行接觸。
在形成預接合之後，兩個經接合基板經熱處理。熱處理在儘可能低之溫度下(理想地在室溫下)發生。此處溫度小於500℃，較佳地 小於400℃，更佳地小於300℃，仍更佳地小於200℃，最佳地小於100℃，特佳地小於50℃。
如本發明中所主張極薄之犧牲層之一版本達成犧牲層之原子尤其僅至接合區中之一迅速擴散。如本發明中所主張之擴散經加速及/或藉由熱處理促進。較佳地，犧牲層之原子如本發明中所主張完全地溶解於接合區之材料及/或塊體材料中。如本發明中所主張，亦可聯想到其中接合區之原子溶解於犧牲層中之一程序；從技術方面來看，此程序因犧牲層之極小厚度而與上文所闡述之版本相同。
較佳地，基板在如本發明中所主張之犧牲層之原子至接合區中之擴散程序期間曝露至壓力。表面上之壓力尤其介於0.01MPa與10MPa之間，較佳地介於0.1MPa與8MPa之間，更佳地介於1MPa與5MPa之間，最佳地介於1.5MPa與3MPa之間。對於一200mm基板而言，此等值大概地對應於1kN至320kN之一力之施加。
在如本發明中所主張之預接合程序之前犧牲層之表面應無污染及/或至少主要地較佳地完全無氧化物。特定而言，在施加犧牲層之前自犧牲層施加於其上之材料移除氧化物亦可係必要的。在如本發明中所主張之一預接合程序之前，因此較佳地犧牲層表面經清潔。氧化物之移除可藉由熟習此項技術者已知之物理及/或化學手段發生。其包含藉由氣體及/或液體之化學還原進行廢品之相應移除、藉由濺鍍及/或電漿及/或CMP進行氧化物之機械移除及/或以下方法中之一或多者：-化學氧化物移除，尤其-氣體還原劑，-液體還原劑， -物理氧化物移除，尤其-電漿，-離子輔助化學蝕刻，-快速離子轟擊(FAB，濺鍍)，-研磨，-拋光。
化學氧化物移除定義為藉由一化學程序之氧化物之移除。一化學程序定義為一轉化。在此情形中，氧化物藉由處於氣相及/或液相之一還原劑還原且因此還原劑氧化成一新化合物。因此，氧化還原劑(因此，反應產物)經移除。一典型還原劑係(舉例而言)氫氣。
物理氧化物移除定義為藉由一物理程序之氧化物之移除。在一物理程序中，轉化並未發生，而是氧化物自基板之表面之一純粹機械移除。最常用之物理還原技術係電漿技術。此處藉由相應場加速之一電漿產生至基板之表面上且達成一相應物理氧化物移除。亦可聯想到濺鍍技術之使用。與電漿相比，其並非在反應室中產生之一統計多粒子系統而是在一預燃室中產生且以一專用方式加速至一基板上之離子。最終，研磨及拋光應作為氧化物移除程序而提及。該氧化物藉由一研磨及拋光工具逐漸移除。當涉及微米範圍中之極厚氧化物層時研磨及拋光主要適合用作一預處理程序。此等方法較不適合於奈米範圍中之氧化物層之正確移除。
表面清潔度之偵測可用接觸角方法極快速且容易地完成。已知其並非具有相當親水性質之氧化物表面(主要為純銅)。此主要藉由一極小接觸角展示。若表面氧化為氧化物(特定而言銅至銅氧化物)，則表面性質變為越來越拒水。一所量測接觸角因此係大的。為了顯示接 觸角之改變隨時間而變且因此隨處理銅氧化物厚度而變，一水滴之接觸角在所定義時間單元之後(自自然銅氧化物之完整氧化物移除之時便開始)經量測。隨時間增加，該接觸角達到一飽和值。此關係可以表面之電子結構藉由迅速增長銅氧化物之改變來闡釋。自一特定銅氧化物層厚度開始，氧化物之一進一步增加不再顯著促進表面之電子結構之改變；此反映於接觸角之一產量遞減對數中(參見圖4)。
以此方式出現之氧化物較佳地在用犧牲層表面塗覆接合區表面及/或塊體材料表面及/或在犧牲層表面之彼此接合之前經移除。此處所提及之接觸角方法用於氧化物狀態之立刻精確及成本有效評估。該方法在無複雜化學及/或物理分析設備之情況下仍可成功完成。接觸角量測裝置可在裝置之相應模組群組中安裝以用於表面之完全自動量測及表徵。替代量測方法將係橢偏法或任何其他已知光學及/或電方法。
在如本發明中所主張之另一實施例中，藉助作為犧牲層之水來實施接合區表面之間的一接合程序。如本發明中所主張之思想在於自接合區表面將氧化物完全地清潔掉且用水來潤濕接合區表面，該水在直接跟隨氧化物移除之一後續步驟中在室溫下允許接合區表面之間的一預接合。潤濕藉由已提及可能方法中之一者而發生，諸如PVD、CVD、自旋抗蝕劑施加、汽相沈積或基板表面在具有一相對高大氣濕度(較佳地甚至充滿水蒸汽)之一大氣中之曝光。
犧牲層之施加在一反應室中發生。較佳地，反應室可係抽空的。此外，尤其反應室之繼續排空對實現大氣之專用設定係有利的。較佳地，反應室係一真空群集之一模組之一部分，較佳地一低真空群集之部分，更佳地一高真空群集之部分，最佳地一超高真空群集之部 分。反應室中之壓力小於1bar，較佳地小於10-1mbar，更佳地小於10-3mbar，最佳地小於10-5mbar，特佳地小於10-8mbar。
1:第一基板/基板/產品晶圓
1':結構化第一基板/基板
1o:界面/表面
1o':界面
2:腔
3:接合區
3':接合區/接合區表面
3o:接合區表面
3o':接合區表面
4:犧牲層
4o:犧牲層表面
5:塊體材料
5o:塊體材料表面
7:層系統/基板
7':層系統
7":層系統
8:模組
9:群集
10:內部空間
11:模組上鎖門
12:機器人
13:輸入FOUP
14:輸出FOUP
15:群集鎖
E:共同平面/平面
本發明之其他優點、特徵及細節將自對較佳例示性實施例之以下說明且使用該等圖式而變得顯而易見。
圖1展示如本發明中所主張之具有一毯覆接合區之一第一實施例之一側視圖，圖2展示如本發明中所主張之具有數個局部接合區之一第二實施例之一側視圖，圖3展示如本發明中所主張之在基板中具有數個局部接合區之一第三實施例之一側視圖，圖4展示液體液滴邊緣與銅/銅氧化物之表面之間的接觸角隨時間而變之實證量測資料，且圖5展示含有裝置之一群集系統之一示意性平面圖。
在圖中，相同組件或具有相同效應之組件用相同參考編號識別。圖式僅示意性地展示如本發明中所主張之實施例且未必按比例繪製。因此，主要地犧牲層、接合區及基板之相對厚度係以與所指示厚度對基板之直徑之比率完全相同之方式而彼此不成比例的。
圖1展示由具有一界面1o之一第一基板1、具有一接合區表面3o之一接合區3及具有犧牲層表面4o之犧牲層4構成之一層系統7。在第一實施例中接合區3在基板1之整個界面1o上方延伸。在此情形中接合區表面3o形成第一基板1之一第一接觸表面。接合區3可(特定而言)係第一基板1之一材料完整(因此由相同材料組成)及/或單片組件。犧牲層4以一毯覆方式施加於第一接觸表面上。
圖2展示其中較佳地規則地分佈於界面1o上方之數個接合區3'以及相應接合區表面3o'施加於第一基板上之一層系統7'。接合區3'因此在基板1之表面1o上方形成一形貌。在所圖解說明之較佳實施例中，接合區3'由一塊體材料5環繞。塊體材料可係任何金屬、非金屬、一陶瓷或一聚合物(例如一抗蝕劑)。較佳地在任何情形中其將係一陶瓷，尤其SixN4或SixOxNx，仍更佳地一氧化物陶瓷，尤其SiO2。接合區表面3'及塊體材料表面5o形成一共同平面E，具體而言第一接觸表面。接合區表面3'及塊體材料表面5o之均勻性以及其共面性允許犧牲層4在第一接觸表面上之一最佳沈積。
圖3展示由具有一界面1o'之一結構化第一基板1'及較佳地規則地分佈於基板1'中之數個接合區3'以及接合區表面3o'構成之一層系統7"。基板1'已藉由蝕刻經結構化以使得腔2已形成於基板1'中。已以此方式形成之腔2尤其使用一PVD或CVD程序填充有用於接合區3'之材料。已沈積於共同平面E上方之接合區3'之材料接著藉由一倒轉程序移除。將可聯想到就平面E而言藉由研磨程序、拋光程序、化學-機械拋光等之移除。基板1'已以此方式產生：其中藉由用材料填充腔2形成接合區3'且因此接著如本發明中所主張將接觸表面聯合地覆蓋於具有犧牲層4之接合區3'上。
如本發明中所主張之所有實施例之犧牲層4之沈積可發生以使得用於犧牲層4之材料沈積直至達成必要層厚度。第二方法在於在一第一步驟中將犧牲層4製作得比所需較厚且在一第二步驟中將其減小至所期望厚度(一倒轉程序)。在此情形中，亦將可聯想到研磨程序及/或拋光程序及/或化學-機械拋光之使用。在液體犧牲層之情形中，所要層厚度亦可藉由被允許生長之犧牲層來繼續堆疊。因此，已知(舉例 而言)在產生具有相應大氣濕度之一大氣時平衡層厚度在一基板之表面上出現。基板表面上之一良好界定之層厚度可藉由對溫度、壓力及濕度含量之專用控制而產生。
在產生兩個層系統7、7'、7"之後，犧牲層表面在其中形成一預接合之接合區上在低溫度下及/或在低壓力下彼此接合。
在預接合之前，犧牲層表面4o可另外用一液體(較佳地水)潤濕。較佳地，所施加水層薄於100nm，更佳地薄於10nm，最佳地薄於1nm，特佳地僅一單層。舉例而言，將可聯想到由一個SiO2層及位於其上之一個水層組成之一雙層系統之使用。SiO2層係(舉例而言)大概地1.5nm厚，SiO2層上之水層僅藉由水分子在大氣中之冷凝而出現。
在方法程序期間及/或之前，兩個基板7、7'、7"可在x及/或y方向上沿著平面E經由對準標記及/或其他對準特徵對準。兩個犧牲層4之彼此接觸較佳地在一點處藉由由一接針中凸地塑形之兩個基板1、1'中之一者發生。在兩個犧牲層表面40進行接觸之後，形成藉由一預接合將兩個犧牲層表面彼此強烈地接合之一接合波。
在如本發明中所主張之另一方法步驟中，在低溫下實施熱處理及/或一接合步驟。增大之溫度及/或一力之作用導致犧牲層4之原子至接合區3、3'中之一擴散。犧牲層4之原子較佳地完全溶解於接合區3、3'及/或環繞其之塊體材料5中且因此在儘可能低溫度下導致接合區材料之一創造性直接接合。直接接合可(舉例而言)藉由在此方面參考之專利EP2372755或專利PCT/EP2012/069268中之方法中之一者發生。
如本發明中所主張用於產生犧牲層之實施例係較佳地一群集9、尤其一低真空群集、較佳地一高真空群集、最佳地一超高真空群集之 一模組8(犧牲層模組)之部分。群集9由可被抽空且可經由模組上鎖門11氣密性地分離成所有現存模組之一內部空間10構成。在內部空間10內，一機器人12將產品晶圓1自模組傳送至模組。產品晶圓1經由一個輸入FOUP 13之一群集鎖15行進以用於將產品晶圓傳入至內部空間10中。在產品晶圓1在群集9內之成功處理之後，機器人12再次經由一個輸出FOUP 14中之一FOUP鎖15沈積產品晶圓1。
1‧‧‧第一基板/基板/產品晶圓
1o‧‧‧界面/表面
3‧‧‧接合區
3o‧‧‧接合區表面
4‧‧‧犧牲層
4o‧‧‧犧牲層表面
7‧‧‧層系統/基板
E‧‧‧共同平面/平面

Claims (6)

  1. 一種用於將一第一基板(1、1')之一第一接觸表面接合至一第二基板之一第二接觸表面之方法，其中該第一接觸表面尤其至少部分為金屬的，該第二接觸表面尤其至少部分為金屬的，該方法尤其包括依以下流程(progression)之步驟： 將一固態犧牲層施加至該等接觸表面中之至少一者； 將一液態犧牲層施加至該固態犧牲層上； 接合(bonding)該等基板(1、1')，其中在該接合步驟期間該等犧牲層溶解於環繞(surrounding)該等犧牲層之材料中或者被消耗(consumed)於該界面中 。
  2. 如請求項1之方法，其中施加具有小於1000 nm、較佳地小於100 nm、更佳地小於10 nm、最佳地小於1 nm之一厚度之該犧牲層(4)。
  3. 如請求項1或2之方法，其中該犧牲層至少主要地，或尤其完全地，由以下材料中之至少一者構成： 金屬，尤其是 Cu、Ag、Au、Al、Fe、Ni、Co、Pt、W、Cr、Pb、Ti、Te、Sn及/或Zn， 合金， 具有相應摻雜的半導體，尤其是 元素半導體，較佳為 Si、Ge、Se、Te、B及/或(α)-Sn， 化合物半導體，較佳為 GaAs、GaN、InP、Inx GE1-x N、InSb、InAs、GaSb、AlN、InN、GaP、BeTe、ZnO、CuInGaSe2 、ZnS、ZnSe、ZnTe、CdS、CdSe、CdTe、Hg(1-x)Cd(x)Te、BeSe、HgS、Alx Ga1-x As、GaS、GaSe、GaTe、InS、InSe、InTe、CuInSe2 、CuInS2 、CuInGaS2 、SiC及/或SiGe， 有機半導體，較佳為 黃烷士酮、紫環酮、Alq3、紫環酮、稠四苯、辛吖啶酮、稠五苯、酞青素、聚噻吩、PTCDA、MePTCDI、吖啶酮及/或陰丹士林。 液體，尤其是 水， 醇， 醛， 酮， 醚， 酸， 鹼基。
  4. 如請求項1或2之方法，其中該犧牲層(4)之厚度對該等基板(1、1')，尤其是對該等基板(1、1')之接合區(3、3')之厚度，之比率小於1、較佳地小於10-2 、較佳地小於10-4 、更佳地小於10-6 、仍更佳地小於10-8 。
  5. 如請求項1之方法，其中該等接觸表面中之至少一者由數個接合區(3、3')及環繞該等接合區(3、3')之塊體材料(5)形成。
  6. 如請求項1之方法，其中該等接觸表面中之至少一者以毯覆方式(blanket fashion)位於一個接合區(3)上。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3217421A1 (de) 2014-06-24 2017-09-13 EV Group E. Thallner GmbH Vorrichtung zur oberflächenbehandlung von substraten
US10340161B2 (en) 2014-12-23 2019-07-02 Ev Group E. Thallner Gmbh Device for prefixing of substrates
US20170330855A1 (en) * 2016-05-13 2017-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Immersion Bonding
US10269771B2 (en) 2016-08-31 2019-04-23 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10971365B2 (en) 2017-02-21 2021-04-06 Ev Group E. Thallner Gmbh Method and device for bonding substrates
CN108324201B (zh) * 2018-05-08 2023-11-17 杨勇 拖把
KR20210021626A (ko) 2019-08-19 2021-03-02 삼성전자주식회사 반도체 장치
WO2021127527A1 (en) * 2019-12-20 2021-06-24 Ohio State Innovation Foundation Method of forming an impact weld
CN112897454B (zh) * 2021-01-20 2024-02-23 杭州士兰集成电路有限公司 Mems器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984873B2 (en) * 2003-06-20 2006-01-10 Intel Corporation Method of forming a stacked device filler
TW201250971A (en) * 2010-12-16 2012-12-16 Soitec Silicon On Insulator Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
TW201310552A (zh) * 2011-08-30 2013-03-01 Ev Group E Thallner Gmbh 晶圓之永久接合之方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130059A (ja) 1984-07-20 1986-02-12 Nec Corp 半導体装置の製造方法
JP2671419B2 (ja) * 1988-08-09 1997-10-29 株式会社日本自動車部品総合研究所 半導体装置の製造方法
US5603779A (en) * 1995-05-17 1997-02-18 Harris Corporation Bonded wafer and method of fabrication thereof
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US20050003652A1 (en) 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
FR2857953B1 (fr) * 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
DE102004015017B4 (de) * 2004-03-26 2006-11-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Erzeugung von mechanischen und elektrischen Verbindungen zwischen den Oberflächen zweier Substrate
US7261793B2 (en) * 2004-08-13 2007-08-28 Hewlett-Packard Development Company, L.P. System and method for low temperature plasma-enhanced bonding
KR100560721B1 (ko) * 2004-08-23 2006-03-13 삼성전자주식회사 금속 챔버층을 구비하는 잉크젯 헤드의 제조방법 및 그에의하여 제조된 잉크젯 헤드
TWI395253B (zh) * 2004-12-28 2013-05-01 Mitsumasa Koyanagi 使用自我組織化功能之積體電路裝置的製造方法及製造裝置
US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion
US7598153B2 (en) * 2006-03-31 2009-10-06 Silicon Genesis Corporation Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species
DE102006031405B4 (de) 2006-07-05 2019-10-17 Infineon Technologies Ag Halbleitermodul mit Schaltfunktionen und Verfahren zur Herstellung desselben
KR100748723B1 (ko) * 2006-07-10 2007-08-13 삼성전자주식회사 기판 접합 방법
JP2008166529A (ja) 2006-12-28 2008-07-17 Spansion Llc 半導体装置の製造方法
JP5492096B2 (ja) 2009-01-23 2014-05-14 日亜化学工業株式会社 半導体装置及びその製造方法
DE102009050426B3 (de) * 2009-10-22 2011-03-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum ausgerichteten Aufbringen von Bauteilen auf einem Trägersubstrat und ein Verfahren zur Herstellung eines Trägersubstrats dafür und ein Verfahren zur Bestückung eines Zielsubstrats damit.
JP5732652B2 (ja) * 2009-11-04 2015-06-10 ボンドテック株式会社 接合システムおよび接合方法
EP2372755B1 (de) 2010-03-31 2013-03-20 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
US20120160903A1 (en) 2010-05-31 2012-06-28 Kouichi Saitou Method of joining metal
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
SG192102A1 (en) * 2011-01-25 2013-08-30 Ev Group E Thallner Gmbh Method for permanent bonding of wafers
WO2012133760A1 (ja) * 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
KR101550121B1 (ko) 2011-04-08 2015-09-03 에베 그룹 에. 탈너 게엠베하 웨이퍼 영구 결합 방법
US8431436B1 (en) 2011-11-03 2013-04-30 International Business Machines Corporation Three-dimensional (3D) integrated circuit with enhanced copper-to-copper bonding
FR2983845A1 (fr) 2012-05-25 2013-06-14 Commissariat Energie Atomique Procede de realisation d'une microstructure comportant deux substrats relies mecaniquement
JP2013251405A (ja) * 2012-05-31 2013-12-12 Tadatomo Suga 金属領域を有する基板の接合方法
CN104661786B (zh) 2012-09-28 2017-05-24 Ev 集团 E·索尔纳有限责任公司 涂覆及接合衬底的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984873B2 (en) * 2003-06-20 2006-01-10 Intel Corporation Method of forming a stacked device filler
TW201250971A (en) * 2010-12-16 2012-12-16 Soitec Silicon On Insulator Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
TW201310552A (zh) * 2011-08-30 2013-03-01 Ev Group E Thallner Gmbh 晶圓之永久接合之方法

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