TWI722754B - 半導體裝置之製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000007789 gas Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 125000001181 organosilyl group Chemical group [SiH3]* 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 2
- 229910000077 silane Inorganic materials 0.000 claims 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 24
- 150000003377 silicon compounds Chemical class 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 230000014509 gene expression Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
實施形態之半導體裝置之製造方法包含以下步驟:在半導體基板之通孔內與第1面側成膜被覆性良好之第1絕緣膜,該半導體基板具有第1面及位於第1面之相反側之第2面,在第2面側設置有包含配線電路之電路基板,且從第1面朝向第2面具有通孔;在通孔內與第1面側成膜被覆性較差之第2絕緣膜;以及藉由各向異性蝕刻去除通孔底部之第1絕緣膜、或通孔內之底部之第1絕緣膜及通孔內之底部之第2絕緣膜。
Description
本發明之實施形態係關於一種半導體裝置之製造方法。
已知在形成半導體裝置之TSV(Through Silicon Via,矽通孔)時,形成用以將TSV與半導體基板絕緣之絕緣膜時要形成使用原矽酸四乙酯作為Si成分之二氧化矽覆膜。
本發明之實施形態提供一種絕緣膜之膜厚控制性優異之半導體裝置之製造方法。
實施形態之半導體裝置之製造方法包含以下步驟:在半導體基板之通孔內與第1面側成膜被覆性良好之第1絕緣膜,該半導體基板具有第1面及位於第1面之相反側之第2面,在第2面側設置有包含配線電路之電路基板,且從第1面朝向第2面具有通孔;在通孔內與第1面側成膜被覆性較差之第2絕緣膜;藉由各向異性蝕刻去除通孔底部之第1絕緣膜、或通孔內之底部之第1絕緣膜及通孔內之底部之第2絕緣膜。
1:第1絕緣膜
2:第2絕緣膜
10:半導體基板
11:TSV
12:凸塊
20:STI膜
30:半導體層
31:配線電路
32:絕緣膜
32:絕緣膜
33:絕緣膜
34:凸塊
35:接著層
36:支持基板
100:半導體裝置
101:構件
102:構件
103:構件
104:構件
105:構件
106:構件
F1:第1面
F2:第2面
VH:通孔
圖1係實施形態之半導體裝置之剖視圖。
圖2係實施形態之半導體裝置之流程圖。
圖3係實施形態之半導體裝置之步驟剖視圖。
圖4係實施形態之半導體裝置之步驟剖視圖。
圖5係實施形態之半導體裝置之步驟剖視圖。
圖6係實施形態之半導體裝置之步驟剖視圖。
圖7係實施形態之半導體裝置之步驟剖視圖。
圖8係實施形態之半導體裝置之步驟剖視圖。
圖9係實施形態之半導體裝置之步驟剖視圖。
圖10係實施形態之半導體裝置之步驟剖視圖。
以下,參照圖式對實施形態進行說明。
在本說明書中,對一些要素附上了多種表述之例。再者,該等表述之例僅為例示,並不否定以其他表述對上述要素進行描述。又,未附上多種表述之要素亦可採用其他表述來進行描述。
又,圖式係模式性之圖,厚度與平面尺寸之關係、各層厚度之比率及厚度之變化等有時與實際不同。又,有時亦包含圖式相互之間彼此之尺寸之關係或比率不同之部分。又,在圖式中省略了一部分符號。
(第1實施形態)第1實施形態係關於一種半導體裝置之製造方法。圖1中表示半導體裝置100之剖視圖。圖2中表示第1實施形態之半導體裝置100之製造方法之流程圖。圖3至圖6中表示半導體裝置100之步驟剖視圖。更具體而言,半導體裝置100係NAND(Not AND,反及)快閃記憶體晶片等記憶裝置。
在圖1之剖視圖中,表示半導體裝置100之一部分區域之主要部分。半導體裝置100、圖1之半導體裝置100係記憶裝置之一例。半導體裝置100係藉由實施形態之半導體裝置100之製造方法製造。半導體裝置100包含半導體基板10、第1絕緣膜1(第2絕緣膜2)、TSV11、凸塊12及半導體層30。以下,對半導體裝置100之構成進行說明,但可實施半導體裝置100之製造方法者並不限定於半導體裝置100所包含之半導體層30之構成。在圖1中,第1絕緣膜1形成於通孔VH之側壁及半導體基板10之第1面F1上,但既可使用第2絕緣膜2代替第1絕緣膜1,亦可在通孔VH之側壁及半導體基板10之第1面F1上形成第1絕緣膜1及第2絕緣膜2兩者,這兩種方式均包含在實施形態中。
半導體基板10具有第1面F1及第2面F2,且從第1面F1朝向第2面F2設置有通孔VH。在通孔VH內設置有第1絕緣膜1及TSV11。在第1面F1側形成有第1絕緣膜1。TSV11係將通孔VH貫通之貫通電極。
半導體基板10例如係矽基板(矽晶圓)。在半導體基板10上(圖1之半導體基板之下側)形成有未圖示之半導體元件。半導體元件例如包含記憶胞
陣列,位於半導體層30之絕緣膜32中。
較佳為第1絕緣膜1與通孔VH之側壁直接相接,利用第1絕緣膜1將通孔VH側壁之半導體基板10與TSV11絕緣。同樣地,較佳為第1絕緣膜1與半導體基板10之第1面F1直接相接,利用第1絕緣膜1將半導體基板10之第1面與TSV11絕緣。
較佳為TSV11與半導體層30所包含之配線電路31直接相接。TSV11與配線電路31電性連接。TSV11經由配線電路31與半導體元件電性連接。
如圖1之剖視圖所示,半導體層30例如具有從半導體基板10側起積層絕緣膜32、絕緣膜33、接著層35及支持基板36而成之構造。利用絕緣膜32及絕緣膜33被覆配線電路31及未圖示之半導體元件。從接著層35之內部跨及絕緣膜32(配線電路31)設置有凸塊34,凸塊34可採用與配線電路31直接電相接之構造。接著層35將絕緣膜33與支持基板36接著。在形成TSV11及凸塊12後將接著層35與支持基板36一同去除所得之裝置亦視為半導體裝置100,同樣包含在實施形態中。
較佳為在配線電路31與半導體基板1之間設置被稱為STI(Shallow Trench Isolation,淺槽隔離)膜20之氧化矽膜等絕緣膜,從而抑制半導體層30與半導體基板1間之漏電。
其次,參照圖2之流程圖及圖3至圖6之步驟剖視圖,對半導體裝置100之製造方法進行說明。以下,對形成TSV11之步驟進行說明。再者,省略形成半導體元件等之步驟等之說明。
如圖2之流程圖所示,半導體裝置100之製造方法具有形成通孔VH之步驟(S00)、成膜第1絕緣膜1之步驟(S01)、成膜第2絕緣膜2之步驟(S02)、藉由各向異性蝕刻去除通孔VH底部之絕緣膜之步驟(S03)、及形成TSV11之步驟(S04)。
參照圖3之步驟剖視圖對形成通孔之步驟(S00)進行說明。如圖3之步驟剖視圖所示,在該步驟(S00)中,獲得構件(101),上述構件(101)形成有從半導體基板10之第1面F1側朝向第2面F2側貫通半導體基板10之通孔。通孔VH例如係使用未圖示之光阻作為遮罩,藉由RIE(Reactive Ion Etching,反應性離子蝕刻)法形成。當形成通孔VH時,半導體層30之半導體基板10側之表面之STI膜20露出。
為了滿足NAND快閃記憶體晶片等之薄型化要求,追求使半導體基板10之厚度變薄。若半導體基板10之厚度變薄,則通孔VH之深寬比(通孔深度(半導體基板10之厚度)/通孔直徑(通孔之外接圓直徑))變小。若通孔VH之深寬比較大,則在通孔VH之底部成膜之絕緣膜變薄,故要藉由其後之蝕刻去除之絕緣膜之厚度變薄,因此,在半導體基板10之第1面F1側容易殘留例如500nm以上之厚度充分之絕緣膜。然而,若通孔VH之深寬比變小,則在僅形成被覆性較高之第1絕緣膜1之情形時,若在側壁及第1面
F1側形成所要求之厚度之第1絕緣膜1,則會在通孔VH之底部形成較厚之第1絕緣膜1。當去除通孔VH底部之較厚之第1絕緣膜1時,通孔VH之側壁或第1面F1側之第1絕緣膜1亦會被去除。若為被覆性較低之第2絕緣膜2,則在通孔VH之側壁之底部側不會形成充分之絕緣膜。因此,若採用先前之在通孔VH內形成絕緣膜之方法,將難以在深寬比較小之通孔VH中形成所要求之厚度之絕緣膜。因此,較佳為採用無論深寬比小或大均容易控制蝕刻後之絕緣膜厚度之實施形態之製造方法。
其次,對成膜第1絕緣膜1之步驟(S01)進行說明。如圖4之步驟剖視圖所示,在該步驟(S01)中,獲得在圖3之構件101之通孔VH內與第1面F1側成膜有被覆性較高之第1絕緣膜1之構件102。第1絕緣膜1因被覆性較高,故較佳為形成於通孔VH之底部及側壁之整個面,且形成於半導體基板10之第1面F1側之整個面。
較佳為第1絕緣膜1藉由電漿CVD(Chemical Vapor Deposition,化學氣相沈積)法成膜。藉由採用電漿CVD法,通孔VH之開口部之第1絕緣膜1變厚(懸突(overhang)變大),能夠抑制通孔VH底部之第1絕緣膜1之厚度。為了在所要製造之半導體裝置100之第1面F1側殘留相對較厚之絕緣膜,較佳為採用電漿CVD法。若通孔VH底部之絕緣膜變厚,則在藉由蝕刻去除通孔VH底部之絕緣膜時,形成於半導體基板10之第1面F1側之絕緣膜或通孔VH之側壁之絕緣膜容易變薄或被去除。
藉由電漿CVD法成膜第1絕緣膜1之成膜溫度較佳為250℃以下。例
如,若在400℃以上成膜第1絕緣膜1,則接著層35將熔融,支持基板36變得容易剝離。又,若溫度過低,則將難以成膜第1絕緣膜1,因此較佳為100℃以上,更佳為120℃以上。
在成膜第1絕緣膜1之一次處理中,較佳為成膜100μm以上1000μm以下之第1絕緣膜1。膜狀進行之厚度視部位不同,因此在實施形態中以第1面F1側之絕緣膜厚度為基準。若第1絕緣膜1之厚度過薄,則通孔VH之底部側之側壁之絕緣膜厚度有可能變得不充分。若第1絕緣膜1之厚度過厚,則存在通孔VH底部之絕緣膜厚度過厚而導致通孔VH底部之蝕刻變得困難、或蝕刻後之第1面F1側之絕緣膜厚度變得不充分之情形。
較佳為第1絕緣膜1係在包含反應性較低之矽化合物之氣氛中成膜之矽氧氮化膜。更具體而言,較佳為第1絕緣膜1係在包含原矽酸四乙酯(TEOS)氣體、含氧氣體及含NH基氣體作為反應性較低之矽化合物之氣氛中成膜。作為典型之含氧氣體,較佳為選自由NO2、O2及NO等所組成之群中之1種以上之氣體。又,作為典型之含NH基氣體,較佳為包含NH3氣體、進而任意包含N2氣體之氣體。
其次,對成膜第2絕緣膜2之步驟(S02)進行說明。如圖5之步驟剖視圖所示,在該步驟(S02)中,獲得在圖4之構件102之通孔VH內與第1面F1側形成有被覆性較低之第2絕緣膜2之構件103。第2絕緣膜2成膜在第1面F1側(第1絕緣膜1上之第1面F1側)與通孔VH內之側壁與底部。
較佳為第2絕緣膜2與第1絕緣膜1同樣藉由電漿CVD法成膜。第2絕緣膜2與第1絕緣膜1相比懸突變大,若僅成膜第2絕緣膜2,則難以控制蝕刻後之膜厚。較佳為以蝕刻後之第1面F1側、通孔VH之側壁之絕緣膜分別成為所要求厚度之絕緣膜之方式成膜厚度適當之第1絕緣膜1與第2絕緣膜2。在實施形態之製造方法中,藉由成膜被覆性較高之第1絕緣膜1與被覆性較低之第2絕緣膜2之兩種膜,有效地利用各自之特性。第2絕緣膜2因被覆性較低,故以相對第1絕緣膜1而言在第1面F1側較厚、通孔VH之開口部分縮窄之方式集中成膜在第1面F1側與通孔VH之開口部。存在第2絕緣膜2不易成膜在通孔VH之底部側,而於通孔VH之底部與底部側之側壁包含未形成第2絕緣膜2之部分之情形。
藉由電漿CVD法成膜第2絕緣膜2之成膜溫度較佳為250℃以下。例如,若在400℃以上成膜第2絕緣膜2,則接著層35將熔融,支持基板36容易剝離。又,若溫度過低,則將難以成膜第2絕緣膜2,因此較佳為100℃以上,更佳為120℃以上。
在成膜第2絕緣膜2之一次處理中,可成膜100μm以上1000μm以下之第2絕緣膜2。成膜之厚度視部位不同,因此在實施形態中以第1面F1側之絕緣膜厚度為基準。若將第2絕緣膜2成膜得過厚,則會存在通孔VH之開口部附近之絕緣膜厚度變得過厚之情形、或通孔VH之開口部被堵塞而難以進行蝕刻之情形。
較佳為第2絕緣膜2係在包含反應性較高之矽化合物之氣氛中成膜之
矽氧氮化膜。更具體而言,較佳為第1絕緣膜1係在包含甲矽烷(SiH4)氣體、含氧氣體及含NH基氣體作為反應性較高之矽化合物之氣氛中成膜。作為典型之含氧氣體,較佳為選自由NO2、O2及NO等所組成之群中之1種以上之氣體。又,作為典型之含NH基氣體,較佳為包含NH3氣體、進而任意包含N2氣體之氣體。
第1絕緣膜1與第2絕緣膜2之成膜之切換係藉由改變反應性較低之矽化合物與反應性較高之矽化合物之供給量而進行。因能夠藉由變更氣體濃度這一簡便操作分別製作被覆性不同之絕緣膜,故能夠抑制步驟數增加,就經濟性之觀點而言亦較佳。
又,在成膜第2絕緣膜時,亦可使用如濺鍍法或真空蒸鍍法等粒子之直進性較高之成膜法以使被覆性變差。
因在成膜第1絕緣膜1後成膜第2絕緣膜2,故第1絕緣膜1與半導體基板10相接,第2絕緣膜2與第1絕緣膜1之和半導體基板10相接之面之相反側的面相接。即,第1絕緣膜1與半導體基板10直接相接,第2絕緣膜2與第1絕緣膜1之和半導體基板10直接相接之面之相反側的面直接相接。
再者,關於成膜第1絕緣膜1之步驟(S01)與成膜第2絕緣膜2之步驟(S02),如在其他實施形態中所說明般,亦可在成膜第1絕緣膜1之步驟(S01)前進行成膜第2絕緣膜2之步驟(S02),還可交替地進行成膜第1絕緣膜1之步驟(S01)與成膜第2絕緣膜2之步驟(S02)從而進行多次成膜第1絕緣膜1之步驟(S01)或/及成膜第2絕緣膜2之步驟(S02)。
在成膜第1絕緣膜1後成膜第2絕緣膜2之情形時,在圖5之構件103中,較佳為位於最靠半導體基板10側之第1絕緣膜1之面向半導體基板10之面(較佳為整個面)與半導體基板10之面向第1絕緣膜1之面直接相接。又,較佳為位於最靠半導體基板10側之第2絕緣膜2之面向半導體基板10之面(較佳為整個面)與第1絕緣膜1之面向第2絕緣膜2之面直接相接,或位於最靠半導體基板10側之第2絕緣膜2之面向半導體基板10之面(較佳為整個面)之一部分與第1絕緣膜1之面向第2絕緣膜2之面直接相接,其餘部分與半導體基板10之面向第2絕緣膜2之面直接相接。
其次,對藉由各向異性蝕刻去除通孔VH底部之絕緣膜之步驟(S03)進行說明。如圖6之步驟剖視圖所示,在該步驟(S03)中,獲得圖5之構件103之通孔VH底部之第1絕緣膜1及第2絕緣膜2被去除而得之構件104。進行蝕刻將通孔VH底部之絕緣膜去除。在圖1之半導體裝置100之構成之情形時,半導體層30之配線電路31之存在於半導體基板10側之絕緣膜(圖1中為STI膜20)亦藉由蝕刻被去除,由此使半導體層30之配線電路31露出。藉由從相對於第1面F1垂直之方向進行各向異性蝕刻,將通孔VH之側壁之絕緣膜亦去除一部分。
例如,若僅成膜第1絕緣膜1,則被覆性較高,故在通孔VH之底部亦會成膜厚度接近第1面F1側之絕緣膜,因此當藉由各向異性蝕刻去除通孔VH底部之絕緣膜時,第1面F1側之第1絕緣膜1亦會被去除。藉由成膜被覆性較高之第1絕緣膜1與被覆性較低之第2絕緣膜2之兩種膜,能夠抑制
通孔VH底部之絕緣膜之厚度並且增加第1面F1側之絕緣膜之厚度。在通孔VH之深寬比較小之情形時,與深寬比較大之情形相比,在通孔VH之底部更容易形成絕緣膜,但由於被覆性較低之第2絕緣膜2不易成膜在通孔VH之底部,故如圖5之步驟剖視圖所示,能夠使通孔VH底部之絕緣膜之厚度與第1面F1側之絕緣膜之厚度相比足夠薄。
在通孔VH之深寬比較大之情形時,亦能享受實施形態之製造方法所產生之容易控制蝕刻後之絕緣膜之厚度之益處,但如上所述,該益處在通孔VH之深寬比較小之情形時更大。當通孔VH之深寬比小於2.8時,實施形態之製造方法所產生之益處更大。在通孔VH之深寬比為2.0以下之情形時,更適合採用實施形態之製造方法,在通孔VH之深寬比為1.5以下之情形時,進而更適合採用實施形態之製造方法。
又,若通孔VH之通孔直徑變大,則容易在通孔VH之底部形成絕緣膜。根據上述理由,在通孔VH之通孔直徑為10μm以上之情形時,更適合採用實施形態之製造方法。
又,在進行各向異性蝕刻時,亦可不藉由光微影法用抗蝕劑覆蓋通孔VH以外之部分。
其次,對形成TSV11之步驟(S04)進行說明。在該步驟(S04)中,與圖6之構件104之通孔VH底部露出之配線電路31連接,形成貫通半導體層30之TSV11及TSV11上之凸塊12,獲得圖1之半導體裝置100。亦可在TSV11或凸塊34與其基底之間形成未圖示之阻擋金屬。
藉由採用第1實施形態之製造方法,即便在深寬比較小之情形時,亦能夠獲得在第1面F1側具有所要求之厚度之絕緣膜之半導體裝置100。
(第2實施形態)第2實施形態係關於一種半導體裝置之製造方法。第2實施形態係第1實施形態之半導體裝置之製造方法之變化例。在第2實施形態中,與第1實施形態之半導體裝置之製造方法不同之處在於:成膜第2絕緣膜2之後成膜第1絕緣膜1。對於第1實施形態與第2實施形態中共通之構成、製造方法,省略其說明。再者,在第2實施形態中,在蝕刻前之通孔VH與配線電路31之間存在絕緣膜32,而並非STI膜20。
在圖1之半導體裝置100中,設置第1絕緣膜1作為阻隔TSV11與半導體基板10之絕緣膜,但在第2實施形態中先形成第2絕緣膜2,故阻隔半導體裝置100之TSV11與半導體基板10之絕緣膜以第2絕緣膜2為主體,局部包含第1絕緣膜1。
在第2實施形態中,在進行成膜第2絕緣膜2之步驟(S02)之後,進行成膜第1絕緣膜1之步驟(S01)。參照圖7與圖8之步驟剖視圖對第2實施形態之半導體裝置之製造方法進行說明。在第2實施形態中,雖然絕緣膜之成膜順序及厚度不同,但成膜之條件與第1實施形態相同。
如圖7之步驟剖視圖所示,在該步驟(S02)中,獲得在圖3之構件101之通孔VH內與第1面F1側成膜有被覆性較低之第2絕緣膜2之構件104。第
2絕緣膜2因被覆性較低,故在通孔VH之側壁及通孔VH之底部不易形成第2絕緣膜2,存在進行成膜第2絕緣膜2之步驟(S02)之後,包含通孔VH之側壁之第2絕緣膜2之厚度較薄之部分之情形、或通孔VH內半導體基板10之表面露出之情形。
其次,從第1面F1側成膜第1絕緣膜1。如圖8之步驟剖視圖所示,在該步驟(S02)中,獲得在圖7之構件105之通孔VH內與第1面F1側成膜有被覆性較低之第1絕緣膜1之構件106。當在通孔VH內存在未於成膜第2絕緣膜2之步驟(S02)中成膜第2絕緣膜2之部分時,第1絕緣膜1便成膜在通孔VH之半導體基板10上。
因在成膜第2絕緣膜2後再成膜第1絕緣膜1,故在成膜第1絕緣膜1後,第2絕緣膜2與半導體基板10相接,第1絕緣膜1與第2絕緣膜2之和半導體基板10相接之面之相反側的面相接。即,第2絕緣膜2與半導體基板10直接相接,第1絕緣膜1與第2絕緣膜2之和半導體基板10直接相接之面之相反側的面直接相接。
在第2實施形態中,藉由在圖7之構件105中絕緣膜之厚度不充分之第1面F1側與通孔VH之側壁(尤其是底部側之側壁)成膜第1絕緣膜1,能夠在蝕刻後於第1面F1側及通孔VH之側壁形成所要求之厚度之絕緣膜。第1絕緣膜1與第2絕緣膜2之成膜順序無論何者在前,在深寬比較小(通孔直徑大之)情形時,均能夠獲得在第1面F1側具有所要求之厚度之絕緣膜之半導體裝置100。
(第3實施形態)第3實施形態係關於一種半導體裝置之製造方法。第3實施形態係第1實施形態之半導體裝置之製造方法之變化例。在第3實施形態中,與第1實施形態之半導體裝置之製造方法不同之處在於:在成膜第2絕緣膜2之後進而成膜第1絕緣膜1。對於第3實施形態與第2實施形態中共通之構成、製造方法,省略其說明。
在第3實施形態中,在進行成膜第2絕緣膜2之步驟(S02)之後,再次進行成膜第1絕緣膜1之步驟(S01)。參照圖9之步驟剖視圖對第3實施形態之半導體裝置之製造方法進行說明。在第3實施形態中,雖然絕緣膜之成膜順序及厚度不同,但成膜之條件與第1實施形態相同。
如圖9之步驟剖視圖所示,在第二次成膜第1絕緣膜1之步驟(S01)中,獲得在第2絕緣膜2上進而形成有第1絕緣膜1之構件107。圖9之構件107中,在通孔VH內與第1面F1側形成有3層絕緣膜。對於圖9之構件107,亦與第1實施形態同樣地進行各向異性蝕刻,由此能夠獲得具有所要求之厚度之絕緣膜之半導體裝置100。有時藉由將絕緣膜積層3層以上,可實現積層2層時難以達成之絕緣膜之膜厚控制。藉由在成膜第1絕緣膜1與第2絕緣膜2後進而成膜第1絕緣膜1,在深寬比較小(通孔直徑大)之情形時,能夠獲得在第1面F1側具有所要求之厚度之絕緣膜之半導體裝置100。
在第3實施形態中,第1絕緣膜1與第2絕緣膜2交替地成膜有2層第1絕
緣膜1,成膜有1層第2絕緣膜2。作為第3實施形態之變化例,亦包含分別交替地成膜2層以上第1絕緣膜1且成膜2層以上第2絕緣膜2之半導體裝置之製造方法。
(第4實施形態)第4實施形態係關於一種半導體裝置之製造方法。第4實施形態係第2實施形態之半導體裝置之製造方法之變化例。在第4實施形態中,與第2實施形態之半導體裝置之製造方法不同之處在於:在成膜第1絕緣膜1之後進而成膜第2絕緣膜2。對於第4實施形態與第2實施形態中共通之構成、製造方法,省略其說明。在第4實施形態中,配線電路31在半導體層30之半導體基板10之第2面側之表面之一部分露出。
在第4實施形態中,進行成膜第1絕緣膜1之步驟(S01)後,再次進行成膜第2絕緣膜2之步驟(S02)。參照圖10之步驟剖視圖對第4實施形態之半導體裝置之製造方法進行說明。在第4實施形態中,雖然絕緣膜之成膜順序及厚度不同,但成膜之條件與第1實施形態相同。
如圖10之步驟剖視圖所示,在第二次成膜第2絕緣膜2之步驟(S02)中,獲得在第1絕緣膜1上進而形成有第2絕緣膜2之構件108。圖10之構件108中,在通孔VH內與第1面F1側形成有3層絕緣膜。對於圖10之構件108,亦與第2實施形態同樣地進行各向異性蝕刻,由此能夠獲得具有所要求之厚度之絕緣膜之半導體裝置100。有時藉由將絕緣膜積層3層以上,可實現積層2層時難以達成之絕緣膜之膜厚控制。藉由在成膜第2絕緣膜2與第1絕緣膜1後進而成膜第2絕緣膜2,在深寬比較小(通孔直徑大)之
情形時,能夠獲得在第1面F1側具有所要求之厚度之絕緣膜之半導體裝置100。
第4實施形態中,第1絕緣膜1與第2絕緣膜2交替地成膜有1層第1絕緣膜1,成膜有2層第2絕緣膜2。作為第4實施形態之變化例,亦包含分別交替地成膜2層以上第1絕緣膜1且成膜2層以上第2絕緣膜2之半導體裝置之製造方法。
以上,對本發明之若干實施形態進行了說明,但該等實施形態係作為示例提出者,並非意在限定發明之範圍。該等新穎之實施形態能以其他各種形態實施,可在不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態及其變化例包含在發明之範圍及主旨中,並且包含在申請專利範圍所記載之發明及與其均等之範圍內。
本申請案以2019年9月13日提出申請之先前日本專利申請案第2019-167317號之優先權之利益為基礎,且主張其利益,藉由引用將其內容整體包含於本文中。
Claims (10)
- 一種半導體裝置之製造方法,其包含以下步驟:在半導體基板之通孔內與第1面側成膜第1絕緣膜,上述半導體基板具有上述第1面及位於上述第1面之相反側之第2面,在上述第2面側設置有包含配線電路之電路基板,且從上述第1面朝向第2面具有上述通孔;在上述通孔內與上述第1面側成膜被覆性比上述第1絕緣膜差之第2絕緣膜;及藉由各向異性蝕刻去除上述通孔底部之上述第1絕緣膜、或上述通孔內之底部之第1絕緣膜及上述通孔內之底部之第2絕緣膜。
- 如請求項1之半導體裝置之製造方法,其中上述第1絕緣膜係在250℃以下藉由電漿CVD法成膜,上述第2絕緣膜係在250℃以下藉由電漿CVD法成膜。
- 如請求項1之半導體裝置之製造方法,其中上述通孔之深寬比(通孔深度/通孔直徑)小於2.8。
- 如請求項1之半導體裝置之製造方法,其中上述通孔之通孔直徑為10μm以上。
- 如請求項1之半導體裝置之製造方法,其中上述第1絕緣膜係在包含原矽酸四乙酯氣體、含氧氣體及含NH基氣體之氣氛中成膜, 上述第2絕緣膜係在包含甲矽烷氣體、含氧氣體及含NH基氣體之氣氛中成膜,藉由改變上述原矽酸四乙酯氣體及上述甲矽烷氣體之供給量,切換上述第1絕緣膜與上述第2絕緣膜之成膜。
- 如請求項1之半導體裝置之製造方法,其中上述第1絕緣膜與上述半導體基板相接,上述第2絕緣膜與上述第1絕緣膜之和上述半導體基板相接之面之相反側的面相接,或者上述第2絕緣膜與上述半導體基板相接,上述第1絕緣膜與上述第2絕緣膜之和上述半導體基板相接之面之相反側的面相接。
- 如請求項1之半導體裝置之製造方法,其中交替地成膜上述第1絕緣膜與第2絕緣膜,上述第1絕緣膜或/及上述第2絕緣膜係2層以上成膜。
- 如請求項1之半導體裝置之製造方法,其不進行利用光微影法之抗蝕劑加工,而藉由各向異性蝕刻去除上述通孔底部之上述第1絕緣膜、或上述通孔內之底部之第1絕緣膜及上述通孔內之底部之第2絕緣膜。
- 如請求項1之半導體裝置之製造方法,其中在上述第1面僅殘留上述第1絕緣膜或上述第2絕緣膜中之一者。
- 一種半導體裝置之製造方法,其包含以下步驟:在半導體基板之通 孔內與第1面側,於包含原矽酸四乙酯氣體、含氧氣體及含NH基氣體之氣氛中,在250℃以下藉由電漿CVD法成膜第1絕緣膜,上述半導體基板具有上述第1面及位於上述第1面之相反側之第2面,在上述第2面側設置有包含配線電路之電路基板,且從上述第1面朝向第2面具有上述通孔;在上述通孔內及上述第1面側,於包含甲矽烷氣體、含氧氣體及含NH基氣體之氣氛中,在250℃以下藉由電漿CVD法成膜第2絕緣膜;及藉由各向異性蝕刻去除上述通孔底部之上述第1絕緣膜、或上述通孔內之底部之第1絕緣膜及上述通孔內之底部之第2絕緣膜,此時在上述第1面僅殘留上述第1絕緣膜或上述第2絕緣膜中之一者。
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