TWI722381B - 包含具超晶格之共振穿隧二極體結構之半導體元件及其相關方法 - Google Patents

包含具超晶格之共振穿隧二極體結構之半導體元件及其相關方法 Download PDF

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TWI722381B
TWI722381B TW108104236A TW108104236A TWI722381B TW I722381 B TWI722381 B TW I722381B TW 108104236 A TW108104236 A TW 108104236A TW 108104236 A TW108104236 A TW 108104236A TW I722381 B TWI722381 B TW I722381B
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layer
superlattice
silicon
barrier
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TW201921683A (zh
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米爾斯羅勃
竹內秀樹
海太馬瑞克
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美商安托梅拉公司
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Abstract

一半導體元件可包含至少一雙阻障共振穿隧二極體(DBRTD)。該至少一雙阻障共振穿隧二極體可包含一第一摻雜半導體層及設置在該第一摻雜半導體層上且包含一超晶格之一第一阻障層。所述超晶格可包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該至少一雙阻障共振穿隧二極體可更包含設置在該第一阻障層上之一本質半導體層、設置在該本質半導體層上之一第二阻障層，以及設置在該第二超晶格層上之一第二摻雜半導體層。

Description

包含具超晶格之共振穿隧二極體結構之半導體元件及其相關方法
本發明一般而言與半導體元件有關，詳細而言，本發明與半導體二極體結構及相關電路與方法有關。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件效能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致效能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與／或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
授予Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘電極上的電場所誘發的電子，便會被侷限在其第二矽層內，因此，即可認定其n通道MOSFET具有較高的遷移率。
授予Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部分(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
授予Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，授予Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
授予Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個阻障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一阻障區各係由厚度範圍大致在二至六個交疊之SiO2／Si單層所構成。阻障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing) pp. 391 – 402中，Tsu於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice, SAS)。此矽／氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species) 及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1 nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol. 89, No. 7 (2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
已公告之Wang, Tsu及Lofgren等人的國際申請案WO 02/103,767 A1號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一阻障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層／阻障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公告之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙 (aperiodic photonic band-gap, APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
除此之外，授予Wang等人的美國專利第6,376,337號揭示，一種用於製作半導體元件絕緣或阻障層之方法，其包括在矽底材上沉積一層矽及至少一另外元素，使該沉積層實質上沒有缺陷，如此實質上無缺陷的磊晶矽便能沉積於該沉積層上。作為替代方案，一或多個元素構成之一單層，較佳者為包括氧元素，在矽底材上被吸收。夾在磊晶矽之間的複數絕緣層，形成阻障複合體。
儘管已有這些方法，使用進階半導體材料及製程技術需要更進一步提升，從而達到半導體元件之效能改善。
一半導體元件可包含至少一雙阻障共振穿隧二極體(double-barrier resonant tunneling diode, DBRTD)。所述之至少一DBRTD可包含一第一摻雜半導體層及設置在該第一摻雜半導體層上且包含一超晶格之一第一阻障層。其超晶格可包含堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，且被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。該至少一DBRTD可更包含設置在第一阻障層上之一本質半導體層、設置在該本質半導體層上之一第二阻障層，以及設置在第二超晶格層上之一第二摻雜半導體層。
依照一示例性實施例， 所述第一及第二摻雜半導體層可包含矽，且其本質層可包含矽及鍺當中至少一者。除此之外，第二阻障層也可包含一超晶格，且第二摻雜半導體層可因而包含一單晶半導體層。依照另一示例，第二阻障層可包含一氧化物層，且第二摻雜半導體層可包含一多晶半導體層。
在一示例性實施例中，第一及第二摻雜半導體層可具有相同的摻雜物導電類型。在另一示例性實施例中，第一及第二摻雜半導體層可具有相反的摻雜物導電類型。所述至少一DBRTD可包含串聯連接之一對DBRTD，以界定出一單穩態-雙穩態傳輸邏輯閘(monostable-bistable transition logic element, MOBILE)。舉例而言，該至少一非半導體單層可包含氧，且該些半導體單層可包含矽。
一種用於製作一半導體元件之方法面向，且其包括透過形成第一摻雜半導體層及在該第一摻雜半導體層上形成第一阻障層，以形成至少一雙阻障共振穿隧二極體(DBRTD)，並包含一超晶格。所述超晶格可包含複數個堆疊之層群組，每一層群組包含複數個堆疊之基底半導體單層，其界定出一基底半導體部份，以及被拘束在相鄰基底半導體部份之一晶格內之至少一非半導體單層。本方法可更包括在第一阻障層上形成一本質半導體層，在該本質半導體層上形成一第二阻障層，及第二超晶格層上形成一第二摻雜半導體層。
更詳細而言，所述第一及第二摻雜半導體層可包含矽，且其本質半導體層可包含鍺。依照一示例性實施例，所述第二阻障層亦可包含一超晶格。再者，該第二摻雜半導體層可包含一單晶半導體層。依照另一示例，第二阻障層可包含一氧化物層，且第二摻雜半導體層可包含一多晶半導體層。
舉例而言，第一及第二摻雜半導體層可具有相同的摻雜物導電類型。依照另一示例，第一及第二摻雜半導體層可具有相反的摻雜物導電類型。所述至少一非半導體單層可包含氧，且該些半導體單層，舉例而言，可包含矽。
茲參考說明書所附圖式詳細說明示例性實施例，圖式中所示者為示例性實施例。不過，實施例可以許多不同形式實施，且不應解釋為僅限於本說明書所提供之特定示例。相反的，這些實施例之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)則用以標示不同實施方式中之類似元件。
大體而言，本發明與當中設有改進效能的半導體超晶格之穿隧二極體元件有關，包括共振穿隧二極體(RTD)元件，其較佳效能之超晶格可提供所需電位阻障(potential barrier)及摻雜物侷限特性，且讓這些元件可在標準CMOS製程中整合。所述具改進效能的半導體超晶格，在本說明書及隨附附錄A中也被稱為「MST」層或「MST技術」。對於如何運用MST技術在半導體元件中提供阻擋摻雜物特性之背景資料，可見於授予Mears等人的美國專利第9,275,996號，其全部內容在此併入成為本說明書之一部分。
詳細而言，MST技術與進階半導體材料(例如下文所述之超晶格25)有關。申請人之理論認為(但申請人並不欲受此理論所束縛)，本說明書所述之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)
Figure 02_image001
及
Figure 02_image003
：
Figure 02_image005
為電子之定義，且：
Figure 02_image007
為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量 (tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所束縛)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子／電洞之導電性有效質量，便可用於分辨出較佳之材料。
申請人已辨識出可用於半導體元件之改進材料或結構。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及／或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。這些結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及／或鐵電特性，下文將進一步討論之。
參考圖1及圖2，該些材料或結構之形式為一超晶格25，超晶格25之結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。超晶格25包含複數個堆疊排列之層群組45a～45n，如圖1之示意剖視圖所示。
如圖所示，超晶格25之每一層群組45a～45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a ～46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖1中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係被拘束在相鄰之基底半導體部份之一晶格內。「被拘束在相鄰之基底半導體部份之一晶格內」一語，係指來自相對之基底半導體部分46a ～46n之至少一些半導體原子，透過該些相對基底半導體部分間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部分46a ～46n上面之非半導體材料之量而成為可能，這樣，可用之半導體鍵結位置便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論之。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時，新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位置。
在其他實施方式中，使用超過一個非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，能帶修改層50與相鄰之基底半導體部份46a～46n，可使超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為超晶格25垂直上下方多個層之間之摻雜物及／或材料擴散之阻擋。因此，這些特性可有利地允許超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進裝置行動性，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，超晶格25可進一步具有對諸如光電元件等尤其有利之實質上之直接能帶間隙。
如圖所示，超晶格25亦包含一上部層群組45n上面之一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部分46a～46n可包含由 IV 族半導體、 III-V 族半導體及 II-VI 族半導體所組成之群組中選定之一基底半導體。當然， IV 族半導體亦包含 IV-IV 族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層(monolayer)」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據(亦即非完全或低於100%之涵蓋範圍)之單層。舉例來說，參照圖2之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4／1重複結構。在圖示之實施例中，氧原子之可能位置僅有一半被佔據。
在其他實施方式及／或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上，熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所束縛)，就一超晶格而言，例如矽／氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。。圖1及圖2所示之矽／氧 4／1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4／1 矽／氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4／1 矽／氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
超晶格25之4／1 矽／氧實施方式之較低導電性有效質量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3／1／5／1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽／氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖4A～4C呈現應用密度功能理論(Density Functional Theory, DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖4A呈現主體矽 (以實線表示)及圖1之4／1 矽／氧超晶格25 (以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4／1 矽／氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然圖中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4／1 矽／氧結構之適當相反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4／1 矽／氧結構之導帶最小值係位於G點，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4／1 矽／氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖4B呈現主體矽(實線)及該4／1 矽／氧超晶格25 (虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖4C呈現主體矽(實線)及圖3之5／1／3／1 矽／氧超晶格25’ (虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5／1／3／1 矽／氧結構之對稱性，在 方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5／1／3／1 矽／氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5／1／3／1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
參考圖5A-6B說明包括上述超晶格技術(在本說明書中也稱為「MST」)之穿隧二極體結構及相關元件。作為背景說明，共振穿隧二極體的操作方式類似P-N 接面二極體(p-n junction diodes)，其中所述二極體會以順向偏壓(forward bias)傳導「導通(ON)」電流。然而，就P-N接面二極體而言，偏壓電流會單調地(monotonically)增加順向電流，而共振穿隧二極體(RTD)則會呈現負微分電阻(NDR)特性，其電流位準隨著偏壓增加而下降。負微分電阻特性會增加負載線(load line)上的操作點，因此對於不同電路應用別具吸引力。
一般而言，多數RTD元件採用III-V族材料，此類材料要整合到矽為主的CMOS平台非常困難。再者，歐姆接點的接觸區域通常需要高摻雜濃度(doping level)。舉例而言，摻雜濃度可為至少10x18 /立方公分，且較低接觸電阻(lower contact resistance)所需濃度可大於 1x1020 /立方公分。
另一方面，在緊鄰雙阻障及介於雙阻障間的三個區域，RTD通常採用相對低摻雜濃度，以防止雜質散射。所需摻雜濃度通常根據電子平均自由路徑相對於雙阻障與穿隧層厚度尺寸來確定。一般而言，摻雜濃度可設定為大約1x1016 /立方公分。
N型及P型MST雙阻障穿隧二極體(DBRTD)結構100、110 及其相關能帶圖 101、111 分別如圖5A、5B 及 6A、6B 所繪示。如圖所示，N型DBRTD 100 包含一層堆疊，其(從底部開始)包含一底部n+矽接觸層102、一第一超晶格阻障層103 (如上述超晶格層25、25’，其在圖式中標示為 MST)、一未摻雜(本質)矽層104、一第二超晶格阻障層105及一上部n+矽接觸層106。同樣地，P型DBRTD 110，如圖所示，包含一層堆疊，其(從底部開始)包含一底部p+矽接觸層112、一第一超晶格阻障層113、一未摻雜(本質)矽層114、一第二超晶格阻障層115及一上部p+矽接觸層116。
超晶格阻障層 103、105 及 113、115 可有利地讓電位阻障在矽導帶(CB)及價帶(VB)中形成，同時在形成上部接觸層106、116時維持矽磊晶生長。亦即，所述超晶格結構可有利地讓半導體(例如矽)鍵穿過介入的氧原子而傳布，不會破壞磊晶生長，讓單晶半導體接觸層可在第二超晶格阻障層105、115的頂部形成。
阻障高度(barrier height)可有利地使用上述不同結構與製造技術，針對給定RTD應用而調整。模擬非半導體(例如氧)單層直接具有15Å間隔之一4/1重複結構，對導帶及價帶的預測皆為大約 0.6 eV 。除此之外，該些MST阻障層產生的電位阻障強度，可根據，舉例而言，每一單層之氧濃度、氧單層之間距、所使用之氧單層數而調整，熟習本發明所屬技術領域者當可理解。
然而，超晶格薄膜之另一重要特性是，可有利地用於阻止摻雜物從高度摻雜接觸層102、106 及 112、116 擴散到未掺雜/本質層 104、114，如上文所詳細討論。亦即，對於RTD結構，所述超晶格材料能有利地藉由相當精確的製程控制，製作出所需的摻雜濃度分布(doping profile)，其在接點附近具有高濃度的摻雜，而在RTD區域中很少或沒有摻雜。再者，所述超晶格材料也為異質磊晶膜生長(hetero epitaxial film growth)提供應變緩衝(strain buffer)能力，以及為異質磊晶膜之晶格不匹配(lattice mismatch)提供應變緩衝效果。
另外參考圖7A-8B，其描繪N型及P型DBRTD結構 120、130 之其他示例，及其各自能帶圖121、131。相較於上述DBRTD結構 100、110，圖示之DBRTD結構 120、130 包含上部二氧化矽阻障層 125、135而非上部超晶格阻障層。更詳細而言，N型DBRTD 120如圖所示，包含(從其層堆疊底部開始)一底部n+矽接觸層122、一超晶格阻障層123、一未摻雜(本質)矽層124、所述二氧化矽阻障層125及一上部n+多晶矽接觸層126。同樣地，P型DBRTD130如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層132、一超晶格阻障層133、一未摻雜(本質)矽層134，一二氧化矽阻障層135及一上部p+多晶矽接觸層136。二氧化矽層 125、135可透過類似在MST單層沉積期間形成氧單層的方式而形成，但須較長曝露時間及/或較高劑量，以讓更多矽鍵結位置填充有氧原子而形成二氧化矽。在這些示例中，上部n+及p+矽接觸層126、136 為多晶矽，因其在二氧化矽上形成，此與上述可在超晶格層 105、115上磊晶生長而成的單晶矽層106、116相反。
參考圖9A-10B說明示例P型DBRTD結構 140、150，其分別類似於圖6A及8A所繪示P型結構110及 130，但以一鍺穿隧層144、154 取代之前實施例中之未掺雜(本質)矽層 114、134 。將鍺薄層整合到矽中，可有利地為適當應用允許價帶偏移(VB offset)。在一些實施例中，矽鍺(例如矽1-x 鍺x 層，其中x=0~1.0)也可用於層144、154。
P型DBRTD140如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層142、一第一超晶格阻障層143、一未摻雜(本質)鍺穿隧層144，一第二超晶格阻障層145及一上部p+矽接觸層146。在第二實施例中，P型DBRTD150如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層152、一超晶格阻障層153、一未摻雜(本質)鍺層154、一二氧化矽層155及一上部p+多晶矽接觸層156。這些相同結構也可以n+接觸層構成，熟習本發明所屬技術領域者當可理解。
參考圖11A-13B，其概要描繪共振帶間穿隧二極體(resonant inter-band tunneling diodes, RITDs) 160、170、180 之三示例及其各自能帶圖 161、171、181，其分別具有類似於圖5A、7A 及 9A所繪示之層結構，差別在於此處示例中，上部及下部接觸層為相反摻雜(oppositely-doped) (亦即以相反導電類型的摻雜物摻雜)。更詳細而言，第一示例之二極體 160如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層162、一第一超晶格阻障層163、一未摻雜(本質)矽層164，一第二超晶格阻障層165及一上部n+矽接觸層166。第二示例之二極體170如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層172、一超晶格阻障層173、一未摻雜(本質)矽層174，一二氧化矽阻障層175及一上部n+多晶矽接觸層176。第三示例如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層182、一第一超晶格阻障層183、一未摻雜(本質)鍺層184，一第二超晶格阻障層185及一上部n+矽接觸層186。
參考圖14-16，其描繪另外三示例之共振穿隧二極體190、210 及 230，其分別類似於圖5A、9A 及 10A 所繪示之三示例，但更包含額外的電子平均自由路徑控制層。更詳細而言，第一示例為一N型DBRTD，如圖所示，包含(從其層堆疊底部開始)一底部n+矽接觸層191、一第一超晶格阻障層192、一第一未摻雜矽層193、一第二超晶格層194、一第二未摻雜矽層195、一第三超晶格層196、一第三未摻雜矽層197、一第四超晶格層198及一上部n+矽接觸層199(請注意在不同實施例中，此結構也可設有p+接觸層)。超晶格層 194、196 作為電位阻障層，且成對之192/193 層及197/198 層分別界定出電子平均自由路徑控制層 200、201 。
第二示例為一P型DBRTD 210，如圖所示，包含(從其層堆疊底部開始)一底部p+矽接觸層211、一第一超晶格層212、一第一未摻雜矽層213、一第二超晶格層214、一未摻雜鍺(或矽鍺)層215、一第三超晶格層216、一第二未摻雜矽層217、一第四超晶格層218及一上部p+接觸層219(請注意在不同實施例中，此結構也可設有N型接觸層)。超晶格層 214、216 作為電位阻障層，且成對之212/213 層及217/218 層分別界定出電子平均自由路徑控制層 220、221 。
第三示例為一共振帶間穿隧二極體230，如圖所示，其包含(從其層堆疊底部開始)一底部 p+矽接觸層231、一第一超晶格層232、一第一未摻雜矽層233、一第二超晶格層234、一第二未摻雜矽層235、一第三超晶格層236、一第三未摻雜矽層237、一第四超晶格層238及一上部n+矽接觸層239(請注意在其他實施例中，所述底部及上部接觸層之導電性可為反向)。超晶格層 234、236 作為電位阻障層，且成對之232/233 層及237/238 層分別界定出電子平均自由路徑控制層 240、241 。
參考圖17，其繪示一種在CMOS FINFET 元件270中以一或多個如上所述之共振穿隧二極體結構272取代至少一部分之鎢插塞271之示例應用。應注意的是，共振穿隧二極體272也可用於平面半導體元件。
參考圖18，在另一示例性實施例中，一單穩態-雙穩態傳輸邏輯閘(MOBILE)元件如圖所示，包含如上文所述之一DBRTD 281及一第二二極體282(在一些實施例中，也可為上文所述之DBRTD) ，兩者在一時脈訊號(clock signal) CLOCK及接地間串聯耦合。除此之外，電晶體283之源極與汲極耦合至二極體282之第一及第二接點 ，且其閘極耦合至一輸入訊號 IN。一輸出訊號 OUT在二極體281、282耦合在一起之點提供。
圖19之流程圖290描繪一示例性 CMOS 製程流程，其可包括一超晶格RTD模組，以在CMOS元件中形成上述超晶格RTD結構。所述製程始於淺溝槽隔離(Shallow Trench Isolation, STI)模組291，接著是井模組292、閘極模組293、輕摻雜汲極(lightly doped drain, LDD)模組294、間隙壁(spacer)及源極/汲極模組295、矽化物模組296、接觸/M1模組297及後端製程(back end of line, BEOL)模組298。更詳細而言，在所繪示例中，DBRTD的形成在矽化物模組296中發生，因為MST共振穿隧二極體模組在氧化物化學氣相沉積(CVD)之後插入，其包括另一(選擇性)氧化物化學氣相沉積、化學機械研磨(CMP)、RTD接觸圖案化(contact patterning)及超晶格RTD磊晶生長，以製作所需RTD元件(其可以地毯式遍及整個晶圓(MST1)，或以選擇性CMP在晶圓選定的不同位置上(MST2))。矽化物模組296可更包含矽化物區塊(block)光罩圖案化，其包括微影、蝕刻及光阻去除，然後是矽化物金屬物理氣相沉積(PVD)，其包括預清洗(pre-clean)及濺鍍，接著是矽化物快速熱回火(RTA)處理，以及透過諸如濕式蝕刻等方式去除金屬。應注意的是，取決於所製作的半導體元件類型，在不同實施例中，某些步驟及模組可循不同順序實施之。
使用上述結構及製程方法可製作多種不同元件。可以製作的元件之一為穿隧式SRAM (TSRAM) 單元。使用上述技術製作出的靜態隨機存取記憶體記憶單元，尺寸小於一般 6T-SRAM單元(~150F2 )，且其功率消耗低於一般DRAM單元(4~8F2 )。對於多位元記憶體單元之應用性，可透過諸如增加RTD數目的方式而獲得。
可實施上述DBRTD之其他邏輯電路元件包括場效電晶體及雙極性接面電晶體。此種組構的可能益處之一包括高速運作，因為穿隧時間的尺度是在數微微秒(pico second)內。另一可能益處是相對低功率運作，因為狀態改變期間的臨界電流(transition current)可以谷電流(valley current)限制。舉例而言，在一些實施給定功能的情況下，可實現電路元件減少50%以上，且負微分電阻(Negative Differential. Resistance, NDR) 元件之電流電壓曲線(I-V curve)與其他元件之負載線(load line)相交(至少)兩次。
如上所述，本發明DBRTD之另一有利應用為MOBILE邏輯元件。RTD不僅使記憶體及邏輯電路更精實小巧，也添增功能性。再者，從系統層面來看，將DBRTD結構整合到標準的矽CMOS，可有助於改變未來的電路設計。舉例而言，可能促成以「神經元網路(neuron network)」邏輯取代傳統布林邏輯。再者，透過與傳統邏輯(例如管線化漣波進位加法器(pipelined ripple carry adder)的混合整合，也可產生立即的影響。
在得益於前文說明及其關聯圖式之教示下，熟習本發明所屬技術領域者將可想到許多變化及其他實施方式。因此，應理解的是，本發明並不限於本說明書所揭露之特定示例性實施例，所有修改及實施例均應落入所附之申請專利範圍內。
21‧‧‧底材25、25’‧‧‧超晶格45a～45n、45a’～45n’‧‧‧層群組46、46’‧‧‧基底半導體單層46a～46n、46a’～46n’‧‧‧基底半導體部份50、50’‧‧‧能帶修改層52、52’‧‧‧頂蓋層100、120、190‧‧‧N型雙阻障共振穿隧二極體101、111、121、131、141、151、161、171、181‧‧‧能帶圖102、122、191‧‧‧底部n+矽接觸層103、105、113、115、123、133、143、145、153、163、165、173、183、185、192、194、196、198、212、214、216、218、232、234、236、238‧‧‧超晶格阻障層104、114、124、134、164、174、193、195、197、233、235、237‧‧‧未摻雜矽層106、166、186、199、239‧‧‧上部n+矽接觸層110、130、140、150、210‧‧‧P型雙阻障共振穿隧二極體112、132、142、152、162、172、182、211、231‧‧‧底部p+矽接觸層116、146、219‧‧‧上部p+矽接觸層125、135、155、175‧‧‧二氧化矽阻障層126、176‧‧‧上部n+多晶矽接觸層136、156‧‧‧上部p+多晶矽接觸層144、154、184‧‧‧未摻雜鍺層160、170、180、230‧‧‧共振帶間穿隧二極體200、201、220、221、240、241‧‧‧電子平均自由路徑控制層270‧‧‧CMOS鰭式場效電晶體元件271‧‧‧鎢插塞272、281‧‧‧共振穿隧二極體280‧‧‧單穩態-雙穩態傳輸邏輯閘元件282‧‧‧二極體283‧‧‧電晶體
圖1為依照一示例性實施例之一半導體元件所用一超晶格之放大示意剖視圖。
圖2為圖1所示超晶格之一部分之透視示意原子圖。
圖3為依照一示例性實施例之一超晶格之另一實施方式之放大示意剖視圖。
圖4A為習知技術之主體矽及圖1～2所示之4／1 矽／氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖4B為習知技術之主體矽及圖1～2所示之4／1 矽／氧超晶格兩者從Z點計算所得能帶結構之圖。
圖4C為習知技術之主體矽及圖3所示之5／1／3／1 矽／氧超晶格兩者從G點與Z點計算所得能帶結構之圖。
圖5A為依照一示例性實施例之一N型雙阻障共振穿隧二極體(DBRTD)之示意剖視圖，其包含超晶格阻障層。
圖5B為圖5A之DBRTD之能帶圖。
圖6A為依照一示例性實施例之一P型DBRTD之示意剖視圖，其包含超晶格阻障層。
圖6B為圖6A之DBRTD之能帶圖。
圖7A為依照一示例性實施例之一N型DBRTD之示意剖視圖，其包括超晶格及二氧化矽阻障層。
圖7B為圖7A之DBRTD之能帶圖。
圖8A為依照一示例性實施例之一P型DBRTD之示意剖視圖，其包括超晶格及二氧化矽阻障層。
圖8B為圖8A之DBRTD之能帶圖。
圖9A為依照一示例性實施例之一P型DBRTD之示意剖視圖，其包括超晶格阻障層及一鍺本質層。
圖9B為圖9A之DBRTD之能帶圖。
圖10A為依照一示例性實施例之一P型DBRTD之示意剖視圖，其包括超晶格及二氧化矽阻障層，以及一鍺本質層。
圖10B為圖10A之DBRTD之能帶圖。
圖11A為依照一示例性實施例之一能帶間(inter-band)DBRTD之示意剖視圖，其包括超晶格阻障層及相反摻雜接觸層(oppositely-doped contact layers)。
圖11B為圖11A之DBRTD之能帶圖。
圖12A為依照一示例性實施例之一能帶間DBRTD之示意剖視圖，其包括超晶格及二氧化矽阻障層，以及相反摻雜接觸層。
圖12B為圖12A之DBRTD之能帶圖。
圖13A為依照一示例性實施例之一能帶間DBRTD之示意剖視圖，其包括超晶格阻障層，以及設有一鍺本質層之相反摻雜接觸層。
圖13B為圖13A之DBRTD之能帶圖。
圖14為依照一示例性實施例之一N型DBRTD之示意剖視圖，其包括超晶格阻障層及電子平均自由路徑控制層(electron mean free path control layer)。
圖15為依照一示例性實施例之一P型DBRTD之示意剖視圖，其包括超晶格阻障層、一鍺本質層及電子平均自由路徑控制層。
圖16為依照一示例性實施例之一能帶間DBRTD之示意剖視圖，其包括設有相反摻雜接觸層及電子平均自由路徑控制層之超晶格阻障層。
圖17為依照一示例性實施例之一鰭式場效電晶體(FINFET)之示意剖視圖，其包括一或多個DBRTD。
圖18為依照一示例性實施例之包括一DBRTD之單穩態-雙穩態傳輸邏輯閘(MOBILE)之示意電路圖。
圖19為依照一示例性實施例之用於製作包括一或多個DBRTD之半導體元件之製程流程圖。
100‧‧‧N型雙阻障共振穿隧二極體
102‧‧‧底部n+矽接觸層
103、105‧‧‧超晶格阻障層
104‧‧‧未摻雜矽層
106‧‧‧上部n+矽接觸層

Claims (20)

  1. 一半導體元件，其包含：至少一雙阻障共振穿隧二極體(DBRTD)，其包含：一第一摻雜半導體層，其包含矽；設置在該第一摻雜半導體層上且包含一超晶格之一第一阻障層；設置在該第一阻障層上之一本質半導體層，其包含矽及鍺當中至少一者；設置在該本質半導體層上之一第二阻障層；及設置在該第二阻障層上之一第二摻雜半導體層，其包含矽。
  2. 如申請專利範圍第1項之半導體元件，其中該第二阻障層亦包含一超晶格。
  3. 如申請專利範圍第1項之半導體元件，其中該第二摻雜半導體層包含一單晶半導體層。
  4. 如申請專利範圍第1項之半導體元件，其中該第二阻障層包含一氧化物層。
  5. 如申請專利範圍第1項之半導體元件，其中該第二摻雜半導體層包含一多晶半導體層。
  6. 如申請專利範圍第1項之半導體元件，其中該第一及第二摻雜半導體層具有相同的摻雜物導電類型。
  7. 如申請專利範圍第1項之半導體元件，其中該第一及第二摻雜半導體層具有相反的摻雜物導電類型。
  8. 如申請專利範圍第1項之半導體元件，其中該至少一雙阻障共振穿隧二極體包含串聯連接之一對雙阻障共振穿隧二極體，以界定出一單穩態-雙穩態傳輸邏輯閘(monostable-bistable transition logic element,MOBILE)。
  9. 一種用於製作一半導體元件之方法，該方法包括：透過以下方式形成至少一雙阻障共振穿隧二極體形成一第一摻雜半導體層使其包含矽，在該第一摻雜半導體層上形成一第一阻障層並使其包含一超晶格，在該第一阻障層上形成一本質半導體層使其包含鍺，在該本質半導體層上形成一第二阻障層，及在該第二阻障層上形成一第二摻雜半導體層使其包含矽。
  10. 如申請專利範圍第9項之方法，其中該第二阻障層亦包含一超晶格。
  11. 如申請專利範圍第9項之方法，其中該第二摻雜半導體層包含一單晶半導體層。
  12. 如申請專利範圍第9項之方法，其中該第二阻障層包含一氧化物層。
  13. 如申請專利範圍第9項之方法，其中該第二摻雜半導體層包含一多晶半導體層。
  14. 如申請專利範圍第9項之方法，其中該第一及第二摻雜半導體層具有相同的摻雜物導電類型。
  15. 如申請專利範圍第9項之方法，其中該第一及第二摻雜半導體層具有相反的摻雜物導電類型。
  16. 如申請專利範圍第9項之方法，其中形成該至少一雙阻障共振穿隧二極體包括形成串聯連接之一對雙阻障共振穿隧二極體，以界定出一單穩態-雙穩態傳輸邏輯閘。
  17. 一半導體元件，其包含：至少一雙阻障共振穿隧二極體(DBRTD)，其包含：一第一摻雜半導體層；設置在該第一摻雜半導體層上且包含一超晶格之一第一阻障層；設置在該第一阻障層上之一本質半導體層；設置在該本質半導體層上之一第二阻障層，其包含一氧化物層；及設置在該第二阻障層上之一第二摻雜半導體層，其包含一多晶半導體層。
  18. 如申請專利範圍第17項之半導體元件，其中該第一及第二摻雜半導體層具有相同的摻雜物導電類型。
  19. 如申請專利範圍第17項之半導體元件，其中該第一及第二摻雜半導體層具有相反的摻雜物導電類型。
  20. 如申請專利範圍第17項之半導體元件，其中該至少一雙阻障共振穿隧二極體包含串聯連接之一對雙阻障共振穿隧二極體，以界定出一單穩態-雙穩態傳輸邏輯閘(MOBILE)。
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