TWI710035B - 半導體裝置之製造方法及半導體裝置 - Google Patents
半導體裝置之製造方法及半導體裝置 Download PDFInfo
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- TWI710035B TWI710035B TW104127817A TW104127817A TWI710035B TW I710035 B TWI710035 B TW I710035B TW 104127817 A TW104127817 A TW 104127817A TW 104127817 A TW104127817 A TW 104127817A TW I710035 B TWI710035 B TW I710035B
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- semiconductor
- semiconductor wafer
- sealing
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- semiconductor device
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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JP2014175135 | 2014-08-29 | ||
JPJP2014-175135 | 2014-08-29 |
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TW201626470A TW201626470A (zh) | 2016-07-16 |
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JP (1) | JPWO2016031684A1 (ko) |
KR (1) | KR101968428B1 (ko) |
CN (1) | CN106796893B (ko) |
TW (1) | TWI710035B (ko) |
WO (1) | WO2016031684A1 (ko) |
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WO2017217307A1 (ja) * | 2016-06-16 | 2017-12-21 | 株式会社村田製作所 | 半導体部品、白色発光ダイオードデバイス、および半導体部品の製造方法 |
JP6777815B2 (ja) * | 2017-05-10 | 2020-10-28 | 三井化学株式会社 | 半導体装置の製造方法および半導体装置の中間体 |
KR102571926B1 (ko) * | 2017-05-22 | 2023-08-28 | 가부시끼가이샤 레조낙 | 반도체 장치의 제조 방법 및 익스팬드 테이프 |
JP6990577B2 (ja) * | 2017-12-22 | 2022-01-12 | 東レエンジニアリング株式会社 | 実装方法および実装装置 |
JP7093953B2 (ja) | 2019-02-27 | 2022-07-01 | 株式会社デンソー | 半導体装置とその製造方法 |
TWI795696B (zh) * | 2020-12-04 | 2023-03-11 | 吳聲欣 | 半導體元件封裝結構及其製造方法 |
CN113192851B (zh) * | 2021-04-29 | 2024-03-29 | 长沙新雷半导体科技有限公司 | 一种晶圆的封装方法 |
Citations (2)
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TW483138B (en) * | 2000-02-28 | 2002-04-11 | Nippon Electric Co | Semiconductor device and method for fabricating same |
JP2002134662A (ja) * | 2000-10-30 | 2002-05-10 | Matsushita Electric Ind Co Ltd | チップ型半導体装置及びその製造方法 |
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JPH09107046A (ja) | 1995-10-11 | 1997-04-22 | Hitachi Chem Co Ltd | 半導体パッケ−ジ |
JP2002141444A (ja) * | 2000-11-01 | 2002-05-17 | Sony Corp | 半導体装置およびその製造方法 |
US7169691B2 (en) * | 2004-01-29 | 2007-01-30 | Micron Technology, Inc. | Method of fabricating wafer-level packaging with sidewall passivation and related apparatus |
JP5534594B2 (ja) | 2010-03-30 | 2014-07-02 | リンテック株式会社 | シート貼付方法およびウエハ加工方法 |
JP2013189544A (ja) * | 2012-03-14 | 2013-09-26 | Unitika Ltd | 樹脂組成物およびそれを加熱硬化してなる熱硬化性エラストマー |
JP2013209503A (ja) * | 2012-03-30 | 2013-10-10 | Nippon Steel & Sumikin Chemical Co Ltd | エポキシ樹脂組成物、及びその硬化物 |
JP2013237780A (ja) * | 2012-05-15 | 2013-11-28 | Hitachi Chemical Co Ltd | フェノール化合物、その製造方法、樹脂組成物及び電子部品装置 |
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- 2015-08-20 WO PCT/JP2015/073438 patent/WO2016031684A1/ja active Application Filing
- 2015-08-20 CN CN201580046732.7A patent/CN106796893B/zh not_active Expired - Fee Related
- 2015-08-20 JP JP2016545476A patent/JPWO2016031684A1/ja active Pending
- 2015-08-20 KR KR1020177008463A patent/KR101968428B1/ko active IP Right Grant
- 2015-08-26 TW TW104127817A patent/TWI710035B/zh not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
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TW483138B (en) * | 2000-02-28 | 2002-04-11 | Nippon Electric Co | Semiconductor device and method for fabricating same |
JP2002134662A (ja) * | 2000-10-30 | 2002-05-10 | Matsushita Electric Ind Co Ltd | チップ型半導体装置及びその製造方法 |
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JPWO2016031684A1 (ja) | 2017-06-22 |
TW201626470A (zh) | 2016-07-16 |
CN106796893A (zh) | 2017-05-31 |
CN106796893B (zh) | 2019-09-20 |
WO2016031684A1 (ja) | 2016-03-03 |
KR20170048482A (ko) | 2017-05-08 |
KR101968428B1 (ko) | 2019-04-11 |
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