TWI710035B - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

The manufacturing method of the semiconductor device of the present invention includes the following steps: a preparation step, which prepares a semiconductor wafer with a circuit formed on the main surface; an attachment step, which attaches the semiconductor wafer to an adhesive layer; and a first dividing step, which Divide the semiconductor wafer attached to the adhesive layer along the dicing area to obtain a plurality of semiconductor wafers; the sealing step, which in the state where the main surfaces of the multiple semiconductor wafers are attached to the adhesive layer, will A semiconductor chip is sealed at one time, whereby a sealing material layer composed of a semiconductor sealing resin composition is formed on the gap between the side surfaces of the semiconductor chip and the back surface of the semiconductor chip; and the second dividing step, which is formed in the semiconductor by pairing The sealing material layer in the gap between the side surfaces of the wafer is divided to obtain a plurality of the above-mentioned semiconductor wafers with sealing material layers formed on the side surface and the back surface.

Description

Manufacturing method of semiconductor device and semiconductor device

The present invention relates to a manufacturing method of a semiconductor device and a semiconductor device.

In the conventional manufacturing process of semiconductor devices, individual semiconductor wafers are individually sealed with sealing resin. As such a technique, there is a technique described in Patent Document 1, for example. This document describes that after a semiconductor wafer is picked up by a collet and mounted on a substrate, the semiconductor wafer is individually sealed by a transfer molding method using an epoxy resin for semiconductor sealing (Patent Document 1).

Patent Document 2 describes a technique for singulating a wafer from a semiconductor wafer. Specifically, a groove is formed on the main surface of the semiconductor wafer by half-cutting. By polishing the back surface, the wafer made of semiconductor is singulated. The singulated chip is picked up with the bottom semiconductor exposed on the surface and then bonded.

Prior art literature

Patent literature

Patent Document 1: Japanese Patent Laid-Open No. 9-107046

Patent Document 2: Japanese Patent Application Publication No. 2011-210927

However, in the manufacturing process of the semiconductor package described in the above document, since each semiconductor wafer is individually sealed, there is room for improvement in terms of productivity.

In addition, the inventor has conducted research and found that when the wafer is picked up by the collet, chip breakage (fragment) occurs. That is, the technology described in the above-mentioned documents has room for improvement in reliability.

The inventors further studied and found that when picking up the semiconductor chip, by protecting the surface of the semiconductor chip, the chipping can be suppressed. Based on this insight, we have further studied and found that by sealing a plurality of semiconductor wafers at one time and dividing the adjacent wafers, a semiconductor wafer whose side and back sides (opposite to the circuit formation surface) are covered by the sealing material layer can be obtained. . Furthermore, it was found that the chipping during handling in the semiconductor wafer was suppressed, and the present invention was completed.

According to the present invention, there is provided a method for manufacturing a semiconductor device, which includes the following steps: a preparation step of preparing a semiconductor wafer with a circuit formed on a main surface; an attaching step of attaching the semiconductor wafer to an adhesive layer; A dividing step of dividing the semiconductor wafer attached to the adhesive layer along the cutting area to obtain a plurality of semiconductor chips; a sealing step of bonding the main surfaces of the plurality of semiconductor chips In the state of attaching to the adhesive layer, a plurality of the semiconductor wafers are sealed at one time, whereby the semiconductor wafers A sealing material layer composed of a semiconductor sealing resin composition is formed on the gap between the side surfaces and the back surface of the semiconductor wafer; and the second dividing step is performed by applying the sealing material formed in the gap between the side surfaces of the semiconductor wafer The layer is divided to obtain a plurality of the semiconductor wafers having the sealing material layer formed on the side surface and the back surface.

In addition, according to the present invention, there is provided a method of manufacturing a semiconductor device, which includes the steps of preparing a structure including an adhesive member and a plurality of semiconductor chips attached to the adhesive surface of the adhesive member, and a plurality of the semiconductor chips The circuit forming surface of the semiconductor chip is attached to the adhesive surface of the adhesive member at a predetermined distance from each other; the resin composition for sealing a semiconductor in a fluid state is brought into contact with the semiconductor wafer, and the The semiconductor sealing resin composition is filled at intervals, and the surface and side surfaces of the semiconductor wafer opposite to the circuit formation surface are covered and sealed with the semiconductor sealing resin composition; and the semiconductor sealing resin composition is cured.

In addition, according to the present invention, there is provided a semiconductor device including: a semiconductor wafer having a circuit formed on a main surface; bumps formed on the main surface; and a sealing material layer covering the side surface of the semiconductor wafer and the The main surface is the back of the opposite side.

According to the present invention, a semiconductor device with excellent reliability and productivity can be provided It provides a manufacturing method and provides a semiconductor device with improved reliability.

The above-mentioned objects, other objects, features, and advantages will be further clarified by the preferred embodiments described below and the accompanying drawings below.

FIG. 1 is a cross-sectional view showing an example of the semiconductor device of this embodiment.

FIG. 2 is a cross-sectional view showing an example of the semiconductor device of this embodiment.

3 is a cross-sectional view for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

4 is a cross-sectional view for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

5 is a cross-sectional view for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

Fig. 6 is a configuration example of an expansion device that can be used when the interval between adjacent semiconductor wafers is enlarged in the manufacturing method of this embodiment.

Fig. 7 is a configuration example of an expansion device that can be used when the interval between adjacent semiconductor wafers is enlarged in the manufacturing method of this embodiment.

FIG. 8 is a cross-sectional view showing an example of the semiconductor device of this embodiment.

FIG. 9 is a diagram for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

FIG. 10 is a diagram for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

FIG. 11 is a conceptual plan view showing a cutting area of a semiconductor wafer in the method of manufacturing a semiconductor device of this embodiment.

FIG. 12 is a diagram for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

FIG. 13 is a diagram for explaining an example of the method of manufacturing the semiconductor device of this embodiment.

Hereinafter, embodiments of the present invention will be described using the drawings. In addition, in all the drawings, the same components are denoted by the same symbols, and the description is appropriately omitted.

<First Embodiment>

The method of manufacturing the semiconductor device of this embodiment will be described.

The manufacturing method of the semiconductor device 8 of the present embodiment includes the following steps: prepare the structure 7 including the adhesive member 10 or 30 (adhesive layer) and a plurality of semiconductor chips 5 attached to the adhesive surface of the adhesive member 10 or 30 , The plurality of semiconductor chips 5 are arranged at a predetermined distance from each other, and the circuit forming surface of the plurality of semiconductor chips 5 is attached to the adhesive surface of the adhesive member 10 or 30; the resin composition 49 for semiconductor sealing in a fluid state is The semiconductor wafer 5 is in contact with each other, the semiconductor sealing resin composition 49 is filled in the space between adjacent semiconductor wafers 5, and the semiconductor sealing resin composition 49 covers the surface and side surfaces of the semiconductor wafer 5 opposite to the circuit formation surface. Sealing; and curing the resin composition 49 for semiconductor sealing.

In the method of manufacturing a semiconductor device of this embodiment, a semiconductor device 8 can be obtained which can cover the circuit forming surface of the semiconductor wafer 5 with the hardened body (sealing material layer 40) of the resin composition for semiconductor sealing ( The main surface 3) is the opposite side surface (rear surface 4) and the side surface 9 and is picked up with a collet while being protected. Thereby, it is possible to prevent the transfer device from directly contacting the semiconductor wafer 5 when picking up with a handling device such as a collet, or to relax the collet by the hardened body (sealant layer 40) of the resin composition for semiconductor sealing. The impact applied to the semiconductor wafer 5 when the conveyor is in contact. Therefore, it is possible to prevent damage (fragmentation) of the semiconductor wafer 5 due to impact applied when the semiconductor wafer 5 is picked up by a conveying device such as a collet. Therefore, a semiconductor device having a structure excellent in reliability can be realized.

Here, regarding the singulated semiconductor wafer described in Patent Document 2, the side surface or the back surface (the surface opposite to the surface on which the bumps are formed) is not protected, and the underlying semiconductor material is exposed. According to the research conducted by the inventors, it has been found that when picking up or transporting is performed in a state where the surface is exposed, there is a high possibility of chipping in the semiconductor wafer.

In contrast, in the manufacturing process of the present embodiment, the semiconductor wafer 5 can be handled in a state where the sealing material layer 40 is formed on the side surface 9 and the back surface 4 (the surface opposite to the main surface 3) of the semiconductor wafer 5. As a result, it is possible to suppress fragments generated during pick-up or transport. Therefore, according to the method of manufacturing a semiconductor device of this embodiment, a semiconductor device 8 with excellent reliability can be obtained compared with the previous manufacturing process.

In addition, according to the method of manufacturing the semiconductor device 8 of this embodiment, after singulation, a plurality of semiconductor wafers 5 can be resin-sealed at once. Therefore, the productivity of the semiconductor device 8 can be improved.

Therefore, in this embodiment, it is possible to realize a method of manufacturing a semiconductor device capable of achieving both reliability and productivity.

Hereinafter, each step of the manufacturing method of the semiconductor device will be described.

3 to 5 are step cross-sectional views for explaining an example of the manufacturing method of the semiconductor device 8 of this embodiment.

FIG. 3(a) is a diagram showing an example of the semiconductor wafer 1 of this embodiment. FIG. 3(b) is a diagram showing the semiconductor wafer 1 with the protective film 10 attached to the circuit formation surface. Figure 3(c) This is a diagram showing the semiconductor wafer 1 after polishing the surface on the opposite side of the circuit formation surface. FIG. 3(d) is a diagram showing the semiconductor wafer 1 with the dicing film 20 attached to the surface opposite to the circuit formation surface. 3(e) is a diagram showing the semiconductor wafer 1 before the singulation of the protective film 10 is peeled from the circuit formation surface.

FIG. 4(a) is a diagram for explaining the steps of obtaining the semiconductor wafer 5. Figure 4(b) is a diagram for explaining the steps of setting the interval. FIG. 4(c) is a diagram for explaining the step of covering the circuit forming surface with the transfer member 30. FIG. FIG. 4(d) is a diagram for explaining the step of peeling off the dicing film 20. FIG. 4(e) and (f) are diagrams for explaining the steps of sealing using the resin composition 49 for semiconductor sealing. FIG. 5(a) is a diagram showing the step of peeling the release film 50. FIG. FIG. 5(b) is a diagram showing a step of singulating the semiconductor device 8 into pieces. FIG. 5(c) is a diagram showing the step of peeling off the transfer member 30. FIG.

As shown in FIGS. 3 to 5, the manufacturing method of the semiconductor device of this embodiment is implemented by a semiconductor wafer-level process. That is, the manufacturing method of the semiconductor device of this embodiment may include the following steps: a preparation step, which prepares the semiconductor wafer 1 with a circuit formed on the main surface 3; and an attachment step, which attaches the semiconductor wafer 1 to the adhesive layer ( Protective film 10); The first dividing step, which divides the semiconductor wafer 1 attached to the adhesive layer (dicing film 20) along the dicing area to obtain a plurality of semiconductor wafers 5; the sealing step is In the state where the main surfaces 3 of the plurality of semiconductor wafers 5 are attached to the adhesive layer (transfer member 30), the plurality of semiconductor wafers 5 are sealed at one time, whereby the gap 12 between the side surfaces 9 of the semiconductor wafers 5 and the semiconductor A sealing material layer 40 composed of a semiconductor sealing resin composition 49 is formed on the back surface 4 of the wafer 5; and a second dividing step by dividing the sealing material layer 40 formed in the gap 12 of the side surface 9 of the semiconductor wafer 5 , And obtain a plurality of semiconductor wafers (semiconductor) with sealing material layer 40 formed on the side 9 and the back 4 Body device 8).

In this embodiment, the semiconductor wafer 1 can be, for example, a "semiconductor wafer with a single layer or multiple wiring layers formed on a silicon substrate". In the semiconductor wafer 1, the surface on the side where the wiring layer is formed is referred to as the circuit formation surface (principal surface 3) and will be described.

In this embodiment, as the above-mentioned adhesive layer, multiple layers of the same or different types of adhesive layers may also be used. For example, as an adhesive layer, the protective film 10, the dicing film 20, the transfer member 30, etc. can also be used for various operation purposes. The adhesive member (protective film 10 or transfer member 30) may be an adhesive tape alone, or a member with an adhesive layer formed on a supporting substrate. The protective film 10 can protect the semiconductor wafer 1 from impact and the like. The transfer member 30 can change the main surface 3 of the bonding layer to the back surface 4, or change the main surface 3 from the back surface 4, that is, to the opposite side, while maintaining the arrangement of the semiconductor wafer 5.

In addition, the details of the dicing film 20, the transfer member 30, the protective film 10, and the release film 50 used in each step of the manufacturing method of this embodiment are described below.

First, the following steps will be described. The semiconductor wafer 1 is singulated with the dicing film 20 attached to the side opposite to the circuit formation surface of the semiconductor wafer 1 to obtain the dicing film 20 attached. The state of multiple semiconductor chips 5 steps.

First, a semiconductor wafer 1 with a circuit formed on the main surface 3 is prepared. As shown in FIG. 3(a), a semiconductor wafer 1 in which a plurality of bumps (solder bumps 2) for external connection are formed over the entire circuit formation surface (main surface 3) is prepared. In this embodiment, the term “wafer” refers to a circular shape or a rectangular shape in a plan view. The wafer means a plate shape of a thin layer, and it is not particularly limited as long as it has an area of at least the extent that a plurality of wafers can be cut out.

Then, the semiconductor wafer 1 is attached to the adhesive layer (protective film 10). Figure 3 As shown in (b), in order to protect the circuit formation surface (main surface 3) of the prepared semiconductor wafer 1, a protective film 10 is attached to the circuit formation surface, and the entire surface of the circuit formation surface is covered with the protective film 10. In this way, it is possible to prevent damage to electronic components mounted on the circuit formation surface due to impact applied to the circuit formation surface when polishing the surface of the semiconductor wafer 1 on the opposite side to the circuit formation surface.

Then, as shown in FIG. 3(c), the surface (rear surface 4) of the semiconductor wafer 1 on which the protective film 10 is attached is removed from the circuit formation surface (main surface 3). Thereby, the film pressure of the semiconductor wafer 1 is reduced. For example, the back surface 4 of the semiconductor wafer 1 can be polished by chemical mechanical polishing (CMP) or the like. Specifically, the semiconductor wafer 1 with the protective film 10 attached thereto is fixed to a polishing device, and the surface opposite to the circuit formation surface is polished so that the thickness of the semiconductor wafer 1 becomes a predetermined thickness.

In this embodiment, the upper limit of the film thickness of the semiconductor wafer 1 after the step of reducing the film thickness can be set to, for example, 300 μm or less, or 200 μm or less. In this way, the obtained semiconductor device can be thinned. On the other hand, the lower limit of the film thickness is not particularly limited. For example, it may be 100 μm or more, or may be 150 μm or more. Thereby, the mechanical strength of the semiconductor wafer 1 or the semiconductor wafer 5 can be sufficiently obtained.

In recent years, there has been an increasing demand for miniaturization and weight reduction of electronic equipment equipped with semiconductor devices. In order to meet this requirement, the thinning of semiconductor wafers has been carried out. In the process of thinning semiconductor wafers in recent years, the above-mentioned problem of damage to semiconductor wafers due to the impact applied when picking up with collets and other conveying devices has become more obvious.

However, according to the manufacturing process of this embodiment, even when the thinned semiconductor wafer 1 is used as described above, it is possible to sufficiently suppress the use of a collet or other conveying device for picking up. The applied impact causes damage to the semiconductor chip. The reason for this is that, as described above, the semiconductor wafer 5 can be handled in a state where the sealing material layer 40 is formed on the side surface 9 and the back surface 4 (the surface opposite to the main surface 3) of the semiconductor wafer 5.

In addition, in the manufacturing method of this embodiment, the surface (rear surface 4) of the semiconductor wafer 1 opposite to the circuit formation surface (principal surface 3) is polished with the protective film 10 attached as described above. Therefore, it is possible to effectively prevent damage to the electronic components mounted on the circuit forming surface of the semiconductor wafer 1 due to the stress generated during polishing.

Then, as shown in FIG. 3(d), the dicing film 20 is attached to the circuit forming surface (principal surface 3) of the semiconductor wafer 1 obtained by polishing with the protective film 10 attached to the circuit forming surface. ) Is the opposite side (back 4).

Then, as shown in FIG. 3(e), the protective film 10 is peeled from the semiconductor wafer 1. Furthermore, the main surface 3 of the semiconductor wafer 1 is exposed. At this time, the protective film 10 is preferably peeled from the semiconductor wafer 1 after reducing the adhesion between the protective film 10 and the semiconductor wafer 1. Specifically, the following method can be cited: by performing, for example, ultraviolet irradiation or heat treatment on the bonding portion of the protective film 10 and the semiconductor wafer 1, the adhesion layer of the protective film 10 forming the bonding portion is deteriorated, thereby reducing the adhesion .

Next, the dividing step (first dividing step) of the semiconductor wafer will be described. In the first dividing step of this embodiment, the semiconductor wafer 5 in the state of being attached to the adhesive layer (dicing film 20) is divided along the dicing area to obtain a plurality of semiconductor wafers 5.

FIG. 11 is a conceptual plan view showing the cutting area of the semiconductor wafer 1 in a plan view. Although the top view conceptual diagram is different from the actual manufacturing process, it can be used to understand the cutting area. The semiconductor wafer 1 of FIG. 11 has a circular shape. Regarding the cutting area, the first cutting line 13 is located at The direction orthogonal to the second cutting line 14. Cutting can be performed along these cutting lines. In addition, the area divided by the first cutting line 13 and the second cutting line 14 becomes the semiconductor wafer area 15 of the semiconductor wafer. By reducing the width of the cutting area, the effective number of chips can be increased. L1 in Figure 11 refers to the cutting width.

Specifically, the semiconductor wafer 1 in a state where the dicing film 20 is attached to the surface (rear surface 4) opposite to the circuit formation surface shown in FIG. 3(e) is singulated to produce FIG. 4(a) A plurality of semiconductor chips 5 in a state where the dicing film 20 is attached is shown. Dicing blades, lasers, etc. can be used for singulation (dividing) of the semiconductor wafer 1.

Regarding the semiconductor wafer 5 shown in FIG. 4( a ), the adjacent semiconductor wafers 5 are separated from each other and arranged on the dicing film 20. A gap 11 is formed between the side surfaces 9 of the semiconductor wafer 5. In a cross-sectional view, the horizontal width of the gap 11 corresponds to the cutting width L1.

In addition, when the semiconductor wafer 1 is singulated, it is necessary that the dicing film 20 is not cut and the obtained semiconductor wafers 5 must be kept attached. The dicing film 20 can also form a cut along the dicing area from the bonding surface with the semiconductor wafer 5 toward the inside. The cut does not penetrate the dicing film 20 from the upper surface to the lower surface. For example, it may be 1/2 depth of the film thickness or 1/3 depth. With this cut, the dicing film 20 can be smoothly expanded in the expansion step between the next semiconductor wafers 5. Thereby, the gap of the semiconductor wafer 5 can be enlarged more evenly.

Next, the expansion step of expanding the gap between the side surfaces of the semiconductor wafer will be described.

In this embodiment, after the semiconductor wafer 1 is divided into a plurality of semiconductor wafers 5, a step of expanding the distance between adjacent semiconductor wafers 5 may be additionally performed.

Specifically, as shown in FIG. 4(b), the dicing film 20 is applied to the semiconductor wafer 5 The in-plane direction expands to expand the interval between adjacent semiconductor chips 5 to a predetermined interval. Thereby, in a cross-sectional view, the width (expansion width L2) of the gap 12 after the expansion step can become larger than the width (L1) of the gap 11 before the expansion step.

For example, the interval between adjacent semiconductor chips 5 is preferably equal. That is, regarding the interval between the adjacent semiconductor wafers 5 in the rectangular semiconductor wafer 5, the direction parallel to one side of the semiconductor wafer 5 is set as the first direction, and the direction orthogonal to the first direction is set as the second direction. In the direction, it may expand at equal intervals only in the first direction, or may expand at equal intervals only in the second direction. Preferably, it expands at equal intervals in the first direction and the second direction. Therefore, when expanding the interval between the adjacent semiconductor wafers 5, it is preferable to expand the interval between the adjacent semiconductor wafers 5 isotropically in the in-plane direction of the dicing film 20.

Here, as described above, the manufacturing method of this embodiment expands the dicing film 20 in the in-plane direction of the circuit formation surface of the semiconductor wafer 5. Therefore, the dicing film 20 preferably has a structure excellent in stretchability.

In the above expansion step, the cutting film 20 can be performed in a heated state. This makes it easy to stretch the dicing film 20. The heating temperature is not particularly limited, but it is preferable that the temperature distribution of the entire dicing film 20 is less uneven.

In the first division step, the expansion step may be performed after the semiconductor wafer 1 is divided and the cut is formed in the dicing film 20 (adhesive layer). Since the dicing film 20 is easily expanded by the cut, it is possible to reduce unevenness in the width (expansion width L2) of the gap 12 after expanding the width of the gap 11 between the semiconductor wafers 5 (cutting width L1). Here, the expansion width L2 is greater than the cutting width L1. The upper limit of the expansion width L2 is not particularly limited. For example, it is preferably greater than the total width of the cutting width and the film thickness of the sealing material layer 40 on the side surface 9.

As above, the above-mentioned first dividing step in this embodiment may include the following steps: by dividing the semiconductor wafer 1 in a state where the back side 4 of the semiconductor wafer 1 is attached to the front bonding layer, a plurality of semiconductor wafers are obtained 5; and the expansion step, which expands the interval between adjacent semiconductor chips 5 (gap 11). Thereby, the sealing step can be performed in a state where the interval between the semiconductor wafers 5 is enlarged.

When expanding the interval between the adjacent semiconductor wafers 5 to a predetermined interval in this embodiment, the dicing film 20 may be expanded using a known dicing device.

Here, when expanding the interval between adjacent semiconductor chips 5, for example, the following expansion device may also be used.

6 and 7 are examples of the configuration of an expansion device that can be used when the interval between adjacent semiconductor chips 5 is enlarged. FIG. 6 is a diagram showing a state before the interval between adjacent semiconductor wafers 5 is enlarged. Fig. 6(a) is a side sectional view, and Fig. 6(b) is a top view. Fig. 7 is a diagram showing a state in which the interval between adjacent semiconductor wafers 5 is enlarged, Fig. 7(a) is a side cross-sectional view, and Fig. 7(b) is a plan view.

The device of FIGS. 6 and 7 includes: a ring-shaped frame 100 that clamps around the dicing film 20 attached to a plurality of semiconductor wafers 5 obtained by singulation; an expansion stage 140 that is arranged inside the frame 100 Below the cutting film 20, the cutting film 20 is expanded by moving upward; the heating part 130 is arranged on the expansion table 140 and heats the expansion table 140; and the expansion table 140 is divided into its central part 110 It is formed from the peripheral portion 120, and the heating portion 130 is provided on a surface of the central portion 110 of the expansion table 140 that is different from the contact surface of the dicing film 20.

In addition, the area on the expansion table 140 where the plurality of semiconductor wafers 5 with the dicing film 20 attached is preferably uniform in temperature. In this way, it can be within the surface of the cutting film 90 To uniformly control the expandability of the dicing film 20.

In addition, the apparatus of FIGS. 6 and 7 can improve the expandability of the dicing film 20 by heating the expansion table 140 by the heating unit 130.

In this way, the apparatus of FIGS. 6 and 7 can move the expansion table 140 upward while heating the central portion 110 and the peripheral portion 120 of the expansion table 140. Thereby, the expandability in the in-plane direction of the dicing film 20 can be uniformly improved, and the expansion table 140 can be moved upward. Therefore, as shown in FIG. 7, the dicing film 20 can be expanded uniformly so that the space|interval between the adjacent semiconductor wafers 5 may become equal intervals.

Next, the one-time sealing step of the semiconductor wafer will be described.

In the first embodiment, the dividing step and the expanding step are performed in a state where the dicing film 20 is attached to the back surface 4 of the semiconductor wafer 1. In the following one-time sealing step, in order to perform the step of also sealing the back surface of the semiconductor wafer 5, it is preferable to expose the back surface 4 in advance. These series of operations are called transfer steps. In addition, when the dividing step or the like is performed in a state where the back surface 4 of the semiconductor wafer 1 is exposed, the above-mentioned transfer step is not necessary, and the manufacturing process can be simplified.

First, the above-mentioned transfer step will be described.

In this embodiment, by the transfer step, the bonding surface of the semiconductor wafer 5 can be changed to the opposite side while maintaining the arrangement state of the semiconductor wafer 5. Specifically, as shown in FIG. 4(c), with the dicing film 20 attached to the back surface 4, the transfer member is attached so as to span the entire circuit formation surface (main surface 3) of the plurality of semiconductor wafers 5 30. At this time, the transfer member 30 can be attached so as to cover the entire surface of the solder bumps 2 and the entire circuit forming surface of the semiconductor chip 5, or it can be attached in a way that the transfer member 30 does not contact the circuit forming surface of the semiconductor chip 5. To It is attached by covering only a part of the surface of the solder bump 2 (refer to Fig. 9(a)). In the manufacturing method of the present embodiment, by controlling the degree of attachment of the transfer member 30 (the embedding depth of the solder bump 2), it is possible to adjust the resin sealing in the step of sealing with the following semiconductor sealing resin composition 49的区。 The area.

Then, as shown in FIG. 4(d), the dicing film 20 is peeled from the semiconductor wafer 5. In this manner, the transfer member 30 is attached with the dicing film 20 attached, and then the dicing film 20 is peeled off, whereby the transfer member 30 can be attached without changing the interval between the gaps formed between the semiconductor wafers 5 Attached to the semiconductor wafer 5. In addition, the dicing film 20 is preferably peeled off from the semiconductor wafer 5 after reducing the adhesion between the dicing film 20 and the semiconductor wafer 5. Specifically, a method can be exemplified in which, for example, ultraviolet irradiation or heat treatment is performed on the bonding portion of the dicing film 20 and the semiconductor wafer 5 to deteriorate the adhesive layer of the dicing film 20 forming the bonding portion, thereby reducing the adhesion.

In addition, the transfer member 30 is not particularly limited. For example, it is preferably configured to have both heat resistance and fixation to the extent that it can withstand the heat applied to harden the resin composition 49 for semiconductor sealing described below. The adhesiveness of the semiconductor chip 5 on the transfer member 30 is not detached. The transfer member 30 may be an adhesive tape alone, or may be a member that attaches an adhesive tape to a plate-shaped member formed of metal or plastic to impart rigidity. In addition, in the present embodiment, for example, a transfer member for attaching an adhesive tape to a metal plate-shaped member made of 42 alloy is used.

Through the steps so far, the structure 7 shown in FIG. 4(d) is obtained. The structure 7 has a structure in which an adhesive member (transfer member 30) and a plurality of semiconductor wafers 5 attached to the adhesive surface of the adhesive member (transfer member 30) are provided with a predetermined distance from each other And the configuration, and the adhesive surface of the adhesive member (transfer member 30) attached a plurality of semiconductors The circuit forming surface of the bulk wafer 5 (main surface 3). That is, as the step of preparing the structure 7 of this embodiment, the step may include the step of attaching the dicing film 20 to the surface (rear surface 4) of the semiconductor wafer 1 opposite to the circuit formation surface. The wafer 1 is singulated to obtain a plurality of semiconductor chips 5 attached to the dicing film 20; the area of the dicing film 20 where the plurality of semiconductor chips 5 are attached is expanded in the direction of the film plane, so that the adjacent semiconductors The interval (gap 11) between the chips 5 is expanded to a predetermined interval; the bonding member is attached so that the circuit forming surface (main surface 3) of the plurality of semiconductor chips 5 is in contact with the bonding surface of the bonding member (transfer member 30); and In the state where the plurality of semiconductor chips 5 are attached to the adhesive surface of the adhesive member, the dicing film 20 is peeled off from the semiconductor chip 5.

Then, the plurality of semiconductor wafers 5 are sealed at one time in a state where the principal surfaces 3 of the plurality of semiconductor wafers 5 are attached to the adhesive layer (transfer member 30). Specifically, as shown in FIG. 4(e), a resin composition 49 for semiconductor sealing in a liquid state is prepared on a supporting base material. For example, the resin composition 49 for semiconductor sealing which is in a fluid state by melting is arrange|positioned on the release film 50 (support base material). That is, the resin composition 49 for semiconductor sealing in a fluid state on the release film 50 and the main surface 3 are arranged facing the back surface 4 of the plurality of semiconductor wafers 5 of the transfer member 30.

Then, as shown in FIG. 4(f), the resin composition 49 for semiconductor sealing in a fluid state is crimped to the surface (rear surface 4) of the plurality of semiconductor wafers 5 opposite to the circuit formation surface. Then, the resin composition 49 for semiconductor sealing is cured by heat treatment, whereby the sealing material layer 40 can be formed. Thereby, the sealing material layer 40 can be filled in the space (gap 12) between the adjacent semiconductor wafers 5. Furthermore, the sealing material layer 40 can be used to seal so as to cover the surface (rear surface 4) and the side surface 9 of the semiconductor wafer 5 opposite to the circuit formation surface. For example, you can also use the secret The sealing material layer 40 fills the space formed between the adjacent semiconductor chips 5 and the whole or part of the solder bumps 2 is exposed to seal the top and side surfaces of the semiconductor chip 5 with the sealing material layer 40. In addition, the sealing material layer 40 may be formed on the outer side surface of the side surface 9 of the semiconductor wafer 5 located on the outer periphery of the plurality of semiconductor wafers 5.

In this embodiment, when the produced semiconductor wafer 5 is picked up by the collet, the hardened body (sealing material layer 40) of the resin composition for sealing a semiconductor body can be used to protect the part sucked by the collet. With this, it is possible to pick up the obtained semiconductor by a conveying device such as a collet while protecting the surface and side surface of the semiconductor wafer 5 opposite to the circuit formation surface with the cured body of the resin composition 49 for semiconductor sealing. Wafer 5. Therefore, according to the manufacturing method of this embodiment, it is possible to prevent in advance the possibility of damage to the semiconductor wafer 5 due to impact applied when the semiconductor wafer 5 is picked up by a conveying device such as a collet.

Here, the so-called resin composition 49 for semiconductor sealing in a fluid state may be a thermosetting resin composition in a molten state, a liquid resin composition, and a resin formed into a film or sheet. A resin composition whose composition is in a softened state. As a method of arranging the resin composition 49 for semiconductor sealing, a film made of a resin composition for semiconductor sealing may be laminated and arranged, or a paste made of a resin composition for semiconductor sealing may be arranged by pouring.

Here, regarding the step of sealing the semiconductor wafer, a case where a solid particulate resin composition is used as the resin composition for semiconductor sealing will be described in detail as an example.

The method of sealing the semiconductor wafer 5 with the resin composition 49 for semiconductor sealing is not particularly limited, and examples thereof include transfer molding, compression molding, injection molding, and lamination. Preferably, the fixed semiconductor wafer 5 is not easily produced Compression forming method with position offset. In addition, When the semiconductor wafer 5 is sealed by compression molding, a powdered resin composition may be used for resin sealing. In addition, the details of the resin composition 49 for semiconductor sealing are described below.

Specifically, a resin material supply container containing the pelletized resin composition is provided between the upper mold and the lower mold of the compression molding mold. Then, the semiconductor wafer 5 to which the adhesive layer (transfer member 30) is attached is fixed to one of the upper mold and the lower mold of the compression molding mold by fixing means such as clamping and suction. Hereinafter, a case where the semiconductor wafer 5 is fixed to the upper mold of the compression molding die with the surface opposite to the circuit formation surface and the resin material supply container facing the semiconductor wafer 5 will be described as an example.

Then, under reduced pressure, while reducing the distance between the upper mold and the lower mold of the mold, a resin material supply mechanism such as a baffle that constitutes the bottom surface of the resin material supply container supplies the weighed granular resin composition to the lower mold. With lower mold cavity. In the cavity of the mold, the release film 50 must be allowed to stand still in advance. Thereby, the pelletized resin composition is heated to a predetermined temperature in the lower mold cavity, and as a result, the semiconductor sealing resin composition 49 in a molten state on the release film 50 can be prepared. Then, by combining the upper mold and the lower mold of the mold, the semiconductor wafer 5 fixed to the upper mold is pressed against the semiconductor sealing resin composition 49 in a molten state. In this way, the gap formed between adjacent semiconductor wafers 5 can be filled with the resin composition 49 for semiconductor sealing in a molten state, and the top surface and side surfaces of the semiconductor wafer 5 can be covered with the resin composition 49 for semiconductor sealing. After that, the resin composition 49 for semiconductor sealing is cured while maintaining the state where the upper mold and the lower mold are joined.

Here, in the case of compression molding, it is preferable to perform resin sealing while reducing the pressure in the mold, and more preferably under vacuum conditions. So, for the adjacent The space between the semiconductor wafers 5 can be filled with the resin composition 49 for semiconductor sealing without leaving an unfilled portion.

The molding temperature during compression molding is not particularly limited, but is preferably 50 to 200°C, particularly preferably 80 to 180°C. In addition, the molding pressure is not particularly limited, but is preferably 0.5 to 12 MPa, particularly preferably 1 to 10 MPa. Furthermore, the molding time is preferably 30 seconds to 15 minutes, particularly preferably 1 to 10 minutes. By setting the molding temperature, pressure, and time in the above-mentioned ranges, it is possible to prevent the position of the semiconductor wafer 5 and the part where the semiconductor sealing resin composition 49 in an unfilled molten state is generated from shifting.

Then, by dividing the sealing material layer 40 formed in the gap 12 of the side surface 9 of the semiconductor wafer 5 (the second dividing step), a plurality of semiconductor wafers 5 having the sealing material layer 40 formed on the side surface 9 and the back surface 4 can be obtained .

Specifically, as shown in FIG. 5(a), first, the release film 50 arranged on the back surface (surface 41) of the sealing material layer 40 is peeled off.

Then, as shown in FIG. 5(b), the sealing material layer 40 located in the gap 12 of the semiconductor wafer 5 is divided. Set the division width of the second division step to L3. By adjusting the second division width L3, the film thickness of the sealing material layer 40 remaining on the side surface 9 can be controlled.

Specifically, for example, in a state where the transfer member 30 is attached to the semiconductor wafer 5, the cured body (sealing material layer 40) of the semiconductor sealing resin composition 49 filled in the space 12 is cut, and a single piece It is transformed into a plurality of semiconductor wafers 5 sealed by the sealing material layer 40. At this time, the transfer member 30 may be cut together with the sealing material layer 40, or it may be kept in a state of being attached across a plurality of semiconductor wafers 5 without being cut. From the viewpoint of improving the productivity of the semiconductor device 8, When the semiconductor wafer 5 is singulated, it is preferred that the transfer member 30 is not cut and the semiconductor wafer Sheet 5 and attached state. In addition, dicing blades, lasers, etc. can be used for the singulation of the aforementioned semiconductor wafer 5.

Then, as shown in FIG. 5( c ), the transfer member 30 is peeled from the semiconductor device 8. In this way, the semiconductor device 8 of this embodiment can be manufactured. In addition, the transfer member 30 is preferably peeled off from the semiconductor wafer 5 after reducing the adhesion between the transfer member 30 and the semiconductor device 8. Specifically, the following method can be cited: by performing ultraviolet irradiation or heat treatment on the bonding portion of the transfer member 30 and the semiconductor wafer 5 to degrade the adhesion layer of the transfer member 30 where the bonding portion is formed, thereby reducing Tightness.

In addition, the obtained semiconductor device 8 can also be mounted on the substrate as needed. In addition, when mounting the manufactured semiconductor device on the substrate, a known device such as a flip chip mounter or die bonder can be used.

Based on the above, the semiconductor device 8 can be obtained by the method of manufacturing a semiconductor device of this embodiment.

According to the manufacturing method of this embodiment, it is possible to obtain a semiconductor wafer 5 in which the surface of the semiconductor wafer 5 opposite to the circuit formation surface can be covered with the hardened body (sealing material layer 40) of the resin composition for semiconductor sealing and When the side is protected, it is picked up by a conveyor such as a collet. Thereby, it is possible to prevent the transfer device such as a collet from directly contacting the semiconductor wafer 5, and the hardened body (sealing material layer 40) of the resin composition for semiconductor sealing can alleviate the application of the semiconductor wafer 5 when picking up by the transfer device such as the collet. The impact. Therefore, according to the manufacturing method of the present embodiment, it is possible to prevent in advance the possibility of damage to the semiconductor wafer 5 due to impact applied when picking up by a conveying device such as a collet. That is, according to the manufacturing method of this embodiment, it is possible to alleviate the problems caused by the use of a conveying device such as a collet to pick The impact of the impact exerted by the semiconductor chip 5. Therefore, according to the manufacturing method of the present embodiment, it is possible to manufacture the semiconductor device 8 with excellent reliability compared with the previous manufacturing method. In addition, according to the manufacturing method of the present embodiment, it is possible to resin-encapsulate the obtained plurality of semiconductor wafers 5 at one time without arranging them on the substrate after singulation. Therefore, compared with the previous manufacturing method, the production efficiency can be dramatically improved. In addition, when the semiconductor device 8 obtained by the manufacturing method of this embodiment is mounted on a substrate, the sealing material layer 40 and the substrate have a structure separated from each other, so it is also possible to suppress adhesion between the sealing material layer 40 and the substrate. Poor, can further improve reliability.

In this embodiment, the protective film 10 is used to protect the circuit formation surface of the semiconductor wafer 1 when the surface of the semiconductor wafer 1 opposite to the circuit formation surface is polished. In the third embodiment, As described below, it also has the function of the dicing film 20 used when the semiconductor wafer 1 is singulated in this embodiment, and covers the surface and the side surface of the semiconductor wafer 5 opposite to the circuit formation surface in this embodiment. The function of the transfer member 30 used for sealing. Therefore, from the viewpoint of production efficiency, the manufacturing method of the following third embodiment is more excellent. According to the manufacturing method of this embodiment, since different adhesive members 10 and 30 are used in each manufacturing step, it is also necessary to maintain the The strength of the adhesive members 10 and 30 can be used separately. That is, according to the manufacturing method of this embodiment, it is possible to accurately manufacture a semiconductor device with excellent reliability.

The semiconductor device of this embodiment will be described.

1 and 2 are cross-sectional views showing an example of the semiconductor device 8 of this embodiment.

As shown in FIGS. 1 and 2, the semiconductor device 8 of this embodiment includes: a semiconductor chip 5; solder bumps 2 provided on the lower surface (principal surface 3) of the semiconductor chip 5; and a sealing material The layer 40 covers at least a part of the top surface and the side surface of the semiconductor chip 5; and the whole or part of the solder bump 2 is exposed.

Specifically, the semiconductor device 8 shown in FIG. 1 includes: a semiconductor wafer 5 on which a circuit is formed on the main surface 3; a sealing material layer 40 that covers the entire side surface 9 and the entire back surface 4 of the semiconductor wafer 5; A bump (solder bump 2), which forms a sealing material layer 40 around the semiconductor chip 5 in a plan view, and is formed only on the main surface 3 area of the semiconductor chip 5.

The semiconductor device 8 of the present embodiment includes a semiconductor wafer 5 in which at least a part of the top surface (rear surface 4) and the side surface 9 of the semiconductor wafer 5 is covered with a sealing material layer 40. In this way, when the semiconductor device 8 is manufactured, even if the semiconductor wafer 5 is picked up by the collet, the semiconductor wafer 5 can be prevented from being damaged in advance. Therefore, the semiconductor device 8 obtained by the manufacturing process of this embodiment is more reliable than the previous semiconductor device.

As shown in FIG. 1, the entire lower surface (main surface 3) of the semiconductor wafer 5 is exposed. In other words, the entire main surface 3 of the semiconductor wafer 5 is not covered by the sealing material layer 40. That is, the main surface 3 of the semiconductor wafer 5 may be formed on the same surface as the surface 45 of the sealing material layer 40 on the opposite side to the top surface (surface 41). Here, the term "same surface" refers to a surface that can tolerate the surface roughness of the transfer member 30 and other inevitable micro-concavities and convexities in the process. That is, in the semiconductor device 8 of FIG. 1, the solder bump 2 as a whole has a structure that is not covered by the sealing material layer 40 and is exposed.

On the other hand, in the semiconductor device 8 of FIG. 2, a part of the lower surface (main surface 3) of the semiconductor wafer 5 and a part of the solder bump 2 are covered by the sealing material layer 40. In other words, in the main surface 3 of the semiconductor wafer 5, the area inside the area where the solder bumps 2 are arranged in the outer peripheral portion is not covered by the sealing material layer 40 and is exposed. The solder bump 2 has a structure in which a part of the solder bump 2 is covered by the sealing material layer 40 from the main surface 3 side of the semiconductor wafer 5 to the opposite side, but the remaining front end is exposed.

The semiconductor device 8 of FIGS. 1 and 2 can realize a structure in which the sealing material layer 40 and the substrate are not in contact with the substrate when they are mounted on the substrate. That is, in this embodiment, the sealing material layer 40 may have a structure that is not sealed to the mounting substrate on which the semiconductor chip 5 is mounted.

According to the semiconductor device 8 of this embodiment, when the semiconductor device 8 is mounted on a substrate, the structure is different from that of the conventional semiconductor device in which the substrate is bonded to the sealing material. That is, a structure in which the sealing material layer 40 and the mounting substrate are not in contact with each other can be realized. As a result, it is possible to provide the semiconductor device 8 which is smaller than the conventional semiconductor device. In addition, since the semiconductor device 8 has a structure different from the structure of the previous semiconductor device in which the substrate is bonded to the sealing material, it can be directly mounted on the motherboard without passing through an interposer. Furthermore, since the semiconductor device 8 can realize a structure in which the sealing material layer 40 and the substrate are not in contact with each other and the two are separated, the problem of poor adhesion between the substrate and the sealing material in the conventional semiconductor device can be solved. Therefore, compared with the conventional semiconductor device, a semiconductor device 8 which is also superior in reliability can be realized. Moreover, since the semiconductor device 8 has a structure in which the hardened body (sealing material layer 40) of the resin composition for semiconductor sealing is used to cover and protect the surface and side surfaces of the semiconductor wafer 5 opposite to the circuit formation surface, it is different from the previous Compared with the semiconductor device, it is also superior in chip resistance.

In addition, since the whole or part of the solder bumps 2 of the semiconductor device 8 of this embodiment is exposed, it is excellent in operability and can be used in various processes. Specifically, the semiconductor device 8 of this embodiment can be mounted on various substrates such as a motherboard, an interposer, and a lead frame.

<Second Embodiment>

The method of manufacturing the semiconductor device of the second embodiment will be described.

FIG. 9 is a diagram for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

In the second embodiment, the transfer step in the first embodiment (Figure 4(c)) However, there is a difference in that the transfer member 30 is embedded in a part of the solder bump 2 on the semiconductor wafer 5 and does not contact the main surface 3 of the semiconductor wafer 5.

Specifically, as shown in FIG. 9( a ), the transfer member 30 is attached to the semiconductor wafer 5 so as to cover a part of the solder bump 2 and not contact the circuit forming surface of the semiconductor wafer 5. In this structured state, the semiconductor wafer 5 is sealed at once.

In this embodiment, the resin composition 49 for semiconductor sealing in a liquid state is not only filled in the surface (rear surface 4) and side surface 9 opposite to the circuit formation surface of the semiconductor wafer 5, but also filled in the circuit formation surface ( Main surface 3). Thereby, it is possible to perform sealing at one time so that the side surface 9, the back surface 4 and the main surface 3 of the semiconductor wafer 5 are covered with the sealing material layer 40. According to the second embodiment, the same effect as the first embodiment can also be obtained, and in particular, it is possible to further suppress fragmentation during operation.

FIG. 8 is a cross-sectional view showing an example of the semiconductor device 8 of this embodiment.

The semiconductor device 8 shown in FIG. 8 is different from the first embodiment in that the entire lower surface (main surface 3) of the semiconductor wafer 5 is covered by the sealing material layer 40. In addition, a part of the front end of the bump (solder bump 2) has a structure protruding from the sealing material layer 40 and is exposed.

Regarding the semiconductor device 8 shown in FIG. 8, as in the first embodiment, at least a part of the top surface and the side surface of the semiconductor wafer 5 is covered by the sealing material layer 40. Therefore, with regard to the semiconductor device 8 shown in FIG. 8, as in the first embodiment, it is possible to solve the problem of damage to the semiconductor chip caused by the shock applied when picking up the semiconductor chip with the collet in the conventional semiconductor device. Therefore, the semiconductor device 8 of this embodiment can be a semiconductor device superior in reliability compared with the conventional semiconductor device.

Moreover, regarding the semiconductor device 8 shown in FIG. 8, as in the first embodiment, since A part of the solder bump 2 is exposed. Therefore, when the semiconductor device 8 is mounted on the substrate, a structure in which the sealing material layer 40 and the substrate are not in contact with each other can be realized.

<Third Embodiment>

The manufacturing method of the semiconductor device of the third embodiment will be described.

FIG. 10 is a diagram for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

The manufacturing method of this embodiment can be simplified without going through the transfer step of the first embodiment. That is, the first dividing step and the one-time sealing step can be performed in a state where the adhesive layer (protective film 10) is attached to the main surface 3 of the semiconductor wafer 5. Specifically, a structure 7 is prepared. The structure 7 is provided with a protective film 10 and a plurality of semiconductor chips 5 attached to the adhesive surface of the protective film 10, which can be attached to a plurality of semiconductors while maintaining the protective film 10 The state of the wafer 5 directly seals the semiconductor wafer 5.

In addition, the step of preparing the structure 7 in the embodiment includes the step of attaching the adhesive member so that the circuit formation surface (main surface 3) of the semiconductor wafer 1 and the adhesive surface of the adhesive member (protective film 10) are in contact with each other. In the state, the semiconductor wafer 1 is singulated to obtain a plurality of semiconductor chips 5 attached to the adhesive member; and the region of the adhesive member where the plurality of semiconductor chips 5 are attached is expanded in the film plane direction, The interval between adjacent semiconductor chips 5 is expanded to a predetermined interval.

Hereinafter, the above steps will be described.

As shown in FIG. 10(a), the semiconductor wafer 1 with the protective film 10 attached to the main surface 3 is singulated, and a plurality of semiconductor wafers 5 with the protective film 10 attached are produced. In addition, when the semiconductor wafer 1 is singulated, the protective film 10 is not cut, thereby maintaining the state in which the obtained semiconductor wafers 5 are attached.

Then, as shown in FIG. 10(b), for example, the protective film 10 may be expanded in the in-plane direction of the semiconductor wafer 5 to expand the interval between adjacent semiconductor wafers 5 to a predetermined interval. In addition, the space between the semiconductor wafers 5 may be expanded isotropically in the in-plane direction of the adhesive member (protective film 10).

Then, as shown in FIGS. 10(c) and (d), the resin composition 49 for semiconductor sealing in a fluid state is brought into contact with the surface of the plurality of semiconductor wafers 5 opposite to the circuit forming surface, and the adjacent semiconductor The space between the wafers 5 is filled with the resin composition 49 for semiconductor sealing, and the surface and side surfaces of the semiconductor wafer 5 opposite to the circuit formation surface are covered and sealed with the resin composition 49 for semiconductor sealing.

By the above method, a semiconductor device 8 having the same configuration as the first embodiment can be obtained. In addition, according to this embodiment, the same effect as the first embodiment can be obtained. Furthermore, according to the manufacturing method of this embodiment, the manufacturing steps of the semiconductor device 8 can be simplified, and therefore, the production efficiency can be further improved drastically compared with the previous manufacturing method.

<Fourth Embodiment>

The manufacturing method of the semiconductor device of the fourth embodiment will be described.

FIG. 12 is a diagram for explaining an example of the manufacturing method of the semiconductor device of this embodiment.

In the fourth embodiment, a step of narrowing the cutting width in which the division width L3 in the second division step is narrower than the division width L1 in the first division step can be implemented. That is, the fourth embodiment is different from other embodiments such as the first embodiment in that the division width is reduced.

First, as shown in FIG. 12(a), the main surface 3 of the semiconductor wafer 1 is attached to the protective film 10 (adhesive layer). Then, as shown in FIG. 12(b), dicing is performed from the back surface 4 side of the semiconductor wafer 1. In the cross-sectional view, set the width of the gap 11 formed by the first cutting as the division Width L1. After that, as shown in FIG. 12(c), a plurality of semiconductor wafers 5 are sealed at one time in a state where the main surface 3 of the semiconductor wafer 1 is attached to the protective film 10. Thereby, the sealing material layer 40 is formed on the side surface 9 and the back surface 4 of the semiconductor wafer 5. In addition, the gap 11 of the side surface 9 of the semiconductor wafer 5 is filled with the sealing material layer 40.

Then, as shown in FIG. 12(d), the sealing material layer 40 located in the gap 11 between the adjacent semiconductor wafers 5 is cut along the cutting area. In the cross-sectional view, the width of the gap formed by the second cutting is set as the division width L3. Thereafter, by peeling off the protective film 10, the semiconductor device 8 of this embodiment can be obtained.

In this embodiment, as the cutting method, blade cutting or laser cutting can be used. In addition, as a method of changing the cutting width, for example, reducing the width of the blade, or reducing the irradiation diameter of the laser, or changing the cutting method from a blade to a laser, or reducing the number of blades of the blade, etc. can be used.

By reducing the cutting width, the thickness of the film thickness of the sealing material layer 40 remaining on the side surface 9 of the semiconductor wafer 5 can be adjusted. Thereby, the film thickness of the sealing material layer 40 on the side surface 9 of the semiconductor wafer 5 can be sufficiently thickened. Therefore, fragmentation during operation can be suppressed, and a structure that improves the reliability of the semiconductor device can be realized. In addition, in order to increase the effective number of chips of the semiconductor wafer 1, the division width L3 may be reduced while the division width L1 is reduced. Thereby, it is possible to increase the effective number of fragments and improve the above-mentioned reliability.

In this embodiment, the lower limit of the division width L1 can be set to 50 μm or more, or 60 μm or more, for example. Thereby, it becomes easy to fill the resin composition for semiconductor sealing between the semiconductor wafers 5. The upper limit of the division width L1 may be 150 μm or less, for example, or 100 μm or less. Thereby, the effective number of chips of the semiconductor wafer 1 can be increased.

In this embodiment, the division width L3 is not particularly limited as long as it is smaller than the aforementioned division width L1. The lower limit of the division width L3 may be 10 μm or more, or 20 μm or more, for example. This can improve the controllability of cutting. The upper limit of the division width L3 may be 50 μm or less, for example, or 40 μm or less. Thereby, the film thickness of the sealing material layer 40 on the side surface 9 of the semiconductor wafer 5 can be ensured. Therefore, in the fourth embodiment, the same effect as the first embodiment can be sufficiently obtained.

<Fifth Embodiment>

The manufacturing method of the semiconductor device of the fifth embodiment will be described.

FIG. 13 is a diagram for explaining an example of the method of manufacturing the semiconductor device of this embodiment.

In the fifth embodiment, after the sealing step, a step of forming external connection bumps (solder bumps 2) on the main surface 3 of the semiconductor wafer 1 is included, which is different from the first embodiment in this respect. That is, in the first embodiment, after the bumps are formed, the first dividing step and the one-time sealing step are performed, and in the fifth embodiment, the bumps are formed after the first dividing step and the one-time sealing step are performed. After that, the second division step is implemented. Thereby, not only the wiring layer and bumps can be formed on the main surface 3 of the semiconductor wafer 5, but also the wiring layer and bumps can be formed on the outside of the region.

Hereinafter, each step will be described.

First, as shown in FIG. 13(a), a semiconductor wafer 1 with a circuit formed on the main surface 3 is prepared. In addition, the main surface 3 has a structure in which the solder bumps 2 are not formed (together with the wiring layer not shown). Then, for example, a protective film 10 is attached to the main surface 3 of the semiconductor wafer 1.

Then, as shown in FIG. 13(b), the above-mentioned first division step and one-time sealing step are implemented. An expansion step can also be implemented.

After that, as shown in FIG. 13(c), the protective film 10 is peeled off. At this time, the main surface 3 of the plurality of semiconductor wafers 5 and the surface 45 on the opposite side to the top surface (surface 41) of the sealing material layer 40 is exposed. The main surfaces 3 and 45 can form the same plane.

Then, wiring layers and solder bumps 2 (not shown) are formed on the main surface 3 of the semiconductor chips 5 and the surface 45 of the sealing material layer 40. The solder bump 2 can be formed not only on the main surface 3 but also on the surface 45 of the sealing material layer 40. Thereby, the pitch width between the semiconductor wafers 5 can be enlarged. After that, singulation is performed by implementing the second division step described above. Through the above method, the semiconductor device 8 shown in FIG. 14(d) can be obtained.

The details of each member used in this embodiment will be described.

Hereinafter, the structure of the semiconductor sealing resin composition 49, the dicing film 20, the transfer member 30, the protective film 10, and the release film 50 of this embodiment is demonstrated.

<Resin composition for semiconductor sealing>

Hereinafter, the aspect in which the resin composition for semiconductor sealing is a particulate resin composition will be described in detail, but it is not limited to this.

The resin composition for semiconductor sealing of the present embodiment preferably contains epoxy resin as its constituent material. As the epoxy resin, for example, monomers, oligomers, and whole polymers having two or more epoxy groups in one molecule, and the molecular weight and molecular structure of the epoxy resin are not particularly limited. Specifically, crystalline epoxy resins such as biphenyl epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, stilbene epoxy resin, hydroquinone epoxy resin, etc. ; Cresol novolac epoxy resin, phenol novolac epoxy resin, naphthol novolac epoxy resin and other novolac epoxy resins; phenol aralkyl epoxy resin containing phenylene skeleton, containing Phenol aralkyl epoxy resin with biphenylene skeleton, naphthol aralkyl epoxy resin with phenylene skeleton Phenol aralkyl type epoxy resin such as fat; trifunctional epoxy resin such as triphenol methane type epoxy resin, alkyl modified triphenol methane type epoxy resin; dicyclopentadiene modified phenol type epoxy resin , Terpene-modified phenol-based epoxy resins and other modified phenol-based epoxy resins; epoxy resins containing triazine cores and other heterocyclic-containing epoxy resins, etc., can use one of these or a combination of two or more use.

In addition, the method for obtaining the pelletized resin composition is not particularly limited. For example, the following method can be cited: the inner side of the rotor composed of a cylindrical outer peripheral portion with a plurality of small holes and a disc-shaped bottom surface is supplied and melted The kneaded resin composition is obtained by using the centrifugal force obtained by rotating the rotor to pass the resin composition through the small holes (hereinafter also referred to as the "centrifugal powdering method"); the raw material components are pre-mixed with a mixer and then used Rolls, kneaders, or extruders and other kneaders are heated and kneaded, and then cooled and pulverized to become pulverized products. The pulverized products are obtained by removing coarse particles and fine powders using a sieve (hereinafter also referred to as "crushing and sieving" Method”); After pre-mixing the ingredients with a mixer, use an extruder equipped with multiple small diameter die nozzles at the tip of the screw for heating and kneading, and the small holes arranged in the die nozzle form a rope The molten resin is extruded in a shape, and the molten resin is cut by a cutter that slides and rotates approximately parallel to the die nozzle surface (hereinafter also referred to as "thermal cutting method"). In either method, the desired particle size distribution or particle density can be obtained by selecting mixing conditions, centrifugal conditions, screening conditions, cutting conditions, etc. A particularly preferred method is the centrifugal powdering method, whereby the obtained granular resin composition can stably exhibit the required particle size distribution or particle density, so it is better in terms of transportability on the transport path or prevention of adhesion. In addition, the centrifugal pulverization method can smooth the surface of the particles to a certain extent, so there is no possibility that the particles are involved in each other or the frictional resistance between the particles and the conveying road surface increases, which prevents bridging (clogging) to the supply port of the conveying path. , It is also better to prevent stagnation on the conveying path. In addition, the centrifugal pulverization method is formed by using centrifugal force in the molten state, so it becomes the particle A state with a certain degree of voids can reduce the particle density to a certain degree, so it is advantageous in terms of transportability during compression molding.

On the other hand, the crushing and sieving method must study the processing method of the large amount of fine powder and coarse particles produced by sieving, but the sieving device is used in the existing production line of the resin composition for semiconductor sealing, so it can be directly Using the previous manufacturing line is better in this respect. In addition, regarding the crushing and sieving method, because the selection of the thickness of the sheet when the molten resin is sheeted before crushing, the crushing conditions or the selection of the sieve when crushing, the selection of the sieve when sieving, etc. are used to express the particle size of the present invention There are many factors in the distribution that can be controlled independently, so there are many options for adjusting the particle size distribution to the desired size, which is better in this respect. In addition, the thermal cutting method can directly use the previous manufacturing line to the extent that, for example, a thermal cutting mechanism is added to the front end of the extruder, it is preferred in this respect.

<Cutting Film>

The dicing film 20 of this embodiment is capable of maintaining the state of being attached to the semiconductor wafer 5 that is not cut when the semiconductor wafer 1 is singulated. This dicing film 20 is not particularly limited as long as it can be attached to the semiconductor wafer 1 and has a small positional deviation from the semiconductor wafer 5. As the dicing film 20, for example, it may have a multilayer laminated structure in which an adhesive layer is laminated on a support film. In addition, the dicing film 20 may also have a function of changing the adhesive force slightly by heating or irradiating ultraviolet rays. Thereby, the peelability from the adherend (semiconductor wafer 5) can be improved.

The constituent material of the support film is not particularly limited. For example, it may contain selected from polyethylene, polypropylene, ethylene-propylene copolymer, polyolefin, polybutene, polybutadiene, polymethylpentene, polyvinyl chloride, and polyvinyl chloride. Vinylidene chloride, vinyl chloride copolymer, polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate, polyurethane, ethylene-vinyl acetate copolymer, ionic polymer, Ethylene-(meth)acrylic acid copolymer, ethylene-(meth)acrylate copolymer Materials, polystyrene, ethylene polyisoprene, polycarbonate, polyphenylene sulfide, polyether ether ketone, acrylonitrile-butadiene-styrene copolymer, polyimide, polyetherimide, One or more resins in the group consisting of polyamide and fluororesin.

In addition, in order to improve the adhesion with the adhesive layer, the surface of the support film can be chemically or physically treated. In addition, the support film may contain various additives (fillers, plasticizers, antioxidants, flame retardants, and antistatic agents) within a range that does not impair the effects of the invention.

In addition, as the adhesive layer of the dicing tape, a first resin composed of acrylic adhesive, rubber adhesive, vinyl alkyl ether adhesive, silicone adhesive, polyester adhesive, etc. can be used. Adhesive layer composed of objects. Among these, acrylic adhesives can be used.

<Transfer member (adhesive member)>

Then, as described above, the transfer member 30 of this embodiment is preferably configured to have heat resistance to the extent that it can withstand the heat applied to harden the resin composition 49 for semiconductor sealing, and to be fixed to The adhesiveness of the semiconductor chip 5 on the transfer member 30 is not detached. Specifically, the transfer member 30 of this embodiment preferably has a structure in which a base material layer and an adhesive layer are laminated.

The adhesive layer is composed of a resin composition containing a resin capable of cross-linking reaction and a compound having flux activity. Examples of resins capable of undergoing a crosslinking reaction include epoxy resins, oxetane resins, phenolic resins, (meth)acrylate resins, unsaturated polyester resins, diallyl phthalate resins Resins, maleimide resins and the like are classified as so-called thermosetting resins. In addition, thermoplastic resins having functional groups such as carboxyl groups and epoxy groups can also be cited as resins capable of undergoing a crosslinking reaction. Among them, it is better to use hardening Epoxy resin with excellent performance and storage properties, heat resistance, moisture resistance, and chemical resistance of hardened materials.

The compound having flux activity is not particularly limited as long as it has the effect of removing the metal oxide film by heating or the like. For example, it can also be active rosin, organic compounds with carboxyl groups and other organic acids, amines, phenols, alcohols, azines, and other compounds that have flux activity by themselves or have the effect of promoting flux activity.

As the compound having flux activity, more specifically, compounds having at least one carboxyl group and/or phenolic hydroxyl group in the molecule can be cited, and the compound may be liquid or solid.

In addition, when heat resistance, dimensional stability, moisture resistance, and other properties are not particularly required, an inorganic filler may be further included. Examples of such inorganic fillers include silicates such as talc, calcined clay, uncalcined clay, mica, and glass; titanium oxide, aluminum oxide, and fused silica (fused spherical silica, fused crushed silica Oxides such as silicon), crystalline silicon dioxide and other powders; carbonates such as calcium carbonate, magnesium carbonate, and hydrotalcite; hydroxides such as aluminum hydroxide, magnesium hydroxide, calcium hydroxide, etc.; barium sulfate, calcium sulfate, calcium sulfite Such as sulfate or sulfite; zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate and other borates; aluminum nitride, boron nitride, silicon nitride and other nitrides. These inorganic fillers can be used alone or in combination. Among them, silicon dioxide powders such as fused silicon dioxide and crystalline silicon dioxide are preferable, and fused spherical silicon dioxide is particularly preferable.

By including the inorganic filler in the resin composition, the heat resistance, moisture resistance, strength, etc. after the resin composition is cured can be improved, and the peelability of the adhesive layer from the semiconductor wafer 5 can be improved. In addition, the shape of the inorganic filler is not particularly limited, and it is preferably a spherical shape, thereby providing a resin composition that is particularly suitable for the adhesive layer without anisotropy Things.

In addition, as the base material layer, for example, polyolefin such as polyethylene and polypropylene, ethylene-vinyl acetate copolymer, polyester, polyimide, polyethylene terephthalate, polyvinyl chloride, and polyolefin Films with excellent heat resistance or chemical resistance made of amide, polyurethane, etc. can be used. The thickness of the substrate layer is not particularly limited, but it is usually preferably 30 to 500 μm.

<Protective film (adhesive member)>

Then, the protective film 10 protects the circuit formation surface when the surface of the semiconductor wafer 1 on the opposite side to the circuit formation surface is polished. The protective film 10 is not particularly limited as long as it adheres to the semiconductor wafer 1, and for example, it may have a structure in which a back polishing tape and an adhesive layer are laminated. In addition, as shown in FIG. 10, the protective film 10 is sometimes used as a protective member when the semiconductor wafer 1 is singulated, and the protective film 10 is sometimes expanded in the in-plane direction, and sometimes it is used to seal the semiconductor. The resin composition 49 is cured and heat is applied. Therefore, the protective film 10 is preferably configured to have a certain degree of expandability, heat resistance to a degree that can withstand the heat applied to harden the resin composition 49 for semiconductor sealing, and be fixed to the protective film The adhesiveness of the semiconductor chip 5 on 10 will not be detached.

The protective film 10 is composed of a back polishing tape and an adhesive layer. In addition, a release film 50 may be provided between the back polishing belt and the adhesive layer. This makes it easy to peel off between the back polishing tape and the adhesive layer.

The adhesive layer is composed of a resin composition containing a resin capable of crosslinking reaction and a compound having flux activity. Examples of resins capable of undergoing a crosslinking reaction include epoxy resins, oxetane resins, phenolic resins, (meth)acrylate resins, unsaturated polyester resins, diallyl phthalate resins Resins, maleimide resins, etc. are classified as so-called thermosetting resins. In addition, resins having functional groups such as carboxyl groups and epoxy groups can also be cited Thermoplastic resins are used as resins capable of undergoing a crosslinking reaction. Among them, it is preferable to use an epoxy resin having excellent curability and storage properties, heat resistance, moisture resistance, and chemical resistance of the cured product.

The compound having flux activity is not particularly limited as long as it has the effect of removing the metal oxide film by heating or the like. For example, it may be organic acids such as activated rosin, organic compounds with carboxyl groups, amines, phenols, alcohols, azines, etc., which have flux activity themselves or have the effect of promoting flux activity.

As the compound having flux activity, more specifically, compounds having at least one carboxyl group and/or phenolic hydroxyl group in the molecule can be cited, and the compound may be liquid or solid.

In addition, as the back polishing belt, for example, it is made of polyolefin such as polyethylene and polypropylene, ethylene-vinyl acetate copolymer, polyester, polyimide, polyethylene terephthalate, polyvinyl chloride, and polyolefin. Films with excellent heat resistance or chemical resistance made of amide, polyurethane, etc. can be used. The thickness of the back polishing tape is not particularly limited, and it can usually be set to 30 to 500 μm.

<Release Film>

Furthermore, the mold release film 50 is not particularly limited as long as it has a configuration having excellent mold release properties. For example, it is preferably a mold release film having a mold release layer containing a polyester resin material.

The release film 50 of the present embodiment is a release film 50 having a release layer (first release layer) containing a polyester resin material.

In the release film 50 of this embodiment, the "release layer" refers to a resin that forms a surface in contact with the object (hereinafter also referred to as "release surface") at least when the release film 50 is placed on the object. The layer, the so-called polyester resin, refers to the polycondensate of polycarboxylic acid (dicarboxylic acid) and polyol (diol), and is a compound having multiple carboxyl groups (-COOH).

In addition, in this embodiment, the polyester resin material is not particularly limited, and examples thereof include polyethylene terephthalate resin, polybutylene terephthalate resin, polytrimethylene terephthalate resin, Polyalkylene terephthalate resin such as polyethylene terephthalate resin. Among them, it is preferable to use polybutylene terephthalate resin.

The release film 50 of this embodiment may have a single-layer structure or a multilayer structure.

The embodiments of the present invention have been described above, but these are examples of the present invention, and various configurations other than the above may be adopted.

In addition, in the above-mentioned embodiment, the case where the granular semiconductor sealing resin composition 49 is used for compression molding when sealing the semiconductor wafer 5 has been described as an example. However, the spin coating method, the printing method, and the dispensing method may also be used for The surface of the semiconductor wafer 5 opposite to the circuit forming surface is coated with the liquid semiconductor sealing resin composition 49 and then dried. The surface of the semiconductor wafer 5 opposite to the circuit forming surface can also be applied under pressure The resin composition 49 for semiconductor sealing in a softened state that is pressed and infiltrated into a film shape can also be used to make the liquid semiconductor sealing resin composition 49 flow into the space between adjacent semiconductor wafers 5 by using the capillary phenomenon.

In addition, in the above-mentioned embodiment, the case where the semiconductor device 8 is manufactured by using the semiconductor wafer 1 with a plurality of solder bumps 2 mounted on the circuit formation surface is described as an example. A semiconductor wafer 1 with a solder bump 2 is used to manufacture a semiconductor device 8 in which at least a part of the lower surface of the semiconductor chip 5 is not covered by the sealing material layer 40. In the subsequent step, solder bumps are mounted on the circuit formation surface of the semiconductor chip 5 2 After mounting on the substrate, the semiconductor chip 5 and the substrate can also be electrically connected by wire bonding.

In addition, when sealing the semiconductor chip 5, a chip processed into a chip can also be used. The sealing material composed of the resin composition 49 for conductor sealing (hereinafter referred to as a sheet-like sealing material) is laminated by the following method.

First, install the sheet-shaped sealing material prepared according to the roll shape to the unwinding device of the vacuum pressure laminator, and connect it to the winding device. Then, the semiconductor wafer 1 with the protective film 10 attached is transported to the diaphragm (elastic film) type bonding machine part. Then, under reduced pressure, when pressure is started, the sheet-like sealing material is heated to a predetermined temperature and becomes a molten state. After that, the molten sheet-like sealing material is pressurized by the intermediary diaphragm to pressurize the semiconductor wafer 1 is pressed so that the cutout 20 formed in the semiconductor wafer 1 can be filled with the sheet-shaped sealing material, and the surface of the semiconductor wafer 1 opposite to the circuit forming surface can be covered with the sheet-shaped sealing material. After that, it takes a predetermined time to harden the sheet-like sealing material. In this way, the semiconductor wafer 5 can be sealed.

In addition, when higher-precision flatness is required for the sheet-like sealing material, it is also possible to add a pressure step with a high-precision adjustment flat pressure device after the pressure is applied by a diaphragm laminator. .

When performing the above-mentioned lamination forming, the forming temperature of the diaphragm (elastic film) type laminating machine is preferably 50 to 120°C, and more preferably 80 to 110°C. In addition, the molding pressure of the diaphragm (elastic film) type laminating machine is preferably 0.5 to 1 Mpa, and more preferably 0.6 to 0.9 MPa. Moreover, the forming time of the diaphragm (elastic film) type laminating machine part is preferably 30 seconds to 5 minutes, and more preferably 1 to 3 minutes. By setting the molding temperature, pressure, and time of the diaphragm (elastic film) type laminating machine part within the above-mentioned ranges, it is possible to prevent the generation of a part of the sheet-shaped sealing material in a molten state that is not filled.

In the lamination forming described above, the pressing temperature of the flat pressing device is preferably 80 to 130°C, and more preferably 90 to 120°C. In addition, the forming pressure of the flat pressing device is preferably 0.5-2Mpa, and more preferably 0.8-1.5MPa. Moreover, the forming time of the flat pressing device It is preferably 30 seconds to 5 minutes, and more preferably 1 to 3 minutes. By setting the pressing temperature, molding pressure, and time of the flat pressing device within the above-mentioned ranges, it is possible to prevent the generation of a portion where the sheet-shaped sealing material is not filled in a molten state.

In addition, after the semiconductor wafer 5 is sealed and molded by the lamination molding method using the above-mentioned sheet-like sealing material, the curing temperature after the implementation is preferably 150 to 200°C, and more preferably 165 to 185°C. Moreover, the post-curing time is preferably 1 hour to 5 hours, and more preferably 2 hours to 4 hours.

This application claims priority based on Japanese Application No. 2014-175135 filed on August 29, 2014, and incorporates all the contents disclosed herein.

Claims (10)

A method of manufacturing a semiconductor device, which includes the following steps: a preparation step, which prepares a semiconductor wafer with a circuit formed on the main surface; an attachment step, which attaches the semiconductor wafer to an adhesive layer; and a first dividing step, which A plurality of semiconductor wafers are obtained by dividing the semiconductor wafer attached to the adhesive layer along the cutting area to obtain a plurality of semiconductor wafers; the sealing step is to attach the main surfaces of the plurality of semiconductor wafers to the adhesive layer In this state, a plurality of the semiconductor wafers are sealed at once, thereby forming a semiconductor sealing resin on the gap between the side surfaces of the semiconductor wafer and the back surface of the semiconductor wafer on the opposite side to the main surface on which the circuit is formed A sealing material layer formed by an object; and a second dividing step, which is obtained by dividing the sealing material layer formed in the gap between the side surfaces of the semiconductor wafer to obtain the sealing material formed on the side surface and the back surface The first dividing step includes the following steps: by dividing the semiconductor wafer in a state where the back surface of the semiconductor wafer is attached to the adhesive layer, a plurality of the semiconductor wafers are obtained A wafer; an expansion step, which expands the interval between the adjacent semiconductor wafers; and reattaches the transfer member to the main surface of the semiconductor wafer and peels off the adhesive layer attached to the back surface; and the sealing step is expanding It is implemented in the state of the interval between the above-mentioned semiconductor wafers. For example, the method for manufacturing a semiconductor device in the first item of the patent application, wherein the above-mentioned attaching step includes the following steps: Attaching the main surface of the semiconductor wafer to the adhesive layer; and removing the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer. For example, the method for manufacturing a semiconductor device of the second patent application, wherein the thickness of the semiconductor wafer after the step of thinning the film thickness is 100 μm or more and 300 μm or less. For example, in the method of manufacturing a semiconductor device in the scope of the patent application, the division width in the second division step is smaller than the division width in the first division step. For example, the method for manufacturing a semiconductor device according to the first patent application, wherein the first dividing step is to perform the expansion step after dividing the semiconductor wafer and forming a cut in the adhesive layer. For example, in the method of manufacturing a semiconductor device according to the first patent application, in the preparation step, bumps for external connection are formed on the main surface of the semiconductor wafer. For example, the method for manufacturing a semiconductor device according to the first patent application, wherein after the sealing step, the step of forming external connection bumps on the main surface of the semiconductor wafer is included, and then the second dividing step is performed . A method of manufacturing a semiconductor device, comprising the steps of preparing a structure including an adhesive member and a plurality of semiconductor wafers attached to the adhesive surface of the adhesive member, the plurality of semiconductor wafers being arranged at a predetermined interval from each other, And the circuit forming surface of a plurality of semiconductor chips is attached to the adhesive surface of the adhesive member; the resin composition for semiconductor sealing in a fluid state is brought into contact with the plurality of semiconductor wafers, and the semiconductor sealing resin is filled in the space The resin composition for semiconductor sealing is used to cover the surface and side surface of the semiconductor chip opposite to the circuit formation surface for sealing; and to seal the surface and side surface opposite to the circuit formation surface of the semiconductor wafer The above-mentioned semiconductor sealing resin composition is cured; the above-mentioned step of preparing the above-mentioned structure includes the steps of: singulating the above-mentioned semiconductor wafer with a dicing film attached to the surface of the semiconductor wafer opposite to the circuit formation surface To obtain a plurality of semiconductor wafers attached to the dicing film; expand the area in the dicing film where the semiconductor wafers are attached to the inward direction of the film to make the space between adjacent semiconductor wafers Expand to the predetermined interval; attach the adhesive member so that the circuit forming surfaces of the semiconductor chips are in contact with the adhesive surface of the adhesive member; and in the state where the semiconductor chips are attached to the adhesive surface of the adhesive member Next, the dicing film is peeled from the semiconductor wafer. For example, the method for manufacturing a semiconductor device according to claim 8, wherein in the step of expanding the interval between the adjacent semiconductor wafers to the predetermined interval, the interval is made isotropically in the in-plane direction of the dicing film expansion. For example, the manufacturing method of semiconductor device in the 8th item of the scope of patent application, in which, The method further includes the step of cutting the cured body of the semiconductor sealing resin composition filled in the space and singulating into a plurality of the semiconductor wafers sealed by the semiconductor sealing resin composition.

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