CN106796893B - The manufacturing method and semiconductor device of semiconductor device - Google Patents

The manufacturing method and semiconductor device of semiconductor device Download PDF

Info

Publication number
CN106796893B
CN106796893B CN201580046732.7A CN201580046732A CN106796893B CN 106796893 B CN106796893 B CN 106796893B CN 201580046732 A CN201580046732 A CN 201580046732A CN 106796893 B CN106796893 B CN 106796893B
Authority
CN
China
Prior art keywords
semiconductor
semiconductor chip
semiconductor device
manufacturing
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580046732.7A
Other languages
Chinese (zh)
Other versions
CN106796893A (en
Inventor
森弘就
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Publication of CN106796893A publication Critical patent/CN106796893A/en
Application granted granted Critical
Publication of CN106796893B publication Critical patent/CN106796893B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The present invention provides a kind of manufacturing method of semiconductor device, and the manufacturing method of the semiconductor device includes: preparatory process, prepares the semiconductor wafer that interarea is formed with circuit；Semiconductor wafer is attached at adhesive layer by attached process；First segmentation process by being split along semiconductor wafer of the cutting region to the state for being attached at adhesive layer, and obtains multiple semiconductor chips；Sealing process, in the state that the interarea of multiple semiconductor chips is attached at adhesive layer, multiple semiconductor chips are sealed together, thus form the sealing material layer comprising semiconductor sealing resin composition on the gap between the side of semiconductor chip and the back side of semiconductor chip；It with the second segmentation process, is split by the sealing material layer to the gap being formed between the side of semiconductor chip, and obtains and be formed with multiple above-mentioned semiconductor chips of sealing material layer in side and the back side.

Description

The manufacturing method and semiconductor device of semiconductor device
Technical field
The present invention relates to a kind of manufacturing method of semiconductor device and semiconductor devices.
Background technique
In the manufacturing process of current semiconductor device, using sealing resin by the semiconductor chip of singualtion individually It is sealed.As this technology, such as there is technology documented by patent document 1.In the publication, it describes and is picked up using collet chuck After taking semiconductor chip and being mounted on substrate, using semiconductor encapsulating epoxy resin and utilize transfer moudling by semiconductor core Piece individually seals (patent document 1).
It is described the technology of chip singualtion in patent document 2 from semiconductor wafer.Specifically, by hemisect, Slot is formed in the interarea of semiconductor wafer.By being ground to the back side, by the chip singualtion comprising semiconductor.Singualtion Chip carries out chip welding after being picked in the state that base semiconductor is exposed on surface.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 9-107046 bulletin
Patent document 2: Japanese Unexamined Patent Publication 2011-210927 bulletin
Summary of the invention
Problems to be solved by the invention
However, in the manufacturing process for the semiconductor package body that above-mentioned document is recorded, since each semiconductor chip is individual Ground is sealed, and has room for improvement in terms of productivity.
Also, inventor learns after studying, and when picking up chip using collet chuck, can generate chip rupture (fragmentation). I.e. above-mentioned technology recorded in the literature has room for improvement in terms of reliability.
The method used for solving the problem
The present inventor has found after further studying, when picking up semiconductor chip, by the surface for protecting semiconductor chip It is able to suppress fragmentation.Found according to this opinion and then after furtheing investigate, by the way that multiple semiconductor chips are sealed together and It is split between adjacent chips, side and the back side (side opposite with circuit forming face) can be obtained by sealing material layer The semiconductor chip of covering.Further, it was found that fragmentation when operating to the semiconductor chip is inhibited, to complete this hair It is bright.
According to the present invention, a kind of manufacturing method of semiconductor device is provided comprising: preparatory process prepares interarea and is formed There is the semiconductor wafer of circuit；Above-mentioned semiconductor wafer is attached at adhesive layer by attached process；First segmentation process, passes through edge Cutting region the above-mentioned semiconductor wafer for the state for being attached at above-mentioned adhesive layer is split and obtains multiple semiconductor cores Piece；Sealing process will be multiple above-mentioned in the state that the above-mentioned interarea of multiple above-mentioned semiconductor chips is attached at above-mentioned adhesive layer Semiconductor chip seals together, thus the back side in the gap between the side of above-mentioned semiconductor chip and above-mentioned semiconductor chip It is upper to form the sealing material layer comprising semiconductor sealing resin composition；With the second segmentation process, to being formed in above-mentioned semiconductor The above-mentioned sealing material layer in the gap between the above-mentioned side of chip is split, and is obtained in above-mentioned side and above-mentioned back side shape At the multiple above-mentioned semiconductor chips for having above-mentioned sealing material layer.
Also, according to the present invention, provide a kind of manufacturing method of semiconductor device comprising: prepare the process of structural body, The structural body has adhering part and is attached at multiple semiconductor chips of the bonding plane of above-mentioned adhering part, multiple above-mentioned partly to lead Body chip is mutually configured across specified interval, and the circuit forming face of multiple above-mentioned semiconductor chips is attached at above-mentioned bonding The above-mentioned bonding plane of component；Make in flow regime resin composition for encapsulating semiconductor and multiple above-mentioned semiconductor chips into Row contact fills above-mentioned resin composition for encapsulating semiconductor at above-mentioned interval, and utilizes above-mentioned semiconductor sealing resin Composition covers face and side and the process that is sealed of the side opposite with circuit forming face of above-mentioned semiconductor chip；With Make the cured process of above-mentioned resin composition for encapsulating semiconductor.
Also, according to the present invention, provide a kind of semiconductor device, have: interarea is formed with the semiconductor chip of circuit； It is formed in the convex block of above-mentioned interarea；With the back side of the side and the side opposite with above-mentioned interarea that cover above-mentioned semiconductor chip Sealing material layer.
Invention effect
In accordance with the invention it is possible to the manufacturing method of a kind of reliability and the excellent semiconductor device of productivity is provided, and It is capable of providing a kind of semiconductor device improved in terms of reliability.
Detailed description of the invention
Above-mentioned purpose and its are further clarified by preferred embodiment as described below and the following drawings subsidiary therewith His objects, features and advantages.
Fig. 1 is the sectional view for indicating an example of semiconductor device involved in present embodiment.
Fig. 2 is the sectional view for indicating an example of semiconductor device involved in present embodiment.
Fig. 3 is the process section for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment Figure.
Fig. 4 is the process section for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment Figure.
Fig. 5 is the process section for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment Figure.
Fig. 6 is can when expanding the interval between adjacent semiconductor chip in manufacturing method involved in present embodiment The structural example of the expanding unit used.
Fig. 7 is can when expanding the interval between adjacent semiconductor chip in manufacturing method involved in present embodiment The structural example of the expanding unit used.
Fig. 8 is the sectional view for indicating an example of semiconductor device involved in present embodiment.
Fig. 9 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
Figure 10 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
Figure 11 is the cutting of the semiconductor wafer in the manufacturing method for indicate semiconductor device involved in present embodiment The top conceptual figure in region.
Figure 12 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
Figure 13 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
Specific embodiment
Hereinafter, using attached drawing, embodiments of the present invention will be described.In addition, in all attached drawings, to identical composition Important document marks identical symbol, and suitably omits the description.
< first embodiment >
The manufacturing method of semiconductor device involved in present embodiment is illustrated.
The manufacturing method of the semiconductor device 8 of present embodiment includes: to prepare the process of structural body 7, which has Adhering part 10 or 30 (adhesive layer) and be attached at adhering part 10 or 30 bonding plane multiple semiconductor chips 5, Duo Geban Conductor chip 5 is mutually configured across specified interval, and the circuit forming face of multiple semiconductor chips 5 is attached at adhering part 10 or 30 bonding plane；Carry out resin composition for encapsulating semiconductor 49 and multiple semiconductor chips 5 in flow regime Contact, the interval filling semiconductor resin composition for encapsulating 49 between adjacent semiconductor chip 5, and it is close using semiconductor Envelope resin combination 49 cover semiconductor chip 5 the side opposite with circuit forming face face and side and be sealed Process；With make the cured process of resin composition for encapsulating semiconductor 49.
In the manufacturing method of the semiconductor device of present embodiment, semiconductor device 8 below, the semiconductor can be obtained Device 8 can cover in the solidified body (sealing material layer 40) using resin composition for encapsulating semiconductor and protect semiconductor core It is picked up in the state of the face (back side 4) of the side opposite with circuit forming face (interarea 3) of piece 5 and side 9 using collet chuck. Thereby, it is possible to prevent operating device from directly contacting semiconductor chip 5, Huo Zheneng when being picked up using operating devices such as collet chucks It is enough to pass through when the operating devices contacts such as solidified body (sealing material layer 40) the mitigation collet chuck of resin composition for encapsulating semiconductor pairs The impact that semiconductor chip 5 applies.Therefore, when can prevent in advance because picking up semiconductor chip 5 using operating devices such as collet chucks The impact of application and cause semiconductor chip 5 damaged (fragmentation).Therefore, it can be realized partly leading with structure excellent in reliability Body device.
Here, the semiconductor chip of the singualtion documented by patent document 2, side and the back side are (convex with being formed with The face of the opposite side in the face of block) it is unprotected, for the state for exposing base semiconductor material.The research of people according to the present invention Can distinguish, if the surface expose in the state of implement pick up or conveying etc. operation, the semiconductor chip generate fragmentation can It can property height.
In contrast, in the manufacturing process of present embodiment, can the side of semiconductor chip 59 and the back side 4 (with The face of the opposite side of interarea 3) it is formed with operation semiconductor chip 5 in the state of sealing material layer 40.Thereby, it is possible to inhibit to pick up The fragmentation for taking or being generated when transporting.Therefore, the manufacturing method of semiconductor device according to the present embodiment, with existing manufacture work Skill is compared, and semiconductor device 8 excellent in reliability can be obtained.
Also, the manufacturing method of semiconductor device 8 according to the present embodiment, can be after singualtion by multiple semiconductors Chip 5 carries out resin seal together.Therefore, it can be improved the productivity of semiconductor device 8.
Therefore, in the present embodiment, it may be implemented can to take into account the manufacture of the semiconductor device of reliability and productivity Method.
Hereinafter, being illustrated to each process of the manufacturing method of semiconductor device.
Fig. 3~Fig. 5 is the process for illustrating an example of the manufacturing method of semiconductor device 8 involved in present embodiment Sectional view.
Fig. 3 (a) is the figure for indicating an example of semiconductor wafer 1 involved in present embodiment.Fig. 3 (b) is to indicate in electricity Road forming face is pasted with the figure of the semiconductor wafer 1 of protective film 10.Fig. 3 (c) is to indicate to the side opposite with circuit forming face Face ground made of semiconductor wafer 1 figure.Fig. 3 (d) is the face paste indicated in the side opposite with circuit forming face The figure of semiconductor wafer 1 with cutting film 20.Fig. 3 (e) be indicate by protective film 10 from circuit forming face removing after, monolithic The figure of semiconductor wafer 1 before change.
Fig. 4 (a) is the figure for illustrating to obtain the process of semiconductor chip 5.Fig. 4 (b) is for illustrating setting interval The figure of process.Fig. 4 (c) is the figure for illustrating to cover circuit forming face using transfer member 30.Fig. 4 (d) is for illustrating to shell The figure of process from cutting film 20.Fig. 4 (e) and Fig. 4 (f) is for illustrating to carry out using resin composition for encapsulating semiconductor 49 The figure of the process of sealing.Fig. 5 (a) is the figure for indicating the process of removing mold release film 50.Fig. 5 (b) is to indicate that semiconductor device 8 is single The figure of the process of piece.Fig. 5 (c) is the figure for indicating the process of removing transfer member 30.
As shown in above-mentioned Fig. 3~Fig. 5, the manufacturing method of the semiconductor device of present embodiment is by semiconductor die chip level technique To implement.That is, the manufacturing method of the semiconductor device of present embodiment may include: preparatory process, prepares interarea 3 and be formed with electricity The semiconductor wafer 1 on road；Semiconductor wafer 1 is attached at adhesive layer (protective film 10) by attached process；First segmentation process, edge Cutting region is split the semiconductor wafer 1 in the state for being attached at adhesive layer (cutting film 20), and obtains and multiple partly lead Body chip 5；Sealing process will in the state that the interarea 3 of multiple semiconductor chips 5 is attached at adhesive layer (transfer member 30) Multiple semiconductor chips 5 seal together, thus the back side in the gap 12 between the side of semiconductor chip 59 and semiconductor chip 5 The sealing material layer 40 comprising semiconductor sealing resin composition 49 is formed on 4；With the second segmentation process, by being formed in half The sealing material layer 40 in the gap 12 of the side 9 of conductor chip 5 is split, and is obtained and be formed with sealing in side 9 and the back side 4 Multiple semiconductor chips (semiconductor device 8) of material layer 40.
In the present embodiment, semiconductor wafer 1, such as can use and be formed with single-layer or multi-layer wiring on a silicon substrate The chip of layer.In semiconductor wafer 1, the face for being formed with wiring layer side is known as circuit forming face (interarea 3) and is said It is bright.
In the present embodiment, as above-mentioned adhesive layer, multiple of the same race or xenogenesis adhesive layer can be used.For example, making Protective film 10, cutting film 20, transfer member 30 etc. also can be used for the purpose of various operations for adhesive layer.Adhering part (protective film 10 or transfer member 30) can be jointing tape monomer, or the portion of adhesive layer is formed on supporting substrate Part.Protective film 10 can protect semiconductor wafer 1 from impact.Transfer member 30 can be in the configuration for maintaining semiconductor chip 5 In the state of so that the bonding plane of opposite adhesive layer is changed to the back side 4 from interarea 3 or is changed to interarea 3 from the back side 4, can be changed to Opposite side.
In addition, cutting film 20, transfer member used in each process to the manufacturing method involved in present embodiment 30, the detailed content of protective film 10 and mold release film 50 is described below.
Firstly, being illustrated to following process, i.e., in the process, in the opposite with circuit forming face of semiconductor wafer 1 In the state of the attached cutting film 20 of the face paste of side, by 1 singualtion of semiconductor wafer, and obtain in the state for being attached at cutting film 20 Under multiple semiconductor chips 5 process.
Firstly, preparing the semiconductor wafer 1 that interarea 3 is formed with circuit.As shown in Fig. 3 (a), preparation is formed in entire circuit Face (interarea 3) is formed with the semiconductor wafer 1 of multiple external connection convex blocks (solder projection 2).In the present embodiment, so-called Chip can be circular shape under overlook view, or rectangular shape.The chip refers to the plate shape of thin layer, as long as extremely It is few that there is the area for cutting out multiple chip degree, then it is not particularly limited.
Then, semiconductor wafer 1 is attached at adhesive layer (protective film 10).As shown in Fig. 3 (b), prepared to protect Semiconductor wafer 1 circuit forming face (interarea 3), to the circuit forming face attach protective film 10, utilize protective film 10 cover The entire surface of the circuit forming face.Thereby, it is possible to prevent to the face of the side opposite with circuit forming face of semiconductor wafer 1 into Lead to the breakages such as the electronic component for being mounted in the circuit forming face due to impact when row grinding because applying to circuit forming face.
Then, as shown in Fig. 3 (c), removal be pasted with protective film 10 semiconductor wafer 1 with circuit forming face (interarea 3) face (back side 4) of opposite side.Thus make the film thickness of semiconductor wafer 1 thinning.For example, can use chemical mechanical grinding (CMP) etc. the back side 4 of semiconductor wafer 1 is ground.Specifically, by partly leading in the state of being pasted with protective film 10 Body chip 1 is fixed on grinding device, the face of the side opposite with circuit forming face is ground, to make the semiconductor wafer 1 Thickness becomes specific thickness.
In present embodiment, the upper limit value of the film thickness of the semiconductor wafer 1 after the process for keeping film thickness thinning, such as can be with 300 μm are set as hereinafter, also can be set to 200 μm or less.Thereby, it is possible to realize the thin layer of semiconductor device obtained.Separately On the one hand, the lower limit value of the film thickness is not particularly limited, such as can be set to 100 μm or more, also can be set to 150 μm or more. Thereby, it is possible to sufficiently obtain the mechanical strength of semiconductor wafer 1 and semiconductor chip 5.
In recent years, the demand to the miniaturization and lightweight of electronic equipment for carrying semiconductor device etc. is improving.With Meet and carries out the thin layer of semiconductor wafer for the purpose of this requirement.In recent years in the technique thin layer to semiconductor wafer, The problem of semiconductor chip breakage is caused to have due to the above-mentioned impact applied when being picked up using operating devices such as collet chucks brighter Tendency clear.
However, manufacturing process according to the present embodiment, even if the case where stating thin layer semiconductor wafer 1 in use Under, it can also sufficiently inhibit the impact applied when being picked up using operating devices such as collet chucks due to cause semiconductor chip broken Damage.As described above, be can be in the side of semiconductor chip 59 and the back side 4 (face of the side opposite with interarea 3) for its reason It is formed in the state of sealing material layer 40 and operates semiconductor chip 5.
In addition, in manufacturing method involved in present embodiment, as described above, in the state of being pasted with protective film 10, The face (back side 4) of the side opposite with circuit forming face (interarea 3) of semiconductor wafer 1 is ground, therefore can be effective Ground prevent because grinding when generate stress due to lead to the breakages such as the electronic component of circuit forming face for being mounted in semiconductor wafer 1.
Then, as shown in Fig. 3 (d), in the state that protective film 10 is attached at circuit forming face, cutting film 20 is attached at The face (back side 4) of the side opposite with circuit forming face (interarea 3) of the semiconductor wafer 1 of grinding and acquisition.
Then, as shown in Fig. 3 (e), protective film 10 is removed from semiconductor wafer 1.Moreover, making the interarea 3 of semiconductor wafer 1 Expose.At this point, protective film 10 is preferably after reducing the adaptation between the protective film 10 and semiconductor wafer 1 from semiconductor wafer 1 removing.Specifically, following methods can be enumerated: being carried out for example by the bonding site to protective film 10 and semiconductor wafer 1 Ultraviolet light irradiation or heat treatment, and make to form the deterioration of the adhesive layer of the protective film of the bonding site 10, thus reduce adaptation.
Then, the segmentation process of semiconductor wafer (the first segmentation process) is illustrated.
In the first segmentation process of present embodiment, by along cutting region to being attached at adhesive layer (cutting film 20) The semiconductor chip 5 of state is split, and obtains multiple semiconductor chips 5.
Figure 11 is the top conceptual figure indicated in the cutting region of overlook view lower semiconductor chip 1.The top conceptual figure Although different from actual process, it can be used as the purpose for understanding cutting region and use.The semiconductor wafer 1 of Figure 11 has circle Shape shape.About cutting region, the first cutting line 13 is located at the direction orthogonal with the second cutting line 14.It can along these cutting lines It is cut.In addition, being partly leading as semiconductor chip by the first cutting line 13 and the region that the second cutting line 14 is divided Body chip region 15.By reducing the width of cutting region, Effective number of chips can be increased.L1 in Figure 11 refers to cutting width.
Specifically, the face (back side 4) of side that will be opposite with circuit forming face shown in Fig. 3 (e) attaches cutting film 1 singualtion of semiconductor wafer of 20 state makes multiple semiconductors that the state of cutting film 20 is pasted with shown in Fig. 4 (a) Chip 5.Cutting blade, laser etc. can be used in the singualtion (segmentation) of semiconductor wafer 1.
Semiconductor chip 5 shown in Fig. 4 (a), adjacent semiconductor chip 5 configures with being separated from each other to be cut On film 20.Gap 11 is formed between the side of semiconductor chip 59.Under section observation, the width in the gap 11 corresponds to Cutting width L1.
In addition, needing to be cut off cutting film 20 not and be able to maintain attaching and obtained when by 1 singualtion of semiconductor wafer The state of the multiple semiconductor chips 5 obtained.Cutting film 20 can also be formed from the bonding plane with semiconductor chip 5 towards inside Along the notch of cutting region.The notch does not penetrate from the upper surface to the lower surface cutting film 20, such as can be film thickness 1/2 depth, or 1/3 depth.Pass through the notch, extension process of the cutting film 20 between semiconductor chip 5 then In can successfully extend.Thereby, it is possible to expand the gap of semiconductor chip 5 more equally among.
Then, the extension process in the mutual gap in side of extension semiconductor chip is illustrated.
In present embodiment, after semiconductor wafer 1 is divided into multiple semiconductor chips 5, implementation can also be added and expanded The process for opening up the adjacent mutual interval of semiconductor chip 5.
Specifically, making the Directional Extension in the face of semiconductor chip 5 of cutting film 20, so that adjacent as shown in Fig. 4 (b) Semiconductor chip 5 between interval be extended to specified interval.As a result, under section observation, the gap 12 after process is extended Width (extension width L2) can become larger than extension process before gap 11 width (L1).
For example, being preferably spaced at equal intervals between adjacent semiconductor chip 5.That is, about partly leading in rectangular shape The direction parallel with one side of semiconductor chip 5 is set as first by the interval in body chip 5 between adjacent semiconductor chip 5 When direction, the direction orthogonal with above-mentioned first direction are set as second direction, only can equally spaced it extend in a first direction, Only can equally spaced extend in a second direction, preferably in a first direction with equally spaced expand in second direction both direction Exhibition.Therefore, when expanding the interval between adjacent semiconductor chip 5, preferably make between above-mentioned adjacent semiconductor chip 5 The direction in 20 face of cutting film that is spaced in isotropically extend.
Here, as described above, manufacturing method involved in present embodiment is to make cutting film 20 in the electricity of semiconductor chip 5 Directional Extension in the face of road forming face.Therefore, the excellent structure of the preferred draftability of cutting film 20.
In above-mentioned extension process, cutting film 20 can carry out in the state of being heated.It is easy to expand cutting film 20 as a result, Exhibition.Heating temperature is not particularly limited, but whole preferably over cutting film 20, Temperature Distribution it is irregular few.
It, can also be in dividing semiconductor wafer 1 and the shape on cutting film 20 (adhesive layer) in above-mentioned first segmentation process Implement above-mentioned extension process later at above-mentioned notch.It is easy to extend cutting film 20 using the notch, therefore can reduce half-and-half The width (extension width L2) at the interval 12 after width (cutting width L1) extension in the gap 11 between conductor chip 5 is no It is even.Here, extension width L2 is greater than cutting width L1.The upper limit value of extension width L2 is not particularly limited, such as is preferably greater than Total width of the film thickness of sealing material layer 40 on cutting width and side 9.
As described above, above-mentioned first segmentation process in present embodiment may include: by by semiconductor wafer 1 The back side 4 is attached in the state of front attachment layer, is split to semiconductor wafer 1, and obtains the work of multiple semiconductor chips 5 Sequence；And expand the extension process at the interval (gap 11) between adjacent semiconductor chip 5.Thereby, it is possible to expand semiconductor Implement sealing process in the state of interval between chip 5.
In the present embodiment, when the interval between adjacent semiconductor chip 5 being made to be extended to specified interval, using known Cutter device extend cutting film 20.
Here, when expanding the interval between adjacent semiconductor chip 5, such as extension dress below also can be used It sets.
Fig. 6 and Fig. 7 is the structure for the expanding unit that the interval between adjacent semiconductor chip 5 can be used when expanding Example.Fig. 6 is the figure of the state before indicating to make the interval between adjacent semiconductor chip 5 to expand.Fig. 6 (a) is side profile Figure, Fig. 6 (b) are top view.Fig. 7 is the figure of the state after indicating to make the interval between adjacent semiconductor chip 5 to expand.Fig. 7 It (a) is side sectional view, Fig. 7 (b) is top view.
The device of Fig. 6 and Fig. 7 has: cyclic annular framework 100 will be attached at the multiple semiconductor cores for being singulated and obtaining It is clamped around the cutting film 20 of piece 5；Expanding table 140, the lower section for the cutting film 20 configured in the inside of framework 100, pass through to Top is mobile and extends cutting film 20；With heating part 130, setting adds in expanding table 140, and to the expanding table 140 Heat, and expanding table 140 is divided into its central portion 110 and its peripheral portion 120, and heating part 130 is arranged in expanding table 140 The faces different from the contact surface of cutting film 20 in centre portion 110.
In addition, the configuring area of multiple semiconductor chips 5 of the state of the attaching cutting film 20 on expanding table 140, excellent Select temperature uniform.Thereby, it is possible in the face of the cutting film 20 direction equably control the scalability of cutting film 20.
In addition, the device of Fig. 6 and Fig. 7 can make cutting film and heating using heating part 130 to expanding table 140 20 scalability improves.
The device of Fig. 6 and Fig. 7 the central portion 110 to expanding table 140 and peripheral portion 120 can heat on one side as a result, On one side it is moved upward expanding table 140.Thereby, it is possible to improve the scalability in direction in the face of cutting film 20 equably, and And it is moved upward expanding table 140.Therefore, as shown in fig. 7, can be become with the interval between adjacent semiconductor chip 5 Equally spaced mode extends cutting film 20 equably.
Then, the sealing process together of semiconductor chip is illustrated.
In the first embodiment, implement segmentation process in the state that the back side of semiconductor wafer 14 attaches cutting film 20 With extension process.In sealing process together below, in order to implement the work being also sealed on the back side to semiconductor chip 5 Sequence preferably exposes in advance the back side 4.These sequence of operations are known as transfer printing process.In addition, in the back for making semiconductor wafer 1 In the case that segmentation process etc. is implemented in the state of exposing in face 4, it is not necessarily to above-mentioned transfer printing process, can be realized the letter of manufacturing process Change.
Firstly, being illustrated to above-mentioned transfer printing process.
It in the present embodiment, can be under the configuration status for maintaining semiconductor chip 5, by semiconductor by transfer printing process The bonding plane of chip 5 is changed to opposite side.Specifically, as shown in Fig. 4 (c), overleaf 4 shape for being pasted with cutting film 20 Under state, transfer member 30 is attached in a manner of the entire circuit forming face (interarea 3) across multiple semiconductor chips 5.At this point, turning Print component 30 can be attached in a manner of covering the whole surface of solder projection 2 and the entire circuit forming face of semiconductor chip 5, It can also be in such a way that the circuit forming face of the transfer member 30 and semiconductor chip 5 be discontiguous, only to cover solder projection 2 The mode of a part on surface attaches (with reference to Fig. 9 (a)).In manufacturing method involved in present embodiment, transferred by control The attaching degree (length of embedment of solder projection 2) of component 30 can use following resin composition for encapsulating semiconductor 49 The region of resin seal is adjusted in the process being sealed.
Then, as shown in Fig. 4 (d), cutting film 20 is removed from semiconductor chip 5.As a result, in the shape for attaching cutting film 20 Transfer member 30 is attached under state, is later removed the cutting film 20, thus, it is possible to not change to be formed between each semiconductor chip 5 Gap interval and transfer member 30 is attached at semiconductor chip 5.In addition, cutting film 20 is preferably reducing the cutting film 20 It is removed after adaptation between semiconductor chip 5 from semiconductor chip 5.Specifically, following methods can be enumerated: by right The bonding site of cutting film 20 and semiconductor chip 5 carries out such as ultraviolet light irradiation or heat treatment, and makes to form the bonding site Cutting film 20 adhesive layer deterioration, thus reduce adaptation.
In addition, transfer member 30 is not particularly limited, for example, it is preferable to constitute below, that is, has both and be resistant to for solidifying Following resin composition for encapsulating semiconductor 49 and apply heat degree heat resistance and be fixed on the transfer member 30 Semiconductor chip 5 without departing from degree cementability.Transfer member 30 can be cementability adhesive tape monomer, or to by The plate-shaped member of the formation such as metal or plastics attaches cementability adhesive tape and assigns rigid component.In addition, in present embodiment, example As used the plate-shaped member in the metal comprising 42 alloys to attach transfer member made of cementability adhesive tape.
By process until the present moment, structural body 7 shown in Fig. 4 (d) is obtained.The structural body 7 has with flowering structure, That is, the structural body 7 has adhering part (transfer member 30) and is attached at the more of the bonding plane of adhering part (transfer member 30) A semiconductor chip 5, multiple semiconductor chips 5 are mutually configured across specified interval, and the circuit shape of multiple semiconductor chips 5 The bonding plane of adhering part (transfer member 30) is attached at face (interarea 3).That is, as the structural body 7 for preparing present embodiment Process, may include: the side opposite with circuit forming face of semiconductor wafer 1 face (back side 4) attach cutting film 20 In the state of, by 1 singualtion of semiconductor wafer, obtain the process for being attached at multiple semiconductor chips 5 of state of cutting film 20； Make the region that multiple semiconductor chips 5 are pasted in cutting film 20 Directional Extension in film surface, to make adjacent semiconductor The process that interval (gap 11) between chip 5 is extended to specified interval；It is (main with the circuit forming face of multiple semiconductor chips 5 Face 3) process that attaches adhering part with the mode of the Nian Jie face contact of adhering part (transfer member 30)；With in multiple semiconductors Chip 5 is attached in the state of the bonding plane of adhering part, the process that cutting film 20 is removed from semiconductor chip 5.
Then, by multiple half in the state that the interarea 3 of multiple semiconductor wafers 5 is attached at adhesive layer (transfer member 30) Conductor chip seals together.Specifically, preparing the semiconductor sealing resin of liquid on supporting substrate as shown in Fig. 4 (e) Composition 49.It is used for example, being configured on mold release film 50 (supporting substrate) by melting the encapsulating semiconductor in flow regime Resin combination 49.That is, the resin composition for encapsulating semiconductor 49 for being in flow regime in mold release film 50 is be bonded with interarea 3 It is oppositely disposed at the back side 4 of multiple semiconductor chips 5 of transfer member 30.
Then, as shown in Fig. 4 (f), the resin composition for encapsulating semiconductor 49 in flow regime is crimped on multiple The face (back side 4) of the side opposite with circuit forming face of semiconductor chip 5.Then, semiconductor can be made by heat treatment Resin composition for encapsulating 49 is solidified to form sealing material layer 40.Between between adjacent semiconductor chip 5 Sealing material layer 40 is filled every (gap 12).In turn, it can use sealing material layer 40 with cover semiconductor chip 5 and circuit The face (back side 4) of the opposite side of forming face and the mode of side 9 are sealed.For example, it is also possible to utilize sealing material layer 40 Filling is formed in the interval between adjacent semiconductor chip 5, and the side exposed with the whole or part of solder projection 2 The top surface of semiconductor chip 5 and side sealing material layer 40 are sealed by formula.Alternatively, it is also possible in multiple semiconductor cores Lateral surface in piece 5 positioned at the side 9 of the semiconductor chip 5 of periphery forms sealing material layer 40.
In the present embodiment, when picking up made semiconductor chip 5 using collet chuck, encapsulating semiconductor can be utilized It is protected with the solidified body (sealing material layer 40) of resin combination by the adsorbed position of the collet chuck.Thereby, it is possible to partly to lead The solidified body of body resin composition for encapsulating 49 covers and protects the face of the side opposite with circuit forming face of semiconductor chip 5 In the state of side, semiconductor chip 5 obtained is picked up using operating devices such as collet chucks.Therefore, according to the present embodiment Related manufacturing method can prevent the impact because applying when picking up semiconductor chip 5 using operating devices such as collet chucks in advance And a possibility that causing the semiconductor chip 5 damaged.
Here, the so-called resin composition for encapsulating semiconductor 49 in flow regime, can be in a molten state Compositions of thermosetting resin can be liquid resin composition, or be shaped at membranaceous or sheet resin combination In the resin combination of soft state.As the configuration method of resin composition for encapsulating semiconductor 49, it can be configured and be wrapped with lamination Film containing resin composition for encapsulating semiconductor can also be configured by encapsulating comprising resin composition for encapsulating semiconductor Cream.
Here, the process about sealing semiconductor chips, enumerates and uses solid granular resin combination as semiconductor The case where resin composition for encapsulating, as an example, is described in detail.
It is not particularly limited using the method for 49 sealing semiconductor chips 5 of resin composition for encapsulating semiconductor, Ke Yiju Out: transfer moudling, compression forming methods, injection moulding, laminating method etc., preferably fixed semiconductor chip 5 are not easy to produce The compression forming methods of raw positional shift.In addition, carrying out compression forming when sealing semiconductor chips 5, granular also can be used Resin combination carries out resin seal.In addition, the detailed content about resin composition for encapsulating semiconductor 49 is described below.
Specifically, setting contains the tree of particulate resins composition between the upper mold and lower die of compression mold Rouge material supply container.Then, the half of adhesive layer (transfer member 30) will be pasted with using the fixing means of clamping, absorption etc Conductor chip 5 is fixed on the side in the upper mold and lower die of compression mold.Hereinafter, enumerating with opposite with circuit forming face Semiconductor chip 5 is fixed on the feelings of the upper mold of compression mold by the face of the side mode opposite with resin material supply container Condition as an example, is illustrated.
Then, under reduced pressure, the upper mold of mold and the interval of lower die are reduced on one side, on one side by constituting resin material supply The particulate resins composition of weighing is supplied and to be had to lower die by the resin material feed mechanism of the baffle of container bottoms etc. In lower die die cavity.In the mould cavity, need to stand mold release film 50 in advance.Particulate resins composition is in lower die mould as a result, Intracavitary to be heated to predetermined temperature, as a result, it is possible to prepare the semiconductor sealing resin group of molten condition in mold release film 50 Close object 49.Then, by making the upper mold of mold in conjunction with lower die, and molten is pressed to the semiconductor chip 5 for being fixed on upper mold The resin composition for encapsulating semiconductor 49 of state.Thereby, it is possible to the resin composition for encapsulating semiconductor 49 using molten condition Landfill is formed in the interval between adjacent semiconductor chip 5, and can be covered using resin composition for encapsulating semiconductor 49 The top surface and side of lid semiconductor chip 5.Then, it keeps making state of the upper mold of mold in conjunction with lower die on one side, makes half on one side Conductor resin composition for encapsulating 49 solidifies.
Here, preferably make to become decompression state in mold on one side, carry out resin seal on one side when carrying out compression forming, More preferably become vacuum condition.Thereby, it is possible to not stay to be not filled by part to the interval being formed between adjacent semiconductor chip 5 And filling semiconductor resin composition for encapsulating 49 well.
Forming temperature when compression forming is not particularly limited, and preferably 50~200 DEG C, particularly preferred 80~180 DEG C.Separately Outside, briquetting pressure is not particularly limited, preferably 0.5~12MPa, particularly preferred 1~10MPa.Moreover, molding time preferably 30 seconds ~15 minutes, particularly preferred 1~10 minute.By the way that forming temperature, pressure, time are set as above range, can prevent from producing The part of the raw resin composition for encapsulating semiconductor 49 for being not filled by molten condition and semiconductor chip 5 occur the two of positional shift Kind situation.
Then, (is split by the sealing material layer 40 in the gap 12 to the side 9 for being formed in semiconductor chip 5 Two segmentation process), it can obtain and be formed with multiple semiconductor chips 5 of sealing material layer 40 in side 9 and the back side 4.
Specifically, as shown in Fig. 5 (a), firstly, mold release film 50 of the removing configuration at the back side (face 41) of sealant 40.
Then, as shown in Fig. 5 (b), the sealing material layer 40 in the gap 12 for being located at semiconductor chip 5 is split.It will The segmentation width of second segmentation process is set as L3.It can be controlled by adjusting the second segmentation width L3 and remain in the close of side 9 The film thickness of closure material layer 40.
Specifically, for example, interval 12 will be filled in the state that transfer member 30 is attached at semiconductor chip 5 Resin composition for encapsulating semiconductor 49 solidified body (sealing material layer 40) cutting, thus monolithic chemical conversion by sealing material layer Multiple semiconductor chips 5 of 40 sealings.At this point, transfer member 30 can be cut off together with sealing material layer 40, it can also not The state for cutting off and maintaining across multiple semiconductor chips 5 and attaching is examined from the viewpoint for the productivity for improving semiconductor device 8 Consider, when by 5 singualtion of semiconductor chip, is preferably set to not cut off transfer member 30 and be able to maintain across semiconductor chip 5 And the state attached.In addition, cutting blade, laser etc. can be used in the singualtion of above-mentioned semiconductor chip 5.
Then, as shown in Fig. 5 (c), transfer member 30 is removed from semiconductor device 8.Thereby, it is possible to make this embodiment party Semiconductor device 8 involved in formula.In addition, transfer member 30 is preferably reducing between the transfer member 30 and semiconductor device 8 Adaptation after from the semiconductor chip 5 remove.Specifically, following methods can be enumerated: by transfer member 30 and half The bonding site of conductor chip 5 carries out such as ultraviolet light irradiation or heat treatment, makes to form the transfer member of the bonding site 30 Adhesive layer deterioration, thus reduces adaptation.
In addition, semiconductor device 8 obtained also can according to need and be installed on substrate.In addition, when will be made When semiconductor device is installed on substrate, the known devices such as flip chip bonder or die bonder can be used.
According to above situation, semiconductor device 8 can be obtained by the manufacturing method of the semiconductor device of present embodiment.
Related manufacturing method according to the present embodiment can obtain semiconductor chip 5 below, the semiconductor chip 5 can cover in the solidified body (sealing material layer 40) using resin composition for encapsulating semiconductor and protect semiconductor chip 5 The side opposite with circuit forming face face and side in the state of, be picked up using operating devices such as collet chucks.As a result, can It enough prevents the operating devices such as collet chuck from directly contacting with semiconductor chip 5, and resin composition for encapsulating semiconductor can be passed through Solidified body (sealing material layer 40) mitigation 5 application of semiconductor chip is rushed when being picked up using operating devices such as collet chucks It hits.Therefore, according to the present embodiment involved in manufacturing method, can prevent in advance because being picked up using operating devices such as collet chucks The impact that applies when taking and a possibility that cause semiconductor chip 5 damaged.That is, manufacturer involved according to the present embodiment Method can be mitigated because the impact applied when being adsorbed and picked up using operating devices such as collet chucks to semiconductor chip 5 is brought Influence.Therefore, related manufacturing method can manufacture reliable compared with existing manufacturing method according to the present embodiment The excellent semiconductor device 8 of property.In addition, manufacturing method involved according to the present embodiment, can not configure after singualtion Multiple semiconductor chips 5 obtained are subjected to resin seal together on substrate.Therefore, with existing manufacturing method phase Than production efficiency can be made to improve tremendously.In addition, the half of the acquisition of manufacturing method involved in present embodiment will be utilized When conductor device 8 is mounted on substrate, since sealing material layer 40 and substrate are isolated structure, it is also able to suppress sealing material What is generated between the bed of material 40 and substrate is closely sealed bad, can further increase reliability.
In the present embodiment, protective film 10 the side opposite with circuit forming face to semiconductor wafer 1 face into For protecting the circuit forming face of the semiconductor wafer 1 when row grinding, but as aftermentioned in the third embodiment, also have It covers in the function and present embodiment of the cutting film 20 used when having 1 singualtion of semiconductor wafer in present embodiment and partly leads The function for the transfer member 30 that the face and side of the side opposite with circuit forming face of body chip 5 and while being sealed use. Therefore, from the viewpoint of production efficiency, manufacturing method involved in aftermentioned third embodiment is more excellent, according to this embodiment party Manufacturing method involved in formula uses different adhering parts 10 and 30 in each manufacturing process, therefore also has to maintain Intensity of the adhering part 10 and 30 etc. and the advantage that can be used separately etc..I.e. according to the present embodiment involved in manufacturer Method can precisely make semiconductor device excellent in reliability.
Semiconductor device involved in present embodiment is illustrated.
Fig. 1 and Fig. 2 is the sectional view for indicating an example of semiconductor device 8 involved in present embodiment.
As depicted in figs. 1 and 2, semiconductor device 8 involved in present embodiment has: semiconductor chip 5；Solder projection 2, the lower surface (interarea 3) of semiconductor chip 5 is set；With sealing material layer 40, cover semiconductor chip 5 top surface and The whole or part of at least part in side, solder projection 2 is exposed.
Specifically, semiconductor device 8 shown in FIG. 1 has: semiconductor chip 5, interarea 3 are formed with circuit；Sealing material The bed of material 40 covers the entire side 9 and the entire back side 4 of semiconductor chip 5；With convex block (solder projection 2), in overlook view Under, sealing material layer 40 is formed with around semiconductor chip 5, and convex block is made only in 3 region of interarea of semiconductor chip 5 On.
Semiconductor device 8 involved in present embodiment has in the top surface (back side 4) and side 9 of semiconductor chip 5 The semiconductor chip 5 that at least part is covered by sealing material layer 40.As a result, when manufacturing semiconductor device 8, even if utilizing cylinder Folder picks up semiconductor chip 5, can also prevent the semiconductor chip 5 damaged in advance.Therefore, by involved in present embodiment Manufacturing process semiconductor device 8 obtained is excellent in reliability compared with existing semiconductor device.
As shown in Figure 1, the lower surface (interarea 3) of semiconductor chip 5 is integrally exposed.In other words, the interarea of semiconductor chip 5 3 whole unsealed material layers 40 cover.I.e. the interarea 3 of semiconductor chip 5 can be with sealing material layer 40 and top surface (face 41) face 45 of opposite side forms the same face.Here, so-called the same face is the rough surface for referring to allow transfer member 30 The convex substantially the same face of inevitable dimple in the techniques such as degree.That is, in the semiconductor device 8 of Fig. 1, the entirety of solder projection 2 The structure for covering and exposing with unsealed material layer 40.
On the other hand, in the semiconductor device of Fig. 28, a part and weldering of the lower surface (interarea 3) of semiconductor chip 5 A part of material convex block 2 is covered by sealing material layer 40.In other words, in the interarea 3 of semiconductor chip 5, than the configuration of peripheral part There is the unsealed covering of material layer 40 in the region of the region of solder projection 2 more in the inner part and exposes.Solder projection 2 has a part It is covered from 3 side of interarea of semiconductor chip 5 towards opposite side by sealing material layer 40, but the knot that remaining front end is exposed Structure.
The semiconductor device 8 of Fig. 1 and Fig. 2 can be realized sealing material layer 40 when being installed on substrate and not contact with substrate And the structure of the two separation.That is, in the present embodiment, sealing material layer 40 can have blow-by to installing semiconductor chip The structure of 5 installation base plate.
Related semiconductor device 8 according to the present embodiment, when the semiconductor device 8 is installed on substrate, with The structure that substrate is bonded on the existing semiconductor device of sealing material is different.That is, can be realized sealing material layer 40 and installation The structure of the discontiguous the two separation of substrate.Its result is capable of providing the semiconductor device than the miniaturization of existing semiconductor device 8.In addition, since to be bonded on the structure of existing semiconductor device of sealing material different for structure and the substrate of semiconductor device 8, Therefore motherboard can not also be directly mounted at via built-in inserted plate.Moreover, because semiconductor device 8 can be realized sealing material layer 40 do not contacted with substrate and structure that the two separates, therefore be able to solve the substrate generated in existing semiconductor device and sealing The closely sealed bad problem in the interface of material.Therefore, it compared with existing semiconductor device, can be realized also excellent in terms of reliability Different semiconductor device 8.Moreover, because semiconductor device 8 have it is (close using the solidified body of resin composition for encapsulating semiconductor Closure material layer 40) cover and protect semiconductor chip 5 the side opposite with circuit forming face face and side state knot Structure, therefore compared with existing semiconductor device, it is also excellent in terms of crumpling resistance.
In addition, whole or part exposing of the semiconductor device 8 involved in present embodiment due to solder projection 2, because This operability is excellent, can be used in various techniques.Specifically, semiconductor device 8 involved in present embodiment can be installed In the various substrates such as motherboard, built-in inserted plate and lead frame.
< second embodiment >
The manufacturing method of the semiconductor device of second embodiment is illustrated.
Fig. 9 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
Different aspect is in second embodiment, in the transfer printing process (Fig. 4 (c)) of first embodiment, makes A part of solder projection 2 on 30 embedded with semi-conductor chip 5 of transfer member and not with 3 face contact of interarea of semiconductor chip 5.
Specifically, as shown in Fig. 9 (a), by transfer member 30 with cover solder projection 2 a part and not with semiconductor The mode that the circuit of chip 5 forms face contact is attached at semiconductor chip 5.Under this configuration state, by semiconductor chip 5 one Play sealing.
In the present embodiment, the resin composition for encapsulating semiconductor 49 of liquid condition is in addition to being filled in semiconductor chip The face (back side 4) of 5 side opposite with circuit forming face and side 9 also fill up the circuit forming face in semiconductor chip 5 (interarea 3).Thereby, it is possible to utilize the covering of sealing material layer 40 to the side of semiconductor chip 59, the side at the back side 4 and interarea 3 Formula is sealed together.According to second embodiment, can also obtain effect same as the first embodiment, more particularly into One step inhibits fragmentation when operation.
Fig. 8 is the sectional view for indicating an example of semiconductor device 8 involved in present embodiment.
Semiconductor device 8 shown in Fig. 8 is covered in the lower surface (interarea 3) of semiconductor chip 5 entirety by sealing material layer 40 It is different from the first embodiment in terms of lid.In addition, a part of the front end of convex block (solder projection 2) has from sealing material 40 structure outstanding of layer, and expose.
About semiconductor device 8 shown in Fig. 8, also in the same manner as first embodiment, the top surface and side of semiconductor chip 5 At least part in face is covered by sealing material layer 40.Accordingly, with respect to semiconductor device 8 shown in Fig. 8, also implement with first Mode similarly, be able to solve generated in existing semiconductor device because using collet chuck pick up semiconductor chip when apply rush Hit and cause the problem of semiconductor chip breakage.Therefore, semiconductor device 8 involved in present embodiment and existing semiconductor Device is compared, and the excellent semiconductor device of reliability aspect can be become.
Moreover, about semiconductor device 8 shown in Fig. 8, also in the same manner as first embodiment, due to solder projection 2 A part is exposed, therefore when the semiconductor device 8 to be installed on substrate, can be realized sealing material layer 40 and do not connect with substrate The structure of touching and the two separation.
< third embodiment >
The manufacturing method of the semiconductor device of third embodiment is illustrated.
Figure 10 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
Manufacturing method involved in present embodiment can simplify without the transfer printing process of first embodiment.That is, It can implement the first segmentation process and together in the state that the interarea 3 of semiconductor chip 5 is pasted with adhesive layer (protective film 10) Sealing process.Specifically, the multiple of state for preparing the bonding plane for having protective film 10 and being attached at the protective film 10 partly lead The structural body 7 of body chip 5 can directly be sealed and partly be led maintaining protective film 10 to be attached at the state of multiple semiconductor chips 5 Body chip 5.
In addition, the process for preparing structural body 7 in embodiment includes: with the circuit forming face (interarea of semiconductor wafer 1 3) in the state of attaching adhering part with the mode of the Nian Jie face contact of adhering part (protective film 10), semiconductor wafer 1 is single Piece obtains the process for being attached at multiple semiconductor chips 5 of state of adhering part；With make in adhering part be pasted with it is more The region of a semiconductor chip 5 Directional Extension in film surface, and the interval between adjacent semiconductor chip 5 is made to be extended to regulation Interval.
Hereinafter, being illustrated to above-mentioned operation.
As shown in Figure 10 (a), it will be pasted with 1 singualtion of semiconductor wafer of the state of protective film 10 in interarea 3, and make It is pasted with multiple semiconductor chips 5 of the state of protective film 10.In addition, making protective film 10 when by 1 singualtion of semiconductor wafer It is not cut off, the state that thus, it is possible to keep being pasted with multiple semiconductor chips 5 obtained.
Then, as shown in Figure 10 (b), such as the Directional Extension in the face of semiconductor chip 5 of protective film 10 can also be made, and The interval between adjacent semiconductor chip 5 is set to be extended to specified interval.Between making between semiconductor chip 5 Direction in the face of adhering part (protective film 10) is interposed between isotropically to extend.
Then, as shown in Figure 10 (c) and (d), make resin composition for encapsulating semiconductor 49 in flow regime with it is more The face of the side opposite with circuit forming face of a semiconductor chip 5 is contacted, between adjacent semiconductor chip 5 between Semiconductor chip is covered every filling semiconductor resin composition for encapsulating 49, and using resin composition for encapsulating semiconductor 49 The face and side of 5 side opposite with circuit forming face and be sealed.
By above method, the semiconductor device 8 for having structure identical with first embodiment can be obtained.In addition, root According to present embodiment, effect same as the first embodiment can be also obtained.Moreover, manufacturer according to the present embodiment Method can simplify the manufacturing process of semiconductor device 8, therefore compared with existing manufacturing method, production efficiency can be made into one It walks and improves tremendously.
The 4th embodiment > of <
The manufacturing method of the semiconductor device of 4th embodiment is illustrated.
Figure 12 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
In the fourth embodiment, can implement to make the segmentation width L3 in the second segmentation process than in the first segmentation process The narrow narrow process of cutting width of segmentation width L1.That is, in the fourth embodiment, reducing segmentation width this respect and the The other embodiments such as one embodiment are different.
Firstly, the interarea 3 of semiconductor wafer 1 is attached at protective film 10 (adhesive layer) as shown in Figure 12 (a).Then, such as Shown in Figure 12 (b), cut from 4 side of the back side of semiconductor wafer 1.Under section observation, it will be formed by first time cutting Gap 11 width be set as segmentation width L1.Later, as shown in Figure 12 (c), guarantor is attached in the interarea 3 of semiconductor wafer 1 Multiple semiconductor chips 5 are sealed together in the state of cuticula 10.The shape on the side of semiconductor chip 59 and the back side 4 as a result, At sealing material layer 40.In addition, the gap 11 in the side of semiconductor chip 59 is filled with sealing material layer 40.
Then, as shown in Figure 12 (d), along cutting region to the gap 11 between adjacent semiconductor chip 5 Sealing material layer 40 cut.It is wide by segmentation is set as by the width for cutting the gap formed for the second time under section observation Spend L3.Hereafter, the semiconductor device 8 of present embodiment can be obtained by removing protective film 10.
In the present embodiment, as cutting method, blade cutting or laser cutting can be used.In addition, as change The method of cutting width, can be used for example reduction blade width, or reduce the irradiation diameter of laser, or by cutting method from knife Piece is changed to laser, or reduces the method etc. of the sword number of blade.
By reducing cutting width, the film of the sealing material layer 40 on the side 9 for remaining in semiconductor chip 5 can be adjusted Thick thickness.Thereby, it is possible to so that the film thickness of the sealing material layer 40 on the side 9 of semiconductor chip 5 is sufficiently thickend.Therefore, energy Enough fragmentations inhibited when operating, can be realized the structure for improving the reliability of semiconductor device.In addition, in order to increase semiconductor die The Effective number of chips of piece 1 can also reduce segmentation width L3 in the state of reducing and dividing width L1.Thereby, it is possible to improve It imitates chip-count and improves above-mentioned reliability.
In the present embodiment, the lower limit value for dividing width L1 for example can be set to 50 μm or more, also can be set to 60 μm More than.It is easy the filling semiconductor resin composition for encapsulating between semiconductor chip 5 as a result,.Divide the upper limit value of width L1 Such as it can be set to 150 μm hereinafter, also can be set to 100 μm or less.Thereby, it is possible to increase effective chip of semiconductor wafer 1 Number.
In the present embodiment, it is not particularly limited as segmentation width L3 as long as being less than above-mentioned segmentation width L1.Point The lower limit value for cutting width L3 for example can be set to 10 μm or more, also can be set to 20 μm or more.Thereby, it is possible to improve the control of cutting Property processed.The upper limit value of segmentation width L3 for example can be set to 50 μm hereinafter, also can be set to 40 μm or less.Thereby, it is possible to ensure The film thickness of sealing material layer 40 on the side 9 of semiconductor chip 5.Therefore, in the fourth embodiment, can sufficiently obtain with The identical effect of first embodiment.
The 5th embodiment > of <
The manufacturing method of the semiconductor device of 5th embodiment is illustrated.
Figure 13 is the figure for illustrating an example of the manufacturing method of semiconductor device involved in present embodiment.
It include forming external connection on the interarea 3 of semiconductor wafer 1 after sealing process in the 5th embodiment The process of convex block (solder projection 2), this point are different from the first embodiment.That is, in the first embodiment, being formed After convex block, implement the first segmentation process and together sealing process, but in the 5th embodiment, implements the first segmentation process Together after sealing process, convex block is formed.Later, implement the second segmentation process.It as a result, not only can be in semiconductor chip 5 Interarea 3 form wiring layer and convex block, and can be in formation wiring layer more more outward than the region and convex block.
Hereinafter, being illustrated to each process.
Firstly, preparing to be formed with the semiconductor wafer 1 of circuit in interarea 3 as shown in Figure 13 (a).In addition, becoming in interarea The structure of the state of (wiring layer (not shown)) not formed on 3 and solder projection 2.Then, for example, semiconductor wafer 1 interarea 3 attach protective film 10.
Then, as shown in Figure 13 (b), implement above-mentioned first segmentation process and together sealing process.Also extension can be implemented Process.
Later, as shown in Figure 13 (c), protective film 10 is removed.At this point, the interarea 3 and sealing material of multiple semiconductor chips 5 Expose in the face 45 of the side opposite with top surface (face 41) of layer 40.These interareas 3 and face 45 can form same plane.
Then, on the interarea 3 of these semiconductor chips 5 and wiring (not shown) is formed on the face 45 of sealing material layer 40 Layer and solder projection 2.Solder projection 2 can be not only formed on interarea 3, but also can be formed in the face of sealing material layer 40 On 45.Thereby, it is possible to expand the spacing width of semiconductor chip 5.Later, list is carried out by implementing above-mentioned second segmentation process Piece.By above method, semiconductor device 8 shown in Figure 14 (d) can be obtained.
The detailed content of each component used in present embodiment is illustrated.
Hereinafter, to resin composition for encapsulating semiconductor 49, cutting film 20, transfer member involved in present embodiment 30, the composition of protective film 10 and mold release film 50 is illustrated.
< resin composition for encapsulating semiconductor >
Hereinafter, the mode that resin composition for encapsulating semiconductor is granular resin combination is described in detail, But not limited to this.
Resin composition for encapsulating semiconductor involved in present embodiment preferably comprises epoxy resin as it and constitutes material Material.As epoxy resin, for example, have the monomer, oligomer, polymer of 2 or more epoxy groups whole in 1 intramolecular, epoxy The molecular weight and molecular structure of resin are not particularly limited.Specifically, can enumerate: biphenyl type epoxy resin, bisphenol-A type ring The Cristalline epoxy resins such as oxygen resin, bisphenol f type epoxy resin, Stilbene type epoxy resin, hydroquinone type epoxy resin；Cresols phenol The novolaks type rings such as Novolac type epoxy resin, phenol novolak type epoxy resin, naphthol novolac type epoxy resin Oxygen resin；The phenol aralkyl type asphalt mixtures modified by epoxy resin of the phenol aralkyl type epoxy resin of the skeleton containing phenylene, the skeleton containing biphenylene The phenol aralkyl-type epoxy resins such as the naphthols aralkyl-type epoxy resin of rouge, the skeleton containing phenylene；Tris-phenol type asphalt mixtures modified by epoxy resin The trifunctionals type epoxy resin such as rouge, alkyl-modified tris-phenol type epoxy resin；Dicyclopentadiene-modified phenol type epoxy tree The modified phenols type epoxy resin such as rouge, terpene modified phenol type epoxy resin；The ring containing heterocycle such as epoxy resin containing triazine core Oxygen resin etc. can be used one of these or be used in combination of two or more.
In addition, being not particularly limited, as the method for obtaining granular resin combination for example, with lower section Method: it the resin combination of melting mixing is supplied to have is made of with discoid bottom surface the cylindric peripheral part of multiple apertures Rotor inside, using make rotor rotate and obtain centrifugal force, obtain the resin combination (below by aperture Referred to as " centrifugation powder method ".)；After each material composition being pre-mixed using mixing machine, utilize roller, kneader or extruder etc. After kneading machine carries out heating mixing, through supercooling, pulverizing process become crushed material, using sieve to the crushed material carry out coarse grain and The removal of micro mist and obtain (hereinafter also referred to " grinding screen point-score ".)；After each material composition is pre-mixed using mixing machine, Carry out heating mixing using the extruder in mould mouth of the screw front end portion setting configured with multiple apertures, and to from configuration in mould The aperture of mouth is in the molten resin that strand form squeezes out, and is cut off using the cutter for sliding rotation substantially in parallel with mould mouth face And obtain (hereinafter also referred to " thermal cutting method ".) etc..Either method can pass through selection compounding conditions, centrifugal condition, screening item Part, cutting condition etc. and obtain needed for size distribution or grain density.As especially preferred preparation method, to be centrifuged powder method processed, Thus obtained granular resin combination can steadily show required size distribution or grain density, therefore remove It is preferred in terms of sending the conveying on path or preventing cementation.In addition, centrifugation powder method processed can make particle surface to a certain degree It is upper smoothened, therefore the case where also stick to each other there is no particle or become larger with the frictional resistance on conveying road surface, prevent to The bridge joint (blocking) of the supply mouth of transport path and the aspect for preventing the delay in transport path are also preferred.In addition, centrifugation system Powder method uses centrifugal force in the molten state and is formed, therefore becomes the state in particle comprising a degree of gap, can Reduce grain density to a certain extent, therefore conveying when to compression forming is advantageous.
On the other hand, grinding screen point-score needs the processing method to a large amount of micro mists and coarse grain that generate by screening to grind Study carefully, but screening plant etc. is in the existing manufacturing line of resin composition for encapsulating semiconductor because use, it can be straight It connects using existing manufacturing line, is preferred in this aspect.In addition, about grinding screen point-score, because setting melting before crushing The selection of sieve etc. when selection, the screening of the selection of sheet thickness when rouge sheet material, pulverization conditions when crushing or sieve is used It is more in the factor for capableing of independent control for showing size distribution of the invention, it is accordingly used in being adjusted to the side of required size distribution The option of method is more, is preferred in this aspect.In addition, thermal cutting method also for example can add thermal cutting in the front end of extruder Existing manufacturing line is directly utilized in the degree of mechanism, is preferred in this aspect.
< cutting film >
Cutting film 20 involved in present embodiment can be not switched off when carrying out singualtion to semiconductor wafer 1 And keep the film for being attached at the state of semiconductor chip 5 obtained.The cutting film 20, as long as semiconductor wafer can be bonded in 1, and it is small with the positional shift of semiconductor chip 5, then it is not particularly limited.As cutting film 20, such as can have in support membrane Superimposed layer has the multi-layer laminate structure of adhesive layer.In addition, cutting film 20 also can have and heating or irradiating ultraviolet light Make the function that bonding force changes smaller.Thereby, it is possible to improve the fissility from adherend (semiconductor chip 5).
The constituent material of support membrane is not particularly limited, such as can be containing selected from polyethylene, polypropylene, ethylene-propylene Copolymer, polyolefin, polybutene, polybutadiene, polymethylpentene, polyvinyl chloride, polyvinylidene chloride, vinyl chloride copolymer, Polyethylene terephthalate, polybutylene terephthalate (PBT), polyethylene naphthalate, polyurethane, ethylene-acetate Vinyl ester copolymers, ethylene-(methyl) acrylic copolymer, ethylene-(methyl) acrylate copolymer, gather ionomer Styrene, vinyl polyisoprene, polycarbonate, polyphenylene sulfide, polyether-ether-ketone, acrylonitrile-butadiene-styrene (ABS) copolymerization The resin of one or more of object, polyimides, polyetherimide, polyamide, fluororesin etc..
In addition, in order to improve the adaptation with adhesive layer, surface chemically or physically is can be implemented in the surface of support membrane Processing.In addition, in support membrane, in the range of lossless invention effect, can containing various additives (filler, plasticizer, Antioxidant, fire retardant, antistatic agent).
In addition, the adhesive layer as dicing tape, can be used by comprising acrylic acid series bonding agent, rubber series bonding The bonding that first resin combination of agent, vinyl alkyl ethers system bonding agent, silicone-based bonding agent, Polyester bonding agent etc. is constituted Oxidant layer.In these, acrylic acid series bonding agent can be used.
< transfer member (adhering part) >
Then, as described above, the preferably following composition of transfer member 30 involved in present embodiment, that is, have both resistance to benefit from The heat resistance of the degree of heat that applies and the transfer member is fixed in solidifying following resin composition for encapsulating semiconductor 49 Semiconductor chip 5 on 30 without departing from degree cementability composition.Specifically, transfer involved in present embodiment Component 30 is preferably structure made of laminated substrate layer and adhesive layer.
Adhesive layer is by the resin comprising being able to carry out cross-linking reaction and the resin group with the active compound of fluxing agent Object is closed to be constituted.As the resin for being able to carry out cross-linking reaction, for example: epoxy resin, oxetane resin, phenol Urea formaldehyde, (methyl) acrylate, unsaturated polyester resin, diallyl phthalate resin, maleimide tree Rouge etc. is classified as the resin of so-called thermosetting resin, alternatively, it is also possible to enumerate the thermoplastic with functional groups such as carboxyl, epoxy groups Property resin etc. is as the resin for being able to carry out cross-linking reaction.In these, it is preferable to use curability and keeping quality, solidfied material it is heat-resisting The epoxy resin of property, moisture-proof, good chemical resistance.
With the active compound of fluxing agent, as long as have the effect of by heating etc. removal metal oxide film, then without It is particularly limited to.For example, it is also possible to for active rosin, organic acids, amine, phenol, alcohol, the azine such as the organic compound with carboxyl etc. from Body is with fluxing agent activity or with the compound for promoting the active effect of fluxing agent.
As this with the active compound of fluxing agent, more specifically, can enumerate in molecule have at least one with The compound of upper carboxyl and/or phenolic hydroxyl group, the compound can be liquid, or solid.
In addition, can also also be filled out containing inorganic when having no special requirements to the characteristics such as heat resistance or dimensional stability, moisture-proof Fill agent.As this kind of inorganic filler, for example: talcum fires the silicic acid such as clay, unfired clay, mica, glass Salt；Titanium oxide, aluminium oxide, fused silica (melting preparing spherical SiO 2 melts broken silica), crystalline silica Deng powder etc. oxide；The carbonate such as calcium carbonate, magnesium carbonate, hydrotalcite；Aluminium hydroxide, magnesium hydroxide, calcium hydroxide etc. Hydroxide；The sulfate such as barium sulfate, calcium sulfate, calcium sulfite or sulphite, zinc borate, barium metaborate, aluminium borate, boric acid The borates such as calcium, Boratex；Nitride such as aluminium nitride, boron nitride, silicon nitride etc..These inorganic fillers can be used alone, It can also be used in mixed way.The SiO 2 powders such as preferred molten silica, crystalline silica in these particularly preferably melt Preparing spherical SiO 2.
By being contained in inorganic filler in resin combination, can be improved heat-resisting after solidifying resin combination Property, moisture-proof, intensity etc., and can be improved fissility of the adhesive layer with respect to semiconductor chip 5.In addition, inorganic filler Shape be not particularly limited, preferred spheroidal is preferred thereby, it is possible to provide as the adhesive layer without special anisotropy Resin combination.
Also, as substrate layer, as long as such as by the polyolefin such as polyethylene, polypropylene, ethylene-vinyl acetate c The heat resistance of the production such as object, polyester, polyimides, polyethylene terephthalate, polyvinyl chloride, polyamide, polyurethane or The film of good chemical resistance, then be able to use.The thickness of substrate layer is not particularly limited, it is usually preferred to 30~500 μm.
< protective film (adhering part) >
Then, protective film 10 is when the face of the side opposite with circuit forming face to semiconductor wafer 1 is ground Protect the film of circuit forming face.As long as the film that this protective film 10 is bonded semiconductor wafer 1, then be not particularly limited, for example, Structure made of lamination tape and adhesive layer.Also, as shown in Figure 10, protective film 10 is also sometimes used as half Guard block when conductor 1 singualtion of chip also makes the Directional Extension in face of protective film 10 sometimes, sometimes also for solidification half Conductor resin composition for encapsulating 49 and heated.Therefore, protective film 10 is preferably following is constituted, that is, is had both a degree of Scalability, the heat resistance and fixation for being resistant to the hot degree applied for curing semiconductor resin composition for encapsulating 49 Semiconductor chip 5 on protective film 10 without departing from degree cementability.
Protective film 10 is made of tape and adhesive layer.Alternatively, it is also possible to overleaf grind adhesive tape and glue Connect setting mold release film 50 between oxidant layer.The removing between tape and adhesive layer becomes easy as a result,.
Adhesive layer is by the resin group containing the resin for being able to carry out cross-linking reaction and with the active compound of fluxing agent Object is closed to be constituted.As the resin for being able to carry out cross-linking reaction, for example: epoxy resin, oxetane resin, phenol Urea formaldehyde, (methyl) acrylate, unsaturated polyester resin, diallyl phthalate resin, maleimide tree Rouge etc. is classified as the resin of so-called thermosetting resin, and can also enumerate the thermoplastic with functional groups such as carboxyl, epoxy groups Property resin etc. is as the resin for being able to carry out cross-linking reaction.In these, it is preferable to use curability and keeping quality, solidfied material it is heat-resisting The epoxy resin of property, moisture-proof, good chemical resistance.
With the active compound of fluxing agent, as long as having the effect of the chemical combination by the removal metal oxide film such as heating Object is then not particularly limited.For example, it is also possible to for active rosin, the organic acids such as the organic compound with carboxyl, amine, phenol, alcohol, Azine etc. itself is with fluxing agent activity or with the compound for promoting the active effect of fluxing agent.
As this with the active compound of fluxing agent, more specifically, can enumerate in molecule have at least one with The compound of upper carboxyl and/or phenolic hydroxyl group, the compound can be liquid, or solid.
In addition, as tape, as long as such as by the polyolefin such as polyethylene, polypropylene, ethane-acetic acid ethyenyl The production such as ester copolymer, polyester, polyimides, polyethylene terephthalate, polyvinyl chloride, polyamide, polyurethane it is resistance to Hot or good chemical resistance film can be used.The thickness of tape is not particularly limited, and usually can be set to 30~500 μm.
< mold release film >
Then, as long as there is mold release film 50 structure of excellent release qualities to be then not particularly limited, such as preferably have containing poly- The mold release film of the release layer of ester resin material.
Mold release film 50 involved in present embodiment is with the release layer (the first release layer) containing material in polyester resin Mold release film 50.
In mold release film 50 involved in present embodiment, so-called release layer refers to and at least configures the mold release film 50 right The face contacted with object is formed when as on object (also is indicated as " stripping surface " below.) resin layer, so-called polyester resin refers to The condensation polymer of polybasic carboxylic acid (dicarboxylic acids) and polyalcohol (glycol), and be the compound with multiple carboxyls (- COOH).
In addition, in the present embodiment, material in polyester resin is not particularly limited, and for example: poly- terephthaldehyde Sour glycol ester resin, polybutylene terephthalate (PBT) resin, polytrimethylene terephthalate resin, polyhexamethylene The polyalkylene terephthalates resin such as terephthalate resin., it is preferable to use polybutylene terephthalate in these Ester resin.
Mold release film 50 involved in present embodiment can form single layer structure, can also form multilayered structure.
More than, embodiments of the present invention are described, but these are example of the invention, can also be used above-mentioned Various compositions in addition.
In addition, in the above-described embodiment, when sealing semiconductor chips 5, enumerates and used using granular encapsulating semiconductor The case where progress compression forming of resin combination 49, is illustrated as an example, but can also pass through method of spin coating, printing Method, distribution method are coated with liquid semiconductor sealing resin group to the face of the side opposite with circuit forming face of semiconductor chip 5 It is made it dry after closing object 49, face that can also under an increased pressure to the side opposite with circuit forming face of semiconductor chip 5 Pressing is shaped to the membranaceous resin composition for encapsulating semiconductor 49 in soft state, is allowed to penetrate into, also can use hair Tubule phenomenon makes liquid semiconductor resin composition for encapsulating 49 flow into the interval between adjacent semiconductor chip 5.
Moreover, in the above-described embodiment, enumerating and being equipped with the semiconductor of multiple solder projections 2 using in circuit forming face Chip 1 and the case where manufacturing semiconductor device 8, are illustrated as an example, but are not installing multiple welderings using circuit forming face Expect the semiconductor wafer 1 of convex block 2, the unsealed material layer 40 of at least part for manufacturing the lower surface of semiconductor chip 5 covers Semiconductor device 8 rear process in, can after the circuit forming face of semiconductor chip 5 installs solder projection 2 installation to base Semiconductor chip 5 can also be electrically connected with substrate by wire bonding by plate.
In addition, processing slabbing also can be used includes semiconductor sealing resin group in sealing semiconductor chips 5 Close sealing material (the hereinafter referred to as sheet-like sealing material of object 49.) be laminated by the following method.
Firstly, installing the sheet-like sealing material prepared with roll shape to the device that rolls out of vacuum pressure type laminating machine, connect It is connected to devices for taking-up.Then, the semiconductor wafer 1 for being pasted with protective film 10 is transported to diaphragm (elastic membrane) formula laminating machine portion. Then, under reduced pressure, when starting pressurization, sheet-like sealing material is heated to predetermined temperature and becomes molten condition, passes through later Diaphragm pressurizes to the sheet-like sealing material of molten condition, and presses semiconductor wafer 1, and thus, it is possible to close using the sheet Closure material fills the notch 20 for being formed in semiconductor wafer 1, and can utilize sheet-like sealing material covering semiconductor wafer 1 The face of the side opposite with circuit forming face.Later, solidify sheet-like sealing material by the stipulated time.Thereby, it is possible to will be partly Conductor chip 5 seals.
In addition, to sheet-like sealing material require higher precision flatness when, can also using diaphragm type laminating machine into It is additional to be formed using the pressurization operation for being adjusted to high-precision flat pressurizing device after row pressurization.
When carrying out above-mentioned laminated into type, the forming temperature in diaphragm (elastic membrane) formula laminating machine portion is preferably 50~120 DEG C, More preferably 80~110 DEG C.In addition, the briquetting pressure in diaphragm (elastic membrane) formula laminating machine portion is preferably 0.5~1MPa, more preferably For 0.6~0.9MPa.Moreover, the molding time in diaphragm (elastic membrane) formula laminating machine portion is preferably 30 seconds~5 minutes, more preferably 1~3 minute.By the way that the forming temperature in diaphragm (elastic membrane) formula laminating machine portion, pressure, time are set as above range, Neng Goufang Only generate the part for being not filled by sheet-like sealing material in a molten state.
When carrying out above-mentioned laminated into type, the pressed temperature of flat pressurizing device is preferably 80~130 DEG C, more preferably 90 ~120 DEG C.In addition, the briquetting pressure of flat pressurizing device is preferably 0.5~2MPa, more preferably 0.8~1.5MPa.Moreover, The molding time of flat pressurizing device is preferably 30 seconds~5 minutes, more preferably 1~3 minute.By by flat pressurizing device Pressed temperature, briquetting pressure, time are set as above range, can prevent to be not filled by flap seal material in a molten state The part of material.
In addition, by using the method laminated into type of above-mentioned sheet-like sealing material that institute after 5 sealing moulding of semiconductor chip is real The rear solidification temperature applied is preferably 150~200 DEG C, and more preferably 165~185 DEG C.Moreover, rear curing time is preferably 1 hour ~5 hours, more preferably 2 hours~4 hours.
This application claims excellent based on August 29th, 2014 Japanese publication Patent 2014-175135 proposed It first weighs, and its entire disclosure is introduced into the application.

Claims (14)

1. a kind of manufacturing method of semiconductor device characterized by comprising
Preparatory process prepares the semiconductor wafer that interarea is formed with circuit；
The semiconductor wafer is attached at adhesive layer by attached process；
First segmentation process, by dividing along the semiconductor wafer of the cutting region to the state for being attached at the adhesive layer It cuts, and obtains multiple semiconductor chips；
Sealing process, in the state that the interarea of multiple semiconductor chips is attached at the adhesive layer, by multiple institutes Semiconductor chip is stated to seal together, thus the gap between the side of the semiconductor chip and be formed with the circuit The solidified body comprising compositions of thermosetting resin is formed on the back side of the semiconductor chip of the opposite side of the interarea Sealing material layer, the compositions of thermosetting resin contain the epoxy resin for having 2 or more epoxy groups in 1 intramolecular；With
Second segmentation process passes through the sealing material to the gap being formed between the side of the semiconductor chip Layer is split, and is obtained and be formed with multiple semiconductor cores of the sealing material layer in the side and the back side Piece.
2. the manufacturing method of semiconductor device as described in claim 1, it is characterised in that:
The attached process includes:
The process that the interarea of the semiconductor wafer is attached at the adhesive layer；With
The process for keeping the film thickness of the semiconductor wafer thinning and removing the back side of the semiconductor wafer.
3. the manufacturing method of semiconductor device as claimed in claim 2, it is characterised in that:
100 μm of film thickness or more 300 μm or less of the semiconductor wafer after the process for keeping film thickness thinning.
4. the manufacturing method of semiconductor device according to any one of claims 1 to 3, it is characterised in that:
Segmentation width in second segmentation process is smaller than the segmentation width in first segmentation process.
5. the manufacturing method of semiconductor device according to any one of claims 1 to 3, it is characterised in that:
First segmentation process includes:
By in the state that the interarea of the semiconductor wafer is attached at the adhesive layer to the semiconductor wafer into The capable process divided and obtain multiple semiconductor chips；With
Expand the extension process at the interval between the adjacent semiconductor chip, alternatively,
First segmentation process includes:
By in the state that the back side of the semiconductor wafer is attached at the adhesive layer to the semiconductor wafer into The capable process divided and obtain multiple semiconductor chips；
Expand the extension process at the interval between the adjacent semiconductor chip；With
Another adhesive layer, and the adhesive layer that the back side will be attached at are attached in the interarea of the semiconductor wafer The process of removing,
The sealing process is implemented in the state of expanding the interval between the semiconductor chip.
6. the manufacturing method of semiconductor device as claimed in claim 5, it is characterised in that:
First segmentation process is dividing the semiconductor wafer and is implementing the expansion after the adhesive layer forms notch Open up process.
7. the manufacturing method of semiconductor device according to any one of claims 1 to 3, it is characterised in that:
In the preparation process, external connection convex block is formed on the interarea of the semiconductor wafer.
8. the manufacturing method of semiconductor device according to any one of claims 1 to 3, it is characterised in that:
After the sealing process, the work including forming external connection convex block on the interarea of the semiconductor wafer Sequence,
Implement second segmentation process later.
9. a kind of manufacturing method of semiconductor device characterized by comprising
Prepare the process of structural body, which has multiple the half of adhering part and the bonding plane for being attached at the adhering part Conductor chip, multiple semiconductor chips are mutually configured across specified interval, and the electricity of multiple semiconductor chips Road forming face is attached at the bonding plane of the adhering part；
It contacts the compositions of thermosetting resin in flow regime with multiple semiconductor chips, is filled out at the interval Fill the compositions of thermosetting resin, and cover the semiconductor chip using the compositions of thermosetting resin and circuit The face and side of the opposite side of forming face and the process being sealed, the compositions of thermosetting resin contain in 1 intramolecular Epoxy resin with 2 or more epoxy groups；With
Make the cured process of the compositions of thermosetting resin.
10. the manufacturing method of semiconductor device as claimed in claim 9, it is characterised in that:
The process for preparing the structural body includes:
In the state that the face paste of the side opposite with circuit forming face of semiconductor wafer has cutting film, by the semiconductor Chip singualtion obtains the process for being attached at multiple semiconductor chips of state of the cutting film；
Make the Directional Extension in film surface of the region for being pasted with multiple semiconductor chips in the cutting film, makes adjacent institute State the process that the interval between semiconductor chip is extended to the specified interval；
It is attached in a manner of the Nian Jie face contact of the adhering part by the circuit forming face of multiple semiconductor chips described The process of adhering part；With
In the state that multiple semiconductor chips are attached at the bonding plane of the adhering part, by the cutting film from described The process of semiconductor chip removing.
11. the manufacturing method of semiconductor device as claimed in claim 10, it is characterised in that:
In the process for making the interval between the adjacent semiconductor chip be extended to the specified interval, make the interval Direction isotropically extends in the face of the cutting film.
12. the manufacturing method of semiconductor device as claimed in claim 9, it is characterised in that:
The process for preparing the structural body includes:
The bonding is pasted in a manner of the Nian Jie face contact of the adhering part in the circuit forming face by semiconductor wafer In the state of component, by the semiconductor wafer singualtion, the multiple semiconductors for being attached at the state of the adhering part are obtained The process of chip；With
Make the Directional Extension in film surface of the region for being pasted with multiple semiconductor chips in the adhering part, to make phase Interval between the adjacent semiconductor chip is extended to the specified interval.
13. the manufacturing method of semiconductor device as claimed in claim 12, it is characterised in that:
In the process for making the interval between adjacent semiconductor chip be extended to the specified interval, make described to be spaced in institute Direction in the face of adhering part is stated isotropically to extend.
14. the manufacturing method of the semiconductor device as described in any one of claim 9~13, which is characterized in that further include:
It will be filled in the solidified body cutting of the compositions of thermosetting resin at the interval, monolithic is melted by the thermosetting property tree Multiple semiconductor chips of oil/fat composition sealing.
CN201580046732.7A 2014-08-29 2015-08-20 The manufacturing method and semiconductor device of semiconductor device Active CN106796893B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014175135 2014-08-29
JP2014-175135 2014-08-29
PCT/JP2015/073438 WO2016031684A1 (en) 2014-08-29 2015-08-20 Production method for semiconductor device, and semiconductor device

Publications (2)

Publication Number Publication Date
CN106796893A CN106796893A (en) 2017-05-31
CN106796893B true CN106796893B (en) 2019-09-20

Family

ID=55399577

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580046732.7A Active CN106796893B (en) 2014-08-29 2015-08-20 The manufacturing method and semiconductor device of semiconductor device

Country Status (5)

Country Link
JP (1) JPWO2016031684A1 (en)
KR (1) KR101968428B1 (en)
CN (1) CN106796893B (en)
TW (1) TWI710035B (en)
WO (1) WO2016031684A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017217307A1 (en) * 2016-06-16 2017-12-21 株式会社村田製作所 Semiconductor component, white-light-emitting diode device, and semiconductor component production method
JP6777815B2 (en) * 2017-05-10 2020-10-28 三井化学株式会社 Manufacturing method of semiconductor devices and intermediates of semiconductor devices
CN110637355B (en) * 2017-05-22 2023-12-05 株式会社力森诺科 Method for manufacturing semiconductor device and extension band
JP6990577B2 (en) * 2017-12-22 2022-01-12 東レエンジニアリング株式会社 Mounting method and mounting device
JP7093953B2 (en) 2019-02-27 2022-07-01 株式会社デンソー Semiconductor devices and their manufacturing methods
TWI795696B (en) * 2020-12-04 2023-03-11 吳聲欣 Semiconductor device package structure and manufacturing method thereof
CN113192851B (en) * 2021-04-29 2024-03-29 长沙新雷半导体科技有限公司 Wafer packaging method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09107046A (en) 1995-10-11 1997-04-22 Hitachi Chem Co Ltd Semiconductor package
JP3456462B2 (en) * 2000-02-28 2003-10-14 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP4508396B2 (en) * 2000-10-30 2010-07-21 パナソニック株式会社 Chip-type semiconductor device and manufacturing method thereof
JP2002141444A (en) * 2000-11-01 2002-05-17 Sony Corp Semiconductor device and method of manufacturing the same
US7169691B2 (en) * 2004-01-29 2007-01-30 Micron Technology, Inc. Method of fabricating wafer-level packaging with sidewall passivation and related apparatus
JP5534594B2 (en) 2010-03-30 2014-07-02 リンテック株式会社 Sheet sticking method and wafer processing method
JP2013189544A (en) * 2012-03-14 2013-09-26 Unitika Ltd Resin composition and thermoset elastomer obtained by heat curing the same
JP2013209503A (en) * 2012-03-30 2013-10-10 Nippon Steel & Sumikin Chemical Co Ltd Epoxy resin composition and cured product thereof
JP2013237780A (en) * 2012-05-15 2013-11-28 Hitachi Chemical Co Ltd Phenol compound, method for producing the same, resin composition and electronic component device

Also Published As

Publication number Publication date
KR101968428B1 (en) 2019-04-11
JPWO2016031684A1 (en) 2017-06-22
KR20170048482A (en) 2017-05-08
TW201626470A (en) 2016-07-16
WO2016031684A1 (en) 2016-03-03
CN106796893A (en) 2017-05-31
TWI710035B (en) 2020-11-11

Similar Documents

Publication Publication Date Title
CN106796893B (en) The manufacturing method and semiconductor device of semiconductor device
CN105489510B (en) The manufacturing method and semiconductor device of semiconductor device
KR20120106623A (en) Highly heat conductive film-shaped adhesive composition, highly heat conductive film-shaped adhesive and method for producing semiconductor package by using the highly heat conductive film-shaped adhesive
TWI691004B (en) Method for manufacturing semiconductor device and semiconductor device
TW201618179A (en) Film for semiconductor device production, method for producing film for semiconductor device production, and method for semiconductor device production
KR20140002533A (en) Encapsulating layer-covered semiconductor element, producing method thereof, and semiconductor device
KR20160037935A (en) Sheet for sealing and method for manufacturing semiconductor device using said sheet for sealing
JP2014210909A (en) Manufacturing method of semiconductor device
TWI624914B (en) Resin sheet for electronic component sealing, resin sealed semiconductor device, and method for manufacturing resin sealed semiconductor device
JP2016096308A (en) Semiconductor device manufacturing method
TWI698962B (en) Method for manufacturing semiconductor device
JP6677966B2 (en) Sealing sheet with separator and method of manufacturing semiconductor device
JP2015126129A (en) Method of manufacturing electronic component package
WO2015072378A1 (en) Sealing resin sheet and method for producing electronic component package
JP7257731B2 (en) resin sheet
CN116670829A (en) Composition for adhesive, film-like adhesive, semiconductor package using film-like adhesive, and method for manufacturing semiconductor package
CN116848208A (en) Adhesive composition, film-like adhesive, dicing die-bonding integrated film, and semiconductor device and method for manufacturing same
CN110240871A (en) Sheet for sealing
CN116685654A (en) Film-like adhesive, dicing die-bonding integrated film, and semiconductor device and method for manufacturing same
KR20100111136A (en) Unified dicing die bonding film and semiconductor packaging method using the same
JP2015097232A (en) Method of manufacturing electronic component package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant