TWI795696B - Semiconductor device package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor device package structure and a manufacturing method thereof are provided. A wafer is provided, the wafer having a plurality of semiconductor device and a plurality of cutting regions intersecting with one another defined thereon. The semiconductor devices each have a contact pad disposed on an active surface thereof. The wafer is disposed on a temporary adhesive, and then the wafer is cut along the cutting regions. After a space between any two adjacent ones of the semiconductor devices is enlarged, all of the semiconductor devices are disposed on a supporting plate. A molding material is formed to cover the semiconductor devices to form an initial mold body, in which the molding material is filled between spaces defined by any two adjacent ones of the semiconductor devices and connects the semiconductor devices. The initial mold body has a first side and a second side, and each of the semiconductor devices is disposed with the active surface and the bottom surface thereof facing toward the first side and the second side, respectively. The initial mold body is separated from the supporting plate. A cutting process is performed on the initial mold body to form a plurality of semiconductor device package structures.

Description

Semiconductor element packaging structure and manufacturing method thereof

The invention relates to a packaging structure of a semiconductor element and a manufacturing method thereof, in particular to a packaging structure of a semiconductor element without a substrate and a manufacturing method thereof.

In the existing packaging technology, the chip is usually placed on the lead frame or the packaging substrate by wire bonding technology or surface-mount technology, and then the molding compound is used to ) to package the chip together with the lead frame or the packaging substrate to form an electronic component packaging structure, such as a quad flat no-lead package (QFN) structure or a double-sided flat no-lead package (Dual Flat No-Lead Package, DFN) structure. However, it is difficult to further reduce the volume of the electronic packaging structure with the lead frame or the packaging substrate.

In order to further reduce the volume of the packaging structure of electronic components, Wafer Level Chip Scale Package (WLCSP) process and Fan-Out Wafer Level Packaging (Fan-Out WLP) process have become the technical means often used in packaging chips . In the wafer-level chip size packaging process or the fan-out wafer level packaging process, in order to reduce the volume of the chip after packaging as much as possible, the entire wafer will be thinned first, and then the thinned wafer will be cut. After forming the plurality of separate wafers, the plurality of wafers are again packaged.

In the manufacturing method of the chip package provided by the patent case of the Republic of China Patent Publication No. I683415, the upper surface of the wafer is first cut to form a plurality of grooves, and then a patterned photoresist layer is formed in the grooves, and then the wafer is The lower surface is thinned. Afterwards, after forming an insulating layer on the lower surface of the wafer, the patterned photoresist layer and the insulating layer are cut along each groove to form a plurality of chip packages.

However, when using the above process to manufacture chip packages, the width of the dicing tool is limited, and the width of the groove needs to be larger than the width of the dicing tool to avoid damage to the chip when cutting the patterned photoresist layer and insulating layer. In addition, the width of the dicing line of the wafer must be wider than the width of the groove, so as to avoid damage to the wafer when forming the groove. That is to say, if the above process is used to package the chip, the width of the dicing line of the wafer will be limited by the subsequent process and cannot be reduced. In this way, a part of the area of the wafer will be reserved as a dicing line and cannot be used for manufacturing components, resulting in a reduction in the number of chips that can be manufactured from a single wafer, and is not conducive to reducing the process cost.

The technical problem to be solved by the present invention is to provide a semiconductor element packaging structure and its manufacturing method for the deficiencies in the prior art, which can form a protective layer on the cut surface of the wafer after dicing, and form a protective layer on the front and back of the wafer, thereby An electronic component package is formed. In addition, the width of the dicing line can be further reduced to increase the area of the wafer used for manufacturing devices, thereby reducing the process cost.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a semiconductor element packaging structure, which includes: providing a wafer, wherein the wafer defines a plurality of semiconductor elements and interlaced a plurality of dicing regions, wherein each of the semiconductor elements includes at least one pad disposed on the active surface; the wafer is disposed on a temporary adhesive layer, and along a plurality of the dicing Cutting the wafer in a region to form a plurality of semiconductor elements separated from each other; expanding the distance between the plurality of semiconductor elements; setting all the expanded semiconductor elements on a carrier board; forming a mold The sealing material covers a plurality of semiconductor elements to form an initial package, wherein the molding material is filled between the plurality of semiconductor elements to connect the plurality of semiconductor elements, the initial package has a first side and a second side, The active surface and a bottom surface of each semiconductor element correspond to the first side and the second side respectively; the initial packaging body and the carrier board are separated; and a cutting step is performed on the initial packaging body to form a plurality of semiconductor element packaging structures.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a substrate-less semiconductor element packaging structure, which includes a semiconductor element, a molding layer, and a conductive and thermally conductive layer. The semiconductor element has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface. The semiconductor element includes at least one pad disposed on the active surface. The molding layer covers the side surface of the semiconductor element and exposes the bottom surface of the semiconductor element. The molding layer has two opposite first surfaces and a second surface, and the second surface is coplanar with the bottom surface of the semiconductor element. The conductive and heat-conducting layer is arranged on the bottom surface of the semiconductor element and the second surface of the molding layer.

In order to solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a substrate-less semiconductor device packaging structure, which includes a semiconductor device and a molding layer. The semiconductor element has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface. The semiconductor element includes at least one pad disposed on the active surface. The molding layer covers the side surface of the semiconductor element and the bottom surface of the semiconductor element. The thickness of the molding layer is between 10 to 50 μm, and has two opposite one first surface and one second surface.

One of the beneficial effects of the present invention is that the semiconductor device packaging structure and manufacturing method provided by the present invention can be achieved by "setting the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of cutting areas, To form a plurality of semiconductor elements separated from each other", "expanding the distance between a plurality of semiconductor elements", "setting all the expanded semiconductor elements on a carrier board" and "forming a molding material to cover a plurality of The above-mentioned semiconductor element to form an initial package" technical solution can further reduce the width of the dicing area, increase the number of semiconductor elements manufactured in the wafer, and further reduce the manufacturing cost. In addition, the packaging structure of the semiconductor element formed by the above method does not have a substrate, a lead frame or a bonding wire, so it can have a smaller volume.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

The following is an illustration of the implementation of the "semiconductor element packaging structure and manufacturing method" disclosed in the present invention through specific specific examples. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

[first embodiment]

Referring to FIG. 1 , it shows a flowchart of a method for manufacturing a semiconductor device package structure according to an embodiment of the present invention. The manufacturing method of the semiconductor element packaging structure according to the embodiment of the present invention can be used to package different types of chips, such as power chips or diode chips.

As shown in FIG. 1, in step S100, a wafer is provided, wherein the wafer defines a plurality of semiconductor elements and a plurality of cutting regions interlaced with each other, wherein each semiconductor element includes at least one semiconductor element disposed on the active surface Pad. Please refer to FIG. 2 and FIG. 3 together. FIG. 2 is a schematic diagram of step S100 of the manufacturing method of a chip package device according to an embodiment of the present invention, and FIG. 3 is a partial cross-sectional schematic diagram along line III-III in FIG. 2 .

In the embodiment of the present invention, the wafer 1 has completed the device manufacturing process, and a plurality of semiconductor devices 10 and a plurality of cutting regions 11 interlaced are defined on the upper surface 1 a of the wafer 1 . The material constituting the wafer 1 is usually silicon, but can also be other semiconductor materials, such as gallium arsenide or gallium nitride.

In detail, the plurality of cutting regions 11 include a plurality of cutting regions 11 extending along different directions, and the plurality of cutting regions 11 intersect each other. A plurality of semiconductor elements 10 are arranged in an array. Any two adjacent semiconductor elements 10 in the same column (that is, arranged along the first direction D1), or any two adjacent semiconductor elements 10 in the same row (that is, arranged along the second direction D2) , are separated from each other by the cutting zone 11.

In addition, in the present embodiment, the width w1 of the cutting area 11 (in the first direction D1 or the second direction D2 ) is about 40 μm to 100 μm. In this embodiment, the dicing region 11 has a smaller width w1 , allowing the wafer 1 to have more semiconductor elements 10 .

As shown in FIG. 3 , in the embodiment of the present invention, each semiconductor device 10 has an active surface 10a, a bottom surface 10b opposite to the active surface 10a, and a side surface 10c connected between the active surface 10a and the bottom surface 10b. In addition, each semiconductor device 10 has at least one pad 100 (two are shown in FIG. 2 as an example) disposed on the active surface 10a. It is worth mentioning that the redistribution circuit structure of the semiconductor element 10 can be pre-formed at the wafer stage, that is, before the wafer is cut.

The redistribution circuit structure may include a patterned dielectric layer (not shown) and at least one pad 100 . The patterned dielectric layer can cover the active surface 10 a of the semiconductor device 10 and has at least one opening. At least one pad 100 is formed in the opening to be electrically connected to a terminal of the semiconductor device 10 .

In one embodiment, the material of the pad 100 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof, but the present invention is not limited to the aforementioned examples. In addition, in one embodiment, the thickness of each pad 100 is about 5 μm to 100 μm. It should be noted that before the wafer is diced, the thickness of the wafer can be reduced to 100 μm to 250 μm. Therefore, the thickness of the semiconductor element 10 of the embodiment of the present invention is also about 100 μm to 250 μm.

In this embodiment, a part of the plurality of semiconductor devices 10 is taken as an example to illustrate the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention. Referring to FIG. 1 again, in step S110 , a wafer is disposed on the temporary adhesive layer, and the wafer is cut along a plurality of dicing regions to form a plurality of semiconductor elements separated from each other. In step S120, the distance between the plurality of semiconductor elements is expanded.

Please refer to FIG. 4 , which is step S120 in the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention. It should be noted that, in one embodiment, when the wafer 1 is placed on the temporary adhesive layer P11, the bottom surface of the wafer 1 faces the temporary adhesive layer P11. Accordingly, after the wafer 1 is diced, as shown in FIG. 4 , the active surface 10 a of each semiconductor element 10 faces upward, and the bottom surface 10 b is adhered to the temporary adhesive layer P11 .

In addition, when the wafer 1 is diced, due to the limitation of the dicing width, the entire dicing area 11 will not be removed. Therefore, after the wafer 1 is diced, the distance d1 between any two adjacent semiconductor elements 10 is substantially smaller than the width w1 of the dicing region 11 . Furthermore, the distance d1 between any two adjacent semiconductor elements 10 is about 40 μm to 80 μm.

As shown in FIG. 4, after dicing the wafer to form a plurality of separated semiconductor elements 10, by applying a horizontal direction (that is, along the first direction D1 and the second direction D2 in FIG. 2 ) to the temporary adhesive layer P11 ) to expand the distance d1 between the plurality of semiconductor elements 10 . In one embodiment, after expansion, the distance d1' between any two semiconductor elements 10 is about 100 μm to 200 μm.

In another embodiment, before the wafer 1 is diced, the wafer 1 may also be disposed on the temporary adhesive layer P11 with the lower surface 1 b facing upward. Therefore, referring to FIG. 5 , when a plurality of semiconductor elements 10 are disposed on the temporary adhesive layer P11 , they are disposed with the active surface 10 a facing the temporary adhesive layer P11 . Afterwards, an expanding step is performed to increase the distance d1 between two adjacent semiconductor elements 10 .

Referring to FIG. 1 again, in step S130, all the expanded semiconductor elements are placed on the carrier board. Please refer to FIG. 6 , which is a schematic diagram of step S130 in the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention. As shown in FIG. 6 , the active surface 10 a of each semiconductor element 10 faces the carrier plate P1 . It is worth noting that, in the embodiment of the present invention, after expanding the distance d1' of the plurality of semiconductor elements 10, the step of selecting the semiconductor elements 10 is not specifically performed, but all the semiconductor elements 10 are transferred and arranged on the carrier board P1 .

Referring to FIG. 6 , a plurality of semiconductor elements 10 are disposed on a carrier board P1 . In one embodiment, in this embodiment, the carrier board P1 has a base plate P10 and another temporary adhesive layer P11, and the material of the base plate P10 is silicon wafer, glass, ceramics, polymer or metal, for example, the present invention Not limited.

If when expanding, a plurality of semiconductor elements 10 are arranged on the temporary adhesive layer P11 with the active surface 10a facing upward, after the expansion is performed, the carrier plate P1 with another temporary adhesive layer P11 is first faced to the plurality of semiconductor elements. The active surfaces 10 a of the semiconductor elements 10 are arranged so that the active surfaces 10 a of the plurality of semiconductor elements 10 are bonded to the temporary adhesive layer P11 of the carrier board P1 .

Afterwards, the temporary adhesive layer P11 originally adhered to the bottom surfaces 10b of the plurality of semiconductor elements 10 is debonded. The debonding method can be selected according to the material of the temporary adhesive layer P11 by heating, irradiating ultraviolet light or laser light to remove the adhesive of the temporary adhesive layer P11 . For example, if the temporary adhesive layer is a UV debonding adhesive layer, the adhesive force of the temporary adhesive layer can be reduced by irradiating ultraviolet light, but the present invention is not limited thereto. Accordingly, when the plurality of semiconductor elements 10 are disposed on the carrier board P1, they are arranged with the active surface 10a facing the carrier board P1.

In another embodiment, when expanding, as shown in FIG. 5, a plurality of semiconductor elements 10 are arranged with the active surface 10a facing the temporary adhesive layer P11, and after the expansion, the temporary adhesive layer P11 together with A plurality of semiconductor elements 10 adhered thereto are directly disposed on the base plate P10.

Referring to FIG. 1 again, in step S140 , a molding material is formed to cover a plurality of semiconductor devices to form an initial package. Please refer to FIG. 7 . FIG. 7 is a schematic diagram of step S140 of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention. The molding material 2 is filled between the plurality of semiconductor elements 10 to connect the plurality of semiconductor elements 10 . The molding material 2 forms an initial package M1 together with the plurality of semiconductor elements 10 . The molding material 2 is, for example, a polymer material or a composite material, wherein the polymer material is such as polyimide (Polyimide, PI), benzocyclobutene (Benzocyclobutene, BCB), epoxy resin or silicone rubber, etc., and the composite The material is, for example, glass fiber reinforced thermosetting plastic, bulk molding material and other adhesive insulating or dielectric materials. The molding material 2 can be formed by compression molding or injection molding.

In this embodiment, the molding material 2 covers the bottom surface 10 b of each semiconductor element 10 , but does not cover the active surface 10 a of each semiconductor element 10 . That is to say, the molding material 2 covers the side surface 10 c and the bottom surface 10 b of each semiconductor device 10 .

As shown in FIG. 7 , the initial package M1 has a first side and a second side, and the active surface 10 a and the bottom surface 10 b of each semiconductor device 10 correspond to the first side and the second side, respectively. As shown in FIG. 5 , the active surface 10 a of each semiconductor device 10 corresponds to the first side of the initial package M1 , and the initial package M1 is the temporary adhesive layer P11 that contacts the carrier board P1 at the first side. Further, the molding material 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. In this embodiment, the first surface 2 a of the molding material 2 and the active surface 10 a of the semiconductor element 10 will jointly contact the temporary adhesive layer P11 of the carrier board P1 .

Referring to FIG. 1 , in step S150 , separate the initial package and the carrier board. In step S160 , a cutting step is performed on the initial package to form a plurality of semiconductor device package structures. Please refer to FIG. 8 . FIG. 8 is a schematic diagram of step S160 of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention. Separate the initial package M1 from the carrier board P1. In detail, when the temporary adhesive layer P11 is a UV debonding adhesive layer, ultraviolet light (UV light) can be used to irradiate the peelable adhesive layer to reduce the adhesive force between the peelable adhesive layer P11 and the initial package M1, and then The initial package M1 can be detached from the peelable adhesive layer P11 of the carrier board P1.

As shown in FIG. 8 , after the carrier board P1 is separated from the initial package M1 , a cutting step L1 is performed on the initial package M1 to form a plurality of semiconductor device packaging structures m1 . Please refer to FIG. 9 . FIG. 9 is a schematic cross-sectional view of the packaging structure of the semiconductor device according to the first embodiment of the present invention. The semiconductor device packaging structure m1 of this embodiment includes a semiconductor device 10 and a molding layer 2A.

As mentioned above, the semiconductor device 10 has an active surface 10a, a bottom surface 10b opposite to the active surface 10a, and a side surface 10c connected between the active surface 10a and the bottom surface 10b. The semiconductor element 10 is, for example, a power chip or other types of chips, which is not limited by the present invention. The semiconductor device 10 also has at least one pad 100 on the active surface 10a.

After the initial package M1 is cut, the molding material 2 wrapping around each semiconductor element 10 forms the molding layer 2A of FIG. 9 . Accordingly, the molding layer 2A covers the side surface 10 c and the bottom surface 10 b of the semiconductor device 10 to provide protection for the semiconductor device 10 . In this embodiment, the thickness T1 of the molding layer 2A is between 10 to 50 μm. In addition, the molding layer 2A has two opposite first surfaces 2a and second surfaces 2b. As shown in FIG. 7 , the active surface 10 a of the semiconductor device 10 and the pads 100 are exposed on the first surface 2 a of the molding layer 2A. In this embodiment, the active surface 10 a of the semiconductor device 10 is aligned with the first surface 2 a of the molding layer 2A. In addition, the pad 100 has a thickness of about 5 μm to 100 μm and protrudes from the active surface 10 a. Therefore, the top surface of the pad 100 is higher than the first surface 2 a of the molding layer 2A.

Please refer to FIG. 10 , which shows a flowchart of a method for manufacturing a semiconductor package device according to another embodiment of the present invention. The steps of the manufacturing method of this embodiment are the same as those of the manufacturing method shown in FIG. 1 and will not be repeated here. In this embodiment, after the initial package and the carrier board are separated, step S170 is further executed. In step S170, a thinning step is performed from the second side of the initial package, so that each semiconductor element is exposed on the second side of the initial package.

Please refer to FIG. 11 , which shows a schematic diagram of the semiconductor device packaging structure in step S170 according to another embodiment of the present invention. In detail, when performing the thinning step on the initial package M1, the initial package M1 is thinned from the second surface 2b of the molding material 2 toward the first surface 2a, so as to remove a part of the molding material 2 and thin Each semiconductor element 10 is formed. Thus, the semiconductor element 10 has a thinner thickness t2. In one embodiment, the thickness of the initial package M1 can be reduced to 25 μm to 75 μm. That is, the thickness t2 of each semiconductor element 10 in the initial package M1 is also thinned to 25 μm to 75 μm. In addition, in the thinned initial package M1, the bottom surface 10b' of each semiconductor element 10 will be exposed on the second surface 2b' of the molding material 2', and will be in contact with the second surface 2b of the molding layer 2'. 'Chezi.

It should be noted that since the semiconductor element 10 is encapsulated in the molding material 2, when the initial package M1 is thinned, the molding material 2 can provide protection for the semiconductor element 10, preventing the semiconductor element 10 from be damaged. That is to say, the method provided by the embodiment of the present invention can not only make the thickness of the semiconductor element 10 thinner, but also reduce the fragmentation rate of the semiconductor element 10 .

Referring to FIG. 12 , after step S170 is performed, step S160 may be directly performed to form a plurality of semiconductor element packaging structures. Further, referring to FIG. 11 and FIG. 12 , after the cutting step L1 is performed on the initial package M1 of FIG. 11 , a semiconductor device package structure m2 as shown in FIG. 12 can be formed.

In the semiconductor device packaging structure m2 of this embodiment, the molding layer 2B only covers the side surface 10c of the semiconductor device 10, but does not cover the active surface 10a and the bottom surface 10b' of the semiconductor device 10. In other words, the active surface 10 a of the semiconductor device 10 is exposed on the first surface 2 a of the molding layer 2B, and the first surface 2 a of the molding layer 2B is aligned with the active surface 10 a of the semiconductor device 10 . In addition, the bottom surface 10b' of the semiconductor device 10 is exposed on the second surface 2b' of the molding layer 2B.

It should be noted that, compared with the previous embodiment, the total thickness of the semiconductor device package structure m2 manufactured by the manufacturing method of the embodiment of the present invention may be thinner. Specifically, the total thickness of the semiconductor device packaging structure m2 may be between 25 μm and 75 μm.

Please refer to FIG. 10 again, after performing step S170, the manufacturing method of this embodiment may further perform step S180. In step S180 , an electrical and thermal conduction layer is formed on the second side of the initial package, wherein the electrical and thermal conduction layer directly contacts the bottom surface of each semiconductor element.

Please refer to FIG. 13 , which is a schematic diagram of step S170 in the manufacturing method of the semiconductor device package structure according to the third embodiment of the present invention. FIG. 13 may continue with step S170 , that is, after the initial package M1 is thinned, the conductive and thermal conduction layer 3 is formed on the second side of the initial package M1 . Furthermore, the conductive and heat-conducting layer 3 is formed on the second surface 2b' of the molding material 2' and the bottom surface 10b' of each semiconductor element 10.

The material of the conductive and heat-conducting layer 3 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof. In addition, each conductive and heat-conducting layer 3 may have a stacked structure, such as a stacked structure of titanium/copper, titanium/nickel/silver, titanium/copper/nickel/tin or titanium/copper/nickel/gold. The thickness of the conductive and thermally conductive layer 3 is about 1 μm to 5 μm. Afterwards, as shown in FIG. 11 , a cutting step L1 is performed on the initial package M1 and the conductive and heat-conducting layer 3 .

Please refer to FIG. 14 . FIG. 14 is a schematic cross-sectional view of a semiconductor device packaging structure according to a third embodiment of the present invention. Compared with the semiconductor element packaging structure m2 in FIG. 10 , the semiconductor element packaging structure m3 of this embodiment further includes a conductive and thermally conductive layer 3 , and the conductive and thermally conductive layer 3 is arranged on the bottom surface 10b' of the semiconductor element 10 and the molding layer 2B. second surface 2b'. The conductive and heat-conducting layer 3 can provide protection for the semiconductor element 10 and can be used for dissipating heat from the semiconductor element 10 .

It should be noted that, in the embodiment of FIG. 14 , the conductive junction of the semiconductor device 10 is located on the active surface 10 a of the semiconductor device 10 . However, in other embodiments, the conductive junction of the semiconductor device 10 may also be located on the bottom surface 10b. Accordingly, the number and position of the conductive junctions of the semiconductor device 10 are determined according to the type of the semiconductor device 10 , which is not limited by the present invention. Accordingly, when the bottom of the semiconductor device 10 has a conductive interface for electrically connecting to the outside, the conductive and heat-conducting layer 3 can be used as a pad, so that the semiconductor device 10 can be electrically connected to another electronic device or a circuit board.

In addition, in the semiconductor device packaging structure m3 of this embodiment, the thickness of the semiconductor device 10 is between 25 to 75 μm, and the thickness of the conductive and heat-conducting layer 3 is about 1 μm to 5 μm, so the total thickness of the semiconductor device packaging structure m3 can be less than 100 μm. Compared with the embodiment shown in FIG. 7 , the total thickness of the semiconductor device packaging structures m2 and m3 can be thinner. Specifically, the total thickness of the semiconductor element packaging structures m2, m3 may be between 25 μm and 100 μm.

In addition, it should be noted that the step of forming the molding material 2 can also be performed before disposing the plurality of semiconductor elements 10 on the carrier board P1 . Please refer to FIG. 15 , which is a flowchart of a manufacturing method of a semiconductor device package structure according to another embodiment of the present invention.

Steps S200 to S220 in this embodiment are respectively the same as steps S100 to S120 in FIG. 10 , and will not be repeated here. In step S230, a molding material is formed to cover the plurality of semiconductor elements to form an initial package, and all the plurality of semiconductor elements are placed on the carrier board. Please refer to FIG. 16 and FIG. 17 , which show a schematic diagram of step S230 of the manufacturing method of the semiconductor device package structure in FIG. 15 .

As shown in FIG. 16, in this embodiment, a plurality of semiconductor elements 10 are sandwiched between a first sheet molding material 21 and a second sheet molding material 22, and the first sheet molding A gap H1 is defined between the material 21 , the second sheet-shaped molding material 22 and any two semiconductor elements 10 .

Further, after dicing the wafer to form a plurality of semiconductor elements 10 that are separated from each other, the plurality of semiconductor elements 10 can be disposed on the temporary adhesive layer P11 as shown in FIG. 4 or FIG. 5 , and then the first Sheet molding compound 21. Since the first sheet-shaped molding material 21 also has adhesiveness, and can fix a plurality of semiconductor elements 10, after the first sheet-shaped molding material 21 is installed, the temporary adhesive layer P11 can be removed first, and then the second one can be installed. The sheet molding material 22 is used so that a plurality of semiconductor elements 10 are sandwiched between the first sheet molding material 21 and the second sheet molding material 22 .

Please refer to FIG. 16 , from the two opposite sides of the semiconductor element 10, the first sheet-shaped molding material 21 and the second sheet-shaped molding material 22 are pressed together to form a mold that fills the gap H1 and completely covers each semiconductor element 10. Molding material 2. In this embodiment, the second sheet-shaped molding compound 22 , the plurality of semiconductor elements 10 and the first sheet-shaped molding compound 21 are disposed on the carrier board P1 first, and then press-bonded.

Please refer to FIG. 17 , through the above steps, a plurality of semiconductor elements 10 will be embedded in the molding material 2 to form an initial package M2. As shown in FIG. 17 , in this embodiment, the molding material 2 covers the bottom surface 10 b and the active surface 10 a of each semiconductor element 10 . The initial package M2 has a first side and a second side, and the active surface 10 a and the bottom surface 10 b of each semiconductor device 10 located in the molding material 2 face the first side and the second side respectively. In this embodiment, the first surface 2 a of the molding material 2 is located on the first side of the initial package M2 , and the second surface 2 b of the molding material 2 is located on the second side of the initial package M2 .

Referring to FIG. 15 again, in step S240, the initial package and the carrier board are separated; in step S250, a thinning step is performed from the first side of the initial package. Please refer to FIG. 18 . In this embodiment, the initial package M2 is thinned from the first side of the initial package M2 to expose the pads 100 of each semiconductor device 10 . That is to say, a part of the molding material 2 covering the pads 100 of the semiconductor device 10 will be removed. Referring to FIG. 19 , after the thinning step is performed on the initial package M2, the first surface 2a' of the molding material 2' will be flush with the surface of the pad 100 of the semiconductor device 10. Referring to FIG. It should be noted that when the initial package M2 is thinned, a part of the pads 100 may also be removed.

Please refer to FIG. 15 again, in an embodiment, after step S250 is performed, step S280 may be directly performed. As shown in FIG. 19 , after the cutting step L1 is performed on the initial package M2 , a plurality of semiconductor device package structures can be formed.

Please refer to FIG. 20 , which is a schematic cross-sectional view of a semiconductor device package structure according to a fourth embodiment of the present invention. The semiconductor device packaging structure m4 includes a semiconductor device 10 and a molding layer 2C. In this embodiment, the molding layer 2C covers the active surface 10 a , the side surface 10 c and the bottom surface 10 b of the semiconductor device 10 , but exposes the pads 100 of the semiconductor device 10 . In one embodiment, the thickness of the molding layer 2C is between 10 to 50 μm. Accordingly, in the semiconductor device packaging structure m4 of this embodiment, all surfaces of the semiconductor device 10 (including the active surface 10a, the side surface 10c, and the bottom surface 10b) are covered by the molding layer 2C, and are relatively completely protected.

In addition, the molding layer 2C has two opposite first surfaces 2a' and second surfaces 2b. A height difference h1 is formed between the first surface 2a' and the active surface 10a of the semiconductor device 10, and the height difference h1 is between 10 μm and 80 μm. As shown in FIG. 18 , the first surface 2a' is flush with the surface of the pad 100 .

Please refer to FIG. 15 again, after performing step S250, the manufacturing method of the embodiment of the present invention may further perform step S260 and step S270, and then perform step S280. Further, in step S260, a thinning step is performed from the second side of the initial package, so that each semiconductor element is exposed on the second side of the initial package. In step S270 , a conductive and thermally conductive layer is formed on the second side of the initial package, wherein the conductive and thermally conductive layer covers and contacts the bottom surface of each semiconductor element.

Please refer to FIG. 21 , which shows a schematic diagram of step S260 of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention. It should be noted that the steps in FIG. 21 may continue with step S250 (refer to FIG. 18 ). That is to say, after performing the thinning step on the initial package M2 from the first side of the initial package M2, another thinning step is performed on the initial package M2 from the second side of the initial package M2 to expose each A bottom surface 10 b ′ of a semiconductor element 10 . Accordingly, in this embodiment, the initial package M2 undergoes two-stage thinning steps. In the thinned initial package M2, the bottom surface 10b' of each semiconductor element 10 will be exposed on the second surface 2b' of the molding material 2", and will be cut from the second surface 2b' of the molding layer 2". together.

Please refer to FIG. 22 . FIG. 22 is a schematic diagram of step S270 of a manufacturing method of a semiconductor device packaging structure according to another embodiment of the present invention. After the initial package M2 is thinned, a conductive and thermally conductive layer 3 is formed on the second side of the initial package M1 . Furthermore, the conductive and heat-conducting layer 3 is formed on the second surface 2b' of the molding material 2' and the bottom surface 10b' of each semiconductor element 10.

The material of the conductive and heat-conducting layer 3 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof. In addition, each conductive and heat-conducting layer 3 may have a stacked structure, such as a stacked structure of titanium/copper, titanium/nickel/silver, titanium/copper/nickel/tin or titanium/copper/nickel/gold. The thickness of the conductive and thermally conductive layer 3 is about 1 μm to 5 μm. Afterwards, as shown in FIG. 20 , the cutting step L1 is performed on the initial package M1 and the conductive and heat-conducting layer 3 .

Please refer to FIG. 23 . FIG. 23 is a schematic cross-sectional view of a semiconductor device package structure according to a fifth embodiment of the present invention. The semiconductor element packaging structure m5 of this embodiment includes a semiconductor element 10, a molding layer 2" and a conductive and thermally conductive layer 3. The molding layer 2D of this embodiment covers the active surface 10a and the side surface 10c of the semiconductor element 10, but does not Cover the bottom surface 10b' of the semiconductor element 10. The molding layer 2D has a first surface 2a' and a second surface 2b'. A height difference will be formed between the first surface 2a' of the molding layer 2D and the active surface 10a of the semiconductor element 10 h1, but the first surface 2 a ′ is flush with the surface of the pad 100 .

In addition, the second surface 2b' of the molding layer 2D is aligned with the bottom surface 10b' of the semiconductor device 10. The conductive and heat-conducting layer 3 is disposed on the second surface 2b' of the molding layer 2D and the bottom surface 10b' of the semiconductor element 10. Furthermore, in this embodiment, the conductive and heat-conducting layer 3 is in direct contact with the bottom surface 10b' of the semiconductor element 10 and the second surface 2b' of the molding layer 2D. The conductive and heat-conducting layer 3 can provide protection for the semiconductor element 10 and can be used for dissipating heat from the semiconductor element 10 . When the bottom of the semiconductor device 10 has a conductive interface for electrically connecting to the outside, the conductive and heat-conducting layer 3 can be used as a solder pad, so that the semiconductor device 10 can be electrically connected to another electronic device or a circuit board.

In addition, in the semiconductor device packaging structure m3 of this embodiment, the thickness of the semiconductor device 10 is between 25 to 75 μm, and the thickness of the conductive and heat-conducting layer 3 is about 1 μm to 5 μm, so the total thickness of the semiconductor device packaging structure m3 can be less than 100 μm.

It should be noted that, in the manufacturing method of another embodiment, the step S270 can also be omitted. As shown in FIG. 15, after step S260 is performed, step S280 is directly performed. In the packaging structure of the semiconductor element formed by the aforementioned manufacturing method, there is no conductive and heat-conducting layer 3, and the molding layer covers the active surface 10a and the side surface 10c of the semiconductor element 10, but exposes the bottom surface 10b' of the semiconductor element 10 .

[Advantageous Effects of Embodiment]

One of the beneficial effects of the present invention is that the semiconductor device packaging structure and manufacturing method provided by the present invention can be achieved by "setting the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of cutting areas, To form a plurality of semiconductor elements separated from each other", "expanding the distance between a plurality of semiconductor elements", "setting all the expanded semiconductor elements on a carrier board" and "forming a molding material to cover a plurality of The above-mentioned semiconductor element to form an initial package" can further reduce the width w1 of the dicing area 11, increase the number of semiconductor elements 10 in the wafer 1, and further reduce the manufacturing cost.

Furthermore, in the manufacturing method of the embodiment of the present invention, after the wafer 1 is diced, the pitch of the plurality of semiconductor elements 10 can be expanded first, and then all the semiconductor elements 10 can be placed on the carrier plate P1 for molding. In this way, the width w1 of the cutting area 11 is not limited by the subsequent molding process and the width of the cutting tool, but can be further reduced. In this way, the area of the wafer 1 that can be used to manufacture the semiconductor elements 10 can be increased, thereby increasing the number of semiconductor elements 10 in the same wafer 1 and reducing the manufacturing cost.

In addition, the manufacturing method provided by the embodiment of the present invention can form semiconductor element packaging structures m1~m5 without substrate, lead frame, and wire bonding, and the molding material 2 (2', 2") can also be used for the semiconductor element 10 Provide protection and improve the yield rate of semiconductor element packaging structures m1~m5.

On the other hand, this embodiment does not reduce the volume by thinning the wafer at the wafer stage, but cuts the wafer into a plurality of semiconductor elements 10, and forms the molding material 2 (2', 2" ) after covering the semiconductor element 10, the initial packaging body M1 (M2) is directly thinned. Accordingly, the thickness t1 of the semiconductor element 10 in the semiconductor element packaging structure m1 ~ m5 can be thinned in the initial packaging body M1 (M2) ) step, rather than in the step of thinning the wafer. Compared with the prior art method of controlling the thickness by thinning the entire wafer, the thinning of the initial package M1 (M2) can be more precisely controlled The thickness t1, t2 of the semiconductor element 10 or the total thickness of the semiconductor element packaging structure m1~m5. In addition, the technical means adopted in the embodiments of the present invention are less likely to cause damage to the semiconductor element 10, which can reduce the difficulty and cost of the thinning process.

In addition, using the manufacturing method of the semiconductor element packaging structure provided by the embodiment of the present invention, the semiconductor element 10 can be further thinned to less than 100 μm, so that the size of the semiconductor element packaging structures m1-m5 can be further reduced. Generally speaking, compared with the existing packaging technology, the semiconductor element packaging structures m1~m5 manufactured by the manufacturing method of the embodiment of the present invention do not have packaging substrates, lead frames and bonding wires, so the overall semiconductor element packaging structures m1~m5 Thickness can be thinner with smaller volume. That is to say, the volume of the semiconductor element packaging structures m1 - m5 is very close to the size of an unpackaged chip.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

1: Wafer 1a: Upper surface 1b: Lower surface m1~m5: semiconductor element packaging structure 10: Semiconductor components 10a: active surface 10b, 10b': bottom surface 10c: side surface 100: Pad 11: Cutting area w1: width of cutting area t1, t2: Thickness of semiconductor element 2,2’,2”: molding material 2A~2D: molding layer 2a, 2a': the first surface 2b, 2b': second surface 3: Conductive heat conduction layer M1, M2: initial package P1: Loading board P10: Bottom plate P11: Temporary adhesive layer L1: cutting step 21: The first sheet molding compound 22: Second sheet molding compound h1: height difference T1: Thickness H1: void d1, d1': spacing D1: the first direction D2: Second direction

FIG. 1 is a flow chart of a manufacturing method of a semiconductor device package structure according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a manufacturing method of a semiconductor device package structure before step S100 according to an embodiment of the present invention.

FIG. 3 is a schematic partial cross-sectional view along line III-III in FIG. 2 .

FIG. 4 is a schematic diagram of step S120 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention.

FIG. 5 is a schematic diagram of step S120 of a manufacturing method of a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of step S130 in the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention.

FIG. 7 is a schematic diagram of step S140 in the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention.

FIG. 8 is a schematic diagram of step S160 of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of the packaging structure of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a flowchart of a manufacturing method of a semiconductor device package structure according to another embodiment of the present invention.

FIG. 11 is a schematic diagram of step S170 in FIG. 10 in the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a semiconductor device package structure according to a second embodiment of the present invention.

FIG. 13 is a schematic diagram of step S180 in FIG. 10 in the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view of a semiconductor device package structure according to a third embodiment of the present invention.

FIG. 15 is a flowchart of a manufacturing method of a semiconductor device package structure according to another embodiment of the present invention.

FIG. 16 is a schematic diagram of step S230 in FIG. 15 in the manufacturing method of the semiconductor device package structure according to another embodiment of the present invention.

FIG. 17 is a schematic diagram of step S230 in FIG. 15 in the manufacturing method of the semiconductor device package structure according to another embodiment of the present invention.

FIG. 18 is a schematic diagram of step S250 in FIG. 15 in the manufacturing method of the semiconductor device package structure according to another embodiment of the present invention.

FIG. 19 is a schematic diagram of step S280 in FIG. 15 in the manufacturing method of the semiconductor device package structure according to another embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view of a semiconductor device package structure according to a fourth embodiment of the present invention.

FIG. 21 is a schematic diagram of step S260 in FIG. 15 in the manufacturing method of the semiconductor device package structure according to another embodiment of the present invention.

FIG. 22 is a schematic diagram of step S270 in FIG. 15 in the manufacturing method of the semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 23 is a schematic cross-sectional view of a packaging structure of a semiconductor device according to a fifth embodiment of the present invention.

S100~S160: process steps

Claims (16)

A method for manufacturing a packaging structure of a semiconductor element, which includes: providing a wafer, wherein the wafer defines a plurality of semiconductor elements and a plurality of dicing regions interlaced with each other, wherein each of the semiconductor elements includes at least one pad on the active surface; placing the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of cutting regions to form a plurality of semiconductor elements separated from each other; expanding The spacing between the plurality of semiconductor elements; the expanded plurality of semiconductor elements are all arranged on a carrier board, wherein the active surface of each of the semiconductor elements faces the carrier board; forming a A molding material covers a plurality of the semiconductor elements to form an initial package, wherein the molding material is filled between the plurality of semiconductor elements to connect a plurality of the semiconductor elements, and the molding material Covering the bottom surface of each of the semiconductor elements, but not covering the active surface of each of the semiconductor elements, the initial package has a first side and a second side, each of the semiconductor elements The active surface and a bottom surface respectively correspond to the first side and the second side; separate the initial package from the carrier board; and perform a cutting step on the initial package to form a plurality of A semiconductor element packaging structure; wherein, the total thickness of the semiconductor element packaging structure is between 25 μm and 150 μm. The manufacturing method according to claim 1, further comprising: performing a thinning step from the second side of the initial package, and after performing the cutting step, the bottom surface of the semiconductor element is exposed Outside a molding layer of the packaging structure of the semiconductor element. The manufacturing method as described in claim 1, further comprising: separating the initial After the primary package and the carrier board are formed, a thinning step is performed from the second side of the primary package, so that each of the semiconductor elements is exposed on the second side of the primary package. The manufacturing method according to claim 3, further comprising: after performing the thinning step from the second side of the initial package, forming a conductive A thermally conductive layer, wherein the conductive and thermally conductive layer directly contacts the bottom surface of each of the semiconductor elements. The manufacturing method according to claim 3, wherein said cutting step is performed directly after said thinning step is performed from said second side of said initial package. The manufacturing method according to claim 1, wherein the width of the cutting area is 40 μm to 80 μm, and after disposing the expanded plurality of semiconductor elements on the carrier board, any two of the semiconductor elements The pitch between them is 100 μm to 200 μm. A method for manufacturing a packaging structure of a semiconductor element, which includes: providing a wafer, wherein the wafer defines a plurality of semiconductor elements and a plurality of dicing regions interlaced with each other, wherein each of the semiconductor elements includes at least one pad on the active surface; placing the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of cutting regions to form a plurality of semiconductor elements separated from each other; expanding The spacing between a plurality of semiconductor elements; a plurality of semiconductor elements are sandwiched between a first sheet molding material and a second sheet molding material, wherein the first sheet molding A gap is defined between the sealing material, the second sheet molding material, and any two semiconductor elements; the first sheet molding material, the plurality of semiconductor elements, and the second The sheet-shaped molding material is arranged on a carrier plate, and pressed against the first sheet-shaped molding material and the second sheet molding material to form a molding material that fills the gap and completely covers each of the semiconductor elements to form an initial package, the initial package has a first side and a second side, the active surface and a bottom surface of each semiconductor element correspond to the first side and the second side respectively; the thinning is carried out by the first side of the initial package body a step of exposing at least one pad of each of the semiconductor elements; and performing a cutting step on the initial package to form a plurality of semiconductor element packaging structures; wherein, the overall structure of the semiconductor element packaging The thickness is between 25 μm and 150 μm. A method for manufacturing a packaging structure of a semiconductor element, which includes: providing a wafer, wherein the wafer defines a plurality of semiconductor elements and a plurality of dicing regions interlaced with each other, wherein each of the semiconductor elements includes at least one pad on the active surface; placing the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of cutting regions to form a plurality of semiconductor elements separated from each other; expanding The spacing between the plurality of semiconductor elements; all the expanded semiconductor elements are placed on a carrier board; a molding material is formed to cover the plurality of semiconductor elements to form an initial package, wherein , the molding material covers the active surface and the bottom surface of each of the semiconductor elements, so that each of the semiconductor elements is completely buried in the molding material, and the initial package has a first One side and a second side, the active surface and a bottom surface of each of the semiconductor elements correspond to the first side and the second side respectively; separate the initial packaging body from the carrier board; by performing a thinning step on the first side of the initial package to expose each at least one bonding pad of the semiconductor device; and performing a cutting step on the initial package to form a plurality of semiconductor device packaging structures; wherein the total thickness of the semiconductor device packaging structure is between 25 μm and 150 μm. The manufacturing method according to claim 8, wherein after performing the thinning step on the first side of the initial package, a first surface of the molding material and each of the semiconductor elements At least one of the bonding pad surfaces is flush with each other. The manufacturing method according to claim 9, before performing the cutting step, further includes: performing another thinning step from the second side of the initial package to expose each of the semiconductor elements the bottom surface; and forming a conductive and heat-conducting layer on the second side of the initial package, wherein the conductive and heat-conducting layer covers and contacts the bottom surface of each of the semiconductor elements. A semiconductor element packaging structure, which includes: a semiconductor element, which has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface, wherein the The semiconductor element includes at least one pad, which is arranged on the active surface; a molding layer, which covers the side surface of the semiconductor element, and exposes the bottom surface of the semiconductor element, and the molding layer It has two opposite first surfaces and a second surface, the second surface is coplanar with the bottom surface of the semiconductor element; and an electrical and thermal conduction layer is arranged on the bottom surface of the semiconductor element and the The second surface of the molding layer; wherein, the total thickness of the semiconductor element packaging structure is between 25 μm and 150 μm. The semiconductor device packaging structure according to claim 11, wherein the active surface of the semiconductor device is aligned with a first surface of the molding layer. The semiconductor element packaging structure according to claim 11, wherein the thickness of at least one of the pads is 5 μm to 100 μm, the molding layer covers the active surface, but exposes at least one of the pads, the first A height difference between a surface and the active surface of the semiconductor device is between 10 μm and 80 μm, and the first surface is flush with the surface of at least one pad. The semiconductor element packaging structure according to claim 11, wherein the thickness of the conductive and heat-conducting layer is between 1 μm and 5 μm, and the thickness of the semiconductor element is between 25 μm and 75 μm. The semiconductor element packaging structure according to claim 11, wherein the material of the conductive and heat-conducting layer is titanium, copper, silver, nickel, tin, gold or any combination thereof. A semiconductor element packaging structure, which includes: a semiconductor element, which has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface, wherein the The semiconductor element includes at least one pad, which is arranged on the active surface, and the thickness of at least one of the pads is 5 μm to 100 μm; and a molding layer, which covers the side surface of the semiconductor element and the The bottom surface, wherein the molding layer has a thickness of 10 to 50 μm and has two opposite first surfaces and a second surface, the molding layer covers the active surface of the semiconductor element, But at least one of the contact pads is exposed, and a height difference between the first surface and the active surface of the semiconductor element is between 10 μm and 80 μm, and the first surface and at least one of the contact pads The surfaces of the pads are aligned; wherein, the total thickness of the semiconductor element packaging structure is between 25 μm and 150 μm.

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