TW202224140A - Semiconductor device package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor device package structure and a manufacturing method thereof are provided. A wafer is provided, the wafer having a plurality of semiconductor device and a plurality of cutting regions intersecting with one another defined thereon. The semiconductor devices each have a contact pad disposed on an active surface thereof. The wafer is disposed on a temporary adhesive, and then the wafer is cut along the cutting regions. After a space between any two adjacent ones of the semiconductor devices is enlarged, all of the semiconductor devices are disposed on a supporting plate. A molding material is formed to cover the semiconductor devices to form an initial mold body, in which the molding material is filled between spaces defined by any two adjacent ones of the semiconductor devices and connects the semiconductor devices. The initial mold body has a first side and a second side, and each of the semiconductor devices is disposed with the active surface and the bottom surface thereof facing toward the first side and the second side, respectively. The initial mold body is separated from the supporting plate. A cutting process is performed on the initial mold body to form a plurality of semiconductor device package structures.

Description

Semiconductor element package structure and manufacturing method thereof

The present invention relates to a semiconductor element packaging structure and a manufacturing method thereof, in particular to a substrate-less semiconductor element packaging structure and a manufacturing method thereof.

In the existing packaging technology, the chip is usually arranged on a lead frame or a packaging substrate by wire bonding technology or surface-mount technology, and then a molding compound is used. ) Co-package the chip with the lead frame or the package substrate to form an electronic component package structure, such as a Quad Flat None-lead Package (QFN) structure or a Dual Flat No-lead Package (Dual). Flat No-Lead Package, DFN) structure. However, it is difficult to further reduce the volume of an electronic package structure having a lead frame or a package substrate.

In order to further reduce the volume of the electronic component packaging structure, the Wafer Level Chip Scale Package (WLCSP) process and the Fan-Out Wafer Level Packaging (Fan-Out WLP) process have become the technical means that are often used when packaging chips . In the wafer-level chip-scale packaging process or the fan-out wafer-level packaging process, in order to reduce the volume of the chip packaged as much as possible, the entire wafer will be thinned first, and then the thinned wafer will be cut. After forming the plurality of separate wafers, the plurality of wafers are again packaged.

In the manufacturing method of the chip package provided by the patent case of the Republic of China Patent Publication No. I683415, the upper surface of the wafer is first cut to form a plurality of grooves, and then a patterned photoresist layer is formed in the grooves. The lower surface is thinned. After that, after forming an insulating layer on the lower surface of the wafer, the patterned photoresist layer and the insulating layer are cut along each groove to form a plurality of chip packages.

However, when the chip package is fabricated by the above process, the width of the groove is limited by the width of the cutting tool, and the width of the groove needs to be larger than the width of the cutting tool to avoid damage to the chip when cutting the patterned photoresist layer and the insulating layer. In addition, the width of the dicing line of the wafer must be wider than the width of the groove to avoid damage to the wafer when the groove is formed. That is to say, by using the above-mentioned process to package the chip, the width of the scribe line of the wafer cannot be reduced due to the subsequent process. In this way, a part of the wafer area will be reserved as a dicing lane and cannot be used to manufacture components, resulting in a reduction in the number of chips that can be produced from a single wafer, which is also not conducive to reducing process costs.

The technical problem to be solved by the present invention is to provide a semiconductor element packaging structure and a manufacturing method thereof in view of the deficiencies of the prior art, which can form a protective layer on the cutting surface of the wafer after dicing, and form a protective layer on the front and back of the wafer, thereby An electronic component package is formed. In addition, the width of the scribe line can be further reduced, thereby increasing the area of the wafer used to manufacture components, thereby reducing the process cost.

In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a semiconductor device packaging structure, which includes: providing a wafer, wherein the wafer defines a plurality of semiconductor devices and is interlaced with each other. a plurality of dicing areas, wherein each of the semiconductor elements includes at least one pad disposed on the active surface; the wafer is disposed on a temporary adhesive layer, and along the plurality of dicing cutting the wafer to form a plurality of semiconductor elements separated from each other; expanding the spacing between the plurality of semiconductor elements; arranging all the expanded semiconductor elements on a carrier board; forming a mold The sealing material covers the plurality of semiconductor elements to form an initial package, wherein the molding material is filled between the plurality of semiconductor elements to connect the plurality of semiconductor elements, and the initial package has a first side and a second side, The active surface and a bottom surface of each semiconductor element correspond to the first side and the second side respectively; the initial package body and the carrier board are separated; and a cutting step is performed on the initial package body to form a plurality of semiconductor device package structures.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a substrate-less semiconductor element packaging structure, which includes a semiconductor element, a molding layer and a conductive and heat-conducting layer. The semiconductor element has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface. The semiconductor element includes at least one pad disposed on the active surface. The molding layer covers the side surface of the semiconductor element and exposes the bottom surface of the semiconductor element. The molding layer has two opposite first surfaces and a second surface, and the second surface is coplanar with the bottom surface of the semiconductor element. The conductive and heat-conductive layer is disposed on the bottom surface of the semiconductor element and the second surface of the molding layer.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a substrate-less semiconductor element packaging structure, which includes a semiconductor element and a molding layer. The semiconductor element has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface. The semiconductor element includes at least one pad disposed on the active surface. The molding layer covers the side surface of the semiconductor element and the bottom surface of the semiconductor element. The thickness of the molding layer is between 10 and 50 μm, and has two opposite first surfaces and a second surface.

One of the beneficial effects of the present invention is that, in the semiconductor device packaging structure and the manufacturing method thereof provided by the present invention, by "arranging the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of dicing regions, to form a plurality of semiconductor elements separated from each other", "to expand the spacing between the plurality of semiconductor elements", "to arrange all the expanded plurality of semiconductor elements on the carrier board", and "to form a molding material to cover a plurality of all semiconductor elements". The technical solution of forming an initial package body by using the above-mentioned semiconductor components can further reduce the width of the dicing area, increase the number of semiconductor components manufactured in the wafer, and further reduce the manufacturing cost. Besides, the semiconductor element package structure formed by the above method does not have a substrate, a lead frame or a wire bonding, so that it can have a smaller volume.

For a further understanding of the features and technical content of the present invention, please refer to the following detailed descriptions and drawings of the present invention. However, the drawings provided are only for reference and description, and are not intended to limit the present invention.

The following are specific embodiments to illustrate the embodiments of the "semiconductor element packaging structure and its manufacturing method" disclosed in the present invention, and those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to the actual size, and are stated in advance. The following embodiments will further describe the related technical contents of the present invention in detail, but the disclosed contents are not intended to limit the protection scope of the present invention. In addition, the term "or", as used herein, should include any one or a combination of more of the associated listed items, as the case may be.

[First Embodiment]

Referring to FIG. 1 , it shows a flowchart of a method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention. The manufacturing method of the semiconductor device package structure according to the embodiment of the present invention can be used to package different types of chips, such as power chips or diode chips.

As shown in FIG. 1 , in step S100 , a wafer is provided, wherein the wafer defines a plurality of semiconductor elements and a plurality of dicing regions interlaced with each other, wherein each semiconductor element includes at least one semiconductor element disposed on the active surface. pad. Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a schematic diagram of step S100 of a method for manufacturing a chip package device according to an embodiment of the present invention, and FIG. 3 is a partial cross-sectional schematic diagram of FIG. 2 along line III-III.

In the embodiment of the present invention, the wafer 1 has completed the device fabrication process, and the upper surface 1 a of the wafer 1 defines a plurality of semiconductor devices 10 and a plurality of intersecting dicing regions 11 . The material constituting the wafer 1 is usually silicon, but other semiconductor materials such as gallium arsenide or gallium nitride can also be used.

In detail, the plurality of cutting regions 11 include a plurality of cutting regions 11 extending along different directions, and the plurality of cutting regions 11 are staggered. A plurality of semiconductor elements 10 are arranged in an array. Any two adjacent semiconductor elements 10 located in the same column (that is, arranged along the first direction D1), or any two adjacent semiconductor elements 10 located in the same row (that is, arranged along the second direction D2) , are separated from each other by the cutting area 11 .

In addition, in this embodiment, the width w1 of the cutting region 11 (in the first direction D1 or the second direction D2 ) is about 40 μm to 100 μm. In this embodiment, the dicing area 11 has a smaller width w1 , which allows the wafer 1 to have more semiconductor elements 10 .

As shown in FIG. 3, in the embodiment of the present invention, each semiconductor element 10 has an active surface 10a, a bottom surface 10b opposite to the active surface 10a, and a side surface 10c connected between the active surface 10a and the bottom surface 10b. In addition, each semiconductor element 10 has at least one pad 100 (two are shown in FIG. 2 as an example) disposed on the active surface 10a. It is worth mentioning that the redistribution circuit structure of the semiconductor element 10 can be formed in advance at the wafer stage, that is, before the wafer is cut.

The redistribution circuit structure may include a patterned dielectric layer (not shown) and at least one pad 100 . The patterned dielectric layer can cover the active surface 10a of the semiconductor device 10 and has at least one opening. At least one pad 100 is formed in the opening to be electrically connected to the terminal of the semiconductor element 10 .

In one embodiment, the material of the pad 100 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof, but the present invention is not limited to the foregoing examples. In addition, in one embodiment, the thickness of each pad 100 is about 5 μm to 100 μm. It should be noted that, before the wafer is diced, the thickness of the wafer can be reduced to 100 μm to 250 μm. Therefore, the thickness of the semiconductor element 10 of the embodiment of the present invention is also about 100 μm to 250 μm.

In this embodiment, a part of a plurality of semiconductor elements 10 is taken as an example to describe the manufacturing method of the semiconductor element package structure according to the embodiment of the present invention. Referring to FIG. 1 again, in step S110 , the wafer is disposed on the temporary adhesive layer, and the wafer is cut along a plurality of dicing regions to form a plurality of semiconductor elements separated from each other. In step S120, the spacing between the plurality of semiconductor elements is expanded.

Please refer to FIG. 4 , which is a manufacturing method of a semiconductor device package structure according to an embodiment of the present invention in step S120 . It should be noted that, in one embodiment, when the wafer 1 is placed on the temporary adhesive layer P11 , the bottom surface of the wafer 1 is disposed toward the temporary adhesive layer P11 . Accordingly, after dicing the wafer 1, as shown in FIG. 4, the active surface 10a of each semiconductor element 10 faces upward, and the bottom surface 10b is attached to the temporary adhesive layer P11.

In addition, when the wafer 1 is diced, the entire dicing area 11 is not removed due to the limitation of the dicing width. Therefore, after dicing the wafer 1 , the distance d1 between any two adjacent semiconductor elements 10 is substantially smaller than the width w1 of the dicing region 11 . Further, the distance d1 between any two adjacent semiconductor elements 10 is about 40 μm to 80 μm.

As shown in FIG. 4 , after the wafer is diced to form a plurality of separated semiconductor elements 10 , a horizontal direction (that is, along the first direction D1 and the second direction D2 in FIG. 2 ) is applied to the temporary adhesive layer P11 ) to expand the distance d1 between the plurality of semiconductor elements 10 . In one embodiment, after expansion, the distance d1' between any two semiconductor elements 10 is about 100 μm to 200 μm.

In another embodiment, before the wafer 1 is diced, the wafer 1 may also be disposed on the temporary adhesive layer P11 with the lower surface 1b facing upward. Therefore, referring to FIG. 5 , when the plurality of semiconductor elements 10 are disposed on the temporary adhesive layer P11 , the active surfaces 10 a are disposed toward the temporary adhesive layer P11 . After that, an expansion step is performed to increase the distance d1 between two adjacent semiconductor elements 10 .

Referring to FIG. 1 again, in step S130 , all the expanded semiconductor elements are arranged on the carrier board. Please refer to FIG. 6 , which is a schematic diagram of step S130 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention. As shown in FIG. 6 , the active surface 10 a of each semiconductor element 10 faces the carrier board P1 . It should be noted that, in the embodiment of the present invention, after the spacing d1 ′ of the plurality of semiconductor elements 10 is expanded, the step of selecting the semiconductor elements 10 is not specially performed, but all the semiconductor elements 10 are transferred and arranged on the carrier board P1 .

Referring to FIG. 6 , a plurality of semiconductor elements 10 are disposed on the carrier board P1. In one embodiment, in this embodiment, the carrier board P1 has a bottom plate P10 and another temporary adhesive layer P11, and the material of the bottom plate P10 is silicon wafer, glass, ceramic, polymer or metal, for example, the present invention Not limited.

If the expansion is performed, the plurality of semiconductor elements 10 are disposed on the temporary adhesive layer P11 with the active surface 10a facing upward. The active surfaces 10a of the semiconductor elements 10 are disposed so that the active surfaces 10a of the plurality of semiconductor elements 10 are attached to the temporary adhesive layer P11 of the carrier board P1.

After that, the temporary adhesive layers P11 originally adhered to the bottom surfaces 10b of the plurality of semiconductor elements 10 are debonded. The debonding method can be selected according to the material of the temporary adhesive layer P11 by heating, irradiating ultraviolet light or laser light, etc., to remove the adhesiveness of the temporary adhesive layer P11 . For example, if the temporary adhesive layer is a UV debonding layer, the adhesive force of the temporary adhesive layer can be reduced by irradiating ultraviolet light, but the present invention is not limited to this. Accordingly, when the plurality of semiconductor elements 10 are arranged on the carrier board P1, they are arranged with the active surface 10a facing the carrier board P1.

In another embodiment, when expanding, as shown in FIG. 5 , the plurality of semiconductor elements 10 are disposed with the active surfaces 10 a facing the temporary adhesive layer P11 . After expanding, the temporary adhesive layer P11 can be combined with The plurality of semiconductor elements 10 adhered thereon are directly disposed on the bottom plate P10.

Referring to FIG. 1 again, in step S140 , a molding material is formed to cover a plurality of semiconductor elements to form an initial package. Please refer to FIG. 7 . FIG. 7 is a schematic diagram of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention in step S140 . The molding material 2 is filled between the plurality of semiconductor elements 10 to connect the plurality of semiconductor elements 10 . The molding material 2 forms the initial package M1 together with the plurality of semiconductor elements 10 . The molding material 2 is, for example, a polymer material or a composite material, wherein the polymer material is, for example, polyimide (PI), Benzocyclobutene (BCB), epoxy resin or silicone rubber, etc. The materials are, for example, glass fiber reinforced thermosetting plastics, bulk molding materials and other adhesive insulating materials or dielectric materials. The molding material 2 may be formed by a compression molding or an injection molding process.

In this embodiment, the molding material 2 covers the bottom surface 10 b of each semiconductor element 10 , but does not cover the active surface 10 a of each semiconductor element 10 . That is, the molding material 2 covers the side surface 10 c and the bottom surface 10 b of each semiconductor element 10 .

As shown in FIG. 7 , the initial package M1 has a first side and a second side, and the active surface 10 a and the bottom surface 10 b of each semiconductor element 10 correspond to the first side and the second side, respectively. As shown in FIG. 5 , the active surface 10 a of each semiconductor element 10 corresponds to the first side of the initial package M1 , and the initial package M1 contacts the temporary adhesive layer P11 of the carrier board P1 with the first side. Further, the molding material 2 has a first surface 2a and a second surface 2b opposite to the first surface 2a. In this embodiment, the first surface 2a of the molding material 2 and the active surface 10a of the semiconductor element 10 are in common contact with the temporary adhesive layer P11 of the carrier board P1.

Referring to FIG. 1 , in step S150 , the initial package body and the carrier board are separated. In step S160, a dicing step is performed on the initial package body to form a plurality of semiconductor device package structures. Please refer to FIG. 8 . FIG. 8 is a schematic diagram of step S160 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention. The initial package body M1 and the carrier plate P1 are separated. In detail, when the temporary adhesive layer P11 is a UV debonding layer, ultraviolet light (UV light) can be used to irradiate the peelable adhesive layer first to reduce the adhesive force between the peelable adhesive layer P11 and the initial package M1, and further The initial package body M1 can be detached from the peelable adhesive layer P11 of the carrier board P1.

As shown in FIG. 8 , after the carrier plate P1 is separated from the initial package body M1 , a cutting step L1 is performed on the initial package body M1 to form a plurality of semiconductor element package structures m1 . Please refer to FIG. 9 . FIG. 9 is a schematic cross-sectional view of a semiconductor device packaging structure according to a first embodiment of the present invention. The semiconductor element packaging structure m1 of the present embodiment includes a semiconductor element 10 and a molding layer 2A.

As described above, the semiconductor device 10 has the active surface 10a, the bottom surface 10b opposite to the active surface 10a, and the side surface 10c connected between the active surface 10a and the bottom surface 10b. The semiconductor element 10 is, for example, a power wafer or other types of wafers, which is not limited in the present invention. The semiconductor device 10 has at least one pad 100 on the active surface 10a.

After the initial package body M1 is cut, the molding material 2 surrounding each semiconductor element 10 is encapsulated to form the molding layer 2A of FIG. 9 . Accordingly, the molding layer 2A covers the side surface 10 c and the bottom surface 10 b of the semiconductor element 10 to provide protection for the semiconductor element 10 . In this embodiment, the thickness T1 of the molding layer 2A is between 10 and 50 μm. In addition, the molding layer 2A has a first surface 2a and a second surface 2b opposite to each other. As shown in FIG. 7 , both the active surface 10 a and the pads 100 of the semiconductor device 10 are exposed on the first surface 2 a of the molding layer 2A. In this embodiment, the active surface 10a of the semiconductor element 10 is flush with the first surface 2a of the molding layer 2A. In addition, the thickness of the pad 100 is about 5 μm to 100 μm, and it protrudes from the active surface 10 a . Therefore, the top surface of the pad 100 is higher than the first surface 2 a of the molding layer 2A.

Referring to FIG. 10 , a flowchart of a method for manufacturing a semiconductor package device according to another embodiment of the present invention is shown. The steps of the manufacturing method of this embodiment are the same as those of the manufacturing method shown in FIG. 1 and will not be described again. In this embodiment, after the initial package body and the carrier board are separated, step S170 is further performed. In step S170, a thinning step is performed from the second side of the initial package, so that each semiconductor element is exposed on the second side of the initial package.

Please refer to FIG. 11 , which shows a schematic diagram of a semiconductor device packaging structure in step S170 according to another embodiment of the present invention. In detail, when the thinning step is performed on the initial package body M1, the initial package body M1 is thinned from the second surface 2b of the molding material 2 toward the first surface 2a, so as to remove a part of the molding material 2 and thin the initial package body M1. Each semiconductor element 10 is fused. In this way, the semiconductor element 10 has a thinner thickness t2. In one embodiment, the thickness of the initial package body M1 may be thinned to 25 μm to 75 μm. That is, the thickness t2 of each semiconductor element 10 in the initial package M1 is also thinned to 25 μm to 75 μm. In addition, in the thinned initial package body M1, the bottom surface 10b' of each semiconductor element 10 will be exposed on the second surface 2b' of the molding material 2', and will be in contact with the second surface 2b of the molding layer 2'. 'Cut it up.

It should be noted that since the semiconductor element 10 is encapsulated in the molding material 2 , the molding material 2 can provide protection for the semiconductor element 10 when the initial package body M1 is thinned, so as to avoid the thinning of the semiconductor element 10 . be damaged. That is to say, the method provided by the embodiment of the present invention can not only make the thickness of the semiconductor element 10 thinner, but also reduce the breakage rate of the semiconductor element 10 .

Referring to FIG. 12 , after step S170 is performed, step S160 may be directly performed to form a plurality of semiconductor device packaging structures. Further, referring to FIGS. 11 and 12 , after the cutting step L1 is performed on the initial package body M1 of FIG. 11 , the semiconductor device package structure m2 shown in FIG. 12 can be formed.

In the semiconductor device package structure m2 of the present embodiment, the molding layer 2B only covers the side surface 10c of the semiconductor device 10, but does not cover the active surface 10a and the bottom surface 10b' of the semiconductor device 10. In other words, the active surface 10a of the semiconductor device 10 is exposed to the first surface 2a of the molding layer 2B, and the first surface 2a of the molding layer 2B is flush with the active surface 10a of the semiconductor device 10 . In addition, the bottom surface 10b' of the semiconductor element 10 is exposed to the second surface 2b' of the molding layer 2B.

It should be noted that, compared with the previous embodiment, the total thickness of the semiconductor device package structure m2 manufactured by the manufacturing method of the embodiment of the present invention can be thinner. Specifically, the total thickness of the semiconductor element package structure m2 may be between 25 μm and 75 μm.

Referring to FIG. 10 again, after step S170 is performed, the manufacturing method of this embodiment may further perform step S180. In step S180, a conductive and thermally conductive layer is formed on the second side of the initial package, wherein the conductive and thermally conductive layer directly contacts the bottom surface of each semiconductor element.

Please refer to FIG. 13 , which is a schematic diagram of step S170 of the manufacturing method of the semiconductor device packaging structure according to the third embodiment of the present invention. FIG. 13 can be followed by step S170 , that is, after the initial package body M1 is thinned, a conductive and thermally conductive layer 3 is formed on the second side of the initial package body M1 . Further, the electrically and thermally conductive layer 3 is formed on the second surface 2b' of the molding material 2' and the bottom surface 10b' of each semiconductor element 10 .

The material of the conductive and thermally conductive layer 3 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof. In addition, each conductive and heat-conducting layer 3 may have a laminated structure, such as a laminated structure of titanium/copper, titanium/nickel/silver, titanium/copper/nickel/tin or titanium/copper/nickel/gold. The thickness of the electrically and thermally conductive layer 3 is about 1 μm to 5 μm. After that, as shown in FIG. 11 , the cutting step L1 is performed on the initial package body M1 and the electrical and thermal conductive layer 3 .

Please refer to FIG. 14 . FIG. 14 is a schematic cross-sectional view of a semiconductor device packaging structure according to a third embodiment of the present invention. Compared with the semiconductor element packaging structure m2 of FIG. 10 , the semiconductor element packaging structure m3 of the present embodiment further includes a conductive and thermally conductive layer 3 , and the conductive and thermally conductive layer 3 is disposed between the bottom surface 10 b ′ of the semiconductor element 10 and the molding layer 2B. The second surface 2b'. The conductive and thermally conductive layer 3 can provide protection for the semiconductor element 10 and can be used to dissipate heat from the semiconductor element 10 .

It should be noted that, in the embodiment of FIG. 14 , the conductive junction of the semiconductor element 10 is located on the active surface 10 a of the semiconductor element 10 . However, in other embodiments, the conductive junction of the semiconductor element 10 may also be located on the bottom surface 10b thereof. Accordingly, the number and position of the conductive junctions of the semiconductor element 10 are determined according to the type of the semiconductor element 10 , and the present invention is not limited. Accordingly, when the bottom of the semiconductor element 10 has a conductive junction for electrically connecting to the outside, the conductive and heat-conducting layer 3 can be used as a bonding pad, so that the semiconductor element 10 can be electrically connected to another electronic device or circuit board.

In addition, in the semiconductor element package structure m3 of the present embodiment, the thickness of the semiconductor element 10 is between 25 and 75 μm, and the thickness of the conductive and heat-conductive layer 3 is about 1 μm to 5 μm. Therefore, the total thickness of the semiconductor element package structure m3 can be less than 100 μm. Compared with the embodiment of FIG. 7 , the total thickness of the semiconductor element packaging structures m2 and m3 can be thinner. Specifically, the total thickness of the semiconductor device package structures m2, m3 may be between 25 μm and 100 μm.

In addition, it should be noted that the step of forming the molding material 2 may be performed before placing the plurality of semiconductor elements 10 on the carrier board P1. Please refer to FIG. 15 , which is a flowchart of a manufacturing method of a semiconductor device packaging structure according to another embodiment of the present invention.

Steps S200 to S220 in this embodiment are respectively the same as steps S100 to S120 in FIG. 10 , and details are not repeated here. In step S230, a molding material is formed to cover the plurality of semiconductor elements to form an initial package, and all the plurality of semiconductor elements are arranged on the carrier board. Please refer to FIG. 16 and FIG. 17 , which are schematic diagrams of the manufacturing method of the semiconductor device package structure of FIG. 15 in step S230 .

As shown in FIG. 16 , in this embodiment, a plurality of semiconductor elements 10 are sandwiched between a first sheet-shaped molding material 21 and a second sheet-shaped molding material 22 , and the first sheet-shaped molding material is sealed A gap H1 is jointly defined between the material 21 , the second sheet-shaped molding material 22 and any two semiconductor elements 10 .

Further, after dicing the wafer to form a plurality of semiconductor elements 10 separated from each other, the plurality of semiconductor elements 10 may be firstly disposed on the temporary adhesive layer P11 as shown in FIG. 4 or FIG. 5 , and then the first Sheet molding material 21 . Since the first sheet-like molding material 21 also has adhesiveness and can fix a plurality of semiconductor elements 10, after the first sheet-like molding material 21 is disposed, the temporary adhesive layer P11 can be removed first, and then the second sheet-like molding material 21 can be removed. The sheet-like molding material 22 is provided so that the plurality of semiconductor elements 10 are sandwiched between the first sheet-like molding material 21 and the second sheet-like molding material 22 .

Referring to FIG. 16 , from opposite sides of the semiconductor element 10 , the first sheet-like molding material 21 and the second sheet-like molding material 22 are pressed together to form a space H1 that fills the gap H1 and completely covers each semiconductor element 10 Molding material 2. In this embodiment, the second sheet-shaped molding material 22 , the plurality of semiconductor elements 10 and the first sheet-shaped molding material 21 are firstly disposed on the carrier plate P1 , and then press-bonded.

Referring to FIG. 17 , through the above steps, a plurality of semiconductor elements 10 are embedded in the molding material 2 to form an initial package M2 . As shown in FIG. 17 , in this embodiment, the molding material 2 covers the bottom surface 10 b and the active surface 10 a of each semiconductor element 10 . The initial package body M2 has a first side and a second side, and the active surface 10a and the bottom surface 10b of each semiconductor element 10 in the molding compound 2 face the first side and the second side, respectively. In this embodiment, the first surface 2a of the molding material 2 is located on the first side of the initial package body M2, and the second surface 2b of the molding material 2 is located on the second side of the initial package body M2.

Referring to FIG. 15 again, in step S240, the initial package body and the carrier board are separated; in step S250, the thinning step is performed from the first side of the initial package body. Please refer to FIG. 18 , in this embodiment, a thinning step is performed on the initial package body M2 from the first side of the initial package body M2 to expose the pads 100 of each semiconductor element 10 . That is, a part of the molding material 2 covering the pads 100 of the semiconductor element 10 is removed. Referring to FIG. 19 , after the thinning step is performed on the initial package body M2, the first surface 2a' of the molding material 2' is flush with the surface of the pads 100 of the semiconductor device 10. It should be noted that, when the initial package body M2 is thinned, a part of the pads 100 may also be removed together.

Referring to FIG. 15 again, in one embodiment, after step S250 is performed, step S280 may be directly performed. As shown in FIG. 19, after the dicing step L1 is performed on the initial package body M2, a plurality of semiconductor element package structures can be formed.

Please refer to FIG. 20 , which is a schematic cross-sectional view of a semiconductor device packaging structure according to a fourth embodiment of the present invention. The semiconductor element package structure m4 includes the semiconductor element 10 and the molding layer 2C. In this embodiment, the molding layer 2C covers the active surface 10 a , the side surface 10 c and the bottom surface 10 b of the semiconductor element 10 , but exposes the pads 100 of the semiconductor element 10 . In one embodiment, the thickness of the molding layer 2C is between 10 and 50 μm. Accordingly, in the semiconductor device package structure m4 of the present embodiment, all surfaces of the semiconductor device 10 (including the active surface 10a, the side surface 10c, and the bottom surface 10b) are covered by the molding layer 2C to be more completely protected.

In addition, the molding layer 2C has two opposing first surfaces 2a' and second surfaces 2b. A height difference h1 is formed between the first surface 2a' and the active surface 10a of the semiconductor element 10, and the height difference h1 is between 10 μm and 80 μm. As shown in FIG. 18, the first surface 2a' is cut flush with the surface of the pad 100.

Referring to FIG. 15 again, after step S250 is performed, the manufacturing method of the embodiment of the present invention may further perform steps S260 and S270, and then perform step S280. Further, in step S260, a thinning step is performed from the second side of the initial package, so that each semiconductor element is exposed on the second side of the initial package. In step S270, a conductive and thermally conductive layer is formed on the second side of the initial package, wherein the conductive and thermally conductive layer covers and contacts the bottom surface of each semiconductor element.

Please refer to FIG. 21 , which shows a schematic diagram of step S260 of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention. It should be noted that, the step in FIG. 21 can be followed by step S250 (refer to FIG. 18 ). That is, after the thinning step is performed on the initial package body M2 by the first side of the initial package body M2, another thinning step is performed on the initial package body M2 by the second side of the initial package body M2 to expose each A bottom surface 10b ′ of a semiconductor element 10 . Accordingly, in this embodiment, the initial package body M2 undergoes two-stage thinning steps. In the thinned initial package body M2, the bottom surface 10b' of each semiconductor element 10 is exposed to the second surface 2b' of the molding material 2", and is cut from the second surface 2b' of the molding layer 2". together.

Please refer to FIG. 22 . FIG. 22 is a schematic diagram of a manufacturing method of a semiconductor device packaging structure in step S270 according to still another embodiment of the present invention. After the initial package body M2 is thinned, a conductive and thermally conductive layer 3 is formed on the second side of the initial package body M1. Further, the electrically and thermally conductive layer 3 is formed on the second surface 2b' of the molding material 2' and the bottom surface 10b' of each semiconductor element 10 .

The material of the conductive and thermally conductive layer 3 is, for example, titanium, copper, silver, nickel, tin, gold or any combination thereof. In addition, each conductive and heat-conducting layer 3 may have a laminated structure, such as a laminated structure of titanium/copper, titanium/nickel/silver, titanium/copper/nickel/tin or titanium/copper/nickel/gold. The thickness of the electrically and thermally conductive layer 3 is about 1 μm to 5 μm. After that, as shown in FIG. 20 , the cutting step L1 is performed on the initial package body M1 and the conductive and thermally conductive layer 3 .

Please refer to FIG. 23 . FIG. 23 is a schematic cross-sectional view of a semiconductor device packaging structure according to a fifth embodiment of the present invention. The semiconductor element packaging structure m5 of this embodiment includes a semiconductor element 10 , a molding layer 2 ″, and a conductive and heat-conducting layer 3 . The molding layer 2D of this embodiment covers the active surface 10 a and the side surface 10 c of the semiconductor element 10 , but does not Covers the bottom surface 10b' of the semiconductor element 10. The molding layer 2D has a first surface 2a' and a second surface 2b'. A height difference is formed between the first surface 2a' of the molding layer 2D and the active surface 10a of the semiconductor element 10 h1, but the first surface 2a' and the surface of the pad 100 will be flush.

In addition, the second surface 2b' of the molding layer 2D is flush with the bottom surface 10b' of the semiconductor element 10. The conductive and thermally conductive layer 3 is disposed on the second surface 2b' of the molding layer 2D and the bottom surface 10b' of the semiconductor element 10. Further, in this embodiment, the conductive and thermally conductive layer 3 directly contacts the bottom surface 10b' of the semiconductor element 10 and the second surface 2b' of the molding layer 2D. The conductive and thermally conductive layer 3 can provide protection for the semiconductor element 10 and can be used to dissipate heat from the semiconductor element 10 . When the bottom of the semiconductor element 10 has a conductive junction for electrically connecting to the outside, the conductive and heat-conducting layer 3 can be used as a bonding pad, so that the semiconductor element 10 can be electrically connected to another electronic device or circuit board.

In addition, in the semiconductor element package structure m3 of the present embodiment, the thickness of the semiconductor element 10 is between 25 and 75 μm, and the thickness of the conductive and heat-conductive layer 3 is about 1 μm to 5 μm. Therefore, the total thickness of the semiconductor element package structure m3 can be less than 100 μm.

It should be noted that, in the manufacturing method of another embodiment, step S270 may also be omitted. As shown in FIG. 15 , after step S260 is performed, step S280 is directly performed. In the semiconductor element package structure formed by the aforementioned manufacturing method, the conductive and heat-conducting layer 3 is not provided, and the molding layer covers the active surface 10 a and the side surface 10 c of the semiconductor element 10 , but exposes the bottom surface 10 b ′ of the semiconductor element 10 . .

[Advantageous effects of the embodiment]

One of the beneficial effects of the present invention is that, in the semiconductor device packaging structure and the manufacturing method thereof provided by the present invention, by "arranging the wafer on a temporary adhesive layer, and cutting the wafer along a plurality of dicing regions, to form a plurality of semiconductor elements separated from each other", "to expand the spacing between the plurality of semiconductor elements", "to arrange all the expanded plurality of semiconductor elements on the carrier board", and "to form a molding material to cover a plurality of all semiconductor elements". The technical solution of forming an initial package body by using the above-described semiconductor device can further reduce the width w1 of the dicing region 11, increase the number of semiconductor devices 10 in the wafer 1, and further reduce the manufacturing cost.

Further, in the manufacturing method of the embodiment of the present invention, after the wafer 1 is diced, the spacing of the plurality of semiconductor elements 10 may be expanded first, and then all the semiconductor elements 10 are placed on the carrier plate P1 for molding. In this way, the width w1 of the cutting area 11 is not limited by the subsequent molding process and the width of the cutting tool, but can be further reduced. In this way, the area of the wafer 1 that can be used to manufacture the semiconductor elements 10 can be increased, thereby increasing the number of semiconductor elements 10 in the same wafer 1 and reducing the manufacturing cost.

In addition, the manufacturing method provided by the embodiment of the present invention can form the semiconductor element packaging structures m1 to m5 without substrate, lead frame, and wire bonding, and the molding material 2 (2', 2") can also be used for the semiconductor element 10. Provide protection and improve the yield of semiconductor component packaging structures m1~m5.

On the other hand, this embodiment does not reduce the volume by thinning the wafer at the wafer stage, but cuts the wafer into a plurality of semiconductor elements 10 and forms the molding material 2 (2', 2") ) after encapsulating the semiconductor element 10, the initial package body M1 (M2) is directly thinned. Accordingly, the thickness t1 of the semiconductor element 10 in the semiconductor element package structures m1 to m5 can be thinned in the initial package body M1 (M2). ), rather than in the step of thinning the wafer. Compared with the prior art method of controlling the thickness by thinning the entire wafer, the thinning of the initial package M1 (M2) can be more precisely controlled The thicknesses t1 and t2 of the semiconductor element 10 or the total thickness of the semiconductor element packaging structures m1 to m5. In addition, the technical means adopted in the embodiments of the present invention are less likely to cause damage to the semiconductor element 10, which can reduce the difficulty and cost of the thinning process.

In addition, by using the manufacturing method of the semiconductor element package structure provided by the embodiment of the present invention, the semiconductor element 10 can be further thinned to less than 100 μm, so that the dimensions of the semiconductor element package structures m1 to m5 can be further reduced. In general, compared with the existing packaging technology, the semiconductor device packaging structures m1-m5 manufactured by the manufacturing method of the embodiment of the present invention do not have a packaging substrate, a lead frame and a wire bonding, so the total size of the semiconductor device packaging structures m1-m5 is The thickness can be thinner with a smaller volume. That is to say, the volume of the semiconductor element package structures m1 to m5 is actively close to the size of an unpackaged chip.

The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, any equivalent technical changes made by using the contents of the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

1: Wafer 1a: upper surface 1b: lower surface m1~m5: Semiconductor component packaging structure 10: Semiconductor components 10a: Active side 10b, 10b': Bottom surface 10c: Side surface 100: Pad 11: Cutting area w1: width of cutting area t1, t2: Thickness of semiconductor element 2,2',2": Molding material 2A~2D: Molding layer 2a, 2a': first surface 2b, 2b': second surface 3: Electrically and thermally conductive layer M1, M2: Initial package body P1: carrier plate P10: Bottom plate P11: Temporary adhesive layer L1: Cutting step 21: The first sheet molding material 22: The second sheet molding material h1: height difference T1: Thickness H1: void d1, d1': spacing D1: first direction D2: Second direction

FIG. 1 is a flowchart of a method for manufacturing a semiconductor element packaging structure according to an embodiment of the present invention.

FIG. 2 is a schematic diagram before step S100 of a method for manufacturing a semiconductor device packaging structure according to an embodiment of the present invention.

FIG. 3 is a schematic partial cross-sectional view along the line III-III of FIG. 2 .

FIG. 4 is a schematic diagram of step S120 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention.

FIG. 5 is a schematic diagram of a manufacturing method of a semiconductor device packaging structure in step S120 according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of step S130 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention.

FIG. 7 is a schematic diagram of step S140 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention.

FIG. 8 is a schematic diagram of step S160 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention.

9 is a schematic cross-sectional view of the semiconductor device packaging structure according to the first embodiment of the present invention.

FIG. 10 is a flowchart of a manufacturing method of a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 11 is a schematic diagram of step S170 in FIG. 10 of the manufacturing method of the semiconductor device packaging structure according to the embodiment of the present invention.

12 is a schematic cross-sectional view of a semiconductor device packaging structure according to a second embodiment of the present invention.

FIG. 13 is a schematic diagram of step S180 in FIG. 10 of the manufacturing method of the semiconductor device package structure according to the embodiment of the present invention.

14 is a schematic cross-sectional view of a semiconductor device packaging structure according to a third embodiment of the present invention.

FIG. 15 is a flowchart of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 16 is a schematic diagram of step S230 in FIG. 15 of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 17 is a schematic diagram of step S230 in FIG. 15 of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 18 is a schematic diagram of step S250 in FIG. 15 of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 19 is a schematic diagram of step S280 in FIG. 15 of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

20 is a schematic cross-sectional view of a semiconductor device packaging structure according to a fourth embodiment of the present invention.

FIG. 21 is a schematic diagram of step S260 in FIG. 15 of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

FIG. 22 is a schematic diagram of step S270 in FIG. 15 of a method for manufacturing a semiconductor device packaging structure according to another embodiment of the present invention.

23 is a schematic cross-sectional view of a semiconductor device packaging structure according to a fifth embodiment of the present invention.

S100~S160: Process steps

Claims (20)

A manufacturing method of a semiconductor element packaging structure, comprising: A wafer is provided, wherein the wafer defines a plurality of semiconductor elements and a plurality of dicing regions interlaced with each other, wherein each of the semiconductor elements includes at least one pad disposed on the active surface; disposing the wafer on a temporary adhesive layer, and dicing the wafer along a plurality of the dicing regions to form a plurality of semiconductor elements separated from each other; expanding the spacing between a plurality of the semiconductor elements; all the expanded semiconductor elements are arranged on a carrier board; forming a molding material to cover a plurality of the semiconductor elements to form an initial package, wherein the molding material is filled between the plurality of the semiconductor elements to connect the plurality of the semiconductor elements, the initial package The package body has a first side and a second side, and the active surface and a bottom surface of each of the semiconductor elements correspond to the first side and the second side respectively; separating the initial package from the carrier board; and A dicing step is performed on the initial package to form a plurality of semiconductor device package structures. The manufacturing method of claim 1, wherein the active surface of each of the semiconductor elements faces the carrier board, and the molding material covers the bottom surface of each of the semiconductor elements, but does not cover the active surface of each of the semiconductor elements. The manufacturing method of claim 2, further comprising: after separating the initial package and the carrier board, performing a thinning step on the second side of the initial package, so that each The semiconductor element is exposed on the second side of the initial package. The manufacturing method of claim 3, further comprising: after the thinning step is performed by the second side of the initial package, forming a conductive layer on the second side of the initial package A thermally conductive layer, wherein the conductive and thermally conductive layer directly contacts the bottom surface of each of the semiconductor elements. The manufacturing method of claim 3, wherein the cutting step is performed directly after the thinning step is performed by the second side of the initial package. The manufacturing method according to claim 1, wherein the width of the dicing region is 40 μm to 80 μm, and after disposing the expanded plurality of the semiconductor elements on the carrier board, any two of the semiconductor elements The spacing therebetween is 100 μm to 200 μm. The manufacturing method according to claim 1, wherein in the step of forming the initial package, all of the plurality of semiconductor elements are arranged on the carrier board, and the step of forming the initial package includes: A plurality of the semiconductor elements are sandwiched between a first sheet-shaped molding material and a second sheet-shaped molding material, wherein the first sheet-shaped molding material and the second sheet-shaped molding material are a gap is jointly defined between the material and any two of the semiconductor elements; and disposing the first sheet-like molding material, a plurality of the semiconductor elements and the second sheet-like molding material on the carrier plate, and pressing the first sheet-like molding material and the A second sheet-like molding compound is formed to fill the voids and completely cover each of the semiconductor elements. The manufacturing method of claim 1, wherein after the initial package is formed, the molding material covers the active surface and the bottom surface of each of the semiconductor elements, so that each of the semiconductor elements is Components are completely embedded in the molding material, and the manufacturing method further includes performing a thinning step from the first side of the initial package to expose at least one of each of the semiconductor components. described pads. The manufacturing method of claim 8, wherein after the thinning step is performed on the first side of the initial package, a first surface of the molding material and each of the semiconductor elements The surface of at least one of the pads is flush. The manufacturing method according to claim 9, before performing the cutting step, further comprising: performing another thinning step from the second side of the initial package to expose the bottom surface of each of the semiconductor elements; and A conductive and thermally conductive layer is formed on the second side of the initial package, wherein the conductive and thermally conductive layer covers and contacts the bottom surface of each of the semiconductor elements. A semiconductor element packaging structure, comprising: A semiconductor device, which has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface, wherein the semiconductor device includes at least one pad, which set on the active surface; a molding layer covering the side surface of the semiconductor element and exposing the bottom surface of the semiconductor element, the molding layer has two opposite first surfaces and a second surface, the The second surface is coplanar with the bottom surface of the semiconductor element; and A conductive and heat-conductive layer is disposed on the bottom surface of the semiconductor element and the second surface of the molding layer. The semiconductor element package structure according to claim 11, wherein the total thickness of the semiconductor element package structure is between 25 μm and 150 μm. The semiconductor device packaging structure according to claim 11, wherein the active surface of the semiconductor device is flush with a first surface of the molding layer. The semiconductor device package structure according to claim 11, wherein the thickness of at least one of the pads is 5 μm to 100 μm, the molding layer covers the active surface, but exposes at least one of the pads, and the first pad has a thickness of 5 μm to 100 μm. A height difference between a surface and the active surface of the semiconductor element is between 10 μm and 80 μm, and the first surface is flush with the surface of at least one of the pads. The packaging structure of a semiconductor element according to claim 11, wherein the thickness of the conductive and heat-conducting layer is between 1 μm and 5 μm, and the thickness of the semiconductor element is between 25 and 75 μm. The semiconductor element packaging structure according to claim 11, wherein the material of the conductive and heat-conducting layer is titanium, copper, silver, nickel, tin, gold, or any combination thereof. A semiconductor element packaging structure, comprising: A semiconductor device, which has an active surface, a bottom surface opposite to the active surface, and a side surface connected between the active surface and the bottom surface, wherein the semiconductor device includes at least one pad, which disposed on the active surface; and a molding layer covering the side surface and the bottom surface of the semiconductor element, wherein the thickness of the molding layer is between 10 and 50 μm, and has two opposing first surfaces and a first surface Second surface. The semiconductor device package structure according to claim 17, wherein the active surface of the semiconductor device is flush with a first surface of the molding layer. The semiconductor device package structure according to claim 17, wherein the thickness of at least one of the contact pads is 5 μm to 100 μm, and the molding layer covers the active surface of the semiconductor device, but exposes at least one of the contact pads. pad, a height difference between the first surface and the active surface of the semiconductor element is between 10 μm and 80 μm, and the first surface is flush with the surface of at least one of the pads. The semiconductor element package structure according to claim 17, wherein the thickness of the electrically conductive and thermally conductive layer is between 1 μm and 5 μm.

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