TW201626470A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

A production method for a semiconductor device, the production method including: a preparation step for preparing a semiconductor wafer that has a circuit formed on a principal surface thereof; an attachment step for attaching the semiconductor wafer to an adhesive layer; a first division step for obtaining a plurality of semiconductor chips by dividing, in accordance with dicing regions, the semiconductor wafer that has been attached to the adhesive layer; a sealing step for collectively sealing the plurality of semiconductor chips, which have the principal surface thereof attached to the adhesive layer, such that a sealing material layer that comprises a semiconductor sealing resin composition is formed in the intervals between the side surfaces of the semiconductor chips and on the rear surface of the semiconductor chips; and a second division step for obtaining a plurality of semiconductor chips that have the sealing material layer formed on the side surfaces and rear surface thereof by dividing the sealing material layer that has been formed in the intervals between the side surfaces of the semiconductor chips.

Description

Semiconductor device manufacturing method and semiconductor device

The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.

In the manufacturing process of the semiconductor device hitherto, the singulated semiconductor wafer is individually sealed with a sealing resin. As such a technique, for example, there is a technique described in Patent Document 1. In this document, it is described that a semiconductor wafer is picked up by a collet and attached to a substrate, and the semiconductor wafer is individually sealed by a transfer molding method using an epoxy resin for semiconductor encapsulation (Patent Document 1).

Patent Document 2 describes a technique of singulating a wafer from a semiconductor wafer. Specifically, a groove is formed on the main surface of the semiconductor wafer by half-cutting. The wafer made of a semiconductor is singulated by polishing the back surface. The singulated wafer is picked up in a state where the semiconductor of the underlayer is exposed on the surface, and then bonded.

Prior technical literature

Patent literature

Patent Document 1: Japanese Laid-Open Patent Publication No. Hei 9-107046

Patent Document 2: Japanese Laid-Open Patent Publication No. 2011-210927

However, in the manufacturing process of the semiconductor package described in the above document, since each semiconductor wafer is individually sealed, there is room for improvement in productivity.

Further, the inventors have found out that when the wafer is picked up by the collet, the wafer is broken (fragmented). That is, the technique described in the above document has room for improvement in terms of reliability.

The inventors further studied and found that when the semiconductor wafer is picked up, the fragment can be suppressed by protecting the surface of the semiconductor wafer. Based on such insights, it has been found that by temporarily sealing a plurality of semiconductor wafers and dividing the adjacent wafers, it is possible to obtain semiconductor wafers covered with a sealing material layer on the side and back sides (opposite sides of the circuit forming surface). . Moreover, it was found that the fragments during operation in the semiconductor wafer were suppressed, thereby completing the present invention.

According to the present invention, there is provided a method of fabricating a semiconductor device, comprising: a preparation step of preparing a semiconductor wafer on which a circuit is formed on a main surface; and an attaching step of attaching the semiconductor wafer to an adhesive layer; a dividing step of obtaining a plurality of semiconductor wafers by dividing the semiconductor wafer attached to the bonding layer along a dicing region; and a sealing step of affixing the main surface of the plurality of semiconductor wafers Attaching to the above-mentioned bonding layer, sealing a plurality of the semiconductor wafers at a time, thereby being used in the semiconductor wafer a sealing material layer composed of a semiconductor sealing resin composition formed on a gap between the side faces and the back surface of the semiconductor wafer; and a second dividing step of the sealing material formed in a gap formed between the side faces of the semiconductor wafer The layer is divided to obtain a plurality of the semiconductor wafers on which the sealing material layer is formed on the side surface and the back surface.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: providing a structure including an adhesive member and a plurality of semiconductor wafers attached to an adhesive face of the adhesive member, and a plurality of the semiconductor wafers Arranging at a predetermined interval from each other, and attaching a plurality of circuit forming surfaces of the semiconductor wafer to the adhesive surface of the adhesive member; and contacting the resin composition for semiconductor sealing in a flowing state with the plurality of semiconductor wafers The resin composition for semiconductor encapsulation is filled at intervals, and the semiconductor sealing resin composition covers the surface and the side surface of the semiconductor wafer opposite to the circuit formation surface to be sealed, and the resin composition for semiconductor encapsulation is cured.

Further, according to the present invention, there is provided a semiconductor device comprising: a semiconductor wafer having a circuit formed on a main surface; a bump formed on the main surface; and a sealing material layer covering a side surface of the semiconductor wafer and The main surface is the back side of the opposite side.

According to the present invention, it is possible to provide a semiconductor package excellent in reliability and productivity A manufacturing method is provided, and a semiconductor device improved in reliability is provided.

The above and other objects, features and advantages of the invention will be apparent from

Fig. 1 is a cross-sectional view showing an example of a semiconductor device of the embodiment.

Fig. 2 is a cross-sectional view showing an example of the semiconductor device of the embodiment.

Fig. 3 is a cross-sectional view showing the steps of an example of a method of manufacturing the semiconductor device of the embodiment.

4 is a cross-sectional view showing the steps of an example of a method of manufacturing the semiconductor device of the embodiment.

Fig. 5 is a cross-sectional view showing the steps of an example of a method of manufacturing the semiconductor device of the embodiment.

Fig. 6 is a view showing an example of a configuration of an expansion device which can be used when the interval between adjacent semiconductor wafers is increased in the manufacturing method of the embodiment.

Fig. 7 is a view showing an example of the configuration of an expansion device which can be used when the interval between adjacent semiconductor wafers is increased in the manufacturing method of the embodiment.

Fig. 8 is a cross-sectional view showing an example of the semiconductor device of the embodiment.

Fig. 9 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

Fig. 10 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

Fig. 11 is a plan conceptual view showing a dicing region of a semiconductor wafer in the method of manufacturing the semiconductor device of the embodiment.

Fig. 12 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

Fig. 13 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and their description will be appropriately omitted.

<First Embodiment>

A method of manufacturing the semiconductor device of the present embodiment will be described.

The manufacturing method of the semiconductor device 8 of the present embodiment includes the steps of preparing the structure 7 including the adhesive member 10 or 30 (the adhesive layer) and the plurality of semiconductor wafers 5 attached to the adhesive faces of the adhesive members 10 or 30. The plurality of semiconductor wafers 5 are disposed at a predetermined interval from each other, and a circuit forming surface of the plurality of semiconductor wafers 5 is attached to the adhesive surface of the adhesive member 10 or 30; and the semiconductor sealing resin composition 49 in a flowing state is provided The semiconductor wafer 5 is brought into contact, and the semiconductor sealing resin composition 49 is filled at intervals between the adjacent semiconductor wafers 5, and the semiconductor sealing resin composition 49 covers the surface and the side surface of the semiconductor wafer 5 opposite to the circuit forming surface. Sealing is performed; and the semiconductor sealing resin composition 49 is cured.

In the method of manufacturing the semiconductor device of the present embodiment, the semiconductor device 8 can be used to cover the circuit formation surface of the semiconductor wafer 5 with the cured body (sealing material layer 40) of the resin composition for semiconductor sealing ( The main surface 3) is picked up by a collet in a state in which the opposite side (back surface 4) and the side surface 9 are protected. With this configuration, it is possible to prevent the transfer device from directly contacting the semiconductor wafer 5 during pick-up by a handling device such as a collet, or to pass the hardened body (sealing material layer 40) of the resin composition for semiconductor sealing to ease the collet, etc. The impact applied to the semiconductor wafer 5 when the conveyor is in contact. Therefore, it is possible to prevent the semiconductor wafer 5 from being damaged (fragmented) due to an impact applied when the semiconductor wafer 5 is picked up by a transport device such as a collet. Therefore, a semiconductor device having a structure excellent in reliability can be realized.

Here, in the singulated semiconductor wafer described in Patent Document 2, the side surface or the back surface (the surface opposite to the surface on which the bump is formed) is not protected, and the underlying semiconductor material is exposed. According to the study by the inventors, it has been found that when an operation such as picking up or transporting is performed in a state where the surface is exposed, there is a high possibility that a fragment is generated in the semiconductor wafer.

On the other hand, in the manufacturing process of the present embodiment, the semiconductor wafer 5 can be operated in a state in which the sealing material layer 40 is formed on the side surface 9 and the back surface 4 of the semiconductor wafer 5 (the surface opposite to the main surface 3). Thereby, it is possible to suppress the fragments generated at the time of picking up or transporting. Therefore, according to the method of manufacturing a semiconductor device of the present embodiment, the semiconductor device 8 having excellent reliability can be obtained as compared with the prior manufacturing process.

Further, according to the method of manufacturing the semiconductor device 8 of the present embodiment, after the singulation, the plurality of semiconductor wafers 5 can be resin-sealed at one time. Therefore, the productivity of the semiconductor device 8 can be improved.

Therefore, in the present embodiment, a method of manufacturing a semiconductor device capable of achieving both reliability and productivity can be realized.

Hereinafter, each step of the method of manufacturing the semiconductor device will be described.

3 to 5 are cross-sectional views showing steps of an example of a method of manufacturing the semiconductor device 8 of the embodiment.

Fig. 3 (a) is a view showing an example of the semiconductor wafer 1 of the present embodiment. Fig. 3(b) is a view showing the semiconductor wafer 1 to which the protective film 10 is attached to the circuit forming surface. Figure 3 (c) The figure shows the semiconductor wafer 1 after grinding the surface on the opposite side of the circuit formation surface. Fig. 3 (d) is a view showing the semiconductor wafer 1 to which the dicing film 20 is attached on the surface opposite to the circuit forming surface. Fig. 3(e) is a view showing the semiconductor wafer 1 before the dicing of the protective film 10 from the circuit formation surface.

4(a) is a view for explaining the steps of obtaining the semiconductor wafer 5. Figure 4(b) is a diagram for explaining the steps of setting the interval. Fig. 4 (c) is a view for explaining a step of covering the circuit forming surface by the transfer member 30. Fig. 4 (d) is a view for explaining the steps of peeling off the dicing film 20. 4(e) and 4(f) are views for explaining the steps of sealing using the semiconductor sealing resin composition 49. Fig. 5(a) is a view showing a step of peeling off the release film 50. Fig. 5(b) is a view showing a step of singulating the semiconductor device 8. Fig. 5 (c) is a view showing a step of peeling off the transfer member 30.

As shown in FIGS. 3 to 5 above, the method of manufacturing the semiconductor device of the present embodiment is carried out by a semiconductor wafer level process. That is, the method of manufacturing the semiconductor device of the present embodiment may include a step of preparing a semiconductor wafer 1 on which a circuit is formed on the main surface 3, and an attaching step of attaching the semiconductor wafer 1 to the adhesive layer ( a protective film 10); a first dividing step of dividing a semiconductor wafer 1 attached to a bonding layer (cut film 20) along a dicing region to obtain a plurality of semiconductor wafers 5; and a sealing step, wherein The main surface 3 of the plurality of semiconductor wafers 5 is attached to the adhesive layer (transfer member 30), and the plurality of semiconductor wafers 5 are once sealed, thereby forming a gap 12 between the side faces 9 of the semiconductor wafer 5 and the semiconductor. A sealing material layer 40 composed of a semiconductor sealing resin composition 49 is formed on the back surface 4 of the wafer 5; and a second dividing step of dividing the sealing material layer 40 formed in the gap 12 of the side surface 9 of the semiconductor wafer 5 And obtaining a plurality of semiconductor wafers having a sealing material layer 40 on the side surface 9 and the back surface 4 (semiconductor Body device 8).

In the present embodiment, for example, a semiconductor wafer in which a single layer or a plurality of wiring layers are formed on a germanium substrate can be used. In the semiconductor wafer 1, the surface on which one side of the wiring layer is formed will be referred to as a circuit forming surface (main surface 3).

In the present embodiment, as the above-mentioned adhesive layer, a plurality of layers of the same type or different types may be used. For example, as the adhesive layer, the protective film 10, the dicing film 20, the transfer member 30, and the like can be used for various operational purposes. The adhesive member (the protective film 10 or the transfer member 30) may be a separate body of the adhesive tape or a member in which an adhesive layer is formed on the support substrate. The protective film 10 can protect the semiconductor wafer 1 from impact or the like. The transfer member 30 can change the contact surface autonomous surface 3 of the adhesive layer to the back surface 4 or the main surface 3 from the back surface 4 while maintaining the arrangement of the semiconductor wafer 5, that is, change to the opposite side.

The details of the dicing film 20, the transfer member 30, the protective film 10, and the release film 50 used in the respective steps of the production method of the present embodiment will be described below.

First, the following steps will be described in which the semiconductor wafer 1 is singulated in a state in which the dicing film 20 is attached to the surface of the semiconductor wafer 1 opposite to the circuit forming surface, and attached to the dicing film 20 is obtained. The step of a plurality of semiconductor wafers 5 in the state.

First, a semiconductor wafer 1 having a circuit formed on the main surface 3 is prepared. As shown in FIG. 3(a), a semiconductor wafer 1 in which a plurality of external connection bumps (solder bumps 2) are formed over the entire circuit formation surface (main surface 3) is prepared. In the present embodiment, the wafer may have a circular shape in plan view or a rectangular shape. The wafer means a plate shape of a thin layer, and is not particularly limited as long as it has at least an area in which a plurality of wafers are cut out.

Then, the semiconductor wafer 1 is attached to the adhesive layer (protective film 10). Figure 3 (b), in order to protect the circuit forming surface (main surface 3) of the prepared semiconductor wafer 1, the protective film 10 is attached to the circuit forming surface, and the entire surface of the circuit forming surface is covered by the protective film 10. In this manner, it is possible to prevent the electronic component mounted on the circuit forming surface from being damaged by the impact applied to the circuit forming surface when the surface of the semiconductor wafer 1 opposite to the circuit forming surface is polished.

Then, as shown in FIG. 3(c), the surface (back surface 4) on the opposite side to the circuit formation surface (main surface 3) of the semiconductor wafer 1 to which the protective film 10 is attached is removed. Thereby, the film pressure of the semiconductor wafer 1 is made thin. For example, the back surface 4 of the semiconductor wafer 1 can be polished by chemical mechanical polishing (CMP) or the like. Specifically, the semiconductor wafer 1 in a state in which the protective film 10 is attached is fixed to a polishing apparatus, and the surface opposite to the circuit formation surface is polished so that the thickness of the semiconductor wafer 1 becomes a predetermined thickness.

In the present embodiment, the upper limit of the film thickness of the semiconductor wafer 1 after the step of thinning the film thickness can be, for example, 300 μm or less, or 200 μm or less. Thereby, the thinning of the obtained semiconductor device can be achieved. On the other hand, the lower limit of the film thickness is not particularly limited, and may be, for example, 100 μm or more, or 150 μm or more. Thereby, the mechanical strength of the semiconductor wafer 1 or the semiconductor wafer 5 can be sufficiently obtained.

In recent years, there has been an increase in demand for miniaturization and weight reduction of electronic devices equipped with semiconductor devices. In order to meet such requirements, thinning of the semiconductor wafer is performed. In the process of thinning a semiconductor wafer in recent years, the above-described problem of damage to the semiconductor wafer due to the impact applied during pick-up by a transport device such as a collet tends to be more conspicuous.

However, according to the manufacturing process of the present embodiment, even when the thinned semiconductor wafer 1 is used as described above, it is possible to sufficiently suppress the pick-up by the transport device such as the collet The impact of the application causes the semiconductor wafer to be damaged. The reason for this is that the semiconductor wafer 5 can be operated in a state in which the sealing material layer 40 is formed on the side surface 9 and the back surface 4 of the semiconductor wafer 5 (the surface opposite to the main surface 3) as described above.

In the manufacturing method of the present embodiment, as described above, the surface (back surface 4) of the semiconductor wafer 1 opposite to the circuit forming surface (main surface 3) is polished while the protective film 10 is attached. Therefore, it is possible to effectively prevent the electronic components mounted on the circuit forming surface of the semiconductor wafer 1 from being damaged due to the stress generated during polishing.

Then, as shown in FIG. 3(d), the dicing film 20 is attached to the circuit forming surface of the semiconductor wafer 1 obtained by the polishing in a state where the protective film 10 is attached to the circuit forming surface (main surface 3). ) is the opposite side (back 4).

Then, as shown in FIG. 3(e), the protective film 10 is peeled off from the semiconductor wafer 1. Further, the main surface 3 of the semiconductor wafer 1 is exposed. At this time, the protective film 10 is preferably peeled off from the semiconductor wafer 1 after the adhesion between the protective film 10 and the semiconductor wafer 1 is lowered. Specifically, a method in which the adhesion layer of the protective film 10 forming the adhesion portion is deteriorated by, for example, ultraviolet irradiation or heat treatment of the protective film 10 and the subsequent portion of the semiconductor wafer 1 is used, thereby reducing the adhesion. .

Next, the division step (first division step) of the semiconductor wafer will be described. In the first dividing step of the embodiment, the semiconductor wafer 5 attached to the bonding layer (cut film 20) is divided along the dicing region to obtain a plurality of semiconductor wafers 5.

Fig. 11 is a plan view showing a cut region of the semiconductor wafer 1 in plan view. Although the plan view is different from the actual process, it can be used to understand the cutting area. The semiconductor wafer 1 of Fig. 11 has a circular shape. Regarding the cutting area, the first cutting line 13 is located The direction in which the second cutting lines 14 are orthogonal. Cutting along these cutting lines is possible. Further, the area defined by the first dicing line 13 and the second dicing line 14 is the semiconductor wafer area 15 of the semiconductor wafer. By reducing the width of the dicing area, the number of effective wafers can be increased. L1 in Fig. 11 refers to the cutting width.

Specifically, the semiconductor wafer 1 in a state in which the dicing film 20 is attached to the surface (back surface 4) opposite to the circuit formation surface shown in FIG. 3(e) is singulated, and FIG. 4(a) is produced. A plurality of semiconductor wafers 5 in the state of the dicing film 20 are attached as shown. The dicing (segmentation) of the semiconductor wafer 1 can use a cutting blade, a laser, or the like.

With respect to the semiconductor wafer 5 shown in FIG. 4(a), the adjacent semiconductor wafers 5 are separated from each other and disposed on the dicing film 20. A gap 11 is formed between the side faces 9 of the semiconductor wafer 5. The cross-sectional width of the gap 11 corresponds to the cutting width L1 in cross section.

In addition, when the semiconductor wafer 1 is singulated, it is necessary to keep the dicing film 20 in a state in which the obtained plurality of semiconductor wafers 5 are attached without being cut. The dicing film 20 may also form a slit along the dicing region from the end face of the semiconductor wafer 5 toward the inside. The slit does not penetrate the dicing film 20 from the upper surface to the lower surface, and may be, for example, 1/2 of the film thickness or 1/3 depth. With this slit, the dicing film 20 can be smoothly expanded in the expansion step between the next semiconductor wafers 5. Thereby, the gap of the semiconductor wafer 5 can be expanded more uniformly.

Next, a step of expanding the gap between the side faces of the semiconductor wafer will be described.

In the present embodiment, after the semiconductor wafer 1 is divided into a plurality of semiconductor wafers 5, a step of expanding the distance between adjacent semiconductor wafers 5 may be additionally performed.

Specifically, as shown in FIG. 4(b), the dicing film 20 is made on the semiconductor wafer 5. The in-plane direction is expanded to expand the interval between adjacent semiconductor wafers 5 to a predetermined interval. Thereby, in the cross-sectional view, the width (expansion width L2) of the gap 12 after the expansion step can be made larger than the width (L1) of the gap 11 before the expansion step.

For example, the spacing between adjacent semiconductor wafers 5 is preferably equally spaced. That is, the interval between the adjacent semiconductor wafers 5 in the rectangular semiconductor wafer 5 is set to be the first direction in the direction parallel to one side of the semiconductor wafer 5, and the direction orthogonal to the first direction as the second direction. The directions may be expanded at equal intervals only in the first direction, or may be expanded at equal intervals only in the second direction, and preferably expanded at equal intervals in the first direction and the second direction. Therefore, when the interval between the adjacent semiconductor wafers 5 is increased, it is preferable that the interval between the adjacent semiconductor wafers 5 is equally expanded in the in-plane direction of the dicing film 20.

Here, as described above, in the manufacturing method of the present embodiment, the dicing film 20 is expanded in the in-plane direction of the circuit formation surface of the semiconductor wafer 5. Therefore, the dicing film 20 is preferably configured to have excellent elongation.

In the above expansion step, the dicing film 20 can be performed in a state of being heated. Thereby, the dicing film 20 is easily stretched. The heating temperature is not particularly limited, and it is preferable that the temperature distribution of the entire dicing film 20 is not uniform.

In the first dividing step, the expanding step may be performed after the semiconductor wafer 1 is divided and the slit is formed in the dicing film 20 (the subsequent layer). Since the slit film 20 is easily spread by the slit, it is possible to reduce the variation in the width (expansion width L2) of the gap 12 after the width (cut width L1) of the gap 11 between the semiconductor wafers 5 is expanded. Here, the expansion width L2 is larger than the cutting width L1. The upper limit of the expansion width L2 is not particularly limited. For example, it is preferably larger than the total width of the film thickness of the sealing material layer 40 on the side surface 9.

As described above, the first dividing step in the embodiment may include the step of obtaining a plurality of semiconductor wafers by dividing the semiconductor wafer 1 by attaching the back surface 4 of the semiconductor wafer 1 to the front and back layers. 5; and an expanding step of expanding the interval between the adjacent semiconductor wafers 5 (gap 11). Thereby, the sealing step can be carried out while expanding the interval between the semiconductor wafers 5.

When the interval between the adjacent semiconductor wafers 5 in the present embodiment is increased to a predetermined interval, the dicing film 20 may be expanded by using a known cutting device.

Here, when the interval between the adjacent semiconductor wafers 5 is enlarged, for example, the following expansion device can be used.

6 and 7 are configuration examples of an expansion device which can be used when the interval between adjacent semiconductor wafers 5 is enlarged. Fig. 6 is a view showing a state before the interval between the adjacent semiconductor wafers 5 is enlarged. Fig. 6(a) is a side cross-sectional view, and Fig. 6(b) is a plan view. Fig. 7 is a view showing a state in which the interval between the adjacent semiconductor wafers 5 is enlarged, Fig. 7(a) is a side cross-sectional view, and Fig. 7(b) is a plan view.

The apparatus of FIGS. 6 and 7 includes an annular frame 100 that is clamped around the dicing film 20 of the plurality of semiconductor wafers 5 obtained by singulation, and an expansion stage 140 disposed inside the frame 100 Below the dicing film 20, the dicing film 20 is expanded by moving upward; the heating unit 130 is disposed on the expansion stage 140, and the expansion stage 140 is heated; and the expansion stage 140 is divided into the central portion 110. The heating portion 130 is provided on the surface of the central portion 110 of the expansion table 140 that is different from the contact surface of the dicing film 20, and the peripheral portion 120.

Further, it is preferable that the region of the plurality of semiconductor wafers 5 in the state in which the dicing film 20 is attached to the expansion stage 140 is uniform in temperature. Thus, the inside of the dicing film 90 can be The expandability of the dicing film 20 is uniformly controlled.

Further, the apparatus of FIGS. 6 and 7 can improve the expandability of the dicing film 20 by heating the expansion stage 140 by the heating unit 130.

As described above, the apparatus of FIGS. 6 and 7 can move the expansion stage 140 upward while heating the central portion 110 and the peripheral portion 120 of the expansion stage 140. Thereby, the expandability of the in-plane direction of the dicing film 20 can be uniformly increased, and the expansion stage 140 can be moved upward. Therefore, as shown in FIG. 7, the dicing film 20 can be uniformly expanded so that the interval between the adjacent semiconductor wafers 5 becomes equal intervals.

Next, the one-time sealing step of the semiconductor wafer will be described.

In the first embodiment, the dividing step and the expanding step are performed in a state where the dicing film 20 is attached to the back surface 4 of the semiconductor wafer 1. In the following one-time sealing step, in order to perform the step of sealing the back surface of the semiconductor wafer 5, it is preferable to expose the back surface 4 in advance. These series of operations are referred to as transfer steps. Further, when the dividing step or the like is performed in a state where the back surface 4 of the semiconductor wafer 1 is exposed, the above-described transfer step is unnecessary, and the manufacturing process can be simplified.

First, the above transfer step will be described.

In the present embodiment, the transfer surface can change the bonding surface of the semiconductor wafer 5 to the opposite side while maintaining the arrangement state of the semiconductor wafer 5. Specifically, as shown in FIG. 4( c ), the transfer member is attached so as to span the entire circuit formation surface (main surface 3 ) of the plurality of semiconductor wafers 5 in a state in which the dicing film 20 is attached to the back surface 4 . 30. At this time, the transfer member 30 may be attached so as to cover the entire surface of the solder bump 2 and the circuit forming surface of the semiconductor wafer 5, or the transfer member 30 may be in contact with the circuit forming surface of the semiconductor wafer 5, Take It is attached only by covering a part of the surface of the solder bump 2 (refer to FIG. 9(a)). In the manufacturing method of the present embodiment, by controlling the degree of adhesion of the transfer member 30 (the depth of embedding of the solder bumps 2), it is possible to adjust the resin sealing in the step of sealing using the semiconductor sealing resin composition 49 described below. The area.

Then, as shown in FIG. 4(d), the dicing film 20 is peeled off from the semiconductor wafer 5. By attaching the transfer member 30 in a state in which the dicing film 20 is attached, the dicing film 20 is peeled off, whereby the transfer member 30 can be attached without intervening the gap formed between the semiconductor wafers 5 Attached to the semiconductor wafer 5. Further, the dicing film 20 is preferably peeled off from the semiconductor wafer 5 after the adhesion between the dicing film 20 and the semiconductor wafer 5 is lowered. Specifically, a method in which the adhesive layer of the dicing film 20 forming the subsequent portion is deteriorated by, for example, ultraviolet irradiation or heat treatment of the dicing film 20 and the subsequent portion of the semiconductor wafer 5 is used, thereby reducing the adhesion.

In addition, the transfer member 30 is not particularly limited, and for example, it is preferably configured to have heat resistance and fixation capable of withstanding the heat applied to cure the semiconductor sealing resin composition 49 described below. The adhesion of the semiconductor wafer 5 on the transfer member 30 to a degree that does not deviate. The transfer member 30 may be a separate body of an adhesive tape, or may be a member that imparts rigidity to an adhesive member made of a metal member such as metal or plastic. Further, in the present embodiment, for example, a transfer member to which an adhesive tape is attached to a metal plate member made of a 42 alloy is used.

The structure 7 shown in Fig. 4(d) is obtained by the steps up to this point. The structure 7 has a structure in which a plurality of semiconductor wafers 5 having an adhesive member (transfer member 30) and an adhesive surface attached to the adhesive member (transfer member 30) are provided, and the plurality of semiconductor wafers 5 are spaced apart from each other by a predetermined interval. And disposed, and attached to the adhesive surface of the adhesive member (transfer member 30) with a plurality of semiconductors The circuit forming surface (main surface 3) of the bulk wafer 5. In other words, the step of preparing the structure 7 of the present embodiment may include a step of attaching the dicing film 20 to the surface (back surface 4) of the semiconductor wafer 1 opposite to the circuit forming surface. The wafer 1 is singulated to obtain a plurality of semiconductor wafers 5 attached to the dicing film 20; the regions of the dicing film 20 to which the plurality of semiconductor wafers 5 are attached are expanded in the in-plane direction, and the adjacent semiconductors are made. The interval between the wafers 5 (gap 11) is expanded to a predetermined interval; the adhesive member is attached in such a manner that the circuit forming surface (main surface 3) of the plurality of semiconductor wafers 5 is in contact with the adhesive surface of the adhesive member (transfer member 30); The dicing film 20 is peeled off from the semiconductor wafer 5 in a state where the plurality of semiconductor wafers 5 are attached to the adhesive surface of the adhesive member.

Then, the plurality of semiconductor wafers 5 are once sealed in a state in which the main faces 3 of the plurality of semiconductor wafers 5 are attached to the adhesive layer (transfer member 30). Specifically, as shown in FIG. 4(e), a resin composition for semiconductor encapsulation 49 which is liquid on the support substrate is prepared. For example, a resin composition for semiconductor encapsulation 49 which is in a flowing state by melting is disposed on the release film 50 (support substrate). In other words, the semiconductor sealing resin composition 49 in the flowing state on the release film 50 and the main surface 3 are disposed to face the back surface 4 of the plurality of semiconductor wafers 5 of the transfer member 30.

Then, as shown in FIG. 4(f), the semiconductor sealing resin composition 49 in a flowing state is pressure-bonded to the surface (back surface 4) of the plurality of semiconductor wafers 5 on the opposite side to the circuit formation surface. Then, the semiconductor sealing resin composition 49 is cured by heat treatment, whereby the sealing material layer 40 can be formed. Thereby, the sealing material layer 40 can be filled in the space (gap 12) between the adjacent semiconductor wafers 5. Further, the sealing material layer 40 can be sealed so as to cover the surface (back surface 4) and the side surface 9 of the semiconductor wafer 5 on the opposite side to the circuit formation surface. For example, you can also use the secret The sealing material layer 40 is filled with a gap between the adjacent semiconductor wafers 5, and the entire surface or a part of the solder bumps 2 is exposed, and the top surface and the side surface of the semiconductor wafer 5 are sealed by the sealing material layer 40. Further, the sealing material layer 40 may be formed on the outer surface of the side surface 9 of the semiconductor wafer 5 located on the outer periphery of the plurality of semiconductor wafers 5.

In the present embodiment, when the semiconductor wafer 5 to be produced is picked up by the collet, the portion to be adsorbed by the collet can be protected by the cured body (sealing material layer 40) of the resin composition for sealing a semiconductor body. By this means, the semiconductor obtained by the semiconductor sealing resin composition 49 is covered with the surface and the side surface opposite to the circuit forming surface of the semiconductor wafer 5, and the semiconductor obtained by picking up the semiconductor can be picked up by a transport device such as a collet. Wafer 5. Therefore, according to the manufacturing method of the present embodiment, it is possible to prevent the semiconductor wafer 5 from being damaged due to the impact applied when the semiconductor wafer 5 is picked up by the transport device such as the collet.

Here, the semiconductor sealing resin composition 49 in a flowing state may be a thermosetting resin composition in a molten state, or may be a liquid resin composition, or may be a resin formed into a film shape or a sheet shape. A resin composition in which the composition is in a softened state. As a method of disposing the resin composition for semiconductor encapsulation 49, a film composed of a resin composition for semiconductor encapsulation can be laminated, and a paste composed of a resin composition for semiconductor encapsulation can be placed by infusion.

Here, a case where the solid particulate resin composition is used as the semiconductor sealing resin composition will be described in detail as an example of the step of sealing the semiconductor wafer.

The method of sealing the semiconductor wafer 5 using the semiconductor sealing resin composition 49 is not particularly limited, and examples thereof include a transfer molding method, a compression molding method, an injection molding method, a lamination method, and the like. Preferably, the semiconductor wafer 5 to be fixed is less likely to be produced. Compression forming method for positional offset. In addition, When the semiconductor wafer 5 is sealed by compression molding, the resin composition may be resin-sealed using a powdery resin composition. Further, details of the semiconductor sealing resin composition 49 will be described below.

Specifically, a resin material supply container that accommodates the particulate resin composition is provided between the upper mold and the lower mold of the compression molding die. Then, the semiconductor wafer 5 to which the adhesive layer (transfer member 30) is attached is fixed to one of the upper mold and the lower mold of the compression molding die by a fixing means such as clamping or suction. Hereinafter, a case where the semiconductor wafer 5 is fixed to the upper mold of the compression molding die so that the surface opposite to the circuit formation surface and the resin material supply container face each other will be described as an example.

Then, while reducing the distance between the upper mold and the lower mold of the mold under reduced pressure, the weighed granular resin composition is supplied to the lower mold by a resin material supply mechanism such as a baffle constituting the bottom surface of the resin material supply container. It has the cavity under the mold cavity. In the mold cavity, the release film 50 must be left in advance. By this, the particulate resin composition is heated to a predetermined temperature in the lower mold cavity, and as a result, the semiconductor sealing resin composition 49 which is in a molten state on the release film 50 can be prepared. Then, the semiconductor wafer 5 fixed to the upper mold is pressed against the resin composition for semiconductor sealing 49 in a molten state by bonding the upper mold of the mold to the lower mold. In this way, the semiconductor sealing resin composition 49 in a molten state can be filled with the interval formed between the adjacent semiconductor wafers 5, and the top surface and the side surface of the semiconductor wafer 5 can be covered by the semiconductor sealing resin composition 49. After that, the semiconductor sealing resin composition 49 is cured while maintaining the state in which the upper mold and the lower mold are joined.

Here, in the case of performing compression molding, it is preferred to perform resin sealing while the inside of the mold is under reduced pressure, and it is preferably under vacuum. So, for forming adjacent In the space between the semiconductor wafers 5, the semiconductor sealing resin composition 49 can be satisfactorily filled without leaving an unfilled portion.

The molding temperature at the time of compression molding is not particularly limited, but is preferably 50 to 200 ° C, particularly preferably 80 to 180 ° C. Further, the molding pressure is not particularly limited, but is preferably 0.5 to 12 MPa, and particularly preferably 1 to 10 MPa. Further, the molding time is preferably from 30 seconds to 15 minutes, and particularly preferably from 1 to 10 minutes. By setting the molding temperature, the pressure, and the time to the above range, it is possible to prevent the occurrence of a positional shift between the portion of the semiconductor sealing resin composition 49 in the unfilled molten state and the semiconductor wafer 5.

Then, by dividing the sealing material layer 40 formed in the gap 12 of the side surface 9 of the semiconductor wafer 5 (second dividing step), a plurality of semiconductor wafers 5 having the sealing material layer 40 formed on the side surface 9 and the back surface 4 can be obtained. .

Specifically, as shown in FIG. 5( a ), first, the release film 50 disposed on the back surface (surface 41 ) of the sealing material layer 40 is peeled off.

Then, as shown in FIG. 5(b), the sealing material layer 40 located in the gap 12 of the semiconductor wafer 5 is divided. The division width of the second division step is set to L3. By adjusting the second division width L3, the film thickness of the sealant layer 40 remaining on the side surface 9 can be controlled.

Specifically, for example, in a state in which the transfer member 30 is attached to the semiconductor wafer 5, the cured body (sealing material layer 40) of the semiconductor sealing resin composition 49 filled in the space 12 is cut, and the single piece is cut. The plurality of semiconductor wafers 5 sealed by the sealing material layer 40 are formed. At this time, the transfer member 30 can be cut together with the sealing material layer 40, or can be attached to the semiconductor wafer 5 without being cut, and the productivity of the semiconductor device 8 can be improved. When the semiconductor wafer 5 is singulated, it is preferable to maintain the semiconductor crystal across the transfer member 30 without cutting the transfer member 30. The state of the sheet 5 attached. Further, the dicing of the above-described semiconductor wafer 5 may use a dicing blade, a laser or the like.

Then, as shown in FIG. 5(c), the transfer member 30 is peeled off from the semiconductor device 8. Thus, the semiconductor device 8 of the present embodiment can be fabricated. Further, the transfer member 30 is preferably peeled off from the semiconductor wafer 5 after the adhesion between the transfer member 30 and the semiconductor device 8 is lowered. Specifically, a method in which the adhesive layer of the transfer member 30 on which the bonding portion is formed is deteriorated by, for example, ultraviolet irradiation or heat treatment of the transfer member 30 and the subsequent portion of the semiconductor wafer 5, thereby reducing the adhesion layer Adhesion.

In addition, the obtained semiconductor device 8 can also be mounted on a substrate as needed. Further, when the fabricated semiconductor device is mounted on a substrate, a known device such as a flip chip mounter or a die bonder can be used.

According to the above, the semiconductor device 8 can be obtained by the method of manufacturing the semiconductor device of the present embodiment.

According to the manufacturing method of the present embodiment, the semiconductor wafer 5 can be obtained by covering the surface of the semiconductor wafer 5 opposite to the circuit formation surface by the cured body (sealing material layer 40) of the semiconductor sealing resin composition. In the state where the side surface is protected, the pick-up is performed by a conveying device such as a collet. With this configuration, it is possible to prevent the transfer device such as the collet from directly contacting the semiconductor wafer 5, and to apply the hardened body (sealing material layer 40) of the resin composition for semiconductor encapsulation to the semiconductor wafer 5 when picking up by a transport device such as a collet. The impact. Therefore, according to the manufacturing method of the present embodiment, it is possible to prevent the semiconductor wafer 5 from being damaged due to an impact applied during picking up by a transport device such as a collet. In other words, according to the manufacturing method of the present embodiment, it is possible to alleviate the suction and picking up by the transport device such as the collet. The impact of the impact applied by the semiconductor wafer 5. Therefore, according to the manufacturing method of the present embodiment, the semiconductor device 8 having excellent reliability can be manufactured as compared with the conventional manufacturing method. Further, according to the manufacturing method of the present embodiment, the plurality of semiconductor wafers 5 obtained can be resin-sealed at one time without being disposed on the substrate after singulation. Therefore, the production efficiency can be drastically improved as compared with the prior manufacturing method. Further, when the semiconductor device 8 obtained by the manufacturing method of the present embodiment is mounted on a substrate, since the sealing material layer 40 is separated from the substrate, the adhesion between the sealing material layer 40 and the substrate can be suppressed. Bad, can further improve reliability.

In the present embodiment, the protective film 10 is used to protect the circuit forming surface of the semiconductor wafer 1 when the surface of the semiconductor wafer 1 opposite to the circuit forming surface is polished. In the third embodiment, As described below, the function of the dicing film 20 used for singulating the semiconductor wafer 1 in the present embodiment and the surface and the side surface of the semiconductor wafer 5 which are opposite to the circuit forming surface are provided in the present embodiment. The function of the transfer member 30 used for sealing. Therefore, the production method of the third embodiment described above is more excellent in terms of production efficiency. According to the manufacturing method of the present embodiment, since the different adhesive members 10 and 30 are used in each manufacturing step, in order to maintain the The strength of the adhesive members 10 and 30 can be used separately or the like. In other words, according to the manufacturing method of the embodiment, it is possible to accurately manufacture a semiconductor device having excellent reliability.

The semiconductor device of this embodiment will be described.

1 and 2 are cross-sectional views showing an example of the semiconductor device 8 of the present embodiment.

As shown in FIGS. 1 and 2, the semiconductor device 8 of the present embodiment includes: a semiconductor wafer 5; a solder bump 2 provided on a lower surface (main surface 3) of the semiconductor wafer 5; and a sealing material The layer 40 covers at least a portion of the top surface and the side surface of the semiconductor wafer 5; and the entirety or a portion of the solder bump 2 is exposed.

Specifically, the semiconductor device 8 shown in FIG. 1 includes a semiconductor wafer 5 having a circuit formed on the main surface 3, and a sealing material layer 40 covering the entire side surface 9 of the semiconductor wafer 5 and the entire back surface 4; A block (solder bump 2) which forms a sealing material layer 40 around the semiconductor wafer 5 in plan view and is formed only on the main surface 3 region of the semiconductor wafer 5.

The semiconductor device 8 of the present embodiment includes a semiconductor wafer 5 in which at least a part of the top surface (back surface 4) and the side surface 9 of the semiconductor wafer 5 is covered with the sealing material layer 40. As described above, when the semiconductor device 8 is manufactured, even if the semiconductor wafer 5 is picked up by the collet, the semiconductor wafer 5 can be prevented from being damaged in advance. Therefore, the semiconductor device 8 obtained by the manufacturing process of the present embodiment is superior in reliability to the conventional semiconductor device.

As shown in FIG. 1, the lower surface (main surface 3) of the semiconductor wafer 5 is entirely exposed. In other words, the entire main surface 3 of the semiconductor wafer 5 is not covered by the sealing material layer 40. That is, the main surface 3 of the semiconductor wafer 5 can be formed on the same surface as the surface 45 of the sealing material layer 40 opposite to the top surface (surface 41). Here, the same surface means that substantially the same surface of the micro unevenness which is unavoidable in the process such as the surface roughness of the transfer member 30 can be allowed. That is, in the semiconductor device 8 of FIG. 1, the entire solder bump 2 has a structure that is not covered by the sealing material layer 40 and is exposed.

On the other hand, in the semiconductor device 8 of FIG. 2, a portion of the lower surface (main surface 3) of the semiconductor wafer 5 and a portion of the solder bump 2 are covered by the sealing material layer 40. In other words, in the main surface 3 of the semiconductor wafer 5, the region on the inner side of the region where the solder bump 2 is disposed on the outer peripheral portion is not covered by the sealing material layer 40 and is exposed. The solder bump 2 has a structure in which a part of the solder bump 2 is covered by the sealing material layer 40 from the main surface 3 side of the semiconductor wafer 5 toward the opposite side, but the front end portion is exposed.

Both of the semiconductor devices 8 of FIGS. 1 and 2 can realize a structure in which the sealing material layer 40 and the substrate are not in contact with each other when mounted on a substrate. That is, in the present embodiment, the sealing material layer 40 may have a structure that is not sealed to the mounting substrate on which the semiconductor wafer 5 is mounted.

According to the semiconductor device 8 of the present embodiment, when the semiconductor device 8 is mounted on a substrate, the structure of the prior semiconductor device in which the substrate is bonded to the sealing material is different. That is, it is possible to realize a structure in which both the sealing material layer 40 and the mounting substrate are not in contact with each other. As a result, it is possible to provide the semiconductor device 8 that is smaller than the conventional semiconductor device. Further, since the semiconductor device 8 has a structure different from the structure of the prior semiconductor device in which the substrate is bonded to the sealing material, the mother board can be directly mounted without passing through the interposer. Further, since the semiconductor device 8 can realize a structure in which the sealing material layer 40 is not in contact with the substrate and is separated from each other, it is possible to solve the problem of poor adhesion between the substrate and the sealing material generated in the conventional semiconductor device. Therefore, the semiconductor device 8 excellent in reliability can be realized as compared with the conventional semiconductor device. In addition, the semiconductor device 8 is configured to cover the surface and the side surface of the semiconductor wafer 5 opposite to the circuit forming surface by the hardened body (sealing material layer 40) of the semiconductor sealing resin composition, and is protected from the previous state. Compared with the semiconductor device, it is also excellent in chipping resistance.

Further, since the entire or a part of the solder bumps 2 of the semiconductor device 8 of the present embodiment is exposed, it is excellent in handleability and can be used in various processes. Specifically, the semiconductor device 8 of the present embodiment can be mounted on various substrates such as a mother board, an interposer, and a lead frame.

<Second embodiment>

A method of manufacturing the semiconductor device of the second embodiment will be described.

Fig. 9 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

In the second embodiment, the transfer step in the first embodiment (Fig. 4(c)) The transfer member 30 is buried in a portion of the solder bump 2 on the semiconductor wafer 5 and does not differ from the main surface 3 of the semiconductor wafer 5 in surface contact.

Specifically, as shown in FIG. 9( a ), the transfer member 30 is attached to the semiconductor wafer 5 so as to cover a portion of the solder bump 2 and not in surface contact with the circuit of the semiconductor wafer 5 . The semiconductor wafer 5 is once sealed in this configuration state.

In the present embodiment, the resin composition for semiconductor encapsulation 49 in a liquid state is filled on the surface (back surface 4) and the side surface 9 of the semiconductor wafer 5 opposite to the circuit formation surface, and is also filled in the circuit formation surface of the semiconductor wafer 5 ( Main face 3). Thereby, it is possible to perform one-time sealing so that the side surface 9, the back surface 4, and the main surface 3 of the semiconductor wafer 5 are covered with the sealing material layer 40. According to the second embodiment, the same effects as those of the first embodiment can be obtained, and in particular, the fragmentation during the operation can be further suppressed.

Fig. 8 is a cross-sectional view showing an example of the semiconductor device 8 of the embodiment.

The semiconductor device 8 shown in FIG. 8 is different from the first embodiment in that the entire lower surface (main surface 3) of the semiconductor wafer 5 is covered by the sealing material layer 40. In addition, a portion of the front end portion of the bump (solder bump 2) has a structure protruding from the sealing material layer 40, and is exposed.

Also in the semiconductor device 8 shown in FIG. 8, as in the first embodiment, at least a part of the top surface and the side surface of the semiconductor wafer 5 is covered with the sealing material layer 40. Therefore, similarly to the first embodiment, the semiconductor device 8 shown in FIG. 8 can solve the problem that the semiconductor wafer is damaged by the impact applied when the semiconductor wafer is picked up by the collet in the conventional semiconductor device. Therefore, the semiconductor device 8 of the present embodiment can be a semiconductor device excellent in reliability as compared with the conventional semiconductor device.

Further, as in the semiconductor device 8 shown in FIG. 8, as in the first embodiment, Since one of the solder bumps 2 is partially exposed, when the semiconductor device 8 is mounted on the substrate, the sealing material layer 40 can be separated from the substrate and the two can be separated.

<Third embodiment>

A method of manufacturing the semiconductor device of the third embodiment will be described.

Fig. 10 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

The manufacturing method of this embodiment can be simplified without going through the transfer step of the first embodiment. In other words, the first dividing step and the one-time sealing step can be performed in a state where the adhesive layer 10 (the protective film 10) is attached to the main surface 3 of the semiconductor wafer 5. Specifically, the structure 7 is provided, and the structure 7 includes a plurality of semiconductor wafers 5 in a state in which the protective film 10 and the adhesive surface of the protective film 10 are attached, and the protective film 10 can be attached to a plurality of semiconductors. The semiconductor wafer 5 is directly sealed in the state of the wafer 5.

Further, the step of preparing the structure 7 in the embodiment includes the step of attaching the adhesive member in such a manner that the circuit forming surface (main surface 3) of the semiconductor wafer 1 is in contact with the adhesive surface of the adhesive member (protective film 10). In the state, the semiconductor wafer 1 is singulated to obtain a plurality of semiconductor wafers 5 attached to the adhesive member, and the region of the adhesive member to which the plurality of semiconductor wafers 5 are attached is expanded in the in-plane direction. The interval between the adjacent semiconductor wafers 5 is expanded to a predetermined interval.

The above steps will be described below.

As shown in FIG. 10(a), the semiconductor wafer 1 in a state in which the protective film 10 is attached to the main surface 3 is singulated, and a plurality of semiconductor wafers 5 in a state in which the protective film 10 is attached are produced. Further, when the semiconductor wafer 1 is diced, the protective film 10 is not cut, whereby the state in which the obtained plurality of semiconductor wafers 5 are attached can be maintained.

Then, as shown in FIG. 10(b), for example, the protective film 10 may be expanded in the in-plane direction of the semiconductor wafer 5, and the interval between the adjacent semiconductor wafers 5 may be increased to a predetermined interval. Further, the semiconductor wafers 5 may be equally expanded in the in-plane direction of the adhesive member (protective film 10).

Then, as shown in FIGS. 10(c) and 10(d), the resin composition for semiconductor encapsulation 49 in a flowing state is brought into contact with the surface of the plurality of semiconductor wafers 5 on the opposite side to the circuit formation surface, and the adjacent semiconductor is adjacent. The semiconductor sealing resin composition 49 is filled between the wafers 5, and the semiconductor sealing resin composition 49 covers the surface and the side surface of the semiconductor wafer 5 opposite to the circuit forming surface, and is sealed.

According to the above method, the semiconductor device 8 having the same configuration as that of the first embodiment can be obtained. Further, according to the present embodiment, the same effects as those of the first embodiment can be obtained. Moreover, according to the manufacturing method of the present embodiment, the manufacturing process of the semiconductor device 8 can be simplified, and thus the production efficiency can be further drastically improved as compared with the conventional manufacturing method.

<Fourth embodiment>

A method of manufacturing the semiconductor device of the fourth embodiment will be described.

Fig. 12 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

In the fourth embodiment, the step of narrowing the cutting width in which the dividing width L3 in the second dividing step is narrower than the dividing width L1 in the first dividing step can be performed. In other words, in the fourth embodiment, the other embodiment is different from the first embodiment in that the division width is reduced.

First, as shown in FIG. 12(a), the main surface 3 of the semiconductor wafer 1 is attached to the protective film 10 (adjacent layer). Then, as shown in FIG. 12(b), the dicing is performed from the side of the back surface 4 of the semiconductor wafer 1. In the cross-sectional view, the width of the gap 11 formed by the first cutting is divided into Width L1. Thereafter, as shown in FIG. 12(c), the plurality of semiconductor wafers 5 are once sealed in a state in which the main surface 3 of the semiconductor wafer 1 is attached to the protective film 10. Thereby, the sealing material layer 40 is formed on the side surface 9 and the back surface 4 of the semiconductor wafer 5. Further, the sealing material layer 40 is filled in the gap 11 of the side surface 9 of the semiconductor wafer 5.

Then, as shown in FIG. 12(d), the sealing material layer 40 located in the gap 11 between the adjacent semiconductor wafers 5 is cut along the dicing region. In the cross-sectional view, the width of the gap formed by the second cutting is set as the division width L3. Thereafter, the semiconductor device 8 of the present embodiment can be obtained by peeling off the protective film 10.

In the present embodiment, as the cutting method, blade cutting or laser cutting can be used. Further, as a method of changing the cutting width, for example, a method of reducing the blade width, reducing the irradiation diameter of the laser, or changing the cutting method from the blade to the laser or reducing the number of blades of the blade can be used.

The thickness of the film thickness of the sealing material layer 40 remaining on the side surface 9 of the semiconductor wafer 5 can be adjusted by reducing the cutting width. Thereby, the film thickness of the sealing material layer 40 on the side surface 9 of the semiconductor wafer 5 can be made thick. Therefore, it is possible to suppress the fragmentation during the operation, and it is possible to realize a structure that improves the reliability of the semiconductor device. Moreover, in order to increase the number of effective wafers of the semiconductor wafer 1, the division width L3 can be reduced in a state where the division width L1 is narrowed. Thereby, the number of effective fragments can be increased and the above reliability can be improved.

In the present embodiment, the lower limit of the division width L1 can be, for example, 50 μm or more, or 60 μm or more. Thereby, it is easy to fill the semiconductor sealing resin composition between the semiconductor wafers 5. The upper limit of the division width L1 can be, for example, 150 μm or less, or 100 μm or less. Thereby, the number of effective wafers of the semiconductor wafer 1 can be increased.

In the present embodiment, the division width L3 is not particularly limited as long as it is smaller than the division width L1. The lower limit of the division width L3 can be, for example, 10 μm or more, or 20 μm or more. Thereby, the controllability of cutting can be improved. The upper limit of the division width L3 can be, for example, 50 μm or less, or 40 μm or less. Thereby, the film thickness of the sealing material layer 40 on the side surface 9 of the semiconductor wafer 5 can be ensured. Therefore, in the fourth embodiment, the same effects as those of the first embodiment can be sufficiently obtained.

<Fifth Embodiment>

A method of manufacturing the semiconductor device of the fifth embodiment will be described.

Fig. 13 is a view for explaining an example of a method of manufacturing the semiconductor device of the embodiment.

In the fifth embodiment, the step of forming the external connection bumps (solder bumps 2) on the main surface 3 of the semiconductor wafer 1 after the sealing step is different from the first embodiment. That is, in the first embodiment, after the bumps are formed, the first dividing step and the one-time sealing step are performed, and in the fifth embodiment, the bumps are formed after the first dividing step and the one-time sealing step are performed. Thereafter, a second segmentation step is performed. Thereby, not only the wiring layer and the bumps can be formed on the main surface 3 of the semiconductor wafer 5, but also the wiring layer and the bumps can be formed outside the region.

Hereinafter, each step will be described.

First, as shown in FIG. 13(a), a semiconductor wafer 1 in which a circuit is formed on the main surface 3 is prepared. Further, the main surface 3 has a structure in which the solder bumps 2 are not formed (together with the wiring layer (not shown)). Then, for example, the protective film 10 is attached to the main surface 3 of the semiconductor wafer 1.

Then, as shown in FIG. 13(b), the above-described first dividing step and one-time sealing step are carried out. An expansion step can also be implemented.

Thereafter, as shown in FIG. 13(c), the protective film 10 is peeled off. At this time, the surface 45 of the main surface 3 of the plurality of semiconductor wafers 5 and the sealing material layer 40 on the opposite side to the top surface (surface 41) is exposed. The main faces 3 and 45 can form the same plane.

Then, a wiring layer (not shown) and solder bumps 2 are formed on the main surface 3 of the semiconductor wafer 5 and the surface 45 of the sealing material layer 40. The solder bumps 2 can be formed not only on the main surface 3 but also on the face 45 of the sealing material layer 40. Thereby, the width between the semiconductor wafers 5 can be increased. Thereafter, singulation is performed by performing the second division step described above. By the above method, the semiconductor device 8 shown in Fig. 14 (d) can be obtained.

Details of each member used in the present embodiment will be described.

Hereinafter, the configuration of the resin composition for semiconductor encapsulation 49, the dicing film 20, the transfer member 30, the protective film 10, and the release film 50 of the present embodiment will be described.

<Resin composition for semiconductor sealing>

Hereinafter, the aspect in which the resin composition for semiconductor encapsulation is a particulate resin composition will be described in detail, but the invention is not limited thereto.

The resin composition for semiconductor encapsulation of the present embodiment preferably contains an epoxy resin as a constituent material thereof. The epoxy resin is, for example, a monomer, an oligomer or a polymer having two or more epoxy groups in one molecule, and the molecular weight and molecular structure of the epoxy resin are not particularly limited. Specific examples thereof include a crystalline epoxy resin such as a biphenyl type epoxy resin, a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a fluorene type epoxy resin, or a hydroquinone type epoxy resin. a phenolic novolac type epoxy resin, a phenol novolac type epoxy resin, a naphthol novolak type epoxy resin, and the like, and a novolac type epoxy resin; a phenylene group-containing phenol aralkyl type epoxy resin, Phenylene aralkyl type epoxy resin of phenylene skeleton, naphthol aralkyl type epoxy tree containing phenylene skeleton Phenol aralkyl type epoxy resin such as lipid; trifunctional epoxy resin such as trisphenol methane epoxy resin, alkyl modified trisphenol methane epoxy resin; dicyclopentadiene modified phenol epoxy resin A modified phenol type epoxy resin such as a terpene-modified phenol type epoxy resin; an epoxy resin containing a heterocyclic ring such as an epoxy resin containing a triazine core, or the like, one or a combination of two or more of them may be used. use.

In addition, the method of obtaining the particulate resin composition is not particularly limited, and examples thereof include a method of supplying a molten inner side of a rotor composed of a cylindrical outer peripheral portion having a plurality of small holes and a disk-shaped bottom surface. The resin composition to be kneaded is obtained by a centrifugal force obtained by rotating the rotor, and the resin composition is obtained by passing through a small hole (hereinafter also referred to as "centrifugal milling method"); the raw material components are premixed by a mixer, and then used. After kneading and kneading by a kneading machine such as a roll, a kneader or an extruder, the mixture is cooled and pulverized to obtain a pulverized product, and the pulverized material is obtained by removing coarse particles and fine powder using a sieve (hereinafter also referred to as "crushing and sieving". The method of pre-mixing the raw material components by a mixer, and then using an extruder equipped with a plurality of small-diameter nozzles at the tip end portion of the screw to perform heating and kneading, and self-distributing the small holes in the nozzle The molten resin is extruded and the molten resin is cut by a cutter that slides in parallel with the die surface to obtain a molten resin (hereinafter also referred to as "thermal cutting method"). In either method, the desired particle size distribution or particle density can be obtained by selecting kneading conditions, centrifugation conditions, sieving conditions, cutting conditions, and the like. As a particularly preferable method, the centrifugal powder forming method can stably exhibit a desired particle size distribution or particle density, and therefore is preferable in terms of transportability on the transport path or adhesion prevention. Further, since the centrifugal milling method can smooth the surface of the particles to some extent, there is no case where the particles are implicated or the frictional resistance with the conveyed road surface is increased, and bridging (clogging) of the supply port to the transport path is prevented. It is also preferable to prevent the retention on the transport path. In addition, since the centrifugal milling method is formed by using centrifugal force in a molten state, it is packaged in a particle. In a state in which a certain degree of void is contained, the particle density can be lowered to some extent, and therefore the conveyance property at the time of compression molding is advantageous.

On the other hand, the pulverization and sieving method must be studied for the treatment of a large amount of fine powder and coarse particles produced by sieving, but the sieving device or the like is used in the existing manufacturing line of the resin composition for semiconductor sealing, so that it can be directly used. The use of previous manufacturing lines is preferred in this regard. Further, regarding the pulverization sieving method, the selection of the thickness of the sheet when the molten resin is sheeted before pulverization, the pulverization conditions at the time of pulverization or the selection of the sieve, the selection of the sieve at the time of sieving, and the like are used to express the particle size of the present invention. There are many factors that can be independently controlled by the distribution, and therefore there are many options for adjusting to the desired particle size distribution, and it is preferable in this respect. In addition, the thermal cutting method can also directly utilize the prior manufacturing line to the extent that the thermal cutting mechanism is added to the front end of the extruder, for example, in this respect.

<cut film>

In the dicing film 20 of the present embodiment, when the semiconductor wafer 1 is singulated, it can be kept attached to the semiconductor wafer 5 which has not been cut. The dicing film 20 is not particularly limited as long as it can follow the semiconductor wafer 1 and has a small shift from the position of the semiconductor wafer 5. The dicing film 20 may have, for example, a multi-layered laminated structure having an adhesive layer laminated on a support film. Further, the dicing film 20 may have a function of changing the adhesion force by a small amount by heating or irradiating ultraviolet rays. Thereby, the peeling property from the adherend (semiconductor wafer 5) can be improved.

The constituent material of the support film is not particularly limited, and for example, may be selected from the group consisting of polyethylene, polypropylene, ethylene-propylene copolymer, polyolefin, polybutene, polybutadiene, polymethylpentene, polyvinyl chloride, poly Vinylidene chloride, vinyl chloride copolymer, polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate, polyurethane, ethylene-vinyl acetate copolymer, ionic polymer, Ethylene-(meth)acrylic acid copolymer, ethylene-(meth)acrylate copolymerization , polystyrene, ethylene polyisoprene, polycarbonate, polyphenylene sulfide, polyetheretherketone, acrylonitrile-butadiene-styrene copolymer, polyimine, polyetherimine, A resin of one or more of the group consisting of polyamines, fluororesins, and the like.

Further, in order to improve the adhesion to the adhesive layer, the surface of the support film may be subjected to chemical or physical surface treatment. Further, in the support film, various additives (filler, plasticizer, antioxidant, flame retardant, antistatic agent) may be contained in the range which does not impair the effects of the invention.

Further, as the adhesive layer of the dicing tape, a first resin composed of an acrylic adhesive, a rubber-based adhesive, a vinyl alkyl ether-based adhesive, an anthrone-based adhesive, a polyester-based adhesive, or the like can be used. The layer of adhesive formed by the object. Among these, an acrylic adhesive can be used.

<transfer member (adhesive member)>

Then, as described above, the transfer member 30 of the present embodiment is preferably configured to have heat resistance to a degree that can withstand heat applied to cure the semiconductor sealing resin composition 49, and is fixed to The semiconductor wafer 5 on the transfer member 30 does not have a degree of adhesion. Specifically, the transfer member 30 of the present embodiment preferably has a structure in which a base material layer and an adhesive layer are laminated.

The subsequent layer is composed of a resin composition containing a resin capable of undergoing a crosslinking reaction and a compound having flux activity. Examples of the resin capable of undergoing a crosslinking reaction include an epoxy resin, an oxetane resin, a phenol resin, a (meth) acrylate resin, an unsaturated polyester resin, and diallyl phthalate. A resin which is classified into a thermosetting resin, such as a resin or a maleimide resin, and a thermoplastic resin having a functional group such as a carboxyl group or an epoxy group, and the like can be used as a resin capable of undergoing a crosslinking reaction. Among these, it is preferred to use hardening An epoxy resin excellent in properties, preservability, heat resistance of a cured product, moisture resistance, and chemical resistance.

The compound having flux activity is not particularly limited as long as it has an effect of removing a metal oxide film by heating or the like. For example, it may be an organic acid such as an active rosin or an organic compound having a carboxyl group, an amine, a phenol, an alcohol or a salt, or the like which has a flux activity or a compound which promotes the activity of the flux.

More specifically, the compound having flux activity may be a compound having at least one or more carboxyl groups and/or phenolic hydroxyl groups in the molecule, and the compound may be in the form of a liquid or a solid.

Further, when there is no particular requirement for properties such as heat resistance, dimensional stability, and moisture resistance, an inorganic filler may be further contained. Examples of such an inorganic filler include talc, calcined clay, uncalcined clay, mica, glass, etc.; titanium oxide, aluminum oxide, molten cerium oxide (melted spherical cerium oxide, melt-crushed oxidizing)矽), oxides such as crystalline cerium oxide; carbonates such as calcium carbonate, magnesium carbonate, hydrotalcite; hydroxides such as aluminum hydroxide, magnesium hydroxide, calcium hydroxide; barium sulfate, calcium sulfate, calcium sulfite Such as sulfate or sulfite; zinc borate, barium metaborate, aluminum borate, calcium borate, sodium borate and other borate; aluminum nitride, boron nitride, tantalum nitride and other nitrides. These inorganic fillers may be used singly or in combination. Among these, cerium oxide powder such as molten cerium oxide or crystalline cerium oxide is preferable, and molten spherical cerium oxide is particularly preferable.

By including the inorganic filler in the resin composition, heat resistance, moisture resistance, strength, and the like after curing the resin composition can be improved, and the peelability of the adhesive layer to the semiconductor wafer 5 can be improved. Further, the shape of the inorganic filler is not particularly limited, and is preferably a true spherical shape, whereby it is possible to provide a resin composition which is preferable as an adhesive layer particularly having no anisotropy. Things.

Further, the substrate layer is, for example, a polyolefin such as polyethylene or polypropylene, an ethylene-vinyl acetate copolymer, a polyester, a polyimide, a polyethylene terephthalate, a polyvinyl chloride, or a poly A film excellent in heat resistance or chemical resistance prepared by guanamine or polyurethane can be used. The thickness of the base material layer is not particularly limited, but is usually preferably from 30 to 500 μm.

<Protective film (adhesive member)>

Then, the protective film 10 protects the circuit forming surface when polishing the surface of the semiconductor wafer 1 opposite to the circuit forming surface. The protective film 10 is not particularly limited as long as it is attached to the semiconductor wafer 1, and may be, for example, a laminated back surface polishing tape and an adhesive layer. Further, as shown in FIG. 10, the protective film 10 may be used as a protective member for singulating the semiconductor wafer 1, and the protective film 10 may be expanded in the in-plane direction, and sometimes for sealing the semiconductor. The resin composition 49 is hardened to apply heat. Therefore, the protective film 10 is preferably configured to have a certain degree of expandability, to withstand heat resistance to the extent of heat applied to cure the semiconductor sealing resin composition 49, and to be fixed to the protective film. The semiconductor wafer 5 on the 10 does not deviate to the extent of adhesion.

The protective film 10 is composed of a back grinding tape and an adhesive layer. Further, a release film 50 may be provided between the back polishing tape and the adhesive layer. Thereby, the back surface grinding tape and the adhesive layer are easily peeled off.

The subsequent layer is composed of a resin composition containing a resin capable of undergoing a crosslinking reaction and a compound having flux activity. Examples of the resin capable of undergoing a crosslinking reaction include an epoxy resin, an oxetane resin, a phenol resin, a (meth) acrylate resin, an unsaturated polyester resin, and diallyl phthalate. A resin which is classified into a thermosetting resin, such as a resin or a maleimide resin, and a functional group such as a carboxyl group or an epoxy group. A thermoplastic resin or the like is used as a resin capable of undergoing a crosslinking reaction. Among these, an epoxy resin excellent in curability and storage stability, heat resistance of a cured product, moisture resistance, and chemical resistance is preferably used.

The compound having flux activity is not particularly limited as long as it has an effect of removing the metal oxide film by heating or the like. For example, it may be an organic acid such as an active rosin or an organic compound having a carboxyl group, an amine, a phenol, an alcohol or a salt, or the like which has a flux activity itself or a function of promoting flux activity.

More specifically, the compound having flux activity may be a compound having at least one or more carboxyl groups and/or phenolic hydroxyl groups in the molecule, and the compound may be in the form of a liquid or a solid.

Further, the back grinding belt is, for example, a polyolefin such as polyethylene or polypropylene, an ethylene-vinyl acetate copolymer, a polyester, a polyimide, a polyethylene terephthalate, a polyvinyl chloride, or a poly A film excellent in heat resistance or chemical resistance produced by guanamine or polyurethane can be used. The thickness of the back surface polishing tape is not particularly limited, and is usually 30 to 500 μm.

<release film>

In addition, the release film 50 is not particularly limited as long as it has a structure having excellent mold release property, and for example, a release film having a release layer containing a polyester resin material is preferable.

The release film 50 of the present embodiment is a release film 50 having a release layer (first release layer) containing a polyester resin material.

In the release film 50 of the present embodiment, the release layer is a resin which forms a surface which is in contact with the object (hereinafter also referred to as a "release surface") when the release film 50 is placed on the object. The layer, the polyester resin, refers to a polycondensate of a polyvalent carboxylic acid (dicarboxylic acid) and a polyhydric alcohol (diol), and is a compound having a plurality of carboxyl groups (-COOH).

In the present embodiment, the polyester resin material is not particularly limited, and examples thereof include polyethylene terephthalate resin, polybutylene terephthalate resin, and polytrimethylene terephthalate resin. A polyalkylene terephthalate resin such as a polybutylene terephthalate resin. Among these, it is preferred to use a polybutylene terephthalate resin.

The release film 50 of the present embodiment can have a single layer structure or a multilayer structure.

Although the embodiments of the present invention have been described above, the various configurations other than the above may be employed as exemplified by the present invention.

In the above-described embodiment, the case where the semiconductor wafer 5 is sealed by the use of the particulate semiconductor sealing resin composition 49 for compression molding has been described as an example. However, it may be a spin coating method, a printing method, or a distribution method. The liquid semiconductor sealing resin composition 49 is applied to the surface of the semiconductor wafer 5 opposite to the circuit forming surface, and then dried, and the surface of the semiconductor wafer 5 opposite to the circuit forming surface may be pressed under pressure. The semiconductor sealing resin composition 49 which is formed into a film shape and softened is pressed and infiltrated, and the liquid semiconductor sealing resin composition 49 can be caused to flow into the space between the adjacent semiconductor wafers 5 by capillary action.

Further, in the above-described embodiment, the case where the semiconductor device 1 is mounted on the semiconductor wafer 1 on which the plurality of solder bumps 2 are mounted on the circuit formation surface has been described as an example. However, "the circuit formation surface is not mounted much." Solder bumps are mounted on the circuit formation surface of the semiconductor wafer 5 in a subsequent step of manufacturing the semiconductor wafer 1 of the solder bumps 2, and manufacturing the semiconductor device 8 in which at least a portion of the lower surface of the semiconductor wafer 5 is not covered by the sealing material layer 40. After mounting to the substrate, the semiconductor wafer 5 and the substrate can be electrically connected by wire bonding.

In addition, when the semiconductor wafer 5 is sealed, it is also possible to use a half processed into a sheet shape. The sealing material (hereinafter referred to as a sheet-like sealing material) composed of the resin composition for conductor sealing 49 is laminated by the following method.

First, the sheet-like sealing material prepared in the shape of a roll is attached to a take-up device of a vacuum press type bonding machine, and is connected to a winding device. Then, the semiconductor wafer 1 to which the protective film 10 is attached is transferred to a separator (elastic film) type laminator. Then, when pressure is applied, the sheet-like sealing material is heated to a predetermined temperature to be in a molten state, and then the sheet-like sealing material in a molten state is pressurized by a separator to be used for the semiconductor wafer. The pressure is applied to the slit 20 formed in the semiconductor wafer 1 by the sheet-like sealing material, and the surface of the semiconductor wafer 1 opposite to the circuit formation surface can be covered with the sheet-like sealing material. Thereafter, it takes a predetermined time to harden the sheet-like sealing material. In this way, the semiconductor wafer 5 can be sealed.

In addition, when it is required to provide higher-precision flatness to the sheet-like sealing material, it may be formed by pressurizing with a flat-type pressurizing device which is adjusted with high precision after being pressurized by a diaphragm type bonding machine. .

In the above-mentioned laminate molding, the forming temperature of the separator (elastic film) type laminator portion is preferably 50 to 120 ° C, more preferably 80 to 110 ° C. Further, the forming pressure of the separator (elastic film) type laminating machine portion is preferably 0.5 to 1 MPa, and more preferably 0.6 to 0.9 MPa. Further, the forming time of the separator (elastic film) type laminating machine portion is preferably from 30 seconds to 5 minutes, more preferably from 1 to 3 minutes. By setting the molding temperature, pressure, and time of the separator (elastic film) type laminating machine portion to the above range, it is possible to prevent the portion of the sheet-like sealing material that is not filled in the molten state from being generated.

In the above lamination molding, the pressing temperature of the flat pressurizing means is preferably 80 to 130 ° C, more preferably 90 to 120 ° C. Further, the forming pressure of the flat pressurizing means is preferably 0.5 to 2 MPa, and more preferably 0.8 to 1.5 MPa. Moreover, the forming time of the flat pressurizing device It is preferably from 30 seconds to 5 minutes, and more preferably from 1 to 3 minutes. By setting the pressurization temperature, the molding pressure, and the time of the flat pressurizing device to the above range, it is possible to prevent the portion of the sheet-like sealing material that is not filled in the molten state from being generated.

Further, after the semiconductor wafer 5 is hermetically formed by the lamination molding method using the sheet-like sealing material, the post-curing temperature is preferably 150 to 200 ° C, more preferably 165 to 185 ° C. Further, the post-cure time is preferably from 1 hour to 5 hours, and more preferably from 2 hours to 4 hours.

The priority of Japanese Patent Application No. 2014-175135, filed on Jan. 29,,,,,,,,,,,

Claims (17)

A method of manufacturing a semiconductor device, comprising: a preparation step of preparing a semiconductor wafer on which a circuit is formed on a main surface; a attaching step of attaching the semiconductor wafer to an adhesive layer; and a first dividing step And obtaining a plurality of semiconductor wafers by dividing the semiconductor wafer attached to the bonding layer along the dicing region; and sealing step of attaching the main surface of the plurality of semiconductor wafers to the bonding layer a plurality of the semiconductor wafers are sealed at one time, thereby forming a sealing material layer composed of a semiconductor sealing resin composition on a gap between the side faces of the semiconductor wafer and a back surface of the semiconductor wafer; and a second dividing step The plurality of semiconductor wafers on which the sealing material layer is formed on the side surface and the back surface are obtained by dividing the sealing material layer formed in a gap between the side faces of the semiconductor wafer. The method of manufacturing a semiconductor device according to claim 1, wherein the attaching step comprises the steps of: attaching a main surface of the semiconductor wafer to the bonding layer; and removing the back surface of the semiconductor wafer The film thickness of the semiconductor wafer is reduced. The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the film thickness of the semiconductor wafer after the step of thinning the film thickness is 100 μm or more and 300 μm or less. The method of manufacturing a semiconductor device according to claim 1, wherein The division width in the second division step is smaller than the division width in the first division step. The method of manufacturing a semiconductor device according to claim 1, wherein the first dividing step includes the step of: performing the semiconductor wafer by attaching the back surface of the semiconductor wafer to the bonding layer Dividing to obtain a plurality of the semiconductor wafers; and expanding the steps to expand the interval between the adjacent semiconductor wafers; and the sealing step is performed while expanding the interval between the semiconductor wafers. The method of manufacturing a semiconductor device according to claim 5, wherein the first dividing step is performed by dividing the semiconductor wafer and forming a slit in the adhesive layer, and then performing the expanding step. The method of manufacturing a semiconductor device according to claim 1, wherein in the preparing step, the external connection bump is formed on the main surface of the semiconductor wafer. The method of manufacturing a semiconductor device according to claim 1, wherein after the sealing step, a step of forming an external connection bump on the main surface of the semiconductor wafer is performed, and then performing the second dividing step . A method of manufacturing a semiconductor device, comprising the steps of: providing a structure including an adhesive member and a plurality of semiconductor wafers attached to an adhesive surface of the adhesive member, wherein the plurality of semiconductor wafers are disposed at a predetermined interval from each other And forming a circuit of the plurality of semiconductor wafers on the adhesive surface of the adhesive member a resin composition for semiconductor encapsulation in a flowing state is brought into contact with a plurality of the semiconductor wafers, and the resin composition for semiconductor encapsulation is filled at the interval, and the semiconductor wafer is covered with the resin composition for semiconductor encapsulation The surface is formed on the opposite side and the side surface is sealed, and the resin composition for semiconductor encapsulation is cured. The method of manufacturing a semiconductor device according to claim 9, wherein the step of preparing the structure includes the step of attaching a dicing film to a surface of the semiconductor wafer opposite to the circuit forming surface, The semiconductor wafer is singulated to obtain a plurality of semiconductor wafers attached to the dicing film; and a region of the dicing film to which the plurality of semiconductor wafers are attached is expanded in a film in-plane direction to be adjacent The interval between the semiconductor wafers is increased to the predetermined interval; the adhesive member is attached to the circuit forming surface of the plurality of semiconductor wafers in contact with the adhesive surface of the adhesive member; and the plurality of semiconductor wafers are attached to the semiconductor wafer The dicing film is peeled off from the semiconductor wafer in a state in which the adhesive member is adhered to the surface. The method of manufacturing a semiconductor device according to claim 10, wherein, in the step of expanding an interval between the adjacent semiconductor wafers to the predetermined interval, the interval is equal to an in-plane direction of the dicing film expansion. The method of manufacturing a semiconductor device according to claim 9, wherein the step of preparing the above-described structure comprises the steps of: The semiconductor wafer is singulated in a state in which the above-mentioned adhesive member is attached so that the circuit forming surface of the semiconductor wafer is in contact with the adhesive surface of the adhesive member, thereby obtaining a state of being attached to the adhesive member. And a semiconductor wafer; and a region of the adhesive member to which the plurality of semiconductor wafers are attached is expanded in a film in-plane direction, and an interval between the adjacent semiconductor wafers is increased to the predetermined interval. The method of manufacturing a semiconductor device according to claim 12, wherein in the step of expanding an interval between adjacent semiconductor wafers to the predetermined interval, the interval is equally expanded in an in-plane direction of the adhesive member . The method of manufacturing a semiconductor device according to the ninth aspect of the invention, further comprising the step of: cutting a cured body of the semiconductor sealing resin composition filled in the space, and singulating the semiconductor sealing resin A plurality of the above semiconductor wafers whose composition is sealed. A semiconductor device comprising: a semiconductor wafer having a circuit formed on a main surface; a bump formed on the main surface; and a sealing material layer covering a side surface of the semiconductor wafer and a back surface opposite to the main surface . The semiconductor device of claim 15, wherein the bump is exposed without being covered by the sealing material layer. The semiconductor device of claim 15, wherein the sealing material layer is formed over the entire main surface of the semiconductor wafer And a portion of the bump is exposed from the sealing material layer.