TWI704688B - 半導體裝置與其製作方法 - Google Patents

半導體裝置與其製作方法 Download PDF

Info

Publication number
TWI704688B
TWI704688B TW107140217A TW107140217A TWI704688B TW I704688 B TWI704688 B TW I704688B TW 107140217 A TW107140217 A TW 107140217A TW 107140217 A TW107140217 A TW 107140217A TW I704688 B TWI704688 B TW I704688B
Authority
TW
Taiwan
Prior art keywords
width
opening
fin
gate
gate structure
Prior art date
Application number
TW107140217A
Other languages
English (en)
Other versions
TW201933608A (zh
Inventor
楊宜偉
洪志昌
古淑瑗
張銘慶
陳嘉仁
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201933608A publication Critical patent/TW201933608A/zh
Application granted granted Critical
Publication of TWI704688B publication Critical patent/TWI704688B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

半導體裝置與其形成方法包括自基板延伸的第一鰭狀物與第二鰭狀物。第一閘極部份位於第一鰭狀物上，且第二閘極部份位於第二鰭狀物上。層間介電層與第一閘極部份及第二閘極部份相鄰。切割區(如第一閘極結構與第二閘極結構之間的開口或間隙)延伸於第一閘極部份與第二閘極部份之間。切割區具有第一寬度的第一部份與第二寬度的第二部份，且第二寬度大於第一寬度。第二部份夾設於第一閘極部份與第二閘極部份之間，且第一部份定義於層間介電層中。

Description

半導體裝置與其製作方法
本發明實施例關於金屬閘極結構與相關方法，更特別關於金屬閘極切割製程與相關結構。
電子產業對更小和更快的電子裝置的需求不斷增長，這些電子設備同時能支援日益複雜的多種功能。綜上所述，半導體產業中持續的趨勢為製作低成本、高效能、與低能耗的積體電路。藉由縮小半導體積體電路尺寸(如最小結構尺寸)可達這些目標，進而改善產能並降低相關成本。然而尺寸縮小亦增加半導體製程的複雜性。因此為實現半導體積體電路與裝置的持續進展，需要半導體製程與技術的類似進展。
多閘極裝置可增加閘極通道耦合、降低關閉狀態的電流、並減少短通道效應以改善閘極控制。多閘極裝置之一為鰭狀場效電晶體。鰭狀場效電晶體的名稱來自於形成於基板上的鰭狀結構自基板向上延伸，且鰭狀結構用於形成場效電晶體的通道。鰭狀場效電晶體與習知的互補式金氧半製程相容，且其三維結構在更緊密地排列時仍可維持閘極控制並減少短通道效應。此外，可導入金屬閘極以置換多晶矽閘極。金屬閘極與多晶矽閘極相較，其優點在於避免多晶矽空乏效應、可選擇合適的閘極金屬以調整功函數、以及其他優點。舉例來說，製作金屬閘極的製程可包含沉積金屬層之後，接著進行金屬層切割製程。在一些例子中，金屬閘極線路切割製程可能導致損失層間介電層的部份、產生不需要的金屬層殘留物、及/或劣化裝置可信度的其他問題。
因此現有技術無法完全符合所有方面的需求。
本發明一實施例提供之半導體裝置，包括自基板延伸的第一鰭狀物與第二鰭狀物。第一閘極部份位於第一鰭狀物上，而第二閘極部份位於第二鰭狀物上。層間介電層與第一閘極部份及第二閘極部份相鄰。切割區(比如第一閘極結構與第二閘極結構之間的開口或間隙)延伸於第一閘極部份與第二閘極部份之間。切割區具有第一寬度的第一部份與第二寬度的第二部份，第二寬度大於第一寬度。第二部份夾設於第一閘極部份與第二閘極部份之間，且第一部份定義於層間介電層中。
本發明一實施例提供半導體裝置的製作方法，其包括形成自半導體基板延伸的第一鰭狀物與第二鰭狀物，其中淺溝槽隔離延伸於第一鰭狀物與第二鰭狀物之間。形成閘極結構以延伸於第一鰭狀物與第二鰭狀物上。提供介電層以與閘極結構相鄰。蝕刻閘極結構與介電層以形成開口於閘極結構中，且開口至少延伸至淺溝槽隔離的上表面。蝕刻所形成的開口中，開口的第一部份具有第一寬度，且開口的第一部份由閘極結構的第一切割部份之第一側壁與閘極結構的第二切割部份之第二側壁所定義。開口的第二部份具有第二寬度，且開口的第二部份具有介電層所定義的邊緣，且第一寬度大於第二寬度。開口的第三部份在上視圖中位於第一部份與第二部份之間。將介電材料填入開口。
本發明一實施例提供之半導體裝置的製作方法，其包括切割金屬閘極結構成同一條線上的第一金屬閘極部份與第二金屬閘極部份。切割步驟包括：進行第一製程以沉積矽層以及進行第二製程以進行蝕穿。實施例亦包括對金屬閘極結構的功函數金屬層進行蝕刻。蝕刻包括高偏壓與高負載循環。可進行聚合物沉積步驟。重複第一製程、第二製程、蝕刻、與聚合物沉積步驟。
θ:角度
D1、D2:深度
T1、T2:厚度
W1、W2、W3、W4:寬度
X-X’、Y-Y’:剖面
100:鰭狀場效電晶體裝置
102:基板
104:鰭狀物
105:源極區
107:汲極區
106:隔離區
108:閘極結構
108A、108B:金屬閘極結構部份
110:閘極介電層
112:金屬層
114、302、304:硬遮罩層
116:側壁間隔物
118、804、902、1202:開口
210:金屬閘極切割圖案
212:部份
306:層間介電層
308:側壁
500:方法
502、504、506、508、510、512:步驟
600:鰭狀場效電晶體結構
702:硬遮罩層堆疊
702A:第一層
702B:第二層
802:三層光阻
802A:底層
802B:中間層
802C:上側層
1002:再沉積層
1402:介電層
圖1係本發明一或多種實施例中，鰭狀場效電晶體裝置的透視圖。
圖2係一些實施例中，相鄰的鰭狀物、金屬閘極結構、與金屬閘極切割圖案的上視圖。
圖3A與3B分別為本發明實施例中，已切割金屬閘極線路的鰭狀場效電晶體結構的剖視圖。
圖4係本發明實施例中，已切割金屬閘極線路的鰭狀場效電晶體結構的上視圖。
圖5係本發明一或多個實施例中，形成半導體裝置的方法之流程圖。
圖6A、7A、8A、9A、10A、11A、12A、13A、與14A係依據圖5的方法中，鰭狀場效電晶體結構沿著實質上平行於圖1的剖面X-X’之平面的剖視圖。
圖6B、7B、8B、9B、10B、11B、12B、13B、與14B係依據圖5的方法中，鰭狀場效電晶體結構沿著實質上平行於圖1的剖面Y-Y’之平面的剖視圖。
圖12C與14C係依據圖5的方法中，如圖1之鰭狀場效電晶體的上視圖。
可以理解的是，下述內容提供的不同實施例或實例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本揭露之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
值得注意的是，本發明實施例形成的多閘極電晶體或鰭狀多閘極電晶體，指的是鰭狀場效電晶體裝置。此裝置可包含p型金氧半鰭狀場效電晶體裝置或n型金氧半鰭狀場效電晶體裝置。鰭狀場效電晶體裝置可為雙閘極裝置、三閘極裝置、基體裝置、絕緣層上矽裝置、及/或其他設置。本技術領域中具有通常知識者應理解，本發明實施例有利於實施半導體裝置的其他實施例。舉例來說，此處所述的一些實施例亦可實施至全環繞式閘極裝置、Ω閘極裝置、或Π閘極裝置。在其他實施例中，可採用此處所述的一或多種結構或方法製作平面裝置。
亦應注意的是，圖式僅為形成於基板上的裝置部份。在一些例子中，圖式中有兩個鰭狀物。在其他例子中，圖式中有其他的額外鰭狀物。在一些例子中，圖式中有兩個閘極。在其他例子中，圖式中只有單一閘極或額外的閘極。本技術領域中具有通常知識者應理解，半導體裝置中通常存在多個閘極與鰭狀物，因此圖式中的閘極或鰭狀物數量僅用以舉例說明而非侷限本發明實施例。
本發明實施例一般關於金屬閘極結構與相關方法。具體而言，本發明實施例關於金屬閘極切割製程與相關結構。可導入金屬閘極以置換多晶矽閘極。金屬閘極與多晶矽閘極相較，具有優點如可避免多晶矽空乏效應、可選擇合適的閘極金屬以調整功函數、或其他優點。舉例來說，金屬閘極製程可包含沉積金屬層。金屬閘極延伸越過基板的多個區域，因此必需切割或分離金屬閘極線路成彼此隔離的部份，以提供設計所需的電晶體等級功能。因此形成金屬閘極後，可依據此處所述的實施例進行後續的金屬閘極切割製程。本發明實施例與現有技術相較具有優點，但應理解其他實施例可具有不同優點，此處不必說明所有優點，且所有實施例不需具有特定優點。一般而言，此處所述的實施例提供金屬閘極切割製程與相關結構。本發明的至少一些實施例的切割可用 於提供切割閘極部份與開口的輪廓，其可改善金屬閘極結構的非切割部份之間的隔離。舉例來說，在至少一些現有製程中，錐形輪廓的開口在切割的閘極部份之間難以達到合適深度，且之後難以將介電材料填入切割區。這些困難會使切割部份之間的隔離效果不足。為減少上述的一或多個問題，本發明實施例提供切割金屬閘極的製程與結構，其可改善切割的閘極部份之間的隔離。
圖1顯示鰭狀場效電晶體裝置100。此處所述的多種實施例可用於製作鰭狀場效電晶體裝置100及/或存在於鰭狀場效電晶體裝置100中的最終結構。鰭狀場效電晶體裝置100包含一或多個鰭狀物為主的多閘極場效電晶體。鰭狀場效電晶體裝置100包含基板102、自基板102延伸的鰭狀物104、隔離區106、與位於鰭狀物104之上及周圍的閘極結構108。基板102可為半導體基板如矽基板。基板可包含多種層狀物，包含形成於半導體基板上的導電層或絕緣層。基板可包含多種摻雜設置，端視本技術領域已知的設計需求而定。基板亦可包含其他半導體如鍺、碳化矽、矽鍺、或鑽石。另一方面，基板可包含半導體化合物及/或半導體合金。此外，一些實施例的基板可包含磊晶層、可具有應變以增進效能、可包含絕緣層上矽基板、及/或可具有其他合適的增進結構。
鰭狀物104如同基板102，可包含矽或另一半導體元素如鍺、半導體化合物(包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、半導體合金(包含矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化銦鎵、磷化鎵銦、及/或磷砷化鎵銦)、或上述之組合。鰭狀物104的製作方法可採用合適製程，包含光微影與蝕刻製程。光微影製程通常包含形成光阻層(光阻)於基板上(如矽層上)、以圖案曝光光阻、進行曝光後烘烤製程、以及顯影光阻以形成含光阻的遮罩單元。在一些實施例中，圖案化光阻以形成遮罩單元，且圖案化方法可採用極紫外線微影製程或電子束微影製程。接著在形成凹陷至矽層中的蝕刻製程時，可採用遮罩單元保護基板的區域，以保留延伸的鰭狀物104。凹陷的蝕刻方 法可採用乾蝕刻(如化學氧化物移除)、濕蝕刻、及/或其他合適製程。亦可採用其他實施例的方法形成鰭狀物104於基板102上。
每一鰭狀物104亦包含源極區105與汲極區107形成於鰭狀物104之中、之上、及/或周圍。源極區105與汲極區107可磊晶成長於鰭狀物104或其部份上。電晶體的通道區位於鰭狀物104中及閘極結構108下。在一些例子中，鰭狀物104的通道區包含高遷移率的材料如鍺、上述半導體化合物或半導體合金、及/或上述之組合。高遷移率的材料包含電子遷移率大於矽之電子遷移率的材料。
隔離區106可為淺溝槽的隔離結構。另一方面，可實施場氧化物、局部氧化矽結構、及/或其他合適的隔離結構於基板102之上及/或之中。隔離區106的組成可為氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃、低介電常數的介電層、上述之組合、及/或本技術領域已知的其他合適材料。在一實施例中，隔離結構如淺溝槽隔離結構的形成方法可為蝕刻溝槽於基板102中。接著可將隔離材料填入溝槽，再進行化學機械研磨製程。然而可能採用其他實施例。在一些實施例中，隔離區106可包含多層結構，比如具有一或多個襯墊層。
在一些實施例中，閘極結構108包含閘極堆疊，其具有界面層形成於鰭狀物104的通道區上、閘極介電層110形成於界面層上、以及至少一金屬層112形成於閘極介電層110上。界面層可包含介電材料如氧化矽或氮氧化矽。界面層的形成方法可為化學氧化、熱氧化、原子層沉積、化學氣相沉積、及/或其他合適方法。閘極介電層110可包含高介電常數的介電層如氧化鉿。另一方面，高介電常數的介電層可包含其他高介電常數的介電層，比如氧化鈦、氧化鉿鋯、氧化鉭、氧化鉿矽、氧化鋯、氧化鋯矽、上述之組合、或其他合適材料。在其他實施例中，閘極介電層可包含氧化矽或其他合適介電層。介電層的形成方法可為原子層沉積、物理氣相沉積、氧化、及/或其他合適方法。金屬層112為一或多種代表性金屬組成，且可包含導電層如鎢、氮化鈦、氮化鉭、氮化鎢、錸、 銥、釕、鉬、鋁、鈷、鎳、上述之組合、及/或其他合適組成。在一些實施例中，金屬層112可包含用於n型鰭狀場效電晶體的第一金屬材料，與用於p型鰭狀場效電晶體的第二金屬材料。因此鰭狀場效電晶體裝置100可包含雙功函數金屬閘極的設置。舉例來說，用於n型裝置的第一金屬材料包含的金屬，其功函數可實質上對準基板導帶的功函數，或至少實質上對準鰭狀物104之通道區的導帶的功函數。類似地，用於p型裝置的第二金屬材料包含的金屬，其功函數可實質上對準基板價帶的功函數，或至少實質上對準鰭狀物104之通道區的價帶的功函數。金屬層112可包含多種額外層狀物以及提供功函數的層狀物，比如阻障層、晶種層、蓋層、充填層、及/或其他合適組成與功能的層狀物如下述。因此金屬層112可用於鰭狀場效電晶體裝置100(包含n型或p型的鰭狀場效電晶體裝置100)的閘極。金屬層112的形成方法可採用物理氣相沉積、化學氣相沉積、電子束蒸鍍、及/或其他合適製程。在一些實施例中，側壁間隔物116形成於閘極結構108的側壁上。側壁間隔物116可包含介電材料如氧化矽、氮化矽、碳化矽、氮氧化矽、或上述之組合。硬遮罩層114(如氮化矽等等)可位於閘極結構108的金屬層112之區域上。
值得注意的是，層間介電層可位於基板上，包括位於隔離區106、源極區105、與汲極區107上。圖1未顯示層間介電層以方便顯示其他層狀物。如下所述，金屬閘極切割圖案(如圖2的金屬閘極切割圖案210)可定義閘極結構108被移除的部份所在的區域，以提供閘極結構108之不連續的金屬閘極結構部份108A與108B。移除金屬閘極切割圖案中的閘極結構之部份，以形成開口118。開口118的輪廓如圖3A、3B、與4所示，其將詳述如下。開口118實質上填有絕緣材料，其包含搭配圖13A、13B、14A、14B、與14C說明的下述例子。
如圖2所示的上視圖，相鄰的鰭狀物104上為金屬的閘極結構108，且金屬的閘極結構108實質上垂直於鰭狀物104。在一些實施例中，圖2的剖面 X-X’可實質上平行於圖1的剖面X-X’所定義的平面，而圖2的剖面Y-Y’可實質上平行於圖1的剖面Y-Y’所定義的平面。在一些例子中，鰭狀物104與前述的鰭狀物104可實質上相同，而金屬的閘極結構108可與前述的金屬的閘極結構108的至少一些部份類似。舉例來說，圖2顯示金屬閘極切割圖案210。在一些例子中，可由圖案化的硬遮罩層(如下述)定義金屬閘極切割圖案210。在一些實施例中，金屬閘極切割圖案210提供開口(又稱作空間或區域，其插置於金屬閘極結構的部份之間)於圖案化的硬遮罩層中，且可經由開口進行金屬閘極線切割製程。可切割開口下之金屬的閘極結構108之部份212，自開口中的基板移除金屬閘極結構，以提供不連續的金屬閘極結構部份108A與108B與上述部份之間的開口118。在一些實施例中，金屬閘極切割圖案210(如硬遮罩中的開口)實質上為矩形，如圖2所示。在一些實施例中，金屬閘極切割圖案210為定義上的矩形，而採用金屬閘極切割圖案210所形成的開口(或區域)118(見圖1、3A、3B、與4)可不為矩形而具有下述輪廓。在一些實施例中，採用蝕刻製程搭配金屬閘極切割圖案210，以定義開口118的輪廓。此處所述的金屬閘極切割製程，可包含乾蝕刻製程、濕蝕刻製程、或上述之組合如下述，其可用於移除金屬閘極切割圖案210所定義的區域中金屬的閘極結構108之部份。舉例來說，金屬閘極線路切割製程可用於切割金屬閘極線路為分開、電性不相連、且物理不連續的金屬閘極結構部份108A與108B。在一些實施例中，金屬閘極線路切割製程的一部份可形成介電層於線路切割區(比如圖1的開口118，即金屬閘極層的部份被移除處)中。如圖所示，金屬閘極切割圖案210可覆蓋基板上的隔離區(如圖1的隔離區106)。然而在其他實施例中，金屬閘極切割圖案210可位於鰭狀物(如鰭狀物104)上，而金屬閘極切割圖案210下的鰭狀物104為虛置鰭狀物的全部或部份。
圖3A係鰭狀場效電晶體裝置100的部份剖視圖，其沿著與圖1及/或圖2之剖面Y-Y’所定義的平面實質上平行的平面。圖3B係鰭狀場效電晶體裝置 100的部份剖視圖，其沿著與圖1及/或圖2之剖面X-X’所定義的平面實質上平行的平面。鰭狀場效電晶體裝置100包含的金屬的閘極結構108已切割成金屬閘極結構部份108A與108B。金屬的閘極結構108之切割方法可依據圖5所示的一些實施例。鰭狀電晶體裝置100可包含一或多個圖1與2所示的上述結構，比如自基板102延伸的鰭狀物104、隔離區106、與鰭狀物104之上及周圍的閘極結構108。閘極結構108可與圖1及/或圖2所示的上述閘極結構108實質上類似。閘極結構108可為金屬閘極結構，比如具有閘極介電層與形成其上的金屬層的閘極堆疊。在一些實施例中，金屬層包含多種金屬材料，比如包含第一金屬材料(如p型功函數金屬)、第一金屬材料上的第二金屬材料(如n型功函數金屬)、以及第二金屬材料上的第三金屬材料(如充填金屬(鎢))等等。硬遮罩層302與304位於閘極結構108上。硬遮罩層302及/或304可與圖1所示的上述硬遮罩層114實質上類似。在一實施例中，硬遮罩層302包含氮化矽。在一實施例中，硬遮罩層304包含氮化鈦。然而可能採用其他合適組成。
圖3A亦顯示硬遮罩層304與302所定義的金屬閘極切割圖案210。在定義金屬閘極切割圖案210的開口下，可切割閘極結構108，並形成分開的閘極結構108之間的開口118。切割可為金屬閘極線路切割製程的一部份，如此處搭配圖5說明的內容。在多種例子中，後續的製程步驟可形成介電層於開口118的區域中，以插入金屬閘極結構部份108A與108B。介電層的組成可與隔離區106及/或相鄰的層間介電層之介電材料不同，如下所述。
值得注意的是，金屬閘極切割圖案210提供的開口118(又稱作溝槽)延伸至淺溝槽的隔離區106，或延伸至淺溝槽的隔離區106中。在一實施例中，開口118自金屬的閘極結構108其最上側的金屬層，延伸至開口118的最低點之距離為深度D1。深度D1可介於近似150nm至180nm之間。開口的深度D1大於金屬閘極的厚度T1，且金屬閘極包含閘極介電層110與其上的多個金屬層。如圖3所 示的實施例，開口118延伸至淺溝槽的隔離區106。開口118延伸至淺溝槽的隔離區106中的距離可為深度D2。深度D2可介於近似30nm至70nm之間。在一實施例中，深度D2至少為淺溝槽的隔離區106其厚度T2的近似45%。過蝕刻(比如45%的過蝕刻)可減少金屬的閘極結構108殘留於金屬閘極切割圖案210的開口118中的風險。
在一實施例中，金屬閘極切割圖案210定義的開口118之輪廓具有實質上線性的側壁308。實質上線性的側壁308實質上垂直於基板102的上表面。此處所述的用語「實質上」指的是金屬的閘極結構108的整個厚度T1中，其側壁與基板102的上表面之間的角度，與90度的偏差在10%以內。值得注意的是，本發明實施例所述的用語「實質上」或「約」對本技術領域中具有通常知識者來說，通常在製程控制的合理容忍度內(比如10%)。
在一實施例中，開口118的輪廓在開口頂部具有寬度W1，且在開口底部具有寬度W4。在另一實施例中，自金屬的閘極結構108之最上側金屬層的上表面量測寬度W1。在又一實施例中，自閘極結構108的部份下之隔離區106的上表面量測寬度W4。寬度W4可大於寬度W1。在一實施例中，寬度W4比寬度W1大至少10%。寬度W4可介於約15nm至25nm之間，而寬度W1可介於10nm至30nm之間。在又一實施例中，在寬度W1與寬度W4之量測值之間的開口118的寬度，可小於寬度W1。在一些實施例中，寬度W1及/或與閘極相鄰的開口118中所量測的寬度(即金屬閘極結構部份108A的側壁至金屬閘極結構部份108B的側壁之寬度)，可比寬度W2小約20%。
在一些實施例中，開口118的輪廓的特徵在於具有角度θ，如圖4所示。角度θ可小於近似45度。圖4所示的角度θ係開口118之側壁，與平行於閘極結構108之側壁的水平平面(垂直於鰭狀物104的方向)之間的角度。
圖3B自圖1的剖面X-X’顯示金屬閘極切割圖案210的開口118。上 述的層間介電層標示為層間介電層306。層間介電層306的形成方法可為化學氣相沉積或其他合適的沉積製程。在一些實施例中，可在沉積層間介電層306之後平坦化層間介電層306。層間介電層306的組成可包含但不限於氧化矽、氮化矽、氮氧化矽、含碳介電層、四乙氧基矽烷氧化物、或上述之組合，且可具有低介電常數、高介電常數、或具有氧化矽的介電常數。層間介電層306亦可為用於層間介電層的其他已知材料。值得注意的是，圖式中的層間介電層306為單層，但裝置亦可包含其他介電材料如額外的間隔物單元、蝕刻停止層、或類似物。值得注意的是，開口118延伸至淺溝槽的隔離區106之上表面。在一些實施例中，開口118延伸至淺溝槽的隔離區106中，如圖3A所示的上述內容。
圖4係例示性裝置(如圖1的鰭狀場效電晶體裝置100)之上視圖。圖式中的鰭狀物104、金屬的閘極結構108、與層間介電層306可與前述實質上類似。由上述金屬閘極切割圖案210所定義之開口118，在上視圖中包括寬度W3與寬度W2。開口的較大寬度W3與金屬的閘極結構108在同一條線上。換言之，開口118位於金屬閘極切割圖案210的部份處，即欲移除的金屬閘極結構之寬度，大於開口118位於金屬閘極切割圖案210的部份與金屬閘極結構相鄰但相隔處的寬度。換言之，介電區如層間介電層306(見圖3B)圍繞閘極結構108。上述尺寸來自於下述的金屬閘極切割製程的蝕刻製程。在一實施例中，開口118具有實質上弧形的側壁，其自較大的寬度部份(如寬度W3)延伸至較窄的寬度部份(如寬度W2)。如圖所示，圖4的寬度W3對應(比如等於)圖3A之剖面Y-Y’的寬度W1。
圖5係一些實施例中，形成半導體裝置的方法500之流程圖。在方法500之前、之中、或之後可進行額外步驟，且方法的額外實施例可置換、省略、或調換一些下述步驟。值得注意的是，方法500僅用以舉例說明，而非侷限本發明實施例至申請專利範圍未實際限縮的範疇。方法500將搭配圖6A、6B、7A、7B、8A、8B、8C、9A、9B、10A、10B、11A、11B、12A、12B、12C、13A、 13B、14A、14B、與14C說明如下。圖6A、7A、8A、9A、10A、11A、12A、13A、與14A係鰭狀場效電晶體結構600沿著實質上平行於圖1的剖面X-X’之平面的剖視圖，而圖6B、7B、8B、9B、10B、11B、12B、13B、與14B係鰭狀場效電晶體結構600沿著實質上平行於圖1的剖面Y-Y’之平面的剖視圖。
在多種實施例中，方法500一開始的步驟502提供基板，其包含鰭狀物與隔離區。在圖6A與6B的例子與步驟502的一實施例中，顯示鰭狀場效電晶體結構600。鰭狀場效電晶體結構600可為鰭狀場效電晶體結構(如鰭狀場效電晶體裝置100)的部份。鰭狀場效電晶體結構600可包含一或多個圖1所示的上述結構，比如自基板102延伸的鰭狀物104、隔離區106、鄰接金屬的閘極結構108之側壁間隔物116、與層間介電層306。
在一些實施例中，方法500經由置換置閘極製程提供金屬的閘極結構108，即形成虛置閘極(如多晶矽)於鰭狀物上，之後移除虛置閘極以形成溝槽，再形成金屬的閘極結構108於溝槽中。溝槽可由側壁間隔物116定義。
方法500接著進行步驟504，以形成金屬閘極結構於基板102上。金屬閘極結構可形成於移除虛置閘極所提供的溝槽中。金屬閘極結構可包含多個層狀物形成於溝槽中，且層狀物包括一或多個界面層、閘極介電層、功函數層、阻障層、黏著層、擴散阻障層、金屬充填層、及/或其他合適的層狀物。
如圖6A與6B所示，形成金屬的閘極結構108於基板102上與鰭狀物104的側壁上。金屬的閘極結構108具有閘極介電層110與其上方的金屬層。
在一些實施例中，金屬的閘極結構108的上方金屬層可包含一或多個功函數層。在一些實施例中，功函數金屬層包括p型功函數金屬。舉例來說，p型功函數金屬層可包含鎳、鈀、鈹、銥、碲、錸、釕、銠、鎢、鉬、氮化鎢、氮化釕、氮化鉬、氮化鈦、氮化鉭、碳化鎢、碳化鉭、碳化鈦、氮化鈦鋁、氮化鉭鋁、或上述之組合。在多種實施例中，p型功函數金屬層的形成方法可採用 物理氣相沉積、化學氣相沉積、電子束蒸鍍、及/或其他合適製程。金屬的閘極結構108可額外包含或改為包含n型功函數的金屬層，比如鎳、鈀、鉑、鈹、銥、碲、錸、釕、銠、鎢、鉬、氮化鎢、氮化釕、氮化鉬、氮化鈦、氮化鉭、碳化鎢、碳化鉭、碳化鈦、氮化鈦鋁、氮化鉭鋁、或上述之組合。在多種實施例中，n型功函數金屬層的形成方法可採用物理氣相沉積、化學氣相沉積、電子束蒸鍍、及/或其他合適製程。在一些實施例中，充填金屬層、阻障層、擴散阻障層、及/或其他合適的層狀物可包含金屬閘極結構的多個層狀物中。金屬的閘極結構108之例示性金屬層可包含其他金屬，比如鎳、鈀、鉑、鈹、銥、碲、錸、釕、銠、鎢、鉬、氮化鎢、氮化釕、氮化鉬、氮化鈦、氮化鉭、碳化鎢、碳化鉭、碳化鈦、氮化鈦鋁、氮化鉭鋁、或上述之組合。
金屬的閘極結構108亦包含閘極介電層110於金屬的閘極結構108之金屬層下。在一些例子中，金屬的閘極結構亦包含下方的界面層於金屬的閘極結構108之金屬層下。閘極介電層110可包含高介電常數的介電層如氧化鉿。金屬的閘極結構108的一或多層之任一者的形成方法，可採用原子層沉積、物理氣相沉積、化學氣相沉積(包含電漿增強化學氣相沉積)、及/或其他合適的沉積製程。值得注意的是，方法500在形成金屬閘極結構時，可包含一或多道的化學機械研磨製程。
方法500進行步驟506，以沉積硬遮罩層於基板上，並圖案化硬遮罩層以提供定義金屬閘極切割區的開口。硬遮罩層可為位於基板102與閘極結構108上的一或多層。在一些實施例中，硬遮罩層可包含圖案化的氮化矽層。在又一實施例中，硬遮罩層可包含圖案化的氮化矽層與下方的氮化鈦層。在其他或額外的一些實施例中，硬遮罩層可包含另一介電材料如氮氧化矽、碳化矽、或其他合適材料。
如圖7A與7B所示，沉積硬遮罩層堆疊702。硬遮罩層堆疊702包含 第一層702A與第二層702B。在一實施例中，第一層702A包含氮化矽，而第二層702B包含氮化鈦。在一些實施例中，硬遮罩層堆疊702的形成方法可為原子層沉積或其他合適的沉積方法。在一些實施例中，硬遮罩層堆疊702的厚度可介於近似25nm至100nm之間。
如圖8A與8B所示的例子，形成圖案化層於硬遮罩層堆疊702上。圖案化層的圖案可實質上轉移至硬遮罩層堆疊702。如圖8A與8B所示，形成三層光阻802的圖案化層於基板102上。三層光阻802可包含底層802A、中間層802B、與上側層802C。在一實施例中，上側層802C為光阻，且可採用合適的微影技術曝光顯影圖案於其中。如圖8A與8B所示，開口804形成於圖案化層中。可定義開口804以提供前述的金屬閘極切割圖案210。開口804可定義矩形的區域，其下將進行金屬閘極線路切割。值得注意的是，單一開口804可延伸於欲切割的多個金屬閘極上。此外值得注意的是，可同時形成多個開口804於基板102上。
如圖9A與9B所示，形成於三層光阻802中的圖案將轉移至硬遮罩層堆疊702，以形成開口902於硬遮罩層堆疊702中。開口902可露出將要自基板切割(或部份移除)的一或多個金屬的閘極結構108。開口902可對應切割金屬閘極圖案210，如上所述。開口902的形成方法可為合適的蝕刻製程(如開放硬遮罩製程)，其可包含電漿蝕刻。
在一些實施例中，在形成開口902於硬遮罩層堆疊702中之後，可進行再沉積製程，如圖10A與10B所示。再沉積製程可包含原子層沉積。在一些實施例中，再沉積製程包括沉積與第一層702A相同的材料。舉例來說，一些實施例的再沉積製程中沉積氮化矽，而第一層702A亦包含氮化矽。在一實施例中，可再沉積小於10nm(如5nm、4nm、或3nm)的層狀物於硬遮罩層堆疊702上，以形成再沉積層1002。再沉積製程之後，可進行開放硬遮罩製程，以自開口902的底部移除再沉積層1002，並保留再沉積層1002於開口902的側壁上，如圖11A與11B 所示。圖11A與11B提供的開口可與金屬閘極切割圖案210實質上類似。舉例來說，開口902的形狀可為實質上矩形，且開口902露出欲切割的一或多個閘極結構108之部份。
值得注意的是，形成開口於硬遮罩層堆疊702中的上述製程，可包括多種常見於製作半導體裝置的其他製程，比如光阻剝除及/或除渣、偵測、清潔、量測、及/或其他合適製程。在進行含有一或多個上述步驟的步驟506之後，位於閘極結構上的硬遮罩層具有開口以定義閘極切割區，其與前述的金屬閘極切割圖案210類似。在後續的閘極切割蝕刻製程中，接著採用硬遮罩層與相關開口作為遮罩單元，如下所述。
方法500接著進行步驟508，採用圖案化的硬遮罩作為遮罩單元，以進行金屬閘極線路切割製程。在一些實施例中，金屬閘極線路切割製程包含依序進行多個沉積與蝕刻步驟。值得注意的是，欲形成的開口深寬比可大於10。以圖3A為例，開口的深度D1可介於近似140nm至170nm之間，而開口的寬度W1可為深度D1的10%。由於開口具有高深寬比，沉積可搭配移除蝕刻以準確控制最終開口(如開口118)的輪廓。
在一實施例中，切割金屬閘極的製程包括第一製程系列，與之後的第二製程系列。在一些實施例中，進行多次第一製程系列之後，再進行多次第二製程系列。在一實施例中，進行第一製程系列六次之後，再進行第二製程系列。在一些實施例中，在進行第一製程系列(比如多次)之後，再進行多次第二製程系列。舉例來說，一實施例進行八次的第二製程系列。因此在一實施例中，進行六次的第一製程系列之後，進行八次的第二製程系列。
切割製程的第一製程系列：在一實施例中，可由乾蝕刻設備進行第一製程系列。在一實施例中，第一製程系列包括一或多個下述步驟：
Figure 107140217-A0305-02-0018-2
在一實施例中，上述沉積步驟可沉積矽為主的層狀物於開口的側壁上。例示性的層狀物可包含碳氧化矽或氧化矽。例示性的製程條件包括：
˙功率-500瓦至1500瓦
˙時間-3秒至8秒
˙製程溫度-80℃至120℃
˙壓力-5mTorr至15mTorr
˙流速-50sccm至100sccm
在一實施例中，蝕穿步驟可蝕刻穿過形成於開口上的任何氧化物。例示性的製程條件包括：
˙功率-50瓦至250瓦
˙時間-5秒至30秒
˙製程溫度-80℃至120℃
˙壓力-5mTorr至15mTorr
˙流速-10sccm至150sccm
金屬(功函數)蝕刻可包含蝕刻化學劑，其對將蝕刻的金屬閘極結構層具有選擇性，而對周圍介電層(如淺溝槽的隔離區106、層間介電層306、與側壁間隔物116)的蝕刻特性最小化。除了上述例子之外，金屬蝕刻製程可包含其 他含氯氣體(如氯氣、氯仿、及/或三氯化硼)、含溴氣體(如溴化氫及/或溴仿)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。例示性的製程條件包括：
˙功率-1000瓦至2000瓦
˙時間-20秒至50秒
˙製程溫度-80℃至120℃
˙壓力-5mTorr至15mTorr
˙流速-500sccm至1000sccm
關於上述的第一製程系列的最終步驟(受控的沉積步驟)，其可與其他步驟一起沉積聚合物以控制最終開口輪廓。舉例來說，甲烷搭配氧氣可控制碳-氫聚合物的沉積步驟，比如在此步驟中以氧氣灰化控制沉積量。在一些實施例中，受控的沉積可避免或減少碗狀輪廓。關於前述的第一製程系列，氧氣可氧化金屬，以利控制切割金屬閘極的關鍵尺寸。受控的沉積步驟可改為包含其他蝕刻化學劑，比如乙烯或二氧化硫。例示性的製程條件包括：
˙功率-300瓦至800瓦
˙時間-5秒至20秒
˙製程溫度-80℃至120℃
˙壓力-5mTorr至30mTorr
˙流速-100sccm至300sccm
切割製程的第二製程系列：在一實施例中，亦可採用乾蝕刻技術進行第二製程系列。可在進行第一製程系列的相同蝕刻器中，進行第二製程系列。在一實施例中，第二製程系列包括一或多個下述步驟：
Figure 107140217-A0305-02-0019-3
Figure 107140217-A0305-02-0020-4
在一實施例中，沉積步驟可與前述的第一製程系列實質上類似。
在一實施例中，蝕穿步驟可與前述的第一製程系列實質上類似。
金屬(功函數)蝕刻可包含高偏功率的電漿蝕刻。高偏功率包含超過1500瓦的功率與超過60V的偏壓。在一實施例中，金屬(功函數)蝕刻可包含高負載循環的電漿蝕刻。高負載循環包含的負載循環大於25%。在一些實施例中，負載循環頻率介於約50Hz至150Hz之間。
金屬(功函數)蝕刻可包含蝕刻化學劑，其對將蝕刻的金屬閘極結構的層狀物具有選擇性，且對周圍介電層(如淺溝槽的隔離區106、層間介電層306、與側壁間隔物116)的蝕刻特性最小化。金屬蝕刻製程可包含其他含氯氣體(如氯氣、氯仿、四氯化碳、及/或三氯化硼)、含溴氣體(如溴化氫及/或溴仿)、含碘氣體、其他合適氣體及/或電漿、及/或上述之組合。
˙時間-10%至50%
˙頻率-50Hz至150Hz
˙蝕刻化學劑-氦氣/氯氣/四氯化矽/三氯化硼
˙製程溫度-80℃至120℃
˙壓力-5mTorr至15mTorr
˙流速-500sccm至1000sccm
受控的沉積步驟(比如甲烷與氧氣)可實質上類似於前述的第一製程系列。
在一些實施例中，提供第一製程系列與第二製程系列的步驟，以用於金屬閘極切割區中的開口輪廓，如圖12A、12B、與12C所示。開口1202可與圖1、3A、3B、與4所示的上述開口118實質上類似。舉例來說，相同的輪廓(包括寬度W1、寬度W2、深度D1、深度D2、厚度T1、與厚度T2的尺寸)，亦可用於圖12A、12B、與12C的鰭狀場效電晶體結構600。在一實施例中，角度θ可與前述實質上類似。值得注意的是，圖12C所示的開口切割兩個閘極結構108。然而開口可延伸穿過任何數目的閘極結構108。
如上所述，本發明實施例之步驟508中的蝕刻步驟系列，其可使開口輪廓變寬(比如開口118的寬度W2，或開口1202)，以提供切割區所需的輪廓，使合適的蝕刻劑到達開口(如開口1202)的底部之速率增加。在一些實施例中，上述步驟可提供更完整的隔離於閘極結構的切割部份之間，以減少漏電流並有利於電晶體效能。
方法500進行步驟510，以持續製作鰭狀場效電晶體結構600。在一些實施例中，沉積介電層於切割區(如開口1202)中。在其他實施例中，可在沉積介電層之後進行化學機械研磨製程。可沉積介電層於硬遮罩層上，如前述的步驟506。在其他實施例中，可在沉積介電層之前先移除步驟506的硬遮罩層。
如圖13A與13B所示的一實施例，步驟510可沉積介電層1402。在一些實施例中，接著進行化學機械研磨製程以平坦化介電層1402的上表面(見圖14A、14B、與14C)。在一些實施例中，介電層1402可包含氧化矽、氮化矽、氮氧化物、及/或其他合適的介電材料層。因此多種實施例中的介電層1402亦可電性隔離相鄰的閘極堆疊之閘極金屬線路。介電層1402的組成可與層間介電層306及/或隔離區106的組成不同。值得注意的是，填入開口1202且插入閘極結構108 的介電層1402具有相同尺寸與輪廓，如上所述。
可繼續對鰭狀場效電晶體結構600進行後續製程如步驟512，以形成本技術領域已知的多種結構與區域。舉例來說，後續製程可形成多種接點/通孔/線路與多層內連線結構(如金屬層與層間介電層)於基板上，其設置為連接多種結構，以形成包含一或多個鰭狀場效電晶體裝置的功能電路。在進一步的例子中，多層內連線可包含垂直內連線如通孔或接點，與水平內連線如金屬線路。多種內連線結構可採用多種導電材料，其包含銅、鎢、及/或矽化物。在一例中，鑲嵌製程與雙鑲嵌製程用於形成銅相關的多層內連線結構。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
在例示性的實施例中，半導體裝置包括自基板延伸的第一鰭狀物與第二鰭狀物。第一閘極部份位於第一鰭狀物上，而第二閘極部份位於第二鰭狀物上。層間介電層與第一閘極部份及第二閘極部份相鄰。切割區(比如第一閘極結構與第二閘極結構之間的開口或間隙)延伸於第一閘極部份與第二閘極部份之間。切割區具有第一寬度的第一部份與第二寬度的第二部份，第二寬度大於第一寬度。第二部份夾設於第一閘極部份與第二閘極部份之間，且第一部份定義於層間介電層中。
在又一實施例中，切割區的側壁自第一部份延伸至第二部份，且側壁與平面之間具有角度θ，而平面垂直於第一鰭狀物的長度方向並垂直於基板的上表面。在另一實施例中，自區域的上視圖量測第一寬度與第二寬度。在一些實施例中，切割區填有介電材料。在一些實施例中，切割區延伸至第一鰭狀 物與第二鰭狀物之間的淺溝槽隔離結構中。在又一實施例中，切割區在淺溝槽隔離結構的上表面具有第三寬度，在第一閘極部份與第二閘極部份之間具有第二寬度，且第二寬度大於第三寬度。在平行於基板的上表面的平面上量測第三寬度與第二寬度。在一實施例中，第一閘極部份具有實質上線性的第一側壁，第二閘極部份具有實質上線性的第二側壁，且介電材料延伸於第一側壁與第二側壁之間。
另一實施例提供半導體裝置的製作方法。方法包括形成自半導體基板延伸的第一鰭狀物與第二鰭狀物，其中淺溝槽隔離延伸於第一鰭狀物與第二鰭狀物之間。形成閘極結構以延伸於第一鰭狀物與第二鰭狀物上。提供介電層以與閘極結構相鄰。蝕刻閘極結構與介電層以形成開口於閘極結構中，且開口至少延伸至淺溝槽隔離的上表面。蝕刻所形成的開口中，開口的第一部份具有第一寬度，且開口的第一部份由閘極結構的第一切割部份之第一側壁與閘極結構的第二切割部份之第二側壁所定義。開口的第二部份具有第二寬度，且開口的第二部份具有介電層所定義的邊緣，且第一寬度大於第二寬度。開口的第三部份在上視圖中位於第一部份與第二部份之間。將介電材料填入開口。
在一些實施例中，開口的第三部份包括側壁，其中側壁與平行於閘極結構之側壁的平面之間具有角度θ，且角度θ小於45度。在一些實施例中，蝕刻包括多個沉積步驟與多個蝕刻步驟的系列。在一些實施例中，沉積步驟的系列包括聚合物沉積步驟。在一些實施例中，沉積步驟的系列更包括沉積矽。
在又一實施例中，提供半導體裝置的製作方法，其包括切割金屬閘極結構成同一條線上的第一金屬閘極部份與第二金屬閘極部份。切割步驟包括：進行第一製程以沉積矽層以及進行第二製程以進行蝕穿。實施例亦包括對金屬閘極結構的功函數金屬層進行蝕刻。蝕刻包括高偏壓與高負載循環。可進行聚合物沉積步驟。重複第一製程、第二製程、蝕刻、與聚合物沉積步驟。
在另一實施例中，高偏壓包括大於約1500瓦的功率與大於約60伏特的偏壓。在一實施例中，高負載循環大於約25%。在一實施例中，切割步驟形成開口於金屬閘極結構與相鄰的介電層中。在一實施例中，金屬閘極結構中的開口寬度大於相鄰的介電層中的開口寬度，且在平行於包含金屬閘極結構的半導體基板之上表面之平面上量測開口寬度。在又一實施例中，切割步驟形成開口於該金屬閘極結構與下方的淺溝槽隔離結構中。在又一實施例中，金屬閘極結構中的開口其第一寬度小於淺溝槽隔離結構中的開口其第二寬度，在平行於金屬閘極結構的長度的平面上量測第一寬度與第二寬度，且第一寬度定義於第二寬度上的一表面上。在一實施例中，重複次數為7次。
D1、D2‧‧‧深度
T1、T2‧‧‧厚度
W1、W4‧‧‧寬度
Y-Y’‧‧‧剖面
100‧‧‧鰭狀場效電晶體裝置
104‧‧‧鰭狀物
106‧‧‧隔離區
108A、108B‧‧‧金屬閘極結構部份
110‧‧‧閘極介電層
118‧‧‧開口
210‧‧‧金屬閘極切割圖案
302、304‧‧‧硬遮罩層
308‧‧‧側壁

Claims (15)

  1. 一種半導體裝置，包括：自一基板延伸的一第一鰭狀物與一第二鰭狀物；一第一閘極部份位於該第一鰭狀物上，與一第二閘極部份位於該第二鰭狀物上；一層間介電層，與該第一閘極部份及該第二閘極部份相鄰；以及一切割區，延伸於該第一閘極部份與該第二閘極部份之間，其中該切割區具有一第一寬度的一第一部份與一第二寬度的一第二部份，該第二寬度大於該第一寬度，其中該第二部份夾設於該第一閘極部份與該第二閘極部份之間，且該第一部份定義於該層間介電層中。
  2. 如申請專利範圍第1項所述之半導體裝置，其中切割區的一側壁自該第一部份延伸至該第二部份，且該側壁與一平面之間具有一角度θ，而該平面垂直於該第一鰭狀物的長度方向並垂直於該基板的上表面。
  3. 如申請專利範圍第1或2項所述之半導體裝置，其中切割區延伸至該第一鰭狀物與該第二鰭狀物之間的一淺溝槽隔離結構中。
  4. 如申請專利範圍第3項所述之半導體裝置，其中該切割區在該淺溝槽隔離結構的上表面具有一第三寬度，在該第一閘極部份與該第二閘極部份之間具有該第二寬度，且該第二寬度大於該第三寬度，其中在平行於該基板的上表面的平面上量測該第三寬度與該第二寬度。
  5. 如申請專利範圍第1或2項所述之半導體裝置，其中該第一閘極部份具有實質上線性的一第一側壁，該第二閘極部份具有實質上線性的一第二側壁，且一介電材料延伸於該第一側壁與該第二側壁之間。
  6. 一種半導體裝置的製作方法，包括：形成自一半導體基板延伸的一第一鰭狀物與一第二鰭狀物，其中一淺溝槽 隔離延伸於該第一鰭狀物與該第二鰭狀物之間；形成一閘極結構以延伸於該第一鰭狀物與該第二鰭狀物上；提供一介電層以與該閘極結構相鄰；蝕刻該閘極結構與該介電層以形成一開口於該閘極結構中，且該開口至少延伸至該淺溝槽隔離的上表面，其中蝕刻形成的該開口具有：該開口的一第一部份具有一第一寬度，且該開口的該第一部份由該閘極結構的一第一切割部份之第一側壁與該閘極結構的一第二切割部份之第二側壁所定義；該開口的一第二部份具有一第二寬度，且該開口的該第二部份具有該介電層所定義的邊緣，且該第一寬度大於該第二寬度；該開口的一第三部份在一上視圖中位於該第一部份與該第二部份之間；以及將一介電材料填入該開口。
  7. 如申請專利範圍第6項所述之半導體裝置的製作方法，其中該開口的該第三部份包括一側壁，其中該側壁與平行於該閘極結構之側壁的平面之間具有角度θ，且角度θ小於45度。
  8. 如申請專利範圍第6或7項所述之半導體裝置的製作方法，其中蝕刻包括多個沉積步驟與多個蝕刻步驟的系列。
  9. 如申請專利範圍第8項所述之半導體裝置的製作方法，其中該些沉積步驟的系列包括聚合物沉積步驟。
  10. 如申請專利範圍第9項所述之半導體裝置的製作方法，其中該些沉積步驟的系列更包括沉積矽。
  11. 一種半導體裝置的製作方法，包括：切割一金屬閘極結構成同一條線上的一第一金屬閘極部份與一第二金屬閘 極部份，且切割步驟包括：進行一第一製程以沉積一矽層；進行一第二製程以進行一蝕穿；對該金屬閘極結構的一功函數金屬層進行一蝕刻，其中該蝕刻包括一高偏壓與一高負載循環；進行一聚合物沉積步驟；以及重複該第一製程、該第二製程、該蝕刻、與該聚合物沉積步驟。
  12. 如申請專利範圍第11項所述之半導體裝置的製作方法，其中切割步驟形成一開口於該金屬閘極結構與相鄰的一介電層中。
  13. 如申請專利範圍第12項所述之半導體裝置的製作方法，其中該金屬閘極結構中的該開口的一寬度大於相鄰的該介電層中的該開口的一寬度，且在平行於包含該金屬閘極結構的一半導體基板之上表面之平面上量測該開口的該寬度。
  14. 如申請專利範圍第11項所述之半導體裝置的製作方法，其中切割步驟形成一開口於該金屬閘極結構與下方的一淺溝槽隔離結構中。
  15. 如申請專利範圍第14項所述之半導體裝置的製作方法，其中該金屬閘極結構中的該開口其第一寬度小於該淺溝槽隔離結構中的該開口其第二寬度，在平行於該金屬閘極結構的長度的一平面上量測第一寬度與第二寬度，且第一寬度定義於第二寬度上的一平面上。
TW107140217A 2017-11-15 2018-11-13 半導體裝置與其製作方法 TWI704688B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762586658P 2017-11-15 2017-11-15
US62/586,658 2017-11-15
US15/998,687 2018-08-15
US15/998,687 US10468527B2 (en) 2017-11-15 2018-08-15 Metal gate structure and methods of fabricating thereof

Publications (2)

Publication Number Publication Date
TW201933608A TW201933608A (zh) 2019-08-16
TWI704688B true TWI704688B (zh) 2020-09-11

Family

ID=66433573

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107140217A TWI704688B (zh) 2017-11-15 2018-11-13 半導體裝置與其製作方法

Country Status (3)

Country Link
US (3) US10468527B2 (zh)
KR (1) KR102138350B1 (zh)
TW (1) TWI704688B (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601567B1 (en) * 2015-10-30 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple Fin FET structures having an insulating separation plug
KR102378471B1 (ko) * 2017-09-18 2022-03-25 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법
US10672613B2 (en) 2017-11-22 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming semiconductor structure and semiconductor device
US11031290B2 (en) * 2017-11-30 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with cutting depth control and method for fabricating the same
KR102636464B1 (ko) * 2018-06-12 2024-02-14 삼성전자주식회사 게이트 분리층을 갖는 반도체 소자 및 그 제조 방법
KR102595606B1 (ko) * 2018-11-02 2023-10-31 삼성전자주식회사 반도체 장치
US11756832B2 (en) * 2019-09-30 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structures in semiconductor devices
DE102020100099A1 (de) 2019-09-30 2021-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gatestrukturen in halbleitervorrichtungen
US12002715B2 (en) 2019-10-29 2024-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
EP3836226A1 (en) * 2019-12-10 2021-06-16 Imec VZW A method for processing a finfet device
DE102020114860A1 (de) 2020-01-31 2021-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor-gates und verfahren zum bilden davon
US11437287B2 (en) 2020-01-31 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor gates and methods of forming thereof
US11177180B2 (en) * 2020-02-11 2021-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Profile control of a gap fill structure
DE102020126070A1 (de) * 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Kontaktbildungsverfahren und entsprechende struktur
US20210335674A1 (en) * 2020-04-28 2021-10-28 Taiwan Semicondutor Manufacturing Company Limited Semiconductor devices and methods of manufacturing thereof
DE102021103461A1 (de) * 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-isolation für multigate-vorrichtung
US11616062B2 (en) 2020-04-30 2023-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Gate isolation for multigate device
US20210351300A1 (en) * 2020-05-07 2021-11-11 Intel Corporation Self-aligned gate endcap (sage) architectures with vertical sidewalls
US11495464B2 (en) 2020-07-08 2022-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US20220037498A1 (en) * 2020-07-31 2022-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor Gate Structures and Methods of Forming the Same
US20220238370A1 (en) * 2021-01-27 2022-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device with Gate Cut Structure and Method of Forming the Same
US11532628B2 (en) * 2021-02-26 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
KR20220143382A (ko) * 2021-04-16 2022-10-25 삼성전자주식회사 비스듬한 절단면을 갖는 게이트 전극을 포함하는 집적회로 칩 및 이의 제조 방법
KR20230036204A (ko) * 2021-09-07 2023-03-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200527600A (en) * 2004-01-22 2005-08-16 Ibm Vertical Fin-FET MOS devices
US20160079353A1 (en) * 2014-09-11 2016-03-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacuting method of the same
TW201616581A (zh) * 2014-10-17 2016-05-01 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
TW201701475A (zh) * 2015-06-23 2017-01-01 聯華電子股份有限公司 半導體結構及製程
TW201730919A (zh) * 2015-11-30 2017-09-01 台灣積體電路製造股份有限公司 半導體裝置及其製造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100230981B1 (ko) * 1996-05-08 1999-11-15 김광호 반도체장치 제조공정의 플라즈마 식각 방법
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9041125B2 (en) * 2013-03-11 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fin shape for fin field-effect transistors and method of forming
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9608086B2 (en) * 2014-05-20 2017-03-28 Global Foundries Inc. Metal gate structure and method of formation
US9331074B1 (en) * 2015-01-30 2016-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9748394B2 (en) * 2015-05-20 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having a multi-portioned gate stack
US10177240B2 (en) 2015-09-18 2019-01-08 International Business Machines Corporation FinFET device formed by a replacement metal-gate method including a gate cut-last step
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10079289B2 (en) * 2016-12-22 2018-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate structure and methods thereof
US9917103B1 (en) * 2017-01-04 2018-03-13 Globalfoundries Inc. Diffusion break forming after source/drain forming and related IC structure
US10163640B1 (en) * 2017-10-31 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Gate isolation plugs structure and method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200527600A (en) * 2004-01-22 2005-08-16 Ibm Vertical Fin-FET MOS devices
US20160079353A1 (en) * 2014-09-11 2016-03-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacuting method of the same
TW201616581A (zh) * 2014-10-17 2016-05-01 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
TW201701475A (zh) * 2015-06-23 2017-01-01 聯華電子股份有限公司 半導體結構及製程
TW201730919A (zh) * 2015-11-30 2017-09-01 台灣積體電路製造股份有限公司 半導體裝置及其製造方法

Also Published As

Publication number Publication date
US10468527B2 (en) 2019-11-05
KR102138350B1 (ko) 2020-08-14
US20210111280A1 (en) 2021-04-15
US10872978B2 (en) 2020-12-22
US11637206B2 (en) 2023-04-25
US20200066900A1 (en) 2020-02-27
KR20190055774A (ko) 2019-05-23
US20190148539A1 (en) 2019-05-16
TW201933608A (zh) 2019-08-16

Similar Documents

Publication Publication Date Title
TWI704688B (zh) 半導體裝置與其製作方法
KR102261369B1 (ko) 메탈 게이트 구조물 절단 프로세스
TWI668758B (zh) 半導體裝置及其製造方法
TWI556295B (zh) 金屬閘極及半導體結構之製造方法
TW201916254A (zh) 半導體結構
CN109786463B (zh) 金属栅极结构及其制造方法
US20180082951A1 (en) Contact having self-aligned air gap spacers
TW201946121A (zh) 半導體裝置的形成方法
TW201839983A (zh) 半導體裝置及其製造方法
TW202017104A (zh) 半導體裝置的形成方法
TW202013522A (zh) 多閘極半導體裝置的製作方法
TW202105735A (zh) 半導體裝置
CN112563192A (zh) 半导体结构的形成方法
TW201820479A (zh) 半導體元件的製造方法
US20210098364A1 (en) Contact Features and Methods of Fabricating the Same in Semiconductor Devices
CN110875252B (zh) 半导体器件和制造半导体器件的方法
TW202243260A (zh) 半導體結構
TW202230740A (zh) 半導體裝置
TWI579899B (zh) 半導體裝置之製造方法
CN111162045A (zh) 一种用于在半导体翅片的阵列上产生栅极切割结构的方法
CN109494149B (zh) 半导体结构的制作方法
US11387331B2 (en) Source/drain contact structure
US20230137766A1 (en) Semiconductor Structures Having A Continuous Active Region
US20240030299A1 (en) Semiconductor device and manufacturing method thereof
TW202407814A (zh) 半導體裝置及其製造方法