TWI697958B - 用於蝕刻遮罩與鰭片結構形成之方法 - Google Patents

用於蝕刻遮罩與鰭片結構形成之方法 Download PDF

Info

Publication number
TWI697958B
TWI697958B TW108104714A TW108104714A TWI697958B TW I697958 B TWI697958 B TW I697958B TW 108104714 A TW108104714 A TW 108104714A TW 108104714 A TW108104714 A TW 108104714A TW I697958 B TWI697958 B TW I697958B
Authority
TW
Taiwan
Prior art keywords
substrate
mandrel structure
hard mask
mandrel
distance
Prior art date
Application number
TW108104714A
Other languages
English (en)
Other versions
TW201935564A (zh
Inventor
永振 林
周清軍
郢 張
Original Assignee
美商應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商應用材料股份有限公司 filed Critical 美商應用材料股份有限公司
Publication of TW201935564A publication Critical patent/TW201935564A/zh
Application granted granted Critical
Publication of TWI697958B publication Critical patent/TWI697958B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241—III-V semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

本文所述的實施例涉及基板處理方法。該方法包括在基板上形成經圖案化的硬遮罩材料，在基板的暴露區域上形成第一心軸結構，以及在基板上在硬遮罩材料和第一心軸結構上方沉積間隙填充材料。移除第一心軸結構以形成包含硬遮罩材料和間隙填充材料的第二心軸結構，並且使用第二心軸結構作為遮罩來蝕刻基板以形成鰭片結構。

Description

用於蝕刻遮罩與鰭片結構形成之方法
本案的實施例大體而言係關於用於蝕刻遮罩和鰭片結構形成的方法。
鰭式場效應電晶體(FinFET)是半導體裝置製造中常用的結構。當前技術節點處的常規FinFET係採用傳統蝕刻技術製造的。然而，在具有減小的臨界尺寸和不斷增加的縱橫比的先進技術節點處，傳統的蝕刻技術不足以製造無缺陷的FinFET元件。
例如，為了製造具有足夠垂直度的FinFET元件以用於各種半導體裝置，利用厚間隔件來圖案化下面的硬遮罩。利用厚間隔件高度來減少經圖案化的間隔件的彎曲或傾斜。然而，當間隔件圖案轉印到硬遮罩時，硬遮罩的不太理想的垂直度可能持續存在，這會導致FinFET元件在相鄰的FinFET結構之間具有傾斜的側壁或封閉的溝槽。
因此，在本領域中所需要的是用於遮罩和鰭片結構製造和蝕刻的改良的方法。
在一個實施例中，提供一種基板處理方法。該方法包括在基板上形成經圖案化的硬遮罩材料，在基板的暴露於經圖案化的硬遮罩材料之間的區域上形成第一心軸結構，以及在基板上在硬遮罩材料和第一心軸結構上方沉積間隙填充材料。該方法還包括移除第一心軸結構以形成第二心軸結構，該第二心軸結構包含硬遮罩材料和間隙填充材料，以及使用該第二心軸結構作為遮罩來蝕刻基板以形成鰭片結構。
在另一個實施例中，提供一種基板處理方法。該方法包括在基板上形成硬遮罩材料，在該硬遮罩材料上沉積間隔件材料，圖案化該間隔件材料，以及藉由蝕刻硬遮罩材料而將間隔件材料的圖案轉印到該硬遮罩材料以暴露基板的區域。在基板的暴露區域上形成第一心軸結構。在基板上在硬遮罩材料和第一心軸結構上方沉積間隙填充材料。移除第一心軸結構以形成第二心軸結構，第二心軸結構包含硬遮罩材料和間隙填充材料。使用該第二心軸結構作為遮罩來蝕刻基板以形成鰭片結構。
在另一個實施例中，提供一種基板處理方法。該方法包括在基板上形成經圖案化的硬遮罩材料，以及在基板的暴露區域上形成III-V族材料的第一心軸結構。III-V族材料的第一心軸結構在基板的頂表面上方延伸第一距離，該第一距離大於約80 nm。在基板上在硬遮罩材料和III-V族材料的第一心軸結構上方沉積可流動的氧化物間隙填充材料。移除III-V族材料的第一心軸結構以形成第二心軸結構，第二心軸結構包含硬遮罩材料和可流動的氧化物間隙填充材料。第二心軸結構在基板的頂表面上方延伸第二距離，該第二距離大致等於第一距離。使用第二心軸結構作為遮罩來蝕刻基板以形成含矽鰭片結構，以及隨後移除第二心軸結構。
本文所述的實施例涉及特別適用於形成鰭片結構的基板處理方法。該方法包括在基板上形成經圖案化的硬遮罩材料，在基板的暴露區域上形成第一心軸結構，以及在基板上在硬遮罩材料和第一心軸結構上方沉積間隙填充材料。移除第一心軸結構以形成第二心軸結構，第二心軸結構包含硬遮罩材料和間隙填充材料，並且使用第二心軸結構作為遮罩來蝕刻基板以形成鰭片結構。利用本文所述的實施例使得能夠有效地製造具有改良的厚度和垂直度輪廓的蝕刻遮罩，該蝕刻遮罩用於隨後形成先進節點鰭片結構。
第7圖圖示根據本文描述的實施例用於圖案化和蝕刻基板的方法700的操作。方法700與第1圖至第6圖中描繪的圖示同時討論。在操作710處，對間隔件材料進行圖案化並將圖案轉印到下面的硬遮罩材料。
第1圖圖示根據本文描述的實施例的基板102的局部橫截面圖，該基板具有在其上形成的硬遮罩材料104和經圖案化的間隔件材料106。在一實施例中，基板102由半導體材料製成，該半導體材料諸如矽。例如，基板102是單晶矽材料，該單晶矽材料是本徵（未摻雜）矽材料或非本徵（摻雜）矽材料。若利用非本徵矽材料，則摻雜劑可以是p型摻雜劑，諸如硼。在另一實施例中，基板102是絕緣體上矽基板。
第1圖圖示在操作710處進行圖案化之後的間隔件材料106和硬遮罩材料104。在圖案化之前，使硬遮罩材料104以毯覆型層沉積在基板102上並與基板102接觸。然後將間隔件材料106沉積在硬遮罩材料104上並與該硬遮罩材料104接觸。經由適用於先進技術節點的各種製程來執行間隔件材料106的圖案化，該先進技術節點為諸如10 nm節點、7 nm節點、5 nm節點以及更先進節點。合適的圖案化製程的實例包括自對準雙重圖案化和自對準四重圖案化，該自對準雙重圖案化和自對準四重圖案化取決於所希望的具體實現而為浸沒式光刻製程或極紫外(EUV)光刻製程。其他合適的圖案化製程包括定向自組裝、193 nm浸沒式光刻-蝕刻-光刻-蝕刻(LELE)、以及EUV LELE等。
經圖案化的間隔件材料106創建遮罩以用於後續蝕刻下面的硬遮罩材料104。在一實施例中，間隔件材料106是氧化矽材料、氮化矽材料、或氧化鈦材料。在一實施例中，經圖案化的間隔件材料106的厚度約等於鰭片間距的一半。例如，經圖案化的間隔件材料的厚度在約15 nm與約20 nm之間。在一實施例中，硬遮罩材料104的厚度在約30 nm與約50 nm之間，諸如約40 nm。硬遮罩材料104在一實施例中由氧化矽材料製成，而在另一實施例中由氮化矽材料製成。
利用蝕刻製程(諸如濕式蝕刻製程或乾式蝕刻製程)來蝕刻硬遮罩材料104，從而將圖案從間隔件材料106轉印到硬遮罩材料。在一實施例中，利用基於氟的蝕刻劑來蝕刻間隔件材料106及/或硬遮罩材料104中的一者或兩者。例如，用電容耦合的含氟電漿蝕刻硬遮罩材料104。在另一實例中，用電感耦合的含氟電漿蝕刻硬遮罩材料104。合適的電漿前驅物的實例包括碳氟化合物或氫氟烴材料，諸如C4 F6 、C4 F8 、CF4 、CH2 F2 和CH3 F。用於產生電漿的源功率在約300 W與約1500 W之間，用於偏置電漿的偏置功率在約50 W與約700 W之間，用於執行蝕刻製程的製程環境的壓力保持在約5 mTorr與約20 mTorr之間，並且在蝕刻製程期間基板102的溫度保持在約10℃與約80℃之間。在蝕刻硬遮罩材料104之後，基板102的區域114暴露在硬遮罩材料104的相鄰部分之間。
經圖案化的硬遮罩106的間距108小於約40 nm，諸如約30 nm或更小。在該實施例中，經圖案化的硬遮罩材料部分的寬度110為約20 nm或更小，諸如約15 nm或更小。類似地，暴露區域114的寬度112為約20 nm或更小，諸如約15 nm或更小。
第2圖圖示根據本文描述的實施例的第1圖的基板的局部橫截面圖，其中在該基板102上移除了間隔件材料106並且形成了第一心軸結構202。在操作720處，在由硬遮罩材料104圖案化的基板上形成第一心軸結構202，如第2圖所示。經由合適的選擇性蝕刻製程來移除間隔件材料106，該合適的選擇性蝕刻製程諸如濕式蝕刻製程或乾式蝕刻製程。
在間隔件材料106是氧化矽材料的實施例中，從以下前驅物中的一或更多種前驅物產生電漿：C4 F6 、O2 、Ar、以及He。在此實施例中，用於產生電漿的源功率在約300 W與約900 W之間，用於偏置電漿的偏置功率在約300 W與約700 W之間，並且用於執行蝕刻製程的製程環境的壓力保持在約5 mTorr與約15 mTorr之間。在間隔件材料106是氮化矽材料的實施例中，從以下前驅物中的一或更多種前驅物產生電漿：CH3 F、CH4 、O2 、H2 、N2 、以及He。在此實施例中，用於產生電漿的源功率在約400 W與約800 W之間，並且用於偏置電漿的偏置功率在約30 W與約100 W之間。在間隔件材料106是氧化矽材料的其他實施例中，利用稀釋HF濕式蝕刻製程。
在一個實施例中，用於執行蝕刻製程的合適設備是可購自加州聖大克勞拉市的應用材料公司(Applied Materials, Inc., Santa Clara, CA)的CENTRISTM SYM3TM 蝕刻設備。可以預期，也可以根據本文描述的實施例利用來自其他製造商的其他適當配置的設備。間隔件移除製程相對於硬遮罩材料104和基板102選擇性地移除間隔件材料106，從而在基板102上留下硬遮罩材料104。
在第1圖所示的暴露區域114中形成第一心軸結構202。將第一心軸結構202沉積在基板102的表面206上，並且使第一心軸結構202從基板102的表面206生長。在一個實施例中，用於執行該第一心軸結構沉積的合適設備是可購自加州聖大克勞拉市的應用材料公司的CENTURA® RP EPI設備。預期來自其他製造商的其他適當配置的設備也可以根據本文描述的實施例利用。經由經圖案化的硬遮罩材料104和孔隙210使每個第一心軸結構202與相鄰的第一心軸結構202分開。使第一心軸結構202生長，以使得第一心軸結構202的頂表面208是在基板102的表面206上方大於約80 nm的距離204。在一個實施例中，距離204在約100 nm與約200 nm之間。
在一個實施例中，使用磊晶沉積製程在基板102上形成第一心軸結構202。在一實施例中，將含鎵前驅物和含砷前驅物以交替方式脈衝以沉積第一心軸結構202。在此實施例中，含鎵前驅物是三甲基鎵，並且含砷前驅物是AsH3 。在此實施例中，在保持於在約1 torr與約10 Torr之間的壓力和在約450℃與約800℃之間的溫度下的環境中製造第一心軸結構202。磊晶沉積製程利用逐層沉積技術，據信該逐層沉積技術當第一心軸結構202從表面206並且在硬遮罩材料104上方繼續生長時，使第一心軸結構202保持基本上垂直的取向。
在一個實施例中，第一心軸結構202是由III-V族材料形成的。例如，第一心軸結構202由以下物質中的一或更多種物質形成：銻化鋁、砷化鋁、砷化鋁鎵、磷化鋁鎵銦、氮化鋁鎵、磷化鋁鎵、砷化鋁銦、氮化鋁、磷化鋁、砷化硼、氮化硼、磷化硼、銻化鎵、砷化鎵、磷砷化鎵、磷化鎵、銻化銦、砷化銦、砷化銦鎵，氮化銦鎵、磷化銦鎵、氮化銦、以及磷化銦等。
在操作730處，在基板102上在硬遮罩材料104和第一心軸結構202上方沉積間隙填充材料302。第3圖圖示根據本文描述的實施例的第2圖的基板102的局部橫截面圖，其中在基板102上在硬遮罩材料104和第一心軸結構202上方形成了間隙填充材料302。沉積間隙填充材料302，以使得該間隙填充材料填充孔隙210並且沉積到厚度超過第一心軸結構202的頂表面208。在一個實施例中，用於執行間隙填充沉積製程的合適的設備是可購自加州聖大克勞拉市的應用材料公司的PRODUCER® ETERNATM FCVDTM 設備。可以預期，也可以根據本文描述的實施例利用來自其他製造商的適當配置的設備。
在一實施例中，間隙填充材料是可流動的材料。可流動的材料具有固體材料的特性，但也具有「流動」的能力，因此使得能夠實現基本上無孔隙的自底向上的材料沉積。在一實施例中，經由可流動的化學氣相沉積(CVD)製程來沉積間隙填充材料302。在一個實例中，利用CVD製程來沉積含有氧化矽的可流動的間隙填充材料302。在此實施例中，順序地使氧化矽材料沉積、固化和退火。在另一實例中，利用CVD製程來沉積氮化矽間隙填充材料302。在此實施例中，順序地使氮化矽材料沉積和經受氮化電漿處理。在另一個實施例中，經由旋塗玻璃(spin on glass, SOG)製程來形成間隙填充材料302。在此實施例中，間隙填充材料302是含氧化物的材料，諸如二氧化矽等。
在操作740處，平坦化間隙填充材料。第4圖圖示根據本文描述的一個實施例的第3圖的基板102在平坦化間隙填充材料302之後的局部橫截面圖。在一個實施例中，經由氧化物或氮化物化學機械拋光製程來執行間隙填充材料302的平坦化。在另一實施例中，經由氧化物或氮化物乾式蝕刻製程或濕式蝕刻製程來執行間隙填充材料302的平坦化。
移除間隙填充材料302至某一點處，在該點處，間隙填充材料302的頂表面402與第一心軸結構202的頂表面208基本上相平。在一個實施例中，預期第一心軸結構202用作移除點。在另一實施例中，使間隙填充材料302經受基於時間的製程以平坦化表面402、208。
在操作750處，移除第一心軸結構202以形成第二心軸結構500，該第二心軸結構500包含硬遮罩材料104和間隙填充材料302。第5圖圖示根據本文描述的實施例的第4圖的基板102的局部橫截面圖，其中第一心軸結構202經移除以形成第二心軸結構500。利用選擇性蝕刻製程來移除第一心軸結構202。例如，利用對III-V族材料具有選擇性的蝕刻化學物質來相對於含氧化物及/或氮化物的間隙填充材料302和硬遮罩材料104優先地移除第一心軸結構202。
在一實施例中，將含氯前驅物(諸如HCl)與含氫前驅物(諸如H2 )一起輸送到製程環境。將該前驅物用惰性載氣(諸如N2 或Ar)輸送到製程環境。在一實例中，以在約1 sccm與約500 sccm之間的流率將HCl輸送到製程環境。使製程環境的溫度保持在約300℃與約700℃之間，並且使製程環境的壓力保持在約0 Torr與約100 Torr之間。
第一心軸結構202的移除導致在相鄰的第二心軸結構500之間形成間隔502。間隔502還使基板102的頂表面206暴露，該頂表面206在後續製程中被蝕刻。第二心軸結構500的高度類似於距離204。據信，藉由利用足夠厚的心軸結構作為遮罩，後續的蝕刻製程表現出改良的垂直度。
在操作760處，使用第二心軸結構500作為遮罩來蝕刻基板102以形成鰭片結構602。第6圖圖示根據本文描述的實施例的第5圖的基板102在蝕刻基板102之後的局部橫截面圖。蝕刻製程對矽材料具有選擇性，並且相對於硬遮罩材料104和間隙填充材料302的氧化物和氮化物材料優先蝕刻基板102。
在一個實施例中，將含鹵素的前驅物(諸如HBr或Cl2 啟動成電漿，並用惰性載氣(諸如Ar)輸送到製程環境。在某些實施例中，還將含氧及/或氮的前驅物(諸如O2 或N2 )輸送到製程環境。在此實施例中，經由電感耦合電漿製程啟動前驅物，其中源功率在約500 W與約2000 W之間，並且偏置功率在約50 W與約500 W之間。在電漿形成和蝕刻基板102期間，製程環境的壓力在約5 mTorr與約15 mTorr之間。
在一實施例中，蝕刻基板102利用各向異性蝕刻製程以獲得鰭片結構602的基本上垂直的側壁。蝕刻製程還在相鄰的鰭片結構602之間形成溝槽604。在將基板102蝕刻到所希望的深度之後，所得鰭片結構602的高度606大於約80 nm，諸如在約100 nm與約200 nm之間。在鰭片結構形成之後，可以移除第二心軸結構500，並且可以在基板102上執行後續的半導體製造操作。
概括地說，改進的遮罩形成和蝕刻製程流程使得能夠進行先進半導體裝置的製造。藉由減小間隔件材料的高度並藉由增加遮罩的高度（即第一心軸結構和第二心軸結構），實現了蝕刻垂直度的改良。還據信，利用本文所述的製程流程，改良了遮罩（第一心軸結構和第二心軸結構)的側壁垂直度，這導致了所希望的蝕刻垂直度特性。因此，更有效地控制了側壁（橫向生長）並且還減小了邊緣粗糙度。
雖然前述內容涉及本案的實施例，但是可以在不脫離本案的基本範圍的情況下設計本案的其他和進一步的實施例，並且本案的範圍由所附申請專利範圍來確定。
102‧‧‧基板104‧‧‧硬遮罩材料106‧‧‧經圖案化的硬遮罩106‧‧‧間隔件材料108‧‧‧間距110‧‧‧寬度112‧‧‧寬度114‧‧‧區域202‧‧‧第一心軸結構204‧‧‧距離206‧‧‧表面208‧‧‧表面210‧‧‧孔隙302‧‧‧間隙填充材料402‧‧‧表面500‧‧‧第二心軸結構502‧‧‧間隔602‧‧‧鰭片結構604‧‧‧形成溝槽606‧‧‧高度700‧‧‧方法710‧‧‧操作720‧‧‧操作730‧‧‧操作740‧‧‧操作750‧‧‧操作760‧‧‧操作
因此，以可以詳細地理解本案的上述特徵的方式，可以經由參考實施例提供對上述簡要概述的本案的更特定描述，該實施例中的一些實施例示出在附圖中。然而，應注意，附圖僅圖示了示例性實施例，因此不應視為限制本發明的範圍，因為本發明可允許其他同等有效的實施例。
第1圖圖示根據本文描述的實施例的基板的局部橫截面圖，該基板具有在其上形成的硬遮罩材料和經圖案化的間隔件材料。
第2圖圖示根據本文描述的實施例的第1圖的基板的局部橫截面圖，其中在該基板上移除了間隔件材料並且形成了第一心軸結構。
第3圖圖示根據本文描述的實施例的第2圖的基板的局部橫截面圖，其中在基板上在硬遮罩材料和第一心軸結構上方形成了間隙填充材料。
第4圖圖示根據本文描述的實施例的第3圖的基板在平坦化間隙填充材料之後的局部橫截面圖。
第5圖圖示根據本文描述的實施例的第4圖的基板的局部橫截面圖，其中第一心軸結構經移除以形成第二心軸結構。
第6圖圖示根據本文描述的實施例的第5圖的基板在蝕刻基板之後的局部橫截面圖。
第7圖圖示根據本文描述的實施例的用於圖案化和蝕刻基板的方法的操作。
為了便於理解，已經盡可能使用相同的元件符號來指示諸圖中共有的相同元件。可以設想，一個實施例的要素和特徵可以有利地併入其他實施例，而無需進一步說明。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
700‧‧‧方法
710‧‧‧操作
720‧‧‧操作
730‧‧‧操作
740‧‧‧操作
750‧‧‧操作
760‧‧‧操作

Claims (20)

  1. 一種鰭片結構處理方法，包含： 在一基板上形成一經圖案化的硬遮罩材料； 在該基板的暴露在該經圖案化的硬遮罩材料之間的區域上形成第一心軸結構； 在該基板上在該硬遮罩材料和該第一心軸結構上方沉積一間隙填充材料； 移除該第一心軸結構以形成第二心軸結構，該第二心軸結構包含該硬遮罩材料和該間隙填充材料；以及 使用該第二心軸結構作為一遮罩來蝕刻該基板以形成溝槽從而形成鰭片結構，其中鰭片結構在相鄰溝槽之間形成。
  2. 如請求項1所述之方法，進一步包含： 在該硬遮罩材料上沉積一間隔件材料並圖案化該間隔件材料。
  3. 如請求項2所述之方法，其中將該間隔件材料的圖案轉印到該硬遮罩材料以形成該經圖案化的硬遮罩材料。
  4. 如請求項2所述之方法，其中經由一自對準雙重圖案化製程、一自對準四重圖案化製程或一定向自組裝製程來執行該圖案化該間隔件材料。
  5. 如請求項1所述之方法，進一步包含： 在移除該第一心軸結構之步驟之前平坦化該間隙填充材料。
  6. 如請求項5所述之方法，其中經由一化學機械拋光製程來執行該平坦化該間隙填充材料之步驟。
  7. 如請求項1所述之方法，其中該硬遮罩材料是氧化矽材料或氮化矽材料。
  8. 如請求項1所述之方法，其中形成該第一心軸結構之步驟包含：在該基板的暴露的該區域上磊晶沉積一III-V族材料。
  9. 如請求項8所述之方法，其中該第一心軸結構是由一GaAs材料形成的。
  10. 如請求項1所述之方法，其中沉積該間隙填充材料之步驟包含：執行一化學氣相沉積製程。
  11. 如請求項10所述之方法，其中該執行化學氣相沉積製程之步驟包含：沉積一可流動的氧化矽材料或一可流動的氮化矽材料。
  12. 如請求項1所述之方法，其中沉積該間隙填充材料之步驟包含：在一含氧化物的材料上進行旋塗。
  13. 如請求項1所述之方法，其中該第一心軸結構在該基板的一頂表面上方延伸一第一距離，該第一距離大於約80 nm。
  14. 如請求項13所述之方法，其中該第一距離在約100 nm與約200 nm之間。
  15. 如請求項13所述之方法，其中該第二心軸結構在該基板的該頂表面上方延伸一第二距離，該第二距離大致等於該第一距離。
  16. 一種鰭片結構處理方法，包含： 在一基板上形成一硬遮罩材料； 在該硬遮罩材料上沉積一間隔件材料； 圖案化該間隔件材料； 藉由蝕刻該硬遮罩材料將該間隔件材料的該圖案轉印到該硬遮罩材料，以暴露該基板的區域； 在該基板的暴露的該區域上形成第一心軸結構； 在該基板上在該硬遮罩材料和該第一心軸結構上方沉積一間隙填充材料； 移除該第一心軸結構以形成第二心軸結構，該第二心軸結構包含該硬遮罩材料和該間隙填充材料；以及 使用該第二心軸結構作為一遮罩來蝕刻該基板以形成溝槽從而形成鰭片結構，其中該鰭片結構在相鄰溝槽之間形成。
  17. 如請求項16所述之方法，其中經由一自對準雙重圖案化製程、一自對準四重圖案化製程或一定向自組裝製程來執行該圖案化該間隔件材料之步驟。
  18. 如請求項16所述之方法，其中該第一心軸結構包含一III-V族材料並且在該基板的一頂表面上方延伸一第一距離，該第一距離大於約80 nm。
  19. 如請求項18所述之方法，其中該第二心軸結構在該基板的該頂表面上方延伸一第二距離，該第二距離大致等於該第一距離。
  20. 一種鰭片結構處理方法，包含： 在一基板上形成一經圖案化的硬遮罩材料； 在該基板的暴露區域上形成III-V族材料的第一心軸結構，其中該III-V族材料的第一心軸結構在該基板的一頂表面上方延伸一第一距離，該第一距離大於約80 nm； 在該基板上在該硬遮罩材料和該III-V族材料的第一心軸結構上方沉積一可流動的氧化物間隙填充材料； 移除該III-V族材料的第一心軸結構以形成第二心軸結構，該第二心軸結構包含該硬遮罩材料和該可流動的氧化物間隙填充材料，其中該第二心軸結構在該基板的該頂表面上方延伸一第二距離，該第二距離大致等於該第一距離； 使用該第二心軸結構作為一遮罩來蝕刻該基板以形成溝槽從而形成含矽鰭片結構，其中該含矽鰭片結構在相鄰溝槽之間形成；以及 移除該第二心軸結構。
TW108104714A 2018-02-14 2019-02-13 用於蝕刻遮罩與鰭片結構形成之方法 TWI697958B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/896,827 US10439047B2 (en) 2018-02-14 2018-02-14 Methods for etch mask and fin structure formation
US15/896,827 2018-02-14

Publications (2)

Publication Number Publication Date
TW201935564A TW201935564A (zh) 2019-09-01
TWI697958B true TWI697958B (zh) 2020-07-01

Family

ID=65351875

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108104714A TWI697958B (zh) 2018-02-14 2019-02-13 用於蝕刻遮罩與鰭片結構形成之方法

Country Status (6)

Country Link
US (1) US10439047B2 (zh)
EP (1) EP3528279A3 (zh)
JP (1) JP2019195044A (zh)
KR (1) KR102135769B1 (zh)
CN (1) CN110164763A (zh)
TW (1) TWI697958B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170110364A1 (en) * 2013-09-13 2017-04-20 Qualcomm Incorporated Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
US20170186842A1 (en) * 2015-12-28 2017-06-29 International Business Machines Corporation Sidewall image transfer nanosheet
US9870942B1 (en) * 2017-01-19 2018-01-16 Globalfoundries Inc. Method of forming mandrel and non-mandrel metal lines having variable widths

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3540633B2 (ja) 1998-11-11 2004-07-07 株式会社東芝 半導体装置の製造方法
US6864164B1 (en) 2002-12-17 2005-03-08 Advanced Micro Devices, Inc. Finfet gate formation using reverse trim of dummy gate
US6855582B1 (en) 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US7018551B2 (en) 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
KR100587672B1 (ko) * 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
US7442976B2 (en) * 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7476933B2 (en) * 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7470570B2 (en) 2006-11-14 2008-12-30 International Business Machines Corporation Process for fabrication of FinFETs
US7772048B2 (en) 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US8404592B2 (en) * 2009-07-27 2013-03-26 GlobalFoundries, Inc. Methods for fabricating FinFET semiconductor devices using L-shaped spacers
JP5731858B2 (ja) 2011-03-09 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及び半導体装置の製造方法
US8637359B2 (en) 2011-06-10 2014-01-28 International Business Machines Corporation Fin-last replacement metal gate FinFET process
US8669186B2 (en) 2012-01-26 2014-03-11 Globalfoundries Inc. Methods of forming SRAM devices using sidewall image transfer techniques
JP2013183085A (ja) * 2012-03-02 2013-09-12 Toshiba Corp 半導体装置の製造方法
CN103855009B (zh) 2012-11-30 2017-06-13 中国科学院微电子研究所 鳍结构制造方法
KR101367989B1 (ko) * 2012-12-11 2014-02-28 한국과학기술원 Ultra-Thin FinFET 제조 방법 및 이를 이용하여 제조된 Ultra-Thin FinFET.
US8828839B2 (en) 2013-01-29 2014-09-09 GlobalFoundries, Inc. Methods for fabricating electrically-isolated finFET semiconductor devices
US8815661B1 (en) * 2013-02-15 2014-08-26 International Business Machines Corporation MIM capacitor in FinFET structure
CN104347421A (zh) 2013-08-07 2015-02-11 中芯国际集成电路制造(北京)有限公司 鳍式场效应管的形成方法
US9245882B2 (en) 2013-09-27 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with gradient germanium-containing channels
US9023705B1 (en) 2013-11-01 2015-05-05 Globalfoundries Inc. Methods of forming stressed multilayer FinFET devices with alternative channel materials
US9412603B2 (en) 2013-11-19 2016-08-09 Applied Materials, Inc. Trimming silicon fin width through oxidation and etch
US9224654B2 (en) 2013-11-25 2015-12-29 International Business Machines Corporation Fin capacitor employing sidewall image transfer
US9379196B2 (en) * 2014-02-06 2016-06-28 Infineon Technologies Austria Ag Method of forming a trench using epitaxial lateral overgrowth and deep vertical trench structure
US9209279B1 (en) * 2014-09-12 2015-12-08 Applied Materials, Inc. Self aligned replacement fin formation
US9530637B2 (en) 2014-10-05 2016-12-27 Applied Materials, Inc. Fin structure formation by selective etching
US9287135B1 (en) * 2015-05-26 2016-03-15 International Business Machines Corporation Sidewall image transfer process for fin patterning
US9899526B2 (en) * 2016-01-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor structure and manufacturing method thereof
KR102207120B1 (ko) * 2016-01-29 2021-01-22 도쿄엘렉트론가부시키가이샤 메모리 핀 패턴을 형성하기 위한 방법 및 시스템
US9852917B2 (en) * 2016-03-22 2017-12-26 International Business Machines Corporation Methods of fabricating semiconductor fins by double sidewall image transfer patterning through localized oxidation enhancement of sacrificial mandrel sidewalls
EP3437120B1 (en) * 2016-03-28 2020-11-18 INTEL Corporation Aligned pitch-quartered patterning for lithography edge placement error advanced rectification
US9722024B1 (en) * 2016-06-09 2017-08-01 Globalfoundries Inc. Formation of semiconductor structures employing selective removal of fins
US10453686B2 (en) * 2016-08-31 2019-10-22 Tokyo Electron Limited In-situ spacer reshaping for self-aligned multi-patterning methods and systems
KR20200083981A (ko) * 2017-11-30 2020-07-09 인텔 코포레이션 진보된 집적 회로 구조체 제조를 위한 핀 패터닝

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170110364A1 (en) * 2013-09-13 2017-04-20 Qualcomm Incorporated Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
US20170186842A1 (en) * 2015-12-28 2017-06-29 International Business Machines Corporation Sidewall image transfer nanosheet
US9870942B1 (en) * 2017-01-19 2018-01-16 Globalfoundries Inc. Method of forming mandrel and non-mandrel metal lines having variable widths

Also Published As

Publication number Publication date
KR102135769B1 (ko) 2020-07-20
US20190252523A1 (en) 2019-08-15
EP3528279A2 (en) 2019-08-21
KR20190098704A (ko) 2019-08-22
US10439047B2 (en) 2019-10-08
CN110164763A (zh) 2019-08-23
EP3528279A3 (en) 2019-12-18
TW201935564A (zh) 2019-09-01
JP2019195044A (ja) 2019-11-07

Similar Documents

Publication Publication Date Title
JP6723227B2 (ja) 自己整合代替フィン形成
US9530637B2 (en) Fin structure formation by selective etching
EP3171409B1 (en) Method for forming a field effect transistor device having an electrical contact
US11164959B2 (en) VFET devices with ILD protection
TW201830494A (zh) 半導體裝置的形成方法
US20080211054A1 (en) Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
TWI668730B (zh) 用於源極/汲極工程的整合系統及方法
US10541139B2 (en) Planarization control in semiconductor manufacturing process
JP2008210909A (ja) 半導体装置の製造方法
US10741393B2 (en) Methods for bottom up fin structure formation
JP2013153120A (ja) 半導体装置の製造方法
TWI697958B (zh) 用於蝕刻遮罩與鰭片結構形成之方法
KR100475025B1 (ko) 반도체소자의 소자분리절연막 형성방법
US11769665B2 (en) Power device structures and methods of making
KR20020049807A (ko) 반도체 디바이스의 소자 분리 방법
KR100645203B1 (ko) 에피 실리콘층 성장 방법
JP2005057147A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees