CN110164763A - 用于蚀刻掩模和鳍片结构形成的方法 - Google Patents
用于蚀刻掩模和鳍片结构形成的方法 Download PDFInfo
- Publication number
- CN110164763A CN110164763A CN201910115403.3A CN201910115403A CN110164763A CN 110164763 A CN110164763 A CN 110164763A CN 201910115403 A CN201910115403 A CN 201910115403A CN 110164763 A CN110164763 A CN 110164763A
- Authority
- CN
- China
- Prior art keywords
- substrate
- mandrel structure
- hard mask
- distance
- mandrel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 87
- 238000005530 etching Methods 0.000 title claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 157
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 238000003672 processing method Methods 0.000 claims abstract description 8
- 125000006850 spacer group Chemical group 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000009969 flowable effect Effects 0.000 claims description 5
- 238000012856 packing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims description 3
- 238000001338 self-assembly Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 239000002243 precursor Substances 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 241000237074 Centris Species 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 235000012377 Salvia columbariae var. columbariae Nutrition 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- CTNCAPKYOBYQCX-UHFFFAOYSA-N [P].[As] Chemical compound [P].[As] CTNCAPKYOBYQCX-UHFFFAOYSA-N 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- LVQULNGDVIKLPK-UHFFFAOYSA-N aluminium antimonide Chemical compound [Sb]#[Al] LVQULNGDVIKLPK-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- ILRRQNADMUWWFW-UHFFFAOYSA-K aluminium phosphate Chemical compound O1[Al]2OP1(=O)O2 ILRRQNADMUWWFW-UHFFFAOYSA-K 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- ROTPTZPNGBUOLZ-UHFFFAOYSA-N arsenic boron Chemical compound [B].[As] ROTPTZPNGBUOLZ-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- FFBGYFUYJVKRNV-UHFFFAOYSA-N boranylidynephosphane Chemical compound P#B FFBGYFUYJVKRNV-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 240000001735 chia Species 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical group C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02241—III-V semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本文所述的实施方式涉及基板处理方法。所述方法包括在基板上形成经图案化的硬掩模材料,在基板的暴露区域上形成第一心轴结构,以及在基板上在硬掩模材料和第一心轴结构上方沉积间隙填充材料。去除第一心轴结构以形成包含硬掩模材料和间隙填充材料的第二心轴结构,并且使用第二心轴结构作为掩模来蚀刻基板以形成鳍片结构。
Description
技术领域
本公开的实施方式大体涉及用于蚀刻掩模和鳍片结构形成的方法。
背景技术
鳍式场效应晶体管(FinFET)是半导体装置制造中常用的结构。当前技术节点处的常规FinFET是采用传统蚀刻技术制造的。然而,在具有减小的临界尺寸和不断增加的纵横比的先进技术节点处,传统的蚀刻技术不足以制造无缺陷的FinFET器件。
例如,为了制造具有足够垂直度的FinFET器件以用于各种半导体装置,利用厚间隔件来图案化下面的硬掩模。利用厚间隔件高度来减少经图案化的间隔件的弯曲或倾斜。然而,当间隔件图案转印到硬掩模时,硬掩模的不太理想的垂直度可能持续存在,这会导致FinFET器件在相邻的FinFET结构之间具有倾斜的侧壁或封闭的沟槽。
因此,在本领域中所需要的是用于掩模和鳍片结构制造和蚀刻的改进的方法。
发明内容
在一个实施方式中,提供一种基板处理方法。所述方法包括在基板上形成经图案化的硬掩模材料,在基板的暴露于经图案化的硬掩模材料之间的区域上形成第一心轴结构,以及在基板上在硬掩模材料和第一心轴结构上方沉积间隙填充材料。所述方法还包括去除第一心轴结构以形成第二心轴结构,该第二心轴结构包含硬掩模材料和间隙填充材料,以及使用所述第二心轴结构作为掩模来蚀刻基板以形成鳍片结构。
在另一个实施方式中,提供一种基板处理方法。所述方法包括在基板上形成硬掩模材料,在所述硬掩模材料上沉积间隔件材料,图案化所述间隔件材料,以及通过蚀刻硬掩模材料而将间隔件材料的图案转印到所述硬掩模材料以暴露基板的区域。在基板的暴露区域上形成第一心轴结构。在基板上在硬掩模材料和第一心轴结构上方沉积间隙填充材料。去除第一心轴结构以形成第二心轴结构,第二心轴结构包含硬掩模材料和间隙填充材料。使用所述第二心轴结构作为掩模来蚀刻基板以形成鳍片结构。
在另一个实施方式中,提供一种基板处理方法。所述方法包括在基板上形成经图案化的硬掩模材料,以及在基板的暴露区域上形成III-V族材料的第一心轴结构。III-V族材料的第一心轴结构在基板的顶表面上方延伸第一距离,所述第一距离大于约80nm。在基板上在硬掩模材料和III-V族材料的第一心轴结构上方沉积能够流动的氧化物间隙填充材料。去除III-V族材料的第一心轴结构以形成第二心轴结构,第二心轴结构包含硬掩模材料和能够流动的氧化物间隙填充材料。第二心轴结构在基板的顶表面上方延伸第二距离,所述第二距离大致等于第一距离。使用第二心轴结构作为掩模来蚀刻基板以形成含硅鳍片结构,以及随后去除第二心轴结构。
附图说明
因此,以可以详细地理解本公开的上述特征的方式,可以通过参考实施方式提供对上述简要概述的本公开的更具体描述,所述实施方式中的一些实施方式示出在附图中。然而,应注意,附图仅示出了示例性实施方式,因此不应视为限制本发明的范围,因为本发明可允许其他同等有效的实施方式。
图1示出了根据本文描述的一个实施方式的基板的局部横截面图,所述基板具有在其上形成的硬掩模材料和经图案化的间隔件材料。
图2示出了根据本文描述的一个实施方式的图1的基板的局部横截面图,其中在所述基板上去除了间隔件材料并且形成了第一心轴结构。
图3示出了根据本文描述的一个实施方式的图2的基板的局部横截面图,其中在基板上在硬掩模材料和第一心轴结构上方形成了间隙填充材料。
图4示出了根据本文描述的一个实施方式的图3的基板在平坦化间隙填充材料之后的局部横截面图。
图5示出了根据本文描述的一个实施方式的图4的基板的局部横截面图,其中第一心轴结构被去除以形成第二心轴结构。
图6示出了根据本文描述的一个实施方式的图5的基板在蚀刻基板之后的局部横截面图。
图7示出了根据本文描述的一个实施方式的用于图案化和蚀刻基板的方法的操作。
为了便于理解,已经尽可能使用相同的附图标记来指示诸图中共有的相同要素。可以设想,一个实施方式的要素和特征可以有利地并入其他实施方式,而无需进一步说明。
具体实施方式
本文所述的实施方式涉及特别适用于形成鳍片结构的基板处理方法。所述方法包括在基板上形成经图案化的硬掩模材料,在基板的暴露区域上形成第一心轴结构,以及在基板上在硬掩模材料和第一心轴结构上方沉积间隙填充材料。去除第一心轴结构以形成第二心轴结构,第二心轴结构包含硬掩模材料和间隙填充材料,并且使用第二心轴结构作为掩模来蚀刻基板以形成鳍片结构。利用本文所述的实施方式使得能够有效地制造具有改善的厚度和垂直度轮廓的蚀刻掩模,所述蚀刻掩模用于随后形成先进节点鳍片结构。
图7示出了根据本文描述的一个实施方式用于图案化和蚀刻基板的方法700的操作。方法700与图1至图6中描绘的图示同时讨论。在操作710处,对间隔件材料进行图案化并将图案转印到下面的硬掩模材料。
图1示出了根据本文描述的一个实施方式的基板102的局部横截面图,所述基板具有在其上形成的硬掩模材料104和经图案化的间隔件材料106。在一个实施方式中,基板102由半导体材料制成,所述半导体材料诸如硅。例如,基板102是单晶硅材料,所述单晶硅材料是本征(未掺杂)硅材料或非本征(掺杂)硅材料。如果利用非本征硅材料,则掺杂剂可以是p型掺杂剂,诸如硼。在另一个实施方式中,基板102是绝缘体上硅基板。
图1示出了在操作710处进行图案化之后的间隔件材料106和硬掩模材料104。在图案化之前,使硬掩模材料104以毯覆型层沉积在基板102上并与基板102接触。然后将间隔件材料106沉积在硬掩模材料104上并与所述硬掩模材料104接触。通过适用于先进技术节点的各种工艺来执行间隔件材料106的图案化,所述先进技术节点为诸如10nm节点、7nm节点、5nm节点以及更先进节点。合适的图案化工艺的示例包括自对准双重图案化和自对准四重图案化,所述自对准双重图案化和自对准四重图案化取决于所希望的具体实现而为浸没式光刻工艺或极紫外(EUV)光刻工艺。其他合适的图案化工艺包括定向自组装、193nm浸没式光刻-蚀刻-光刻-蚀刻(LELE)、以及EUV LELE等。
经图案化的间隔件材料106创建掩模以用于后续蚀刻下面的硬掩模材料104。在一个实施方式中,间隔件材料106是氧化硅材料、氮化硅材料、或氧化钛材料。在一个实施方式中,经图案化的间隔件材料106的厚度约等于鳍片间距的一半。例如,经图案化的间隔件材料的厚度在约15nm与约20nm之间。在一个实施方式中,硬掩模材料104的厚度在约30nm与约50nm之间,诸如约40nm。硬掩模材料104在一个实施方式中由氧化硅材料制成,而在另一个实施方式中由氮化硅材料制成。
利用蚀刻工艺(诸如湿法蚀刻工艺或干法蚀刻工艺)来蚀刻硬掩模材料104,从而将图案从间隔件材料106转印到硬掩模材料。在一个实施方式中,利用基于氟的蚀刻剂来蚀刻间隔件材料106和/或硬掩模材料104中的一者或两者。例如,用电容耦合的含氟等离子体蚀刻硬掩模材料104。在另一个示例中,用电感耦合的含氟等离子体蚀刻硬掩模材料104。合适的等离子体前体的示例包括碳氟化合物或氢氟烃材料,诸如C4F6、C4F8、CF4、CH2F2和CH3F。用于产生等离子体的源功率在约300W与约1500W之间,用于偏置等离子体的偏置功率在约50W与约700W之间,用于执行蚀刻工艺的工艺环境的压力保持在约5mTorr与约20mTorr之间,并且在蚀刻工艺期间基板102的温度保持在约10℃与约80℃之间。在蚀刻硬掩模材料104之后,基板102的区域114暴露在硬掩模材料104的相邻部分之间。
经图案化的硬掩模106的间距108小于约40nm,诸如约30nm或更小。在该实施方式中,经图案化的硬掩模材料部分的宽度110为约20nm或更小,诸如约15nm或更小。类似地,暴露区域114的宽度112为约20nm或更小,诸如约15nm或更小。
图2示出了根据本文描述的一个实施方式的图1的基板的局部横截面图,其中在所述基板102上去除了间隔件材料106并且形成了第一心轴结构202。在操作720处,在由硬掩模材料104图案化的基板上形成第一心轴结构202,如图2所示。通过合适的选择性蚀刻工艺来去除间隔件材料106,所述合适的选择性蚀刻工艺诸如湿法蚀刻工艺或干法蚀刻工艺。
在间隔件材料106是氧化硅材料的实施方式中,从以下前体中的一种或多种前体产生等离子体:C4F6、O2、Ar、以及He。在此实施方式中,用于产生等离子体的源功率在约300W与约900W之间,用于偏置等离子体的偏置功率在约300W与约700W之间,并且用于执行蚀刻工艺的工艺环境的压力保持在约5mTorr与约15mTorr之间。在间隔件材料106是氮化硅材料的实施方式中,从以下前体中的一种或多种前体产生等离子体:CH3F、CH4、O2、H2、N2、以及He。在此实施方式中,用于产生等离子体的源功率在约400W与约800W之间,并且用于偏置等离子体的偏置功率在约30W与约100W之间。在间隔件材料106是氧化硅材料的其他实施方式中,利用稀释HF湿法蚀刻工艺。
在一个实施方式中,用于执行蚀刻工艺的合适设备是可购自加利福尼亚州圣克拉拉市的应用材料公司(Applied Materials,Inc.,Santa Clara,CA)的CENTRISTM SYM3TM蚀刻设备。可以预期,也可以根据本文描述的实施方式利用来自其他制造商的其他适当配置的设备。间隔件去除工艺相对于硬掩模材料104和基板102选择性地去除间隔件材料106,从而在基板102上留下硬掩模材料104。
在图1所示的暴露区域114中形成第一心轴结构202。将第一心轴结构202沉积在基板102的表面206上,并且使第一心轴结构202从基板102的表面206生长。在一个实施方式中,用于执行所述第一心轴结构沉积的合适设备是可购自加利福尼亚州圣克拉拉市的应用材料公司的RP EPI设备。预期来自其他制造商的其他适当配置的设备也可以根据本文描述的实施方式利用。通过经图案化的硬掩模材料104和空隙210使每个第一心轴结构202与相邻的第一心轴结构202分开。使第一心轴结构202生长,以使得第一心轴结构202的顶表面208是在基板102的表面206上方大于约80nm的距离204。在一个实施方式中,距离204在约100nm与约200nm之间。
在一个实施方式中,使用外延沉积工艺在基板102上形成第一心轴结构202。在一个实施方式中,将含镓前体和含砷前体以交替方式脉冲以沉积第一心轴结构202。在此实施方式中,含镓前体是三甲基镓,并且含砷前体是AsH3。在此实施方式中,在保持于在约1torr与约10Torr之间的压力和在约450℃与约800℃之间的温度下的环境中制造第一心轴结构202。外延沉积工艺利用逐层沉积技术,据信所述逐层沉积技术当第一心轴结构202从表面206并且在硬掩模材料104上方继续生长时,使第一心轴结构202保持基本上垂直的取向。
在一个实施方式中,第一心轴结构202是由III-V族材料形成的。例如,第一心轴结构202由以下物质中的一种或多种物质形成:锑化铝、砷化铝、砷化铝镓、磷化铝镓铟、氮化铝镓、磷化铝镓、砷化铝铟、氮化铝、磷化铝、砷化硼、氮化硼、磷化硼、锑化镓、砷化镓、磷砷化镓、磷化镓、锑化铟、砷化铟、砷化铟镓,氮化铟镓、磷化铟镓、氮化铟、以及磷化铟等。
在操作730处,在基板102上在硬掩模材料104和第一心轴结构202上方沉积间隙填充材料302。图3示出了根据本文描述的实施方式的图2的基板102的局部横截面图,其中在基板102上在硬掩模材料104和第一心轴结构202上方形成了间隙填充材料302。沉积间隙填充材料302,以使得所述间隙填充材料填充空隙210并且沉积到厚度超过第一心轴结构202的顶表面208。在一个实施方式中,用于执行间隙填充沉积工艺的合适的设备是可购自加利福尼亚州圣克拉拉市的应用材料公司的ETERNATM FCVDTM设备。可以预期,也可以根据本文描述的实施方式利用来自其他制造商的适当配置的设备。
在一个实施方式中,间隙填充材料是能够流动的材料。能够流动的材料具有固体材料的特性,但也具有“流动”的能力,因此使得能够实现基本上无空隙的自底向上的材料沉积。在一个实施方式中,通过能够流动的化学气相沉积(CVD)工艺来沉积间隙填充材料302。在一个示例中,利用CVD工艺来沉积含有氧化硅的能够流动的间隙填充材料302。在此实施方式中,顺序地使氧化硅材料沉积、固化和退火。在另一示例中,利用CVD工艺来沉积氮化硅间隙填充材料302。在此实施方式中,顺序地使氮化硅材料沉积和经受氮化等离子体处理。在另一个实施方式中,通过旋涂玻璃(spin on glass,SOG)工艺来形成间隙填充材料302。在此实施方式中,间隙填充材料302是含氧化物的材料,诸如二氧化硅等。
在操作740处,平坦化间隙填充材料。图4示出了根据本文描述的一个实施方式的图3的基板102在平坦化间隙填充材料302之后的局部横截面图。在一个实施方式中,通过氧化物或氮化物化学机械抛光工艺来执行间隙填充材料302的平坦化。在另一实施方式中,通过氧化物或氮化物干法蚀刻工艺或湿法蚀刻工艺来执行间隙填充材料302的平坦化。
去除间隙填充材料302至某一点处,在所述点处,间隙填充材料302的顶表面402与第一心轴结构202的顶表面208基本上相平。在一个实施方式中,预期第一心轴结构202用作去除点。在另一实施方式中,使间隙填充材料302经受基于时间的工艺以平坦化表面402、208。
在操作750处,去除第一心轴结构202以形成第二心轴结构500,所述第二心轴结构500包含硬掩模材料104和间隙填充材料302。图5示出了根据本文描述的一个实施方式的图4的基板102的局部横截面图,其中第一心轴结构202被去除以形成第二心轴结构500。利用选择性蚀刻工艺来去除第一心轴结构202。例如,利用对III-V族材料具有选择性的蚀刻化学物质来相对于含氧化物和/或氮化物的间隙填充材料302和硬掩模材料104优先地去除第一心轴结构202。
在一个实施方式中,将含氯前体(诸如HCl)与含氢前体(诸如H2)一起输送到工艺环境。将所述前体用惰性载气(诸如N2或Ar)输送到工艺环境。在一个示例中,以在约1sccm与约500sccm之间的流率将HCl输送到工艺环境。使工艺环境的温度保持在约300℃与约700℃之间,并且使工艺环境的压力保持在约0Torr与约100Torr之间。
第一心轴结构202的去除导致在相邻的第二心轴结构500之间形成间隔502。间隔502还使基板102的顶表面206暴露,所述顶表面206在后续工艺中被蚀刻。第二心轴结构500的高度类似于距离204。据信,通过利用足够厚的心轴结构作为掩模,后续的蚀刻工艺表现出改善的垂直度。
在操作760处,使用第二心轴结构500作为掩模来蚀刻基板102以形成鳍片结构602。图6示出了根据本文描述的一个实施方式的图5的基板102在蚀刻基板102之后的局部横截面图。蚀刻工艺对硅材料具有选择性,并且相对于硬掩模材料104和间隙填充材料302的氧化物和氮化物材料优先蚀刻基板102。
在一个实施方式中,将含卤素的前体(诸如HBr或Cl2)激活成等离子体,并用惰性载气(诸如Ar)输送到工艺环境。在某些实施方式中,还将含氧和/或氮的前体(诸如O2或N2)输送到工艺环境。在此实施方式中,通过电感耦合等离子体工艺激活前体,其中源功率在约500W与约2000W之间,并且偏置功率在约50W与约500W之间。在等离子体形成和蚀刻基板102期间,工艺环境的压力在约5mTorr与约15mTorr之间。
在一个实施方式中,蚀刻基板102利用各向异性蚀刻工艺以获得鳍片结构602的基本上垂直的侧壁。蚀刻工艺还在相邻的鳍片结构602之间形成沟槽604。在将基板102蚀刻到所希望的深度之后,所得鳍片结构602的高度606大于约80nm,诸如在约100nm与约200nm之间。在鳍片结构形成之后,可以去除第二心轴结构500,并且可以在基板102上执行后续的半导体制造操作。
概括地说,改进的掩模形成和蚀刻工艺流程使得能够进行先进半导体装置的制造。通过减小间隔件材料的高度并通过增加掩模的高度(即第一心轴结构和第二心轴结构),实现了蚀刻垂直度的改善。还据信,利用本文所述的工艺流程,改善了掩模(第一心轴结构和第二心轴结构)的侧壁垂直度,这导致了所希望的蚀刻垂直度特性。因此,更有效地控制了侧壁(横向生长)并且还减小了边缘粗糙度。
虽然前述内容涉及本公开的实施方式,但是可以在不脱离本公开的基本范围的情况下设计本公开的其他和进一步的实施方式,并且本公开的范围由所附权利要求书来确定。
元件符号列表
102 基板
104 硬掩模材料
106 经图案化的硬掩模
106 间隔件材料
108 间距
110 宽度
112 宽度
114 区域
202 第一心轴结构
204 距离
206 表面
208 表面
210 空隙
302 间隙填充材料
402 表面
500 第二心轴结构
502 间隔
602 鳍片结构
604 形成沟槽
606 高度
700 方法
710 操作
720 操作
730 操作
740 操作
750 操作
760 操作
Claims (20)
1.一种鳍片结构处理方法,包括:
在基板上形成经图案化的硬掩模材料;
在所述基板的暴露在所述经图案化的硬掩模材料之间的区域上形成第一心轴结构;
在所述基板上在所述硬掩模材料和所述第一心轴结构上方沉积间隙填充材料;
去除所述第一心轴结构以形成第二心轴结构,所述第二心轴结构包含所述硬掩模材料和所述间隙填充材料;以及
使用所述第二心轴结构作为掩模来蚀刻所述基板以形成沟槽从而形成鳍片结构,其中鳍片结构在相邻沟槽之间形成。
2.根据权利要求1所述的方法,还包括:
在所述硬掩模材料上沉积间隔件材料并图案化所述间隔件材料。
3.根据权利要求2所述的方法,其中将所述间隔件材料的图案转印到所述硬掩模材料以形成所述经图案化的硬掩模材料。
4.根据权利要求2所述的方法,其中通过自对准双重图案化工艺、自对准四重图案化工艺或定向自组装工艺来执行所述图案化所述间隔件材料。
5.根据权利要求1所述的方法,还包括:
在去除所述第一心轴结构之前平坦化所述间隙填充材料。
6.根据权利要求5所述的方法,其中通过化学机械抛光工艺来执行所述平坦化所述间隙填充材料。
7.根据权利要求1所述的方法,其中所述硬掩模材料是氧化硅材料或氮化硅材料。
8.根据权利要求1所述的方法,其中形成所述第一心轴结构包括在所述基板的暴露的所述区域上外延沉积III-V族材料。
9.根据权利要求8所述的方法,其中所述第一心轴结构是由GaAs材料形成的。
10.根据权利要求1所述的方法,其中沉积所述间隙填充材料包括执行化学气相沉积工艺。
11.根据权利要求10所述的方法,其中所述执行化学气相沉积工艺包括沉积能够流动的氧化硅材料或能够流动的氮化硅材料。
12.根据权利要求1所述的方法,其中沉积所述间隙填充材料包括在含氧化物的材料上进行旋涂。
13.根据权利要求1所述的方法,其中所述第一心轴结构在所述基板的顶表面上方延伸第一距离,所述第一距离大于约80nm。
14.根据权利要求13所述的方法,其中所述第一距离在约100nm与约200nm之间。
15.根据权利要求13所述的方法,其中所述第二心轴结构在所述基板的所述顶表面上方延伸第二距离,所述第二距离大致等于所述第一距离。
16.一种鳍片结构处理方法,包括:
在基板上形成硬掩模材料;
在所述硬掩模材料上沉积间隔件材料;
图案化所述间隔件材料;
通过蚀刻所述硬掩模材料将所述间隔件材料的所述图案转印到所述硬掩模材料,以暴露所述基板的区域;
在所述基板的暴露的所述区域上形成第一心轴结构;
在所述基板上在所述硬掩模材料和所述第一心轴结构上方沉积间隙填充材料;
去除所述第一心轴结构以形成第二心轴结构,所述第二心轴结构包含所述硬掩模材料和所述间隙填充材料;以及
使用所述第二心轴结构作为掩模来蚀刻所述基板以形成沟槽从而形成鳍片结构,其中所述鳍片结构在相邻沟槽之间形成。
17.根据权利要求16所述的方法,其中通过自对准双重图案化工艺、自对准四重图案化工艺或定向自组装工艺来执行所述图案化所述间隔件材料。
18.根据权利要求16所述的方法,其中所述第一心轴结构包含III-V族材料并且在所述基板的顶表面上方延伸第一距离,所述第一距离大于约80nm。
19.根据权利要求18所述的方法,其中所述第二心轴结构在所述基板的所述顶表面上方延伸第二距离,所述第二距离大致等于所述第一距离。
20.一种鳍片结构处理方法,包括:
在基板上形成经图案化的硬掩模材料;
在所述基板的暴露区域上形成III-V族材料的第一心轴结构,其中所述III-V族材料的第一心轴结构在所述基板的顶表面上方延伸第一距离,所述第一距离大于约80nm;
在所述基板上在所述硬掩模材料和所述III-V族材料的第一心轴结构上方沉积能够流动的氧化物间隙填充材料;
去除所述III-V族材料的第一心轴结构以形成第二心轴结构,所述第二心轴结构包含所述硬掩模材料和所述能够流动的氧化物间隙填充材料,其中所述第二心轴结构在所述基板的所述顶表面上方延伸第二距离,所述第二距离大致等于所述第一距离;
使用所述第二心轴结构作为掩模来蚀刻所述基板以形成沟槽从而形成含硅鳍片结构,其中所述含硅鳍片结构在相邻沟槽之间形成;以及
去除所述第二心轴结构。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/896,827 | 2018-02-14 | ||
US15/896,827 US10439047B2 (en) | 2018-02-14 | 2018-02-14 | Methods for etch mask and fin structure formation |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110164763A true CN110164763A (zh) | 2019-08-23 |
Family
ID=65351875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910115403.3A Pending CN110164763A (zh) | 2018-02-14 | 2019-02-13 | 用于蚀刻掩模和鳍片结构形成的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10439047B2 (zh) |
EP (1) | EP3528279A3 (zh) |
JP (1) | JP2019195044A (zh) |
KR (1) | KR102135769B1 (zh) |
CN (1) | CN110164763A (zh) |
TW (1) | TWI697958B (zh) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050078749A (ko) * | 2004-02-02 | 2005-08-08 | 삼성전자주식회사 | 다마신 공법을 이용한 핀 트랜지스터 형성방법 |
US20110021026A1 (en) * | 2009-07-27 | 2011-01-27 | Globalfoundries Inc. | Methods for fabricating finfet semiconductor devices using l-shaped spacers |
US20130230953A1 (en) * | 2012-03-02 | 2013-09-05 | Gaku Sudo | Method for manufacturing semiconductor device |
KR101367989B1 (ko) * | 2012-12-11 | 2014-02-28 | 한국과학기술원 | Ultra-Thin FinFET 제조 방법 및 이를 이용하여 제조된 Ultra-Thin FinFET. |
US20150076704A1 (en) * | 2013-09-13 | 2015-03-19 | Qualcomm Incorporatd | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device |
CN104835715A (zh) * | 2014-02-06 | 2015-08-12 | 英飞凌科技奥地利有限公司 | 使用外延横向过生长来形成沟槽的方法和深垂直沟槽结构 |
US9287135B1 (en) * | 2015-05-26 | 2016-03-15 | International Business Machines Corporation | Sidewall image transfer process for fin patterning |
CN107039435A (zh) * | 2016-01-15 | 2017-08-11 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管结构及其制造方法 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3540633B2 (ja) | 1998-11-11 | 2004-07-07 | 株式会社東芝 | 半導体装置の製造方法 |
US6864164B1 (en) | 2002-12-17 | 2005-03-08 | Advanced Micro Devices, Inc. | Finfet gate formation using reverse trim of dummy gate |
US6855582B1 (en) | 2003-06-12 | 2005-02-15 | Advanced Micro Devices, Inc. | FinFET gate formation using reverse trim and oxide polish |
US7018551B2 (en) | 2003-12-09 | 2006-03-28 | International Business Machines Corporation | Pull-back method of forming fins in FinFets |
US7442976B2 (en) * | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7476933B2 (en) * | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7470570B2 (en) | 2006-11-14 | 2008-12-30 | International Business Machines Corporation | Process for fabrication of FinFETs |
US7772048B2 (en) | 2007-02-23 | 2010-08-10 | Freescale Semiconductor, Inc. | Forming semiconductor fins using a sacrificial fin |
JP5731858B2 (ja) | 2011-03-09 | 2015-06-10 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及び半導体装置の製造方法 |
US8637359B2 (en) | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
US8669186B2 (en) | 2012-01-26 | 2014-03-11 | Globalfoundries Inc. | Methods of forming SRAM devices using sidewall image transfer techniques |
CN103855009B (zh) | 2012-11-30 | 2017-06-13 | 中国科学院微电子研究所 | 鳍结构制造方法 |
US8828839B2 (en) | 2013-01-29 | 2014-09-09 | GlobalFoundries, Inc. | Methods for fabricating electrically-isolated finFET semiconductor devices |
US8815661B1 (en) * | 2013-02-15 | 2014-08-26 | International Business Machines Corporation | MIM capacitor in FinFET structure |
CN104347421A (zh) | 2013-08-07 | 2015-02-11 | 中芯国际集成电路制造(北京)有限公司 | 鳍式场效应管的形成方法 |
US9245882B2 (en) | 2013-09-27 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with gradient germanium-containing channels |
US9023705B1 (en) | 2013-11-01 | 2015-05-05 | Globalfoundries Inc. | Methods of forming stressed multilayer FinFET devices with alternative channel materials |
US9412603B2 (en) | 2013-11-19 | 2016-08-09 | Applied Materials, Inc. | Trimming silicon fin width through oxidation and etch |
US9224654B2 (en) | 2013-11-25 | 2015-12-29 | International Business Machines Corporation | Fin capacitor employing sidewall image transfer |
US9209279B1 (en) | 2014-09-12 | 2015-12-08 | Applied Materials, Inc. | Self aligned replacement fin formation |
US9530637B2 (en) | 2014-10-05 | 2016-12-27 | Applied Materials, Inc. | Fin structure formation by selective etching |
US9722022B2 (en) * | 2015-12-28 | 2017-08-01 | International Business Machines Corporation | Sidewall image transfer nanosheet |
KR102207120B1 (ko) * | 2016-01-29 | 2021-01-22 | 도쿄엘렉트론가부시키가이샤 | 메모리 핀 패턴을 형성하기 위한 방법 및 시스템 |
US9852917B2 (en) | 2016-03-22 | 2017-12-26 | International Business Machines Corporation | Methods of fabricating semiconductor fins by double sidewall image transfer patterning through localized oxidation enhancement of sacrificial mandrel sidewalls |
CN108885974A (zh) * | 2016-03-28 | 2018-11-23 | 英特尔公司 | 用于光刻边缘放置误差提前矫正的对齐节距四等分图案化 |
US9722024B1 (en) * | 2016-06-09 | 2017-08-01 | Globalfoundries Inc. | Formation of semiconductor structures employing selective removal of fins |
US10453686B2 (en) * | 2016-08-31 | 2019-10-22 | Tokyo Electron Limited | In-situ spacer reshaping for self-aligned multi-patterning methods and systems |
US9870942B1 (en) * | 2017-01-19 | 2018-01-16 | Globalfoundries Inc. | Method of forming mandrel and non-mandrel metal lines having variable widths |
US11881520B2 (en) * | 2017-11-30 | 2024-01-23 | Intel Corporation | Fin patterning for advanced integrated circuit structure fabrication |
-
2018
- 2018-02-14 US US15/896,827 patent/US10439047B2/en not_active Expired - Fee Related
-
2019
- 2019-02-04 JP JP2019017582A patent/JP2019195044A/ja not_active Ceased
- 2019-02-05 EP EP19155551.5A patent/EP3528279A3/en not_active Withdrawn
- 2019-02-08 KR KR1020190015180A patent/KR102135769B1/ko active IP Right Grant
- 2019-02-13 CN CN201910115403.3A patent/CN110164763A/zh active Pending
- 2019-02-13 TW TW108104714A patent/TWI697958B/zh not_active IP Right Cessation
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20050078749A (ko) * | 2004-02-02 | 2005-08-08 | 삼성전자주식회사 | 다마신 공법을 이용한 핀 트랜지스터 형성방법 |
US20110021026A1 (en) * | 2009-07-27 | 2011-01-27 | Globalfoundries Inc. | Methods for fabricating finfet semiconductor devices using l-shaped spacers |
US20130230953A1 (en) * | 2012-03-02 | 2013-09-05 | Gaku Sudo | Method for manufacturing semiconductor device |
KR101367989B1 (ko) * | 2012-12-11 | 2014-02-28 | 한국과학기술원 | Ultra-Thin FinFET 제조 방법 및 이를 이용하여 제조된 Ultra-Thin FinFET. |
US20150076704A1 (en) * | 2013-09-13 | 2015-03-19 | Qualcomm Incorporatd | Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device |
CN104835715A (zh) * | 2014-02-06 | 2015-08-12 | 英飞凌科技奥地利有限公司 | 使用外延横向过生长来形成沟槽的方法和深垂直沟槽结构 |
US9287135B1 (en) * | 2015-05-26 | 2016-03-15 | International Business Machines Corporation | Sidewall image transfer process for fin patterning |
CN107039435A (zh) * | 2016-01-15 | 2017-08-11 | 台湾积体电路制造股份有限公司 | 鳍式场效应晶体管结构及其制造方法 |
Non-Patent Citations (1)
Title |
---|
刘洪图等: "超大规模集成电路的一些材料物理问题(Ⅱ)──尺寸缩小带来的巨大挑战", 《物理》 * |
Also Published As
Publication number | Publication date |
---|---|
US10439047B2 (en) | 2019-10-08 |
EP3528279A3 (en) | 2019-12-18 |
EP3528279A2 (en) | 2019-08-21 |
KR20190098704A (ko) | 2019-08-22 |
JP2019195044A (ja) | 2019-11-07 |
TWI697958B (zh) | 2020-07-01 |
KR102135769B1 (ko) | 2020-07-20 |
TW201935564A (zh) | 2019-09-01 |
US20190252523A1 (en) | 2019-08-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6723227B2 (ja) | 自己整合代替フィン形成 | |
US9768031B2 (en) | Semiconductor device manufacturing methods | |
US9530637B2 (en) | Fin structure formation by selective etching | |
KR20180097763A (ko) | 측방향 하드마스크 리세스 감소를 위한 하이브리드 탄소 하드마스크 | |
US9947548B2 (en) | Self-aligned single dummy fin cut with tight pitch | |
CN110164973A (zh) | 用于自底向上鳍片结构形成的方法 | |
KR102425110B1 (ko) | 적층된 층을 형성하는 방법 및 그에 의해 형성된 소자 | |
JP2008218999A (ja) | 半導体装置の製造方法 | |
JP7407583B2 (ja) | 自己整合マルチパターニングにおいてスペーサプロファイルを再整形する方法 | |
US9741567B2 (en) | Method of forming multiple patterning spacer structures | |
TWI751328B (zh) | 使用獨立式垂直碳結構來實現金屬觸點上的自對準微影術與選擇性沉積的方法 | |
CN110164763A (zh) | 用于蚀刻掩模和鳍片结构形成的方法 | |
TWI462175B (zh) | 調整半導體基板槽深的製造方法 | |
TW202349493A (zh) | 多晶半導體的蝕刻 | |
CN118511282A (zh) | 功率器件结构及制造方法 | |
WO2017153194A1 (en) | Method for providing a tungsten layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190823 |
|
WD01 | Invention patent application deemed withdrawn after publication |