CN110164973A - 用于自底向上鳍片结构形成的方法 - Google Patents

用于自底向上鳍片结构形成的方法 Download PDF

Info

Publication number
CN110164973A
CN110164973A CN201910116287.7A CN201910116287A CN110164973A CN 110164973 A CN110164973 A CN 110164973A CN 201910116287 A CN201910116287 A CN 201910116287A CN 110164973 A CN110164973 A CN 110164973A
Authority
CN
China
Prior art keywords
substrate
hard mask
mandrel structure
gap filling
mandrel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910116287.7A
Other languages
English (en)
Inventor
Y-C·林
Q·周
X·包
Y·张
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN110164973A publication Critical patent/CN110164973A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本文描述的实施方式涉及基板处理方法。所述方法包括:在基板上形成图案化硬掩模材料;在所述基板的暴露区域上形成第一心轴结构;和在所述基板上将填隙材料沉积在所述硬掩模材料和所述第一芯轴结构之上。移除所述第一心轴结构以暴露所述基板的第二区域,以形成包括了所述硬掩模材料的第二心轴结构,并且使用所述第二心轴结构作为掩模,将所述间隙填充材料和鳍片结构沉积在所述基板上。

Description

用于自底向上鳍片结构形成的方法
技术领域
本公开内容的实施方式总的来说涉及用于自底向上鳍片结构形成的方法。
背景技术
鳍片场效应晶体管(FinFET)是普遍用于半导体器件的制造中的结构。在当前技术节点处的常规FinFET采用常规蚀刻技术制造。然而,在具有减小的临界尺寸和增大的深宽比的先进技术节点处,常规蚀刻技术不足以制造出无缺陷FinFET器件。
例如,为了制造具有足够的竖直度的FinFET器件以用于各种半导体器件中,利用厚间隔件来将下层的硬掩模图案化。厚间隔件高度用于减少图案化间隔件的弯曲或倾斜。然而,当间隔件图案被转移到硬掩模时,硬掩模的不太理想的竖直度可能持续,这导致了在相邻FinFET结构之间具有倾斜侧壁或闭塞沟槽的FinFET器件。
因此,本领域需要用于鳍片结构形成的改进的方法。
发明内容
在一个实施方式中,提供了一种基板处理方法。所述方法包括:在基板上形成图案化硬掩模材料;在所述基板的暴露区域上形成第一心轴结构;和将间隙填充材料沉积在所述硬掩模材料和所述第一心轴结构上。所述方法还包括:移除所述第一心轴结构以暴露所述基板的第二区域并形成包括所述硬掩模材料和所述间隙填充材料的第二心轴结构;和使用所述第二心轴结构作为掩模在所述基板的所述第二区域上形成鳍片结构。
在另一个实施方式中,提供了一种基板处理方法。所述方法包括:在基板上形成硬掩模材料;将间隔件材料沉积在所述硬掩模材料上;将所述间隔件材料图案化;和通过蚀刻所述硬掩模材料以将所述间隔件材料的图案转移到所述硬掩模材料来暴露所述基板的区域。在所述基板的所述暴露区域上形成第一心轴结构。将间隙填充材料沉积在所述硬掩模材料和所述第一心轴结构上。移除所述第一心轴结构以暴露所述基板的第二区域并形成包括了所述硬掩模材料和所述间隙填充材料的第二心轴结构。使用所述第二心轴结构作为掩模在所述基板的所述第二区域上形成鳍片结构,并且使所述间隙填充材料在所述鳍片结构的顶表面下方凹陷。
在又一个实施方式中,提供了一种基板处理方法。所述方法包括:在基板上形成图案化硬掩模材料;和在所述基板的暴露区域上形成III-V材料第一心轴结构。所述III-V材料第一心轴结构在所述基板的顶表面上方延伸大于约80nm的第一距离。将可流动氧化物间隙填充材料沉积在所述硬掩模材料和所述III-V材料第一心轴结构上。移除所述III-V材料以暴露所述基板的第二区域并形成包括所述硬掩模材料和所述可流动氧化物间隙填充材料的第二心轴结构。所述第二心轴结构在所述基板的所述顶表面上方延伸近似等于所述第一距离的第二距离。在所述基板的所述第二区域上外延沉积鳍片结构,并且在形成所述鳍片结构之后蚀刻所述间隙填充材料。
附图简述
为了能够详细地理解本公开内容的上述特征方式,可以通过参考实施例来对以上简要概括的实施例进行更具体的描述,这些实施例中的一些在附图中被示出。然而,将注意,附图仅示出了示例性实施方式,并且因此不应被视为限制本公开内容的范围,因为本公开内容可允许其它等效实施方式。
图1示出了根据本文描述的实施方式的具有图案化间隔件材料和在其上形成的硬掩模材料的基板的局部剖视图。
图2示出了根据本文描述的实施方式的图1的基板的局部截面图,其中间隔件材料被移除并且第一心轴结构形成在基板上。
图3示出了根据本文描述的实施方式的图2的基板的局部截面图,其中在基板上将间隙填充材料形成在硬掩模材料和第一心轴结构之上。
图4示出了根据本文描述的实施方式的在间隙填充材料平面化之后的图3的基板的局部截面图。
图5示出了根据本文描述的实施方式的图4的基板的局部截面图,其中第一心轴结构被移除以形成第二心轴结构。
图6示出了根据本文描述的实施方式在基板上形成鳍片结构之后的图5的基板的局部截面图。
图7示出了根据本文描述的实施方式的在蚀刻间隙填充材料之后的图6的基板的局部截面图。
图8示出了根据本文描述的实施方式的用于将基板图案化并蚀刻基板的方法的操作。
为了促进理解,已尽可能使用相同的参考标记标示各附图共有的相同元素。将设想到,可以将一个实施方式的要素和特征有益地并入其它实施方式而不再进一步叙述。
具体实施方式
本文描述的实施方式涉及有利地形成鳍片结构的基板处理方法,所述鳍片结构自底向上形成。所述方法包括:在基板上形成图案化硬掩模材料;在所述基板的暴露区域上形成第一心轴结构;和在所述基板上将间隙填充材料沉积在所述硬掩模材料和所述第一心轴结构之上。移除所述第一心轴结构以暴露所述基板的第二区域,形成包括所述硬掩模材料的第二心轴结构,并且使用所述第二心轴结构作为掩模将所述间隙填充材料和鳍片结构沉积在所述基板上。
图8示出了根据本文描述的实施方式的用于自底向上地将基板图案化并蚀刻基板的方法800的流程图。方法800与图1至图6中描绘的图示一同讨论。在操作810处,将间隔件材料图案化并将图案转移到下层的硬掩模材料。
图1示出了根据本文描述的实施方式的基板102的局部截面图,所述基板102具有图案化间隔件材料106和在其上形成的硬掩模材料104。在一个实施方式中,基板102由半导体材料(诸如硅)制成。例如,基板102是单晶硅材料,所述单晶硅材料是本征(未掺杂)硅材料或非本征(掺杂)硅材料。如果使用非本征硅材料,那么掺杂剂可以是p型掺杂剂,诸如硼。在另一个实施方式中,基板102是绝缘体上硅基板。
如图1所示,间隔件材料106和硬掩模材料104被图案化。在图案化之前,硬掩模材料104以覆盖型层的方式沉积在基板102上并与基板102接触。然后将间隔件材料106沉积在硬掩模材料104上并与硬掩模材料104接触。通过适于先进技术节点(诸如10nm节点、7nm节点、5nm节点和更小的节点)的各种工艺来执行间隔件材料106的图案化。合适的图案化工艺的示例包括作为浸没式光刻或极紫外(EUV)光刻工艺的自对准双重图案化和自对准四重图案化,这取决于所期望的实现方式。其它合适的图案化工艺包括定向自组装、193nm浸没式光刻-蚀刻-光刻-蚀刻(LELE)和EUV LELE等。
图案化间隔件材料106形成掩模,以用于随后蚀刻下层的硬掩模材料104。在一个实施方式中,间隔件材料106是氧化硅材料、氮化硅材料或氧化钛材料。在一个实施方式中,图案化间隔件材料106的厚度近似等于鳍片间距的一半。例如,图案化间隔件材料的厚度在约15nm与约20nm之间。在一个实施方式中,硬掩模材料104的厚度在约30nm与约50nm之间,诸如约40nm。在一个实施方式中,硬掩模材料104由氧化硅材料制成,在另一个实施方式中,硬掩模材料104由氮化硅材料制成。
利用诸如湿法蚀刻工艺或干法蚀刻工艺之类的蚀刻工艺来蚀刻硬掩模材料104,由此将图案从间隔件材料106转移到硬掩模材料。在一个实施方式中,蚀刻工艺是干法蚀刻工艺。在此实施方式中,利用由以下前驱物中的一种或多种前驱物产生的含氟等离子体来蚀刻含有氮化物或氧化物的膜:CF4、CHF3、CH2F2、CH3F、C4F6或C4F8。用于产生等离子体的源功率在约300W与约1500W之间,用于偏置等离子体的偏置功率在约50W与约700W之间,用于执行蚀刻工艺的工艺环境的压力保持在约5毫托(mTorr)与约20毫托之间,并且在蚀刻工艺期间将基板102的温度保持在约10℃与约80℃之间。在蚀刻硬掩模材料104之后,基板102的区域114暴露在硬掩模材料104的相邻部分之间。
图案化硬掩模106的间距108小于约40nm,诸如约30nm或更小。在此实施方式中,某些硬掩模材料部分的宽度110为约20nm或更小,诸如约15nm或更小。类似地,暴露区域114的宽度112为约20nm或更小,诸如约15nm或更小。
在操作820处,第一心轴结构202形成在由硬掩模材料104图案化的基板上。图2示出了根据本文描述的实施方式的图1的基板的局部截面图,其中间隔件材料106被移除并且第一心轴结构202形成在基板102上。通过合适的选择性蚀刻工艺(诸如湿法蚀刻或干法蚀刻工艺)移除间隔件材料106。
在间隔件材料106是氧化硅材料的实施方式中,从以下前驱物中的一种或多种前驱物产生等离子体:C4F6、O2、Ar和He。在此实施方式中,用于产生等离子体的源功率在约300W与约900W之间,用于偏置等离子体的偏置功率在约300W与约700W之间,并且将用于执行蚀刻工艺的工艺环境的压力保持在约5毫托至约15毫托之间。在间隔件材料106是氮化硅材料的实施方式中,从以下前驱物中的一种或多种前驱物产生等离子体:CH3F、CH4O2、H2、N2和He。在此实施方式中,用于产生等离子体的功率源在约400W与约800W之间,并且用于偏置等离子体的偏置功率在约30W与约100W之间。在间隔件材料106是氧化硅材料的其它实施方式中,使用稀HF湿法蚀刻工艺。
在一个实施方式中,用于执行蚀刻工艺的合适的装置是可从加利福尼亚州圣克拉拉市应用材料公司(Applied Materials,Inc.,Santa Clara,CA)获得的CENTRISTMSYM3TM蚀刻装置。可设想,根据本文描述的实施方式,也可以利用来自其它制造商的其它适当配置的装置。间隔件移除工艺将间隔件材料106选择性地移除到硬掩模材料104和基板102,从而将硬掩模材料104留在基板102上。
第一心轴结构202形成在图1中所示的暴露区域114中。第一心轴结构202沉积在基板的表面206上,并且第一心轴结构202从基板102的表面206生长。在一个实施方式中。用于执行第一心轴结构沉积的合适装置是可从加利福尼亚州圣克拉拉市应用材料公司获得的RP EPI装置。可设想,根据本文描述的实施方式,也可以使用来自其它制造商的其它适当配置的装置。通过图案化硬掩模材料104和空间210将第一心轴结构202中的每一个心轴结构与相邻的第一心轴结构202分开。将第一心轴结构202生长为使得第一心轴结构202的顶表面208在基板102的表面206上方的距离204处或大于约80nm处。在一个实施方式中,距离204在约100nm与约200nm之间。
在一个实施方式中,通过外延沉积工艺在基板102上形成第一心轴结构202。在一个实施方式中,以交替方式脉冲含镓前驱物和含砷前驱物以沉积第一心轴结构202。在此实施方式中,含镓前驱物是三甲基镓并且含砷前驱物是AsH3。在此实施方式中,在被保持在约1托与约10托之间的压力和约450℃与约800℃之间的温度的环境中制造第一心轴结构202。外延沉积工艺利用逐层沉积技术,据信,当第一心轴结构202从表面206且在硬掩模材料104上方继续生长时,所述逐层沉积技术保持第一心轴结构202的基本上竖直的取向。
在一个实施方式中,第一心轴结构202由III-V材料形成。例如,第一心轴结构202由以下材料中的一种或多种材料形成:锑化铝、砷化铝、砷化铝镓、磷化铝镓铟、氮化铝镓、磷化铝镓、砷化铝铟、氮化铝、磷化铝、砷化硼、氮化硼、磷化硼、锑化镓、砷化镓、磷砷化镓、磷化镓、锑化铟、砷化铟、砷化铟镓,氮化铟镓、磷化铟镓、氮化铟和磷化铟等。。
在操作830处,间隙填充材料302沉积在基板102上的硬掩模材料104和第一心轴结构202之上。图3示出了根据本文描述的实施方式的图2的基板102的局部截面图,其中在基板102上将间隙填充材料302形成在硬掩模材料104和第一心轴结构202之上。沉积间隙填充材料302,以使得间隙填充材料填充空隙210并被沉积到超过第一心轴结构202的顶表面208的厚度。在一个实施方式中,用于执行间隙填充沉积工艺的合适装置是可从加利福尼亚州圣克拉拉市应用材料公司获得的ETERNATMFCVDTM装置。可设想,根据本文描述的实施方式,也可以利用来自其它制造商的适当配置的装置。
在一个实施方式中,间隙填充材料是可流动材料。可流动材料具有固体材料的特性,但是也具有“流动”的能力,因此能够实现基本上无空隙的自底向上的材料沉积。在一个实施方式中,通过可流动化学气相沉积(CVD)工艺来沉积间隙填充材料302。在一个示例中,利用CVD工艺来沉积含有间隙填充材料302的可流动氧化硅。在此实施方式中,依次沉积、固化和退火氧化硅材料。在另一个示例中,利用CVD工艺来沉积氮化硅间隙填充材料302。在此实施方式中,依次沉积氮化硅材料并使氮化硅材料经受氮化等离子体处理。在另一个实施方式中,间隙填充材料302通过旋涂玻璃(SOG)工艺形成。在此实施方式中,间隙填充材料302是含氧化物的材料,诸如二氧化硅等。
在操作840处,间隙填充材料被平面化。图4示出了根据本文描述的实施方式的在间隙填充材料302的平面化之后的图3的基板102的局部截面图。在一个实施方式中,通过化学机械抛光工艺来执行间隙填充材料302的平面化。在另一个实施方式中,通过蚀刻工艺来执行间隙填充材料302的平面化。
间隙填充材料302被移除到间隙填充材料302的顶表面402与第一心轴结构202的顶表面208基本上平面的点。在一个实施方式中,可设想,利用第一心轴结构202作为移除点。在另一个实施方式中,使间隙填充材料302经受基于时间的蚀刻工艺以使表面402、208平面化。
在操作850处,移除第一心轴结构202以形成包括了硬掩模材料104和间隙填充材料302的第二心轴结构500。图5示出了根据本文描述的实施方式的图4的基板102的局部截面图,其中第一心轴结构202被移除以形成第二心轴结构500。利用选择性蚀刻工艺移除第一心轴结构202。例如,利用对III-V材料选择性的蚀刻化学物质将第一芯轴结构202选择性移除到含有氧化物和/或氮化物的间隙填充材料302和硬掩模材料104。
在一个实施方式中,含氯前驱物(诸如HCl)与含氢前驱物(诸如H2)一起被输送到工艺环境。利用惰性载气(诸如N2或Ar)将前驱物输送到工艺环境。在一个示例中,以约1sccm至约500sccm之间的流率将HCl输送到工艺环境。工艺环境的温度保持在约300℃至约700℃之间,并且工艺环境的压力保持在约0托至约100托之间。
移除第一心轴结构202导致在相邻的第二心轴结构500之间形成空间502。空间502还暴露了基板102的顶表面206的第二区域。第二心轴结构500的高度与距离204相似,例如基本上等于距离204。
在操作860处,使用第二心轴结构500作为掩模将鳍片结构602沉积在基板102上。图6示出了根据本文描述的实施方式的在基板102上形成鳍片结构602之后的图5的基板102的局部截面图。鳍片结构602在表面206上方延伸大于约80nm(诸如在约100nm至约200nm之间)的第二距离606。在一个实施方式中,通过外延沉积工艺形成鳍片结构602。在此实施方式中,用于形成鳍片结构602的材料与用于形成基板102的材料相同。在其它实施方式中,用于形成鳍片结构的材料包括含硅材料、含锗材料、含硅锗材料和III-V材料等。例如,以交替方式来活化和脉冲二氯硅烷前驱物和GeH4前驱物,从而沉积硅锗材料以作为鳍片结构602。
鳍片结构602延伸第二距离606,使得鳍片结构602的顶表面604与间隙填充材料302的顶表面402基本上共面。通过利用第二心轴结构500作为掩模或模具/限制结构中,据信,由于第二心轴结构500的硬掩模材料104和间隙填充材料302的改进的竖直度,所以鳍片结构602呈现改进的竖直度轮廓。第二心轴结构500也被认为减少鳍片结构602在形成期间的横向生长并还可以减少鳍片结构602内不期望的小面形成。
在操作870处,蚀刻第二心轴结构500的间隙填充材料302以暴露鳍片结构602。图7示出了根据本文描述的实施方式的在蚀刻间隙填充材料302之后的图6的基板102的局部截面图。在一个实施方式中,间隙填充材料302的顶表面402从鳍片结构的顶表面604凹陷大于约80nm(诸如在约100nm至约200nm之间)的第三距离704。通过选择性蚀刻来工艺蚀刻间隙填充材料302,所述选择性蚀刻工艺优先蚀刻到间隙填充材料302的氧化物或氮化物材料。在一个实施方式中,可从加利福尼亚州圣克拉拉市应用材料公司获得的工艺用于蚀刻间隙填充材料302。
在使间隙填充材料302凹陷以暴露鳍片结构602之后,可以执行后续半导体处理操作。可设想,第二心轴结构500的剩余部分可以保持设置在基板102上以提供鳍片隔离或者第二心轴结构500的剩余部分可以被移除,这取决于所期望的设备实现方式。
总之,改进的掩模形成和蚀刻工艺流程提供了用于制造先进半导体器件的自底向上的鳍片形成。通过减小间隔件材料高度并通过增加掩模高度(即第一心轴结构和第二心轴结构),可以实现改进的蚀刻竖直度。还相信,通过利用本文描述的工艺流程,可以改进掩模的侧壁竖直度(第一心轴结构和第二心轴结构),这产生了所期望的蚀刻竖直度特性。因此,更有效地对侧壁(横向生长)进行控制并且还减小了边缘粗糙度。
虽然上述内容针对本公开内容的实施方式,但是可以在不脱离本公开内容的基本范围的情况下设计本公开内容的其它和进一步的实施方式,并且本公开内容的范围由所附权利要求书确定。

Claims (20)

1.一种基板处理方法,包括:
在基板上形成图案化硬掩模材料;
在所述基板的暴露的第一区域上形成第一心轴结构;
将间隙填充材料沉积在所述硬掩模材料和所述第一心轴结构上;
移除所述第一心轴结构以暴露所述基板的第二区域并形成第二心轴结构,所述第二心轴结构包括所述硬掩模材料和所述间隙填充材料;和
使用所述第二心轴结构作为掩模在所述基板的所述第二区域上形成鳍片结构。
2.如权利要求1所述的方法,进一步包括:
将间隔件材料沉积在所述硬掩模材料上并将所述间隔件材料图案化,其中所述间隔件材料图案被转移到所述硬掩模材料以形成所述图案化硬掩模材料。
3.如权利要求2所述的方法,其特征在于,所述将所述间隔件材料图案化包括执行自对准双重图案化工艺、自对准四重图案化工艺或定向自组装工艺。
4.如权利要求1所述的方法,进一步包括:
在形成所述鳍片结构之后蚀刻所述间隙填充材料。
5.如权利要求1所述的方法,其特征在于,所述形成所述鳍片结构包括在所述基板的所述第二区域上外延沉积选自由以下材料组成的组中的材料:含硅材料、含锗材料、含硅锗材料和III-V材料。
6.如权利要求1所述的方法,进一步包括:
在移除所述第一心轴结构之前,执行化学机械抛光工艺以将所述间隙填充材料平面化。
7.如权利要求1所述的方法,其特征在于,所述硬掩模材料是氧化硅材料或氮化硅材料。
8.如权利要求1所述的方法,其特征在于,所述形成所述第一心轴结构包括在所述基板的所述暴露区域上外延沉积III-V材料。
9.如权利要求8所述的方法,其特征在于,所述第一心轴结构由GaAs材料形成。
10.如权利要求1所述的方法,其特征在于,沉积所述间隙填充材料包括执行化学气相沉积工艺。
11.如权利要求10所述的方法,其特征在于,执行所述化学气相沉积工艺包括沉积可流动氧化硅材料或可流动氮化硅材料。
12.如权利要求1所述的方法,其特征在于,沉积所述间隙填充材料包括沉积通过旋涂玻璃工艺沉积的含氧化物材料。
13.如权利要求1所述的方法,其特征在于,所述第一心轴结构在所述基板的顶表面上方延伸大于约80nm的第一距离。
14.如权利要求13所述的方法,其特征在于,所述第一距离在约100nm与约200nm之间。
15.如权利要求13所述的方法,其特征在于,所述第二心轴结构在所述基板的顶表面上方延伸第二距离,所述第二距离近似等于所述第一距离。
16.一种基板处理方法,包括:
在基板上形成硬掩模材料;
将间隔件材料沉积在所述硬掩模材料上;
将所述间隔件材料图案化;
通过蚀刻所述硬掩模材料以暴露所述基板的区域,从而将所述间隔件材料的所述图案转移到所述硬掩模材料;
在所述基板的所述暴露区域上形成第一心轴结构;
将间隙填充材料沉积在所述硬掩模材料和所述第一心轴结构上;
移除所述第一心轴结构以暴露所述基板的第二区域并形成第二心轴结构,所述第二心轴结构包括所述硬掩模材料和所述间隙填充材料;
使用所述第二心轴结构作为掩模在所述第二区域上形成鳍片结构;和
使所述间隙填充材料在所述鳍片结构的顶表面下方凹陷。
17.如权利要求16所述的方法,其特征在于,通过外延沉积工艺形成所述鳍片结构。
18.如权利要求16所述的方法,其特征在于,所述鳍片结构由选自由以下材料组成的组中的材料形成:含硅材料、含锗材料、含硅锗材料和III-V材料。
19.如权利要求16所述的方法,其特征在于,所述间隙填充材料从所述鳍片结构的所述顶表面凹陷大于约80nm的距离。
20.一种基板处理方法,包括:
在基板上形成图案化硬掩模材料;
在所述基板的暴露区域上形成III-V材料第一心轴结构,其中所述III-V材料第一心轴结构在所述基板的顶表面上方延伸大于约80nm的第一距离;
将可流动氧化物间隙填充材料沉积在所述硬掩模材料和所述III-V材料第一心轴结构上;
移除所述III-V材料第一心轴结构以暴露所述基板的第二区域并形成第二心轴结构,所述第二心轴结构包括所述硬掩模材料和所述可流动氧化物间隙填充材料,其中所述第二心轴结构在所述基板的所述顶表面上方延伸第二距离,所述第二距离近似等于所述第一距离;
在所述基板的所述第二区域上外延沉积鳍片结构;和
在形成所述鳍片结构之后蚀刻所述间隙填充材料。
CN201910116287.7A 2018-02-14 2019-02-13 用于自底向上鳍片结构形成的方法 Pending CN110164973A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/896,839 US10204781B1 (en) 2018-02-14 2018-02-14 Methods for bottom up fin structure formation
US15/896,839 2018-02-14

Publications (1)

Publication Number Publication Date
CN110164973A true CN110164973A (zh) 2019-08-23

Family

ID=65241821

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910116287.7A Pending CN110164973A (zh) 2018-02-14 2019-02-13 用于自底向上鳍片结构形成的方法

Country Status (6)

Country Link
US (2) US10204781B1 (zh)
EP (1) EP3528290A3 (zh)
JP (1) JP2019140395A (zh)
KR (1) KR20190098715A (zh)
CN (1) CN110164973A (zh)
TW (1) TW201935527A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10204781B1 (en) * 2018-02-14 2019-02-12 Applied Materials, Inc. Methods for bottom up fin structure formation
US11482411B2 (en) * 2020-06-30 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3540633B2 (ja) 1998-11-11 2004-07-07 株式会社東芝 半導体装置の製造方法
US6864164B1 (en) 2002-12-17 2005-03-08 Advanced Micro Devices, Inc. Finfet gate formation using reverse trim of dummy gate
US6855582B1 (en) 2003-06-12 2005-02-15 Advanced Micro Devices, Inc. FinFET gate formation using reverse trim and oxide polish
US7018551B2 (en) 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7470570B2 (en) 2006-11-14 2008-12-30 International Business Machines Corporation Process for fabrication of FinFETs
US7772048B2 (en) 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
JP5731858B2 (ja) 2011-03-09 2015-06-10 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体装置及び半導体装置の製造方法
US8637359B2 (en) 2011-06-10 2014-01-28 International Business Machines Corporation Fin-last replacement metal gate FinFET process
US8669186B2 (en) 2012-01-26 2014-03-11 Globalfoundries Inc. Methods of forming SRAM devices using sidewall image transfer techniques
CN103855009B (zh) 2012-11-30 2017-06-13 中国科学院微电子研究所 鳍结构制造方法
US8828839B2 (en) 2013-01-29 2014-09-09 GlobalFoundries, Inc. Methods for fabricating electrically-isolated finFET semiconductor devices
US8975155B2 (en) * 2013-07-10 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a shallow trench isolation structure
CN104347421A (zh) 2013-08-07 2015-02-11 中芯国际集成电路制造(北京)有限公司 鳍式场效应管的形成方法
US9564361B2 (en) 2013-09-13 2017-02-07 Qualcomm Incorporated Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
US9245882B2 (en) 2013-09-27 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with gradient germanium-containing channels
US8993419B1 (en) 2013-10-03 2015-03-31 Applied Materials, Inc. Trench formation with CD less than 10 NM for replacement Fin growth
US9023705B1 (en) 2013-11-01 2015-05-05 Globalfoundries Inc. Methods of forming stressed multilayer FinFET devices with alternative channel materials
US9412603B2 (en) 2013-11-19 2016-08-09 Applied Materials, Inc. Trimming silicon fin width through oxidation and etch
US9224654B2 (en) 2013-11-25 2015-12-29 International Business Machines Corporation Fin capacitor employing sidewall image transfer
US20150187909A1 (en) * 2013-12-30 2015-07-02 Global Foundries, Inc. Methods for fabricating multiple-gate integrated circuits
US9252208B1 (en) 2014-07-31 2016-02-02 Stmicroelectronics, Inc. Uniaxially-strained FD-SOI finFET
US9209279B1 (en) 2014-09-12 2015-12-08 Applied Materials, Inc. Self aligned replacement fin formation
US9530637B2 (en) 2014-10-05 2016-12-27 Applied Materials, Inc. Fin structure formation by selective etching
US10096524B1 (en) * 2017-10-18 2018-10-09 International Business Machines Corporation Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors
US10204781B1 (en) * 2018-02-14 2019-02-12 Applied Materials, Inc. Methods for bottom up fin structure formation

Also Published As

Publication number Publication date
KR20190098715A (ko) 2019-08-22
JP2019140395A (ja) 2019-08-22
US10741393B2 (en) 2020-08-11
EP3528290A3 (en) 2019-12-18
US20190252187A1 (en) 2019-08-15
US10204781B1 (en) 2019-02-12
TW201935527A (zh) 2019-09-01
EP3528290A2 (en) 2019-08-21

Similar Documents

Publication Publication Date Title
US8017463B2 (en) Expitaxial fabrication of fins for FinFET devices
JP6723227B2 (ja) 自己整合代替フィン形成
JP5532303B2 (ja) 半導体デバイスのクリティカルディメンジョンを縮小する方法
US9437443B2 (en) Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides
CN109427870A (zh) 半导体结构及其形成方法
US10181401B1 (en) Method for manufacturing a semiconductor device
US20150035064A1 (en) Inverse side-wall image transfer
TW201639011A (zh) 鰭式場效電晶體與其製造方法
JP5008786B2 (ja) プレーナ・ヘテロ構造の製造方法
CN102214676A (zh) 包含鳍片的半导体结构及其制造方法
CN110164973A (zh) 用于自底向上鳍片结构形成的方法
TW202215494A (zh) 半導體結構的製造方法
US11935838B2 (en) Method and system for fabricating fiducials using selective area growth
KR102425110B1 (ko) 적층된 층을 형성하는 방법 및 그에 의해 형성된 소자
CN111261593A (zh) 半导体器件及其形成方法
CN108091553B (zh) 掩模图形的形成方法
US20210296438A1 (en) Vertically stacked fin semiconductor devices
KR102360542B1 (ko) 게이트 형성 공정
CN110164763A (zh) 用于蚀刻掩模和鳍片结构形成的方法
CN111261507B (zh) 用于制造半导体布置的方法
KR102448769B1 (ko) 반도체 장치 및 제조 방법
CN115346875A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190823

WD01 Invention patent application deemed withdrawn after publication