TWI690004B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

Info

Publication number
TWI690004B
TWI690004B TW108137562A TW108137562A TWI690004B TW I690004 B TWI690004 B TW I690004B TW 108137562 A TW108137562 A TW 108137562A TW 108137562 A TW108137562 A TW 108137562A TW I690004 B TWI690004 B TW I690004B
Authority
TW
Taiwan
Prior art keywords
conductive
insulating block
conductive blocks
insulating
block
Prior art date
Application number
TW108137562A
Other languages
English (en)
Other versions
TW202111828A (zh
Inventor
陳子平
林昆賢
莊哲豪
曾奕銘
Original Assignee
晶焱科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 晶焱科技股份有限公司 filed Critical 晶焱科技股份有限公司
Application granted granted Critical
Publication of TWI690004B publication Critical patent/TWI690004B/zh
Publication of TW202111828A publication Critical patent/TW202111828A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明係揭露一種半導體封裝，其係包含一內連接基板、一絕緣膠、一暫態電壓抑制晶片、至少一第一導電線與至少一第二導電線。內連接基板包含一底層與一頂層，底層包含二第一導電區塊及其之間的一第一絕緣區塊，頂層包含二第二導電區塊及其之間的一第二絕緣區塊。所有第二導電區塊分別設於所有第一導電區塊上，第二絕緣區塊設於第一絕緣區塊上。絕緣膠設於第二絕緣區塊上。暫態電壓抑制晶片設於絕緣膠上，且並未重疊第二導電區塊。第一導電線與第二導電線分別電性連接所有第二導電區塊，又皆電性連接暫態電壓抑制晶片。

Description

半導體封裝
本發明係關於一種封裝結構，且特別關於一種半導體封裝。
因為積體電路裝置縮小到奈米等級，所以一些電子產品，如筆記型電腦或手機亦作的比以前更加輕薄短小，對靜電放電（ESD）衝擊的承受能力更為降低。對於這些電子產品，若沒有利用適當的ESD保護裝置來進行保護，則電子產品很容易受到ESD的衝擊，而造成電子產品發生系統重新啟動，甚至硬體受到傷害而無法復原的問題。目前，所有的電子產品都被要求能通過IEC 61000-4-2標準之ESD測試需求。對於電子產品的ESD問題，使用暫態電壓抑制器（TVS）是較為有效的解決方法，讓ESD能量快速透過TVS予以釋放，避免電子產品受到ESD的衝擊而造成傷害。
為了節省印刷電路板之面積，半導體封裝，例如DFN1006或DFN0603，被設計地盡可能微小化。在先前技術中，許多暫態電壓抑制晶片封裝在引腳上晶片(COL)封裝中，以達到微小化之目的。如第1圖所示，COL封裝包含二導線架10、一絕緣膠12、一暫態電壓抑制晶片14與二接合導線16。暫態電壓抑制晶片14經由絕緣膠12設於導線架10上，並經由接合導線16電性連接導線架10。暫態電壓抑制晶片14本身具有一寄生電容C chip。導線架10形成一寄生電容C LF。暫態電壓抑制晶片14與導線架10形成二寄生電容C OL。因此，COL封裝之總電容C total= C chip+ C LF+ C OL×C OL/( C OL+C OL)。換句話說，被封裝的暫態電壓抑制晶片14之電容遠大於暫態電壓抑制晶片14本身之電容。
因此，本發明係在針對上述的困擾，提出一種半導體封裝，以解決習知所產生的問題。
本發明的主要目的，在於提供一種半導體封裝，其係增加介於暫態電壓抑制晶片與內連接基板之導電部分之間的距離，以大幅減少暫態電壓抑制晶片與內連接基板形成的寄生電容。
為達上述目的，本發明提供一種半導體封裝，其係包含一內連接基板，其包括一底層和一頂層，底層包括二第一導電區塊和位於所有第一導電區塊之間的一第一絕緣區塊，頂層包括二第二導電區塊和位於所有第二導電區塊之間的一第二絕緣區塊，所有第二導電區塊分別設於所有第一導電區塊上，第二絕緣區塊設於第一絕緣區塊上；一絕緣膠，設於第二絕緣區塊上；一暫態電壓抑制晶片，設於絕緣膠上，且並未重疊所有第二導電區塊；以及至少一第一導電線與至少一第二導電線，其係分別電性連接第二導電區塊，第一導電線與第二導電線電性連接暫態電壓抑制晶片。
在本發明之一實施例中，第一絕緣區塊之寬度短於第二絕緣區塊之寬度，暫態電壓抑制晶片重疊每一第一導電區塊之一部分。
在本發明之一實施例中，內連接基板更包含至少一中間層，其係設於頂層與底層之間，中間層包括二第三導電區塊與位於所有第三導電區塊之間的一第三絕緣區塊，第一絕緣區塊之寬度短於第三絕緣區塊之寬度，所有第三導電區塊分別設於所有第一導電區塊上，所有第二導電區塊分別設於所有第三導電區塊上，第三絕緣區塊設於所有第一導電區塊與第一絕緣區塊上，第二絕緣區塊設於第三絕緣區塊上，暫態電壓抑制晶片位於第三絕緣區塊之上方，且並未重疊所有第三導電區塊。
在本發明之一實施例中，第三絕緣區塊之寬度大於第二絕緣區塊之寬度。
在本發明之一實施例中，絕緣膠重疊每一第一導電區塊之一部分，且並未重疊所有第二導電區塊及所有第三導電區塊。
在本發明之一實施例中，第一絕緣區塊、第二絕緣區塊與第三絕緣區塊之材質為絕緣化合物。
在本發明之一實施例中，內連接基板為模封基板(Molded Interconnect Substrate，MIS)。
在本發明之一實施例中，半導體封裝更包含一封裝膠體，其係包覆暫態電壓抑制晶片、第一導電線與第二導電線。
在本發明之一實施例中，封裝膠體包含矽樹脂或環氧樹脂。
在本發明之一實施例中，第一導電線與第二導電線之材質為金、銀、銅或鋁。
茲為使　貴審查委員對本發明的結構特徵及所達成的功效更有進一步的瞭解與認識，謹佐以較佳的實施例圖及配合詳細的說明，說明如後：
本發明之實施例將藉由下文配合相關圖式進一步加以解說。盡可能的，於圖式與說明書中，相同標號係代表相同或相似構件。於圖式中，基於簡化與方便標示，形狀與厚度可能經過誇大表示。可以理解的是，未特別顯示於圖式中或描述於說明書中之元件，為所屬技術領域中具有通常技術者所知之形態。本領域之通常技術者可依據本發明之內容而進行多種之改變與修改。
於下文中關於“一個實施例”或“一實施例”之描述係指關於至少一實施例內所相關連之一特定元件、結構或特徵。因此，於下文中多處所出現之“一個實施例”或 “一實施例”之多個描述並非針對同一實施例。再者，於一或多個實施例中之特定構件、結構與特徵可依照一適當方式而結合。
以下請參閱第2圖。以下介紹本發明之半導體封裝之第一實施例，此半導體封裝為引腳上晶片（COL）封裝，其係包含一內連接基板18、一絕緣膠20、一暫態電壓抑制晶片22、至少一第一導電線24、至少一第二導電線26與一封裝膠體27。舉例來說，封裝膠體27包含矽樹脂或環氧樹脂。第一導電線24與第二導電線26之材質為金、銀、銅或鋁。在本發明之一實施例中，受限於引腳上晶片封裝之緣故，內連接基板18為模封基板(Molded Interconnect Substrate，MIS)，其係具有1毫米(mm) ×0.3-0.6mm。
內連接基板18包含一底層28與一頂層30。底層28包含二第一導電區塊32與一第一絕緣區塊34，第一絕緣區塊34位於二第一導電區塊32之間。頂層30包含二第二導電區塊36與一第二絕緣區塊38，第二絕緣區塊38位於所有第二導電區塊36之間。第一絕緣區塊34與第二絕緣區塊38之材質為絕緣化合物。所有第二導電區塊36分別設於所有第一導電區塊32上。第二絕緣區塊38設於第一絕緣區塊34上。絕緣膠20設於第二絕緣區塊38上。暫態電壓抑制晶片22具有一寬度L1，寬度L1大於第一絕緣區塊34之寬度L2，並小於第二絕緣區塊38之寬度L3。
暫態電壓抑制晶片22設於絕緣膠20上，且並未重疊所有第二導電區塊36。第一導電線24與第二導電線26分別電性連接所有第二導電區塊36，且皆電性連接暫態電壓抑制晶片22。封裝膠體27包覆暫態電壓抑制晶片22、第一導電線24與第二導電線26。此外，受限於引腳上晶片封裝之外部尺寸，第一絕緣區塊34之寬度L2短於第二絕緣區塊38之寬度L3。暫態電壓抑制晶片22重疊每一第一導電區塊32之一部分。因為絕緣膠20之尺寸等於暫態電壓抑制晶片22之尺寸，絕緣膠20重疊每一第一導電區塊32之一部分，且並未重疊所有第二導電區塊36。所有第二導電區塊36形成一寄生電容C S。暫態電壓抑制晶片22與所有第一導電區塊32形成二寄生電容C CS。與第1圖相較，第二絕緣區塊38之寬度L3較長。因此，寄生電容C S小於第1圖之寄生電容C LF。此外，介於暫態電壓抑制晶片22與頂層30之間的距離小於介於暫態電壓抑制晶片22與底層28之間的距離。因此，寄生電容C CS小於第1圖之寄生電容C OL。由於受到降低後之電容C S、C CS的影響，半導體封裝之總電容是接近暫態電壓抑制晶片22本身之寄生電容。
以下請參閱第3圖。以下介紹本發明之半導體封裝之第二實施例。相較第一實施例，第二實施例之內連接基板18更包含至少一中間層40，其係設於頂層28與底層30之間。中間層40包含二第三導電區塊42與一第三絕緣區塊44。第三絕緣區塊44位於二第三導電區塊42之間。第三絕緣區塊44之材質為絕緣化合物。第一絕緣區塊34之寬度L2短於第三絕緣區塊44之寬度L4。所有第三導電區塊42分別設於所有第一導電區塊32上，所有第二導電區塊36分別設於所有第三導電區塊42上。第三絕緣區塊44設於所有第一導電區塊32與第一絕緣區塊34上。第二絕緣區塊38設於第三絕緣區塊44上，暫態電壓抑制晶片22與絕緣膠20位於第三絕緣區塊44之上方，且並未重疊所有第三導電區塊42。此外，第三絕緣區塊44之寬度L4大於第二絕緣區塊38之寬度L3。與第一實施例相較，中間層40增加介於暫態電壓抑制晶片22與每一第一導電區塊32之間的距離，以降低寄生電容C CS與半導體封裝之總電容。
綜上所述，本發明增加介於暫態電壓抑制晶片與內連接基板之導電部分之間的距離，以大幅減少暫態電壓抑制晶片與內連接基板形成的寄生電容。
以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
10:導線架 12  絕緣膠 14:暫態電壓抑制晶片 16:接合導線 18:內連接基板 20:絕緣膠 22:暫態電壓抑制晶片 24:第一導電線 26:第二導電線 27:封裝膠體 28:底層 30:頂層 32:第一導電區塊 34:第一絕緣區塊 36:第二導電區塊 38:第二絕緣區塊 40:中間層 42:第三導電區塊 44:第三絕緣區塊
第1圖為先前技術之引腳上晶片封裝之示意圖。 第2圖為本發明之半導體封裝之第一實施例之結構剖視圖。 第3圖為本發明之半導體封裝之第二實施例之結構剖視圖。
18:內連接基板
20:絕緣膠
22:暫態電壓抑制晶片
24:第一導電線
26:第二導電線
27:封裝膠體
28:底層
30:頂層
32:第一導電區塊
34:第一絕緣區塊
36:第二導電區塊
38:第二絕緣區塊

Claims (10)

  1. 一種半導體封裝，包含： 一內連接基板，包括一底層和一頂層，該底層包括二第一導電區塊和位於該些第一導電區塊之間的一第一絕緣區塊，該頂層包括二第二導電區塊和位於該些第二導電區塊之間的一第二絕緣區塊，該些第二導電區塊分別設於該些第一導電區塊上，該第二絕緣區塊設於該第一絕緣區塊上； 一絕緣膠，設於該第二絕緣區塊上； 一暫態電壓抑制晶片，設於該絕緣膠上，且並未重疊該些第二導電區塊；以及 至少一第一導電線與至少一第二導電線，其係分別電性連接該些第二導電區塊，該至少一第一導電線與該至少一第二導電線電性連接該暫態電壓抑制晶片。
  2. 如請求項1所述之半導體封裝，其中該第一絕緣區塊之寬度短於該第二絕緣區塊之寬度，該暫態電壓抑制晶片重疊每一該第一導電區塊之一部分。
  3. 如請求項1所述之半導體封裝，其中該內連接基板更包含至少一中間層，其係設於該頂層與該底層之間，該至少一中間層包括二第三導電區塊與位於該些第三導電區塊之間的一第三絕緣區塊，該第一絕緣區塊之寬度短於該第三絕緣區塊之寬度，該些第三導電區塊分別設於該些第一導電區塊上，該些第二導電區塊分別設於該些第三導電區塊上，該第三絕緣區塊設於該些第一導電區塊與該第一絕緣區塊上，該第二絕緣區塊設於該第三絕緣區塊上，該暫態電壓抑制晶片位於該第三絕緣區塊之上方，且並未重疊該些第三導電區塊。
  4. 如請求項3所述之半導體封裝，其中該第三絕緣區塊之寬度大於該第二絕緣區塊之寬度。
  5. 如請求項3所述之半導體封裝，其中該絕緣膠重疊每一該第一導電區塊之一部分，且並未重疊該些第二導電區塊及該些第三導電區塊。
  6. 如請求項3所述之半導體封裝，其中該第一絕緣區塊、該第二絕緣區塊與該第三絕緣區塊之材質為絕緣化合物。
  7. 如請求項1所述之半導體封裝，其中該內連接基板為模封基板(Molded Interconnect Substrate，MIS)。
  8. 如請求項1所述之半導體封裝，更包含一封裝膠體，其係包覆該暫態電壓抑制晶片、該至少一第一導電線與該至少一第二導電線。
  9. 如請求項8所述之半導體封裝，其中該封裝膠體包含矽樹脂或環氧樹脂。
  10. 如請求項1所述之半導體封裝，其中該至少一第一導電線與該至少一第二導電線之材質為金、銀、銅或鋁。
TW108137562A 2019-09-10 2019-10-17 半導體封裝 TWI690004B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/565,874 US20210074621A1 (en) 2019-09-10 2019-09-10 Semiconductor package
US16/565,874 2019-09-10

Publications (2)

Publication Number Publication Date
TWI690004B true TWI690004B (zh) 2020-04-01
TW202111828A TW202111828A (zh) 2021-03-16

Family

ID=69549511

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108137562A TWI690004B (zh) 2019-09-10 2019-10-17 半導體封裝

Country Status (3)

Country Link
US (1) US20210074621A1 (zh)
CN (1) CN110828415B (zh)
TW (1) TWI690004B (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246633A (en) * 2011-05-12 2012-11-16 Siliconware Precision Industries Co Ltd Package structure and method of making same
TW201537785A (zh) * 2014-03-28 2015-10-01 Formosa Microsemi Co Ltd 內建穩壓晶片之覆晶式ｌｅｄ元件
TW201807802A (zh) * 2016-08-23 2018-03-01 萬國半導體（開曼）股份有限公司 通用序列匯流排c型負荷開關的靜電放電保護裝置
TW201838120A (zh) * 2017-04-07 2018-10-16 思鷺科技股份有限公司 封裝結構
WO2019005163A1 (en) * 2017-06-30 2019-01-03 Intel Corporation CAPACITIVE ELECTRODE FOR MEMORY APPLICATIONS AND METHODS OF MANUFACTURE
TW201903906A (zh) * 2017-03-14 2019-01-16 新加坡商星科金朋有限公司 具有雙側成型的系統級封裝

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
KR100828956B1 (ko) * 2006-06-27 2008-05-13 하나 마이크론(주) Ｕｓｂ 메모리 패키지 및 그 제조 방법
CN101882589B (zh) * 2009-05-06 2013-01-16 台湾积体电路制造股份有限公司 集成电路结构的形成方法
TWI418002B (zh) * 2009-12-01 2013-12-01 Xintec Inc 晶片封裝體及其製造方法
US8951833B2 (en) * 2011-06-17 2015-02-10 Wafertech, Llc Defect free deep trench method for semiconductor chip
TWI601250B (zh) * 2011-07-22 2017-10-01 先進封裝技術私人有限公司 用於製造半導體封裝元件之半導體結構及其製造方法
TWI500124B (zh) * 2011-11-29 2015-09-11 Advanpack Solutions Pte Ltd 基板結構、半導體封裝元件及基板結構之製造方法
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
KR20170006944A (ko) * 2015-07-10 2017-01-18 삼성전자주식회사 다중 피치의 복수개의 단위 기판 영역들을 포함하는 기판 구조체
JP6780903B2 (ja) * 2016-12-05 2020-11-04 大口マテリアル株式会社 リードフレーム
US10600743B2 (en) * 2017-11-08 2020-03-24 Inari Semiconductor Labs Sdn Bhd Ultra-thin thermally enhanced electro-magnetic interference shield package
US11322455B2 (en) * 2017-12-18 2022-05-03 Intel Corporation Robust mold integrated substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246633A (en) * 2011-05-12 2012-11-16 Siliconware Precision Industries Co Ltd Package structure and method of making same
TW201537785A (zh) * 2014-03-28 2015-10-01 Formosa Microsemi Co Ltd 內建穩壓晶片之覆晶式ｌｅｄ元件
TW201807802A (zh) * 2016-08-23 2018-03-01 萬國半導體（開曼）股份有限公司 通用序列匯流排c型負荷開關的靜電放電保護裝置
TW201903906A (zh) * 2017-03-14 2019-01-16 新加坡商星科金朋有限公司 具有雙側成型的系統級封裝
TW201838120A (zh) * 2017-04-07 2018-10-16 思鷺科技股份有限公司 封裝結構
WO2019005163A1 (en) * 2017-06-30 2019-01-03 Intel Corporation CAPACITIVE ELECTRODE FOR MEMORY APPLICATIONS AND METHODS OF MANUFACTURE

Also Published As

Publication number Publication date
US20210074621A1 (en) 2021-03-11
CN110828415B (zh) 2021-04-13
CN110828415A (zh) 2020-02-21
TW202111828A (zh) 2021-03-16

Similar Documents

Publication Publication Date Title
US7453153B2 (en) Circuit device
US9406595B2 (en) Semiconductor package
KR20040070020A (ko) 반도체 장치
JP6892360B2 (ja) 半導体装置
KR20140008175A (ko) 멀티 칩 패키지
JP2010103475A (ja) 半導体マルチチップパッケージ
US9997477B2 (en) Method of manufacturing semiconductor package
US7435621B2 (en) Method of fabricating wafer level package
US20050184313A1 (en) Semiconductor device and method for mitigating electrostatic discharge (ESD)
US9105463B2 (en) Semiconductor device
TWI524438B (zh) 具有導線架的積體電路封裝系統及其製造方法
US8809118B2 (en) Chip on leads
TWI690004B (zh) 半導體封裝
US9281243B2 (en) Chip scale package structure and manufacturing method thereof
TWI664683B (zh) 半導體封裝件的製造方法
US11107807B1 (en) IC package having a metal die for ESP protection
US10910349B2 (en) Stacked semiconductor chips having transistor in a boundary region
US7592672B2 (en) Grounding structure of semiconductor device including a conductive paste
JP2004165246A (ja) 半導体装置
JP4536808B2 (ja) 半導体装置およびインターポーザチップ
KR20110001182A (ko) 반도체 패키지의 제조방법
US20220148955A1 (en) Semiconductor package
TWI656612B (zh) 半導體封裝件
TWI411090B (zh) 多晶片堆疊封裝結構
TW202327018A (zh) 電路保護晶片封裝件及其製造方法