TWI669784B - 形成接觸插塞的方法 - Google Patents

形成接觸插塞的方法 Download PDF

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TWI669784B
TWI669784B TW106135929A TW106135929A TWI669784B TW I669784 B TWI669784 B TW I669784B TW 106135929 A TW106135929 A TW 106135929A TW 106135929 A TW106135929 A TW 106135929A TW I669784 B TWI669784 B TW I669784B
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Taiwan
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contact
metal
contact opening
forming
layer
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TW106135929A
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TW201839911A (zh
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王喻生
洪奇成
歐陽良岳
高承遠
邱意為
白岳青
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台灣積體電路製造股份有限公司
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Abstract

形成接觸插塞的方法包含形成層間介電質以覆蓋電晶體的閘極堆疊，層間介電質和閘極堆疊為晶圓的部分。蝕刻層間介電質以形成接觸開口，且經由接觸開口暴露出電晶體的源/汲極區或閘極堆疊內的閘極電極。形成導電蓋層延伸進入接觸開口。使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，含金屬材料具有一部份填入接觸開口，鍍覆溶液的硫含量低於約100ppm。對晶圓進行平坦化製程以移除含金屬材料的過量部分，含金屬材料的剩餘部分和導電蓋層的剩餘部分結合形成接觸插塞。

Description

形成接觸插塞的方法
本發明實施例是關於形成接觸插塞的方法，特別是有關於降低接觸插塞的侵蝕的方法。
在積體電路的製造方法中，接觸插塞係用於連接電晶體的源極和汲極區以及閘極。一般而言，源/汲極接觸插塞係與源/汲極矽化物(silicide)區連接，源/汲極矽化物區的形成包含形成接觸開口以暴露出源/汲極區，沉積金屬層，進行退火以使金屬層與源/汲極區進行反應，在剩餘的接觸開口內填入鎢，以及進行化學機械研磨(chemical mechanical polish，CMP)以移除過量的鎢，然後進行清潔。在化學機械研磨以及後續的清潔製程中，接觸插塞的頂面可能受到凹陷(dishing)和侵蝕(corrosion)。
根據本發明的一些實施例，提供形成接觸插塞的方法。此方法包含形成層間介電質覆蓋電晶體的閘極堆疊，層間介電質和閘極堆疊為晶圓的部分，蝕刻層間介電質以形成接觸開口，且經由接觸開口暴露出電晶體的源/汲極區或閘極堆疊內的閘極電極。此方法還包含形成導電蓋層，導電蓋層延伸進入接觸開口，使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，含金屬材料具有一部分填入接觸開口，且鍍覆溶 液的硫含量低於約100ppm。此方法更包含對晶圓進行平坦化製程以移除含金屬材料的過量部分，含金屬材料的剩餘部分和導電蓋層的剩餘部分結合形成接觸插塞。
根據本發明的一些實施例，提供形成接觸插塞的方法。此方法包含形成層間介電質，以及蝕刻層間介電質以形成第一接觸開口和第二接觸開口，經由第一接觸開口和該第二接觸開口分別暴露出電晶體的源/汲極區和閘極電極。此方法還包含沉積金屬層，金屬層延伸進入第一接觸開口和第二接觸開口，以及沉積導電蓋層，導電蓋層延伸進入第一接觸開口和第二接觸開口。此方法更包含使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，鍍覆溶液實質上不含硫。此外，此方法包含進行平坦化製程以移除含金屬材料的過量部分，含金屬材料的剩餘部分和導電蓋層的剩餘部分形成源/汲極接觸插塞和閘極接觸插塞。
根據本發明的一些實施例，提供形成接觸插塞的方法。此方法包含形成層間介電質，以及蝕刻層間介電質以形成接觸開口，經由接觸開口暴露出電晶體的源/汲極區或閘極電極。此方法還包含沉積金屬層，金屬層延伸進入接觸開口，以及沉積導電蓋層，導電蓋層具有第一部分延伸進入接觸開口以及第二部分與層間介電質重疊。此方法更包含使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，且鍍覆溶液實質上不含硫。此外，此方法包含進行平坦化製程以移除含金屬材料的過量部分，其中含金屬材料的剩餘部分和導電蓋層的剩餘部分結合形成接觸插塞，且接觸插塞的頂面自層間介電質相鄰 的頂面凹陷以形成凹陷。此方法還包含在凹陷內選擇性地形成金屬蓋。
10‧‧‧晶圓
20‧‧‧基底
22‧‧‧源/汲極區
24‧‧‧閘極介電質
26、26A、26B‧‧‧閘極堆疊
28‧‧‧閘極電極
30‧‧‧閘極間隙物
34‧‧‧接觸蝕刻停止層
35‧‧‧虛線
36‧‧‧層間介電質
36A、36B‧‧‧層
38‧‧‧硬遮罩
40‧‧‧源/汲極接觸開口
41‧‧‧閘極接觸開口
43‧‧‧光阻
44、45‧‧‧接觸間隙物
46‧‧‧金屬層
48‧‧‧導電蓋層
50‧‧‧矽化物區
52‧‧‧箭頭
54、56‧‧‧金屬材料
55‧‧‧鍍覆溶液
56A‧‧‧源/汲極接觸插塞
56B‧‧‧閘極接觸插塞
57‧‧‧研磨墊
60‧‧‧凹槽
62‧‧‧金屬蓋
68‧‧‧蝕刻停止層
70‧‧‧介電層
72‧‧‧導電特徵
74‧‧‧導電黏著/阻障層
200‧‧‧製造流程
202、204、206、208、210、212、214、216‧‧‧步驟
D1、D2‧‧‧深度
藉由以下的詳述配合所附圖式，我們能更加理解本發明實施例的內容。需注意的是，根據工業上的標準慣例，許多部件(feature)並未按照比例繪製。事實上，為了能清楚地討論，這些部件的尺寸可能被任意地增加或減少。
第1-9、10A、10B、11A、11B和12圖是根據一些實施例，顯示形成電晶體和接觸插塞的中間階段的剖面示意圖；第13圖是根據一些實施例，顯示電晶體和接觸插塞的剖面示意圖；第14圖是根據一些實施例，顯示形成電晶體的製造流程。
以下提供了很多不同的實施例或範例，用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下，以簡化本發明實施例的說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，以下敘述中提及第一部件形成於第二部件之上或上方，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。此外，本發明實施例在各種範例中可能重複參考數字及/或字母，此重複是為了簡化和清楚，並非在討論的各種實施例及/或組態之間指定其關係。
再者，空間上相關的措辭，例如「在......之下」、 「在......下方」、「下方的」、「在......上方」、「上方的」和其他類似的用語可用於此，使得描述圖中所示之一元件或部件與其他元件或部件之間的關係更容易。此空間上相關的措辭意欲包含除圖式描繪之方向外，使用或操作中的裝置之不同方向。設備可以其他方向定位(旋轉90度或其他定位方向)，且在此使用的空間相關描述可同樣依此解讀。
電晶體具有與源/汲極區和閘極電極電性連接的接觸插塞，且根據各種示範的實施例提供形成接觸插塞的方法。以下說明形成電晶體的中間階段。一些實施例的變化討論如下。在各種示意圖和說明的實施例中，使用相似的參考數字以指出相似的元件。
第1-9、10A、10B、11A、11B和12圖是根據一些實施例，顯示形成電晶體和各個接觸插塞的中間階段的剖面示意圖。第1-9、10A、10B、11A、11B和12圖所繪示的步驟也大致地顯示於第14圖的製造流程200中。參見第1圖，形成晶圓10上的初始結構。晶圓10包含基底20，基底20可由半導體材料製成，例如矽、矽鍺、碳化矽、III-V族化合物半導體材料或其相似物。基底20可為塊狀半導體或絕緣層上覆半導體(semiconductor-on-insulator，SOI)基底。
閘極堆疊26A和26B形成於基底20上，且閘極堆疊26A和26B合稱為閘極堆疊26。根據本發明的一些實施例，閘極堆疊26A和26B係形成為縱向(lengthwise)方向彼此平行的閘極堆疊條狀物(strip)(在晶圓10的上視圖中)。閘極堆疊26A和26B各自可包含閘極介電質24、閘極介電質24上的閘極電極28 以及閘極電極28上的硬遮罩38。根據本發明的一些實施例，閘極堆疊26為替代閘極堆疊，其形成方法係藉由形成虛設閘極堆疊(未繪示)，移除虛設閘極堆疊以形成凹槽，以及在凹槽內形成替代閘極。結果，閘極介電質24各自包含一底部部分位於相應的閘極電極28之下，以及包含側壁部分在相應的閘極電極28的側壁上。側壁部分形成環繞各自的閘極電極28的環。
根據本發明的一些實施例，形成延伸進入基底20的源極和汲極區22(以下以源/汲極區22表示)，且源/汲極區22係形成於接觸蝕刻停止層(contact etch stop layer，CESL)34、層間介電質(inter-layer dielectric，ILD)36和其中之接觸開口的形成之前。根據一些其他的實施例，源/汲極區22係形成於如第2圖所示之接觸開口的形成之後。一或多個源/汲極區22可為與相鄰的閘極堆疊(包含26A和26B)共同使用的共用源極區或共用汲極區。因此，閘極堆疊26A可與位於閘極堆疊26A兩側的源/汲極區22結合形成第一電晶體，且閘極堆疊26B可與位於閘極堆疊26B兩側的源/汲極區22結合形成第二電晶體。第一電晶體和第二電晶體可以並聯的形式電性連接，以作為單一電晶體。
閘極介電質24可為單一層或包含複數層的複合層。舉例而言，閘極介電質24可包含界面氧化層和位於氧化層上的高介電常數(high-k)介電層。氧化層可為藉由熱氧化法或化學氧化法形成的氧化矽層。高介電常數介電層可具有大於7的介電常數值，或甚至大於20。高介電常數介電材料可包含例如氧化鉿、氧化鋯、氧化鑭及其相似物。
根據本發明的一些實施例，每一個閘極電極28具有一個由均質的(homogengous)導電材料形成的單層結構。根據一些其他的實施例，每一個閘極電極28具有一個包含複數層由TiN、TaSiN、WN、TiAl、TiAlN、TaC、TaN、鋁或前述之合金形成的複合結構。閘極電極28的形成可包含物理氣相沉積法(physical vapor deposition，PVD)、金屬有機化學氣相沉積法(metal-organic chemical vapor deposition，MOCVD)及/或其他合適的方法。舉例而言，硬遮罩38可由氮化矽或氮氧化矽形成。
根據本發明一些其他的實施例，閘極堆疊26A和26B並非作為替代閘極堆疊，閘極堆疊26A和26B係由沉積披覆(blanket)閘極介電層和披覆閘極電極層(例如多晶矽層)，然後將披覆閘極介電層和披覆閘極電極層圖案化以形成。
再參見第1圖，形成覆蓋基底20的接觸蝕刻停止層(CESL)34，且接觸蝕刻停止層34可延伸至閘極間隙物30的側壁上。根據本發明的一些實施例，接觸蝕刻停止層34係由氮化矽、碳化矽或其他介電材料製成。層間介電質(ILD)36(或稱為ILD0 36)係形成於接觸蝕刻停止層34以及閘極堆疊26A和26B上。層間介電質36可由氧化物製成，例如磷矽酸鹽玻璃(phosphor-silicate glass，PSG)、硼矽酸鹽玻璃(boron-silicate glass，BSG)、硼磷矽酸鹽玻璃(boron-doped phosphor-silicate glass，BPSG)、四乙氧基矽烷(tetraethyl orthosilicate，TEOS)氧化物或其相似物。形成方法可包含例如化學氣相沉積法(CVD)、流動式化學氣相沉積法(flowable CVD，FCVD)、旋轉 塗佈(spin-on coating)或其相似的方法。層間介電質36可包含頂面齊平於閘極堆疊26A和26B之頂面的第一層，且閘極堆疊26A和26B為形成於第一層內的替代閘極。層間介電質36可更包含形成於第一層上的第二層，且第二層係形成於閘極堆疊26A和26B的形成之後。第一和第二層可由相同的材料或不同的材料製成，且兩者之間可具有明顯的界面或不具有明顯的界面。
參見第2圖，蝕刻層間介電質36和接觸蝕刻停止層34以形成源/汲極接觸開口40。相應的步驟顯示於第14圖的製造流程200中的步驟202。源/汲極區22(若已形成)由源/汲極接觸開口40所暴露出來。蝕刻為異向性(anisotropic)，因此使得源/汲極接觸開口40的側壁實質上為垂直的。
根據一些實施例，其中源/汲極區22在此階段仍未形成，可進行預先非晶向化植入(pre-amorphization implantation，PAI)和源/汲極植入以形成源/汲極區22，為了形成源/汲極區22，預先非晶向化植入(PAI)的植入物種類以及植入的雜質係藉由源/汲極接觸開口40植入基底20。預先非晶向化植入的實施可使用鍺、矽或其相似物，破壞植入區的晶格結構以控制接續之源/汲極植入的深度。若相應的電晶體為P型電晶體，則源/汲極植入的實施可使用硼或銦，若相應的電晶體為N型電晶體，則源/汲極植入的實施可使用磷、砷或銻。
根據一些實施例，層間介電質36係由均質的介電材料形成。根據一些其他的實施例，如第2圖所示，繪製虛線35以顯示層間介電質36可包含層36A和位於層36A上的層36B。層36A和36B皆為介電層。層36B可由不同於層36A之材料的介 電材料製成。舉例而言，層36A和層36B皆可由選自於與形成層間介電質36的候選介電材料相同群組的材料製成，例如磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽酸鹽玻璃(BPSG)和四乙氧基矽烷(TEOS)，且層36A和層36B可選擇不同材料。在後續的形成方法中可移除層36B，故層36B係作為犧牲層使用。
根據本發明的一些實施例，第3圖顯示介電接觸(插塞)間隙物44的形成。一些其他的實施例中，並未形成介電接觸間隙物44(或稱為接觸間隙物44)。接觸間隙物44的形成可包含沉積一或複數個共形(conformal)的介電層。介電層延伸進入源/汲極接觸開口40，且包含位於層間介電質36的側壁上的垂直部分，以及位於源/汲極接觸開口40之底部和層間介電質36上方的水平部分。沉積製程係使用共形的沉積製程以進行，例如原子層沉積法(atomic layer deposition，ALD)、化學氣相沉積法(CVD)或其相似的方法，使得沉積層的水平部分和垂直部分具有相似的厚度。然後進行異向性蝕刻以移除介電層的水平部分，留下垂直部分作為接觸間隙物44。異向性蝕刻的實施係使用氨(NH3)和三氟化氮(NF3)為蝕刻氣體。值得注意的是，在晶圓10的上視圖中，同一源/汲極接觸開口40內的接觸間隙物44為一整體間隙環(spacer ring)的部分。
根據本發明的一些實施例，接觸間隙物44係由相對於氧化物具有較高蝕刻選擇性的介電材料所製成，因此，在後續的清潔製程(移除氧化物)中，使得接觸間隙物44不會受到損壞。舉例而言，接觸間隙物44可由氮化矽、碳氧化矽、氮氧 化矽或其相似物所製成。
參見第4圖，在層間介電質36上方形成微影(lithography)遮罩，例如光阻43。光阻43填入源/汲極接觸開口40(如第3圖所示)，然後將光阻43圖案化。使用光阻43為蝕刻遮罩，進行蝕刻製程以蝕刻層間介電質36，進而形成閘極接觸開口41。相應的步驟顯示於第14圖的製造流程200中的步驟204。接著蝕刻硬遮罩38，閘極接觸開口41延伸進入兩側的閘極間隙物30之間的空間。閘極電極28(或者閘極介電質24)因此由閘極接觸開口41所暴露出來。根據本發明的一些實施例，閘極接觸開口41的形成包含蝕刻穿過層間介電質36的異向性蝕刻，以及蝕刻硬遮罩38的等向性蝕刻(乾式蝕刻)或異向性蝕刻(乾式蝕刻或濕式蝕刻)。在蝕刻之後，閘極間隙物30的側壁可由閘極接觸開口41所暴露出來或不由閘極接觸開口41所暴露出來。
根據一些實施例，如第5圖所示，在閘極接觸開口41內形成接觸間隙物45。一些其他的實施例中省略了接觸間隙物45的形成。接觸間隙物45可由選自於與形成接觸間隙物44的候選材料相同群組之材料製成。接觸間隙物44和45可由相同材料或不同材料製成。根據一些實施例，接觸間隙物44和45在不同的製程中形成，各自形成於相應的源/汲極接觸開口40或閘極接觸開口41的形成之後。根據一些其他的實施例，接觸間隙物44和45的形成皆在源/汲極接觸開口40和閘極接觸開口41的形成之後，且接觸間隙物44和45係由共同的製程所形成，其中包含沉積披覆介電層，然後對披覆介電層進行異向性蝕刻。接觸間隙物44和45的任一者或兩者的形成也可省略，後續形成的 接觸插塞將與層間介電質36接觸。
接著，參見第6圖，沉積金屬層46。相應的步驟顯示於第14圖的製造流程200中的步驟206。根據本發明的一些實施例，金屬層46為鈦(Ti)層，且可使用物理氣相沉積法(PVD)形成。金屬層46包含位於源/汲極接觸開口40之底部的底部部分，以及在層間介電質36的側壁表面上的側壁部分。金屬層46有兩個功用。第一個功用是金屬層46的底部部分可與在其之下的源/汲極區22進行反應，以形成源/汲極矽化物區。第二個功用是金屬層46可作為後續形成之蓋層的黏著層。
在其他的實施例中，在不同的製程中填充源/汲極接觸開口40和閘極接觸開口41，且金屬層46係填入源/汲極接觸開口40，而非填入閘極接觸開口41。然而，根據這些實施例，後續形成之導電蓋層48和金屬材料54仍皆填入源/汲極接觸開口40和閘極接觸開口41兩者。
參見第7圖，沉積導電蓋層48(或稱為蓋層48)。相應的步驟顯示於第14圖的製造流程200中的步驟208。蓋層48也作為擴散阻障(barrier)層。根據本發明的一些實施例，蓋層48係由金屬氮化物製成，例如氮化鈦。蓋層48的形成可使用物理氣相沉積法(PVD)、化學氣相沉積法(CVD)或其相似的方法。
第8圖顯示形成源/汲極矽化物區50(或稱為矽化物區50)的矽化(silicidation)製程。根據本發明的一些實施例，藉由退火，如箭頭52所示，以進行矽化製程。相應的步驟顯示於第14圖的製造流程200中的步驟210。藉由快速熱退火(rapid thermal anneal，RTA)、爐(furnace)退火或其相似的方法以進行 退火。因此，金屬層46的底部部分與源/汲極區22進行反應以形成矽化物區50。在矽化製程之後，留下金屬層46的側壁部分。根據本發明的一些實施例，金屬層46的底部部分係完全反應，且矽化物區50的頂面接觸蓋層48的底面。
接著，在剩餘的源/汲極接觸開口40內和閘極接觸開口41內填入金屬材料54，使得結果產生的晶圓10如第9圖所示。相應的步驟顯示於第14圖的製造流程200中的步驟212。金屬材料54可由含鈷材料或含鎢材料製成，且可藉由純的或實質上純的鎢或鈷(例如原子百分比大於約95%)製成。
根據本發明的一些實施例，金屬材料54的形成係藉由電化學鍍(electrochemical plating，ECP)以進行。在進行電化學鍍(ECP)的期間，鍍覆溶液(如55所示)接觸晶圓10，且藉由鍍覆溶液55通入電流。舉例而言，藉由將晶圓10浸沒於鍍覆溶液55中以進行鍍覆(plating)。根據一些實施例，鍍覆溶液55具有含金屬的化學物質，例如硼酸(boric acid)、硫酸(H2SO4)中的硫酸鈷(CoSO4)以及其他的化學物質，例如具有碳-氫鍵及/或氮-氫鍵的有機化合物。
鍍覆溶液55可包含硫(S)在其電解液內。結果使得鍍覆的金屬材料54也包含硫。金屬材料54中的硫將導致金屬材料54在後續的步驟中受到侵蝕，此部分將於後續的段落中進行討論。因此，在鍍覆之前可降低或消除電解液中的硫含量。根據本發明的一些實施例，鍍覆溶液55中不具有任何含硫的化學物質，使得硫不會沉積於金屬材料54中。根據一些其他的實施例，調整鍍覆溶液55，使得含硫的化學物質即使存在於鍍覆溶 液55中(例如包含硫以及具有碳-氫鍵及/或氮-氫鍵的有機化合物)，鍍覆溶液55中的硫含量仍低於100百萬分之一(parts per million，ppm)。鍍覆溶液55也可實質上不含硫，舉例而言，當鍍覆溶液55中的硫含量低於約20ppm或低於約10ppm，若金屬材料54有受到侵蝕也不會影響到最後形成的接觸插塞的品質。若已購買(或提供)鍍覆溶液55，且其具有高於約100ppm的硫含量，將鍍覆溶液55進行處理以移除硫，使其硫含量少於約100ppm，以及在將其用於進行鍍覆之前使其硫含量符合預期值，例如低於約20ppm或約10ppm，用於進行鍍覆的鍍覆溶液55將可不含或實質上不含硫。此外，鍍覆溶液55可能具有少量的硫，例如大於約1ppm，因此，硫含量可在約1ppm至約100ppm的範圍內，在約1ppm至約20ppm的範圍內，或在約1ppm至約10ppm的範圍內。結果形成的金屬材料54可包含微量的硫，且藉由鍍覆溶液55中硫的還原(reduction)或消除(elimination)，可顯著地減少或完全刪除此含量。
金屬材料54在進行電化學鍍(ECP)時可將其底部朝上置放，亦即在源/汲極接觸開口40和閘極接觸開口41的底部的沉積速度大於頂部區域的沉積速度，頂部區域例如位於層間介電質36上之蓋層48的一部分。因此，金屬材料54可填入源/汲極接觸開口40和閘極接觸開口41且持續成長。
根據本發明的一些實施例，在沉積金屬材料54之後進行退火。使用快速熱退火(RTA)以進行退火，且退火的持續時間在約2分鐘至約10分鐘的範圍內。退火的溫度可在約300℃至約500℃的範圍內。若金屬材料54中存在硫，退火將導致 硫的擴散，使得金屬材料54和蓋層48之間的界面的硫含量因硫的擴散而增加。
接著，進行平坦化製程，例如化學機械研磨(CMP)，以移除金屬材料54、蓋層48和金屬層46位於層間介電質36上的過量(excess)部分。因此，如第10A圖所示，形成源/汲極接觸插塞56A和閘極接觸插塞56B。相應的步驟顯示於第14圖的製造流程200中的步驟214。第10A圖示意性地顯示出研磨墊57。在實際的化學機械研磨製程中，研磨墊57的尺寸/直徑可大於晶圓10的尺寸。在進行化學機械研磨製程的期間，研磨墊57可正面向上擺置，而晶圓10可正面向下且相對於研磨墊57施加應力。在進行化學機械研磨的期間旋轉晶圓10。在進行化學機械研磨的期間於研磨墊57上供給研磨漿(slurry)。
在一些實施例中，層間介電質36包含層36A和層36B(如第9圖所示)，進行平坦化製程直到完全移除層36B。因此，層36B係作為保護在其之下的層間介電質36的犧牲層使用。
若金屬材料54中存在硫，在進行化學機械研磨的期間，源/汲極接觸插塞56A和閘極接觸插塞56B可能受侵蝕而產生凹槽60，如第10B圖所示。反之，若金屬材料54中不存在硫，在進行化學機械研磨的期間不會產生侵蝕，且源/汲極接觸插塞56A和閘極接觸插塞56B的頂面可為平坦的，不會形成凹槽。侵蝕可由硫與研磨漿進行反應而產生，形成侵蝕源/汲極接觸插塞56A和閘極接觸插塞56B的硫酸。退火更導致硫集中在靠近金屬材料54和蓋層48之間的界面的區域。結果，集中 在界面處的硫造成凹槽60在界面處的深度大於源/汲極接觸插塞56A和閘極接觸插塞56B其他部分的深度，進而形成第10B圖所示之凹槽輪廓。凹槽60的邊緣部分具有深度D1，且凹槽60的中央部分具有深度D2，深度D2小於深度D1。根據一些實施例，深度D1對深度D2的比值(D1/D2)大於2。應注意的是深度D1、深度D2和比值D1/D2與各種因素有關，例如金屬材料54的硫含量、退火狀況和研磨漿。硫也可能擴散進入蓋層48中較淺的部分，因此，凹槽60也可擴展至蓋層48。
當未發生侵蝕或侵蝕的狀況非常輕微時，可在晶圓10上直接形成介電層和導電特徵，如第10A圖所示。若仍發生侵蝕或侵蝕的狀況不容忽視時，可形成填入凹槽60(如第10B圖所示)的金屬蓋62，產生的晶圓10如第11A圖所示。金屬蓋62因此延伸進入凹槽60。根據一些實施例，金屬蓋62的頂面實質上與層間介電質36的頂面共平面。金屬蓋62可使用化學氣相沉積法(CVD)來沉積，選擇前驅物(precursor)以使其選擇性地生成。金屬蓋62係形成在源/汲極接觸插塞56A和閘極接觸插塞56B上，並未形成在層間介電質36上。金屬蓋62可由鈷、鎢、鎳或前述之合金形成。再者，金屬蓋62和金屬材料54可由相同材料或不同材料製成。在第11A圖和後續之圖式中，金屬蓋62係使用虛線表示以說明他們在第10A圖的相應結構中可能不會形成，或可能形成在第10B圖的相應結構中。
根據一些實施例，第11B圖顯示晶圓10，進行化學機械研磨直至移除所有在閘極間隙物30上的層間介電質36，且暴露出閘極間隙物30。結果，每一個閘極接觸插塞56B係完全 位於兩側的閘極間隙物30之間的空間裡。根據這些實施例，源/汲極接觸插塞56A和閘極接觸插塞56B的侵蝕可能發生或不會發生，進而形成金屬蓋62或不形成金屬蓋62，如繪示金屬蓋62的虛線所表達之意涵。
在第1-9、10A、10B、11A和11B圖所示之步驟中形成電晶體。參見第12圖，形成蝕刻停止層68後，形成介電層70。根據一些實施例，介電層70為層間介電質，故可以ILD1 70表示。一些實施例中也可省略蝕刻停止層68。因此，使用虛線繪示蝕刻停止層68以說明其可以被形成或不用被形成。蝕刻停止層68可由碳化矽、氮氧化矽、碳氮化矽、前述之組合或前述之複合層以形成。蝕刻停止層68可使用沉積方法形成，例如化學氣相沉積法(CVD)、電漿增強化學氣相沉積法(plasma enhanced chemical vapor deposition，PECVD)、原子層沉積法(ALD)或其相似的方法。介電層70(ILD1 70)可包含選自於磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽酸鹽玻璃(BPSG)、氟矽酸鹽玻璃(fluorine-doped silicon glass，FSG)或四乙氧基矽烷(TEOS)氧化物的材料。介電層70(ILD1 70)也可由無孔(non-porous)低介電常數(low-k)的介電材料製成，可為含碳介電材料。介電層70(ILD1 70)可使用旋轉塗佈、流動式化學氣相沉積法(FCVD)、或其相似的方法形成，或者可使用沉積方法，例如化學氣相沉積法(CVD)、電漿增強化學氣相沉積法(PECVD)、低壓化學氣相沉積法(low pressure chemical vapor deposition，LPCVD)或其相似的方法。
第12圖更顯示導電特徵72的形成，導電特徵72可 為金屬線、金屬導孔(via)、金屬墊等。蝕刻停止層68、介電層70和導電特徵72的形成顯示於第14圖的製造流程200中的步驟216。根據本發明的一些實施例，導電特徵72為接觸插塞，且未形成如第12圖所示之蝕刻停止層68。根據一些其他的實施例，導電特徵72為銅導孔或銅線，且在這些實施例中形成蝕刻停止層68。
導電特徵72的形成可包含在蝕刻停止層68和介電層70內形成開口以暴露出導電插塞56，在開口內填入導電材料，以及進行平坦化製程。導電特徵72可包含導電黏著/阻障層74，以及位於導電黏著/阻障層74上的金屬材料76。導電黏著/阻障層74可由選自於鈦、氮化鈦、鉭、氮化鉭、前述之組合或前述之多層的材料製成。金屬材料76可由鎢、銅、鋁或前述之合金製成，且可使用物理氣相沉積法(PVD)、金屬有機化學氣相沉積法(MOCVD)或鍍覆來形成。根據一些實施例，使用電化學鍍(ECP)以形成金屬材料76，且相應的鍍覆溶液可具有相似於第9圖之鍍覆溶液55的硫含量，其中鍍覆溶液55的硫含量係低於約100ppm，或不含硫以降低侵蝕。
本發明的一些實施例具有一些優勢的技術特徵。藉由減少或移除用於形成接觸插塞的鍍覆溶液中的硫含量，以降低或消除接觸插塞在進行化學機械研磨期間的侵蝕。此外，若有因侵蝕而形成的凹槽產生時，可選擇性地形成金屬蓋以填充凹槽。在閘極間隙物之間也可形成閘極接觸插塞以減少閘極接觸插塞上的金屬導孔/插塞未對準(misalignment)所產生的電性短路或漏電流。
根據本發明的一些實施例，提供形成接觸插塞的方法。此方法包含形成層間介電質覆蓋電晶體的閘極堆疊，層間介電質和閘極堆疊為晶圓的部分，蝕刻層間介電質以形成接觸開口，且經由接觸開口暴露出電晶體的源/汲極區或閘極堆疊內的閘極電極。此方法還包含形成導電蓋層，導電蓋層延伸進入接觸開口，使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，含金屬材料具有一部分填入接觸開口，且鍍覆溶液的硫含量低於約100ppm。此方法更包含對晶圓進行平坦化製程以移除含金屬材料的過量部分，含金屬材料的剩餘部分和導電蓋層的剩餘部分結合形成接觸插塞。
根據本發明的一些實施例，提供形成接觸插塞的方法。此方法包含形成層間介電質，以及蝕刻層間介電質以形成第一接觸開口和第二接觸開口，經由第一接觸開口和該第二接觸開口分別暴露出電晶體的源/汲極區和閘極電極。此方法還包含沉積金屬層，金屬層延伸進入第一接觸開口和第二接觸開口，以及沉積導電蓋層，導電蓋層延伸進入第一接觸開口和第二接觸開口。此方法更包含使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，鍍覆溶液實質上不含硫。此外，此方法包含進行平坦化製程以移除含金屬材料的過量部分，含金屬材料的剩餘部分和導電蓋層的剩餘部分形成源/汲極接觸插塞和閘極接觸插塞。
根據本發明的一些實施例，提供形成接觸插塞的方法。此方法包含形成層間介電質，以及蝕刻層間介電質以形成接觸開口，經由接觸開口暴露出電晶體的源/汲極區或閘極 電極。此方法還包含沉積金屬層，金屬層延伸進入接觸開口，以及沉積導電蓋層，導電蓋層具有第一部分延伸進入接觸開口以及第二部分與層間介電質重疊。此方法更包含使用電化學鍍在鍍覆溶液中在導電蓋層上鍍覆含金屬材料，且鍍覆溶液實質上不含硫。此外，此方法包含進行平坦化製程以移除含金屬材料的過量部分，其中含金屬材料的剩餘部分和導電蓋層的剩餘部分結合形成接觸插塞，且接觸插塞的頂面自層間介電質相鄰的頂面凹陷以形成凹槽。此方法還包含在凹槽內選擇性地形成金屬蓋。
以上概述數個實施例或範例之特徵，以便在本發明所屬技術領域中具有通常知識者可以更理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應該理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例或範例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並無悖離本發明實施例的精神與範圍，且他們能在不違背本發明實施例之精神和範圍之下，做各式各樣的改變、取代和替換。

Claims (14)

  1. 一種形成接觸插塞的方法，包括：形成一層間介電質覆蓋一電晶體的一閘極堆疊，其中該層間介電質和該閘極堆疊為一晶圓的部分；蝕刻該層間介電質以形成一第一接觸開口，其中經由該第一接觸開口暴露出該電晶體的一源/汲極區或該閘極堆疊內的一閘極電極；形成一導電蓋層，其中該導電蓋層延伸進入該第一接觸開口；在該導電蓋層上鍍覆一含金屬材料，使用電化學鍍在一鍍覆溶液中鍍覆該含金屬材料，其中該含金屬材料包括一部分填入該第一接觸開口，且該鍍覆溶液的硫含量低於約100ppm；對該晶圓進行一平坦化製程以移除該含金屬材料的過量部分，其中該含金屬材料的剩餘部分和該導電蓋層的剩餘部分結合形成一第一接觸插塞，且其中進行該平坦化製程使得該第一接觸插塞內產生一凹槽；以及在該凹槽內選擇性地沉積一金屬蓋。
  2. 如申請專利範圍第1項所述之形成接觸插塞的方法，更包括：提供具有硫含量的該鍍覆溶液；以及在鍍覆該含金屬材料之前，自該鍍覆溶液中移除硫以降低該鍍覆溶液中的硫含量。
  3. 如申請專利範圍第1項所述之形成接觸插塞的方法，其中該鍍覆溶液不含硫。
  4. 如申請專利範圍第1項所述之形成接觸插塞的方法，更包括在形成該導電蓋層之前，在該第一接觸開口內形成一介電接觸間隙物。
  5. 如申請專利範圍第1項所述之形成接觸插塞的方法，更包括：蝕刻該層間介電質以形成一第二接觸開口，其中經由該第一接觸開口暴露出該源/汲極區，且經由該第二接觸開口暴露出該閘極電極，以及該導電蓋層和該含金屬材料係同時形成於該第一接觸開口和該第二接觸開口內。
  6. 一種形成接觸插塞的方法，包括：形成一層間介電質；蝕刻該層間介電質以形成一第一接觸開口和一第二接觸開口，其中經由該第一接觸開口和該第二接觸開口分別暴露出一電晶體的一源/汲極區和一閘極電極；沉積一金屬層，延伸進入該第一接觸開口和該第二接觸開口；沉積一導電蓋層，其中該導電蓋層延伸進入該第一接觸開口和該第二接觸開口；使用電化學鍍在一鍍覆溶液中在該導電蓋層上鍍覆一含金屬材料，其中該鍍覆溶液實質上不含硫；進行一平坦化製程以移除該含金屬材料的過量部分，其中該含金屬材料的剩餘部分和該導電蓋層的剩餘部分形成一源/汲極接觸插塞和一閘極接觸插塞，且其中進行該平坦化製程使得該源/汲極接觸插塞內產生一第一凹槽且該閘極接觸插塞內產生一第二凹槽；以及在該第一凹槽和該第二凹槽內選擇性地沉積金屬蓋。
  7. 如申請專利範圍第6項所述之形成接觸插塞的方法，其中該第一接觸開口和該第二接觸開口係在不同的蝕刻製程中形成。
  8. 如申請專利範圍第7項所述之形成接觸插塞的方法，更包括在該第一接觸開口和該第二接觸開口內分別沉積一第一介電接觸間隙物和一第二介電接觸間隙物。
  9. 如申請專利範圍第6項所述之形成接觸插塞的方法，更包括：提供包括硫的該鍍覆溶液，以及自該鍍覆溶液中移除硫；或者提供不含硫的該鍍覆溶液。
  10. 如申請專利範圍第1或6項所述之形成接觸插塞的方法，更包括：在該層間介電質上形成一附加介電層，其中該附加介電層和該層間介電質係由不同材料製成，其中該第一接觸開口穿過該層間介電質和該附加介電層，且該導電蓋層包括一部分與該附加介電層重疊。
  11. 如申請專利範圍第1或6項所述之形成接觸插塞的方法，更包括在進行該平坦化製程之前，對該含金屬材料進行退火。
  12. 一種形成接觸插塞的方法，包括：形成一層間介電質；蝕刻該層間介電質以形成一接觸開口，其中經由該接觸開口暴露出一電晶體的一源/汲極區或一閘極電極；沉積一金屬層，延伸進入該接觸開口；沉積一導電蓋層，具有一第一部分延伸進入該接觸開口以及一第二部分與該層間介電質重疊；使用電化學鍍在一鍍覆溶液中在該導電蓋層上鍍覆一含金屬材料，其中該鍍覆溶液實質上不含硫；進行一平坦化製程以移除該含金屬材料的過量部分，其中該含金屬材料的剩餘部分和該導電蓋層的剩餘部分結合形成一接觸插塞，且該接觸插塞的頂面自該層間介電質相鄰的頂面凹陷以形成一凹槽；以及在該凹槽內選擇性地形成一金屬蓋。
  13. 如申請專利範圍第12項所述之形成接觸插塞的方法，其中該凹槽的邊緣部分較深，且中央部分較淺。
  14. 如申請專利範圍第12項所述之形成接觸插塞的方法，其中該金屬蓋係由與該含金屬材料相同之材料製成。
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US20190115256A1 (en) 2019-04-18
KR20180118031A (ko) 2018-10-30
US20200075407A1 (en) 2020-03-05
TW201839911A (zh) 2018-11-01
US10985061B2 (en) 2021-04-20
CN108735660B (zh) 2020-12-01
US20180308751A1 (en) 2018-10-25
KR102030242B1 (ko) 2019-10-10
US10483165B2 (en) 2019-11-19
DE102017117796A1 (de) 2018-10-25
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US20210257254A1 (en) 2021-08-19
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