TWI669764B - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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Publication number
TWI669764B
TWI669764B TW107126394A TW107126394A TWI669764B TW I669764 B TWI669764 B TW I669764B TW 107126394 A TW107126394 A TW 107126394A TW 107126394 A TW107126394 A TW 107126394A TW I669764 B TWI669764 B TW I669764B
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Taiwan
Prior art keywords
die
forming
metal foil
carrier
semiconductor
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TW107126394A
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English (en)
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TW201946165A (zh
Inventor
吳志偉
林俊成
李隆華
盧思維
施應慶
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台灣積體電路製造股份有限公司
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Publication of TWI669764B publication Critical patent/TWI669764B/zh
Publication of TW201946165A publication Critical patent/TW201946165A/zh

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Abstract

一種形成半導體元件的方法，包含：將金屬箔附接至載 體，其中金屬箔是在附接金屬箔之前預製；在金屬箔的遠離載體的第一側上形成導電柱；將半導體晶粒附接至金屬箔的第一側；在半導體晶粒及導電柱周圍形成模製材料；以及在模製材料上方形成重佈線結構。

Description

半導體元件及其形成方法
本發明實施例是有關於半導體元件及其形成方法。
由於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的積體密度的持續改良，半導體產業經歷了快速的增長。主要而言，積體密度的此改良來自最小特徵尺寸的逐漸減小，此允許將更多的組件整合至給定區域中。由於近年來對更小的電子元件的要求增長，因而對半導體晶粒的更小及更具創造性的封裝技術的需求隨之增長。
此等封裝技術的一實例為疊層封裝(Package-on-Package；PoP)技術。在PoP封裝中，頂部半導體封裝件堆疊於底部半導體封裝件的頂部上以允許高水平的積集度及組件密度。另一實例為多晶片模組(Multi-Chip-Module；MCM)技術，其中多個半導體晶粒封裝於一個半導體封裝件中，以提供具有整合多種功能的半導體元件。
先進封裝技術的高水平積集度能夠產生具有增強型功能及較小佔據面積的半導體元件，其有利於諸如行動電話、平板電腦 以及數位音樂播放器的較小形狀因子(form factor)元件。另一優勢為縮短連接半導體封裝件內的交互操作部件的導電路徑的長度。縮短電路之間的內連線的佈線長度能得到較快的訊號傳播且能降低雜訊及串擾(cross-talk)，因此可改良半導體元件的電性效能。
在一實施例中，一種形成半導體元件的方法包含：將金屬箔附接至載體，其中金屬箔是在附接金屬箔之前預製；在金屬箔遠離載體的第一側上形成導電柱；將半導體晶粒附接至金屬箔的第一側；在半導體晶粒及導電柱周圍形成模製材料；以及在模製材料上方形成重佈線結構。
在一實施例中，形成半導體元件的方法包含：在載體的第一側上方形成導電柱；將晶粒的背側附接至載體的第一側；在晶粒及導電柱周圍形成模製材料；在晶粒、導電柱以及模製材料上方形成重佈線結構；移除載體，其中在移除載體之後，暴露遠離重佈線結構之導電柱的第一表面；在晶粒的背側上方形成散熱片；以及將半導體封裝接合至導電柱的第一表面，散熱片在半導體封裝與晶粒之間。
在一實施例中，半導體元件包含：重佈線結構；晶粒，其中晶粒的第一側附接至重佈線結構的第一側；模製材料，在重佈線結構的第一側面及晶粒周圍；以及散熱片，附接至與晶粒的第一側相對的晶粒的第二側，其中遠離重佈線結構之散熱片的第一側比遠離重佈線結構之模製材料的第一表面更接近重佈線結構。
100、200、300、400、500‧‧‧半導體元件
101‧‧‧載體
103、141、187‧‧‧介電層
105、121、185‧‧‧黏著層
106、107‧‧‧金屬箔
108、109‧‧‧導電柱
108U、130U、137U‧‧‧上表面
123‧‧‧開口
125‧‧‧凹口
130、162‧‧‧半導體晶粒
131‧‧‧元件
133‧‧‧介電材料
135‧‧‧晶粒連接件
137、165‧‧‧模製材料
140‧‧‧重佈線結構
143‧‧‧導電特徵
145‧‧‧連接件
151、181‧‧‧框架
153、183‧‧‧膠帶
160‧‧‧半導體封裝
161‧‧‧基底
161L‧‧‧下表面
163‧‧‧導電接墊
167‧‧‧打線
168‧‧‧導電接合件
168L‧‧‧下部部分
168T‧‧‧界面
168U‧‧‧上部部分
169‧‧‧金屬間化合物
171‧‧‧導熱材料
3000‧‧‧方法
3010、3020、3030、3040、3050‧‧‧步驟
D1、D2、T‧‧‧厚度
D3、W1、W2‧‧‧寬度
H‧‧‧高度
W3‧‧‧偏移量
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1至圖9根據一實施例說明在各個製造階段上的半導體元件的橫截面視圖。
圖10至圖11根據一實施例說明在各個製造階段上的半導體元件的橫截面視圖。
圖12至圖19根據一實施例說明在各個製造階段上的半導體元件的橫截面視圖。
圖20根據一實施例說明半導體元件的橫截面視圖。
圖21根據一實施例說明半導體晶粒的橫截面視圖。
圖22至圖27根據一實施例說明在各個製造階段上的半導體元件的橫截面視圖。
圖28根據一些實施例說明用於形成半導體元件的方法的流程圖。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然，此等組件及配置僅係實例且並不意欲係限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包括第 一特徵以及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。
此外，在本文中，為了易於描述，空間相對術語，諸如「在...下方(beneath)」、「下方(below)」、「下(lower)」、「上(above)」、「上方(upper)」及類似者可用於描述如圖式中所說明的一個元件或特徵與其他元件或特徵的關係。除圖中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本揭露的實施例是在半導體元件及形成所述半導體元件的方法之技術背景中論述，且特別是關於積體扇出型(integrated fan-out；InFO)半導體封裝的技術背景。在一些實施例中，形成半導體元件的方法包含將金屬箔附接至半導體晶粒的背側，以及在半導體晶粒及金屬箔周圍形成模製材料。金屬箔充當散熱片(heat sink)，以助於耗散來自半導體晶粒的熱能。在一些實施例中，諸如金屬膏的導熱材料形成於半導體晶粒的背側上方，以充當散熱片。模製材料形成於半導體晶粒及導熱材料周圍，且重佈線結構形成於半導體晶粒及模製材料上方。
圖1至圖9根據一實施例說明在各個製造階段上的半導體元件100的橫截面視圖。在圖1中，於載體101上方形成介電層103，所述介電層可充當離形層以有助於後續的載體分離(de-bonding)製程。在一些實施例中，省略介電層103。金屬箔107藉由黏著層105以及介電層103(若形成)附接至載體101。
載體101可由如矽、聚合物、聚合物複合材料、金屬箔、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、膠帶的材料或用於支撐結構的其他適合的材料製成。在載體101上方沈積或層壓(laminate)介電層103。介電層103可為感光性的，且可例如藉由在後續載體分離製程中在載體101上照射紫外光(ultra-violet，UV)而簡單地自載體101剝離。舉例而言，介電層103可為由明尼蘇達州聖保羅之3M公司(3M Company)製造的光-熱轉換(light-to-heat-conversion；LTHC)膜。
接著，金屬箔107藉由黏著層105附接至載體101(例如，經由介電層103)，所述黏著層105可例如是晶粒貼合膜(die attaching film；DAF)。在所說明的實施例中，金屬箔107是在附接至載體101之前預製(亦可被稱作預成型)。金屬箔107具有高熱導率，例如，在約100W/(m-k)與約400W/(m-K)之間，使得金屬箔107充當如下文中更詳細描述的所形成之半導體元件100的散熱片。另外，金屬箔107可不需要形成用於在金屬箔107上形成導電柱109(參見圖2)的晶種層。與藉由物理氣相沈積(physical vapor deposition；PVD)、化學氣相沈積(chemical vapor deposition；CVD)或類似者在載體101上方形成(例如，沈積)金屬箔107的製程相比，藉由使用預製金屬箔可改善製造時間(亦即產能)。此外，相較於使用沈積製程(例如，PVD、CVD)所獲得的表面，預製金屬箔107可具有更平滑(例如，更平面)的表面(例如，上表面及下表面)。更平面的表面可有利於後續諸如是微影及蝕刻製程的處理。
在所說明的實施例中，儘管金屬箔107為銅箔，但亦可 使用包括合適的材料的其他金屬箔，合適的材料諸如金、鎢、鋁、銀、類似者或其組合。儘管金屬箔107的厚度T在約10μm與約50μm之間，諸如30μm，但其他尺寸亦為可能的。
參考圖2，於金屬箔107上方形成導電柱109。由於金屬箔107(例如，銅箔)可充當晶種層，可藉由在金屬箔107上方形成經圖案化光阻(未繪示)而將導電柱109形成於金屬箔107上方，其中經圖案化光阻中的開口中的每一者對應於待形成的導電柱109的位置；使用例如電鍍或無電鍍於開口填充導電材料(諸如銅)；以及使用例如灰化或剝離製程移除光阻。用於形成導電柱109的其他方法亦為可能的，且完全意欲包含於本揭露的範疇內。
一旦形成導電柱109，導電柱109可具有寬度W1，其可比目標寬度W2(參見圖4)大約20μm至約60μm。如下文中所描述，較大寬度W1被設計成補償在後續蝕刻製程中導電柱109被縮減的寬度。在一些實施例中，寬度W1在約100μm至約300μm之間，諸如190μm。儘管如此，寬度W1的其他尺寸亦為可能的。
接著，在圖3中，藉由使用黏著層121而將半導體晶粒130(亦被稱作晶粒或積體電路(integrated circuit；IC)晶粒)附接至金屬箔107的上表面，例如附接在導電柱109之間。黏著層121可為DAF。DAF的熱導率通常較低，諸如約0.25W/(m-k)。因此，在其中黏著層121為DAF的實施例中，具有例如在約3μm與約20μm之間的厚度的薄DAF可有助於耗散來自於半導體晶粒130的熱能。在一些實施例中，黏著層121由具有在例如約0.2W/(m-k)與約10W/(m-k)之間的熱導率的高熱導率介電材料(例如，包括丙烯酸聚合物或SiO2的材料)形成，在此情況下黏著層121 的厚度可能較厚，諸如在約20μm與約50μm之間。
在黏附至金屬箔107之前，晶粒130可根據可應用的製造製程處理，以在晶粒130中形成積體電路。舉例而言，晶粒130可包含半導體基底及一或多個上覆的金屬化層，其共同地說明為元件131。半導體基底可為例如經摻雜的矽或未經摻雜的矽，或為絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，諸如多層基底或梯度基底。諸如電晶體、二極體、電容器、電阻器等的元件(未繪示)可形成於半導體基底中及/或上，且可由金屬化層(未繪示)互連以形成一或多個積體電路，所述金屬化層例如是半導體基底上的一或多個介電層中的金屬化圖案。
晶粒130更包括進行外部連接的接墊(未繪示)，諸如鋁接墊。接墊在可被稱為晶粒130的主動側或前側的位置上。晶粒130更包括位於晶粒130的前側處及部分的接墊上之保護膜(未繪示)。開口延伸穿過保護膜至接墊。諸如導電柱(例如包括諸如銅的金屬)的晶粒連接件135延伸至保護膜的開口中且機械地及電性地耦接至各別接墊。可藉由例如電鍍或其類似方法形成晶粒連接件135。晶粒連接件135電耦接至晶粒130的積體電路。
介電材料133形成於晶粒130的主動側上，諸如形成於保護膜及/或晶粒連接件135上。介電材料133側向包封晶粒連接件135，且介電材料133可能與晶粒130側向共端(coterminous)。 介電材料133可為：聚合物，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或類似者；或其組合，且可例如藉由旋轉塗佈、層壓、CVD或類似者形成。
接著，參考圖4，執行蝕刻製程以移除部分的金屬箔107。在一些實施例中，蝕刻製程為濕式蝕刻製程。蝕刻製程可為等向性，且對於導電柱109的材料(例如銅)及金屬箔107(例如銅箔)的材料可具有選擇性(例如對於導電柱109及金屬箔107有較高的蝕刻速率)。作為蝕刻製程(例如，濕式蝕刻製程)的結果，導電柱109的外部部分被移除，且在蝕刻製程之後，導電柱109的剩餘部分(例如，內部部分)及直接設置在導電柱109下的金屬箔107的剩餘部分形成具有寬度W2的導電柱108。與導電柱109的寬度W1(參見圖2)相比較，寬度W2小約20μm至約60μm。換言之，由於蝕刻製程，導電柱108的側壁與其中心軸線(例如，垂直於載體101的上表面的縱軸)之間的距離比導電柱109的側壁與其中心軸線之間的距離小約10μm至約30μm。蝕刻製程亦可能減小導電柱109的高度。因此，為補償蝕刻製程所致的高度損失，導電柱109的高度可形成為例如比晶粒130的高度H大至少10μm至30μm，使得在蝕刻製程之後，導電柱108的上表面108U齊平於或高於(例如，距載體101更遠)晶粒130的上表面130U。
如圖4中所說明，蝕刻製程亦移除部分的金屬箔107以暴露黏著層105的上表面的區域。舉例而言，金屬箔107的側向設置在導電柱108與晶粒130之間的部分被移除。在蝕刻製程之 後，在一些實施例中，保留金屬箔107的直接在晶粒130下方的部分(標記為金屬箔106)，保留金屬箔107的直接在導電柱109下方的部分，而移除金屬箔107的其他部分。在圖4的所說明實例中，由於濕式蝕刻製程，於晶粒130下方的金屬箔106中形成底切(under cut)。在一些實施例中，晶粒130的側壁與金屬箔106的側壁之間的偏移量W3在約10μm至約30μm之間。
可選擇性地在蝕刻製程之後執行氧化製程，以對導電柱108進行處理。氧化製程可在導電柱108的表面上方形成氧化物層(氧化物例如是氧化銅)。氧化物的層可有利於增加導電柱108與隨後形成的模製材料137(參見圖5)之間的黏著力。
接著，在圖5中，於黏著層105上方形成模製材料137。模製材料137包圍晶粒130、導電柱108以及金屬箔106。作為實例，模製材料137可包括環氧樹脂、有機聚合物、添加或不添加氧化矽類或玻璃的填充劑的聚合物或其他材料。在一些實施例中，模製材料137包括在施予時為凝膠型液體的液體模製化合物(liquid molding compound；LMC)。模製材料137在施予時亦可包括液體或固體。替代地，模製材料137可包括其他絕緣及/或包封材料。在一些實施例中，使用晶圓級模製製程來應用模製材料137。可使用例如壓縮模製、轉移模製或其他方法來對模製材料137進行模製。
接著，在一些實施例中，使用固化製程來固化模製材料137。固化製程可包括使用退火製程或其他加熱製程，在預定時間段將模製材料137加熱至預定溫度。固化製程亦可包括紫外(UV)曝光製程、紅外(IR)能量曝光製程、其組合或其與加熱製程的組 合。替代地，可使用其他方法來固化模製材料137。在一些實施例中，不包含固化製程。
接著，可執行諸如化學機械研磨(chemical and mechanical polish；CMP)的平坦化製程，以移除模製材料137於晶粒130的前側上方的過量部分。在平坦化製程之後，在一些實施例中，模製材料137、導電柱108以及晶粒連接件135上部表面共面。在一些實施例中，省略平坦化製程。
接著，在圖6中，於晶粒130、導電柱108以及模製材料137上方形成重佈線結構140。重佈線結構140包括形成於一或多個介電層141中的導電特徵143(例如，導電線及導電通孔)的一或多個層。重佈線結構140電耦接至導電柱108及晶粒130(例如，藉由晶粒連接件135)。
在一些實施例中，一或多個介電層141由以下材料形成：聚合物，諸如PBO、聚醯亞胺、BCB或類似者；氮化物，諸如氮化矽；氧化物，諸如氧化矽、PSG、BSG、BPSG或類似者。可藉由合適的沈積製程來形成一或多個介電層141，沈積製程諸如旋塗、CVD、層壓、類似者或其組合。
在一些實施例中，重佈線結構140的導電特徵包括由諸如銅、鈦、鎢、鋁或類似者的合適導電材料形成的導電線及導電通孔。可藉由以下操作形成重佈線結構140：形成介電層；在介電層中形成開口以暴露下層導電特徵；在介電層上方及開口中形成晶種層(未繪示)；在晶種層上方形成具有經設計圖案的經圖案化光阻(未繪示)；將導電材料電鍍(例如電鍍或無電鍍)於經設計圖案的光阻中及晶種層上方；以及移除光阻及晶種層上未形成有導 電材料的部分。可重複上述製程以形成用於重佈線結構140的多個導電特徵層及多個介電層。
形成重佈線結構140的其他方法亦為可能的且完全意欲包含於本揭露內容的範疇內。舉例而言，可使用鑲嵌及/或雙金屬鑲嵌製程以形成重佈線結構140。在一些實施例中，藉由鑲嵌/雙金屬鑲嵌製程形成重佈線結構140的導電特徵的一些層，且藉由上文所描述的方法(亦即使用例如經圖案化光阻及電鍍)形成重佈線結構140的導電特徵的一些其他層。
圖6的重佈線結構140中的介電層141的數目及導電特徵143的層的數目僅為非限制性實例。介電層的其他數目及導電特徵的層的其他數目亦為可能的，且完全意欲包含於本發明內容的範疇內。
仍參考圖6，於重佈線結構140的導電特徵(例如導電線及通孔)上方形成連接件145(亦可被稱作外部連接件、導電凸塊)，且連接件145電耦接至所述導電特徵。在所說明的實施例中，連接件145藉由重佈線結構140的導電特徵電耦接至晶粒130。在一些實施例中，連接件145中的至少一者藉由重佈線結構140電耦接至導電柱108。
連接件145可為焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微型凸塊、無電鍍鎳-無電鍍鈀-浸鍍金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸塊、其組合(例如，具有附接至其的焊球的金屬柱)或其類似物。連接件145可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似者或 其組合。在一些實施例中，作為實例，連接件145包括共晶材料，且可包括焊料凸塊或焊球。連接件145可形成柵格(grid)，諸如球柵陣列(ball grid array；BGA)。可使用任何合適的製程形成連接件145。儘管連接件145在圖6中說明為具有部分球形形狀，但連接件145可包括其他形狀。舉例而言，連接件145亦可包括非球形導電連接件。
在一些實施例中，連接件145包括金屬柱(諸如銅柱)，所述金屬柱藉由濺鍍、印刷、電鍍、無電鍍、CVD或類似者形成，在金屬柱上具有或不具有焊料材料。金屬柱可不含焊料，且具有實質上垂直的側壁或傾斜側壁(tapered sidewall)。
儘管圖6中未示出，但在形成連接件145之前，可於重佈線結構140上方形成凸塊下金屬化物(under bump metallization；UBM)結構。換言之，可於連接件145與重佈線結構140之間形成UBM結構，且UBM結構電耦接至所述連接件145及所述重佈線結構140。UBM結構可包括導電材料的一或多個層，所述導電材料諸如銅、鎢、鈦、金、鎳、其類似者、其合金，或其組合。為形成UBM結構，在重佈線結構140的最頂部介電層中形成開口，以暴露重佈線結構140的導電特徵(例如，銅線或銅墊)。在形成開口之後，可形成UBM結構，以使UBM結構電接觸於所暴露的的導電特徵。
接著，在圖7中，翻轉圖6中所說明的半導體元件100，且將連接件145附接至藉由框架151(例如，金屬框架)支撐的膠帶153(例如，切割膠帶)。接著，藉由合適製程自半導體元件100分離載體101，所述製程諸如蝕刻、研磨或機械剝離。在介電層103 為LTHC膜的一實施例中，藉由將載體101暴露至雷射或UV光而分離載體101。雷射或UV光破壞黏合至載體101的LTHC膜的化學鍵結，且接著可易於剝離載體101。在一些實施例中，亦在載體分離製程之後移除介電層103(例如，LTHC膜)。
接著，在圖8中，執行清潔製程以移除黏著層105(例如，DAF)。在一些實施例中，清潔製程為乾式蝕刻製程，諸如電漿製程。在一些實施例中，清潔製程為濕式蝕刻製程。在清潔製程之後，暴露出金屬箔106的上表面、導電柱108的上表面以及模製材料137的上表面。在所說明的實施例中，金屬箔106的上表面、導電柱108的上表面以及模製材料137的上表面彼此齊平。所暴露的金屬箔106有利地促進晶粒130的熱耗散，使得由晶粒130產生的熱能可易於經由黏著層121及金屬箔106耗散。出於此原因，金屬箔106在本文論述中亦可被稱作散熱片。
接著參考圖9，諸如包括記憶體元件的封裝的半導體封裝160(亦被稱作頂部封裝)附接至圖8中所示的半導體元件100(亦被稱作底部封裝)，以形成圖9中的半導體元件100，由此形成具有疊層封裝(PoP)結構的半導體元件100。
如圖9中所說明，半導體封裝160具有基底161及附接至基底161的上表面的一或多個半導體晶粒162(例如，記憶體晶粒)。在一些實施例中，基底161包含矽、砷化鎵、絕緣層上覆矽(silicon-on-insulator，SOI)或其他類似材料。在一些實施例中，基底161為多層電路板。在一些實施例中，基底161包含雙馬來醯亞胺三嗪(bismaleimide triazine；BT)樹脂、FR-4(由編織玻璃纖維布與耐火的環氧樹脂黏合劑形成的複合材料)、陶瓷、玻璃、塑 膠、膠帶、膜或其他支撐材料。基底161可包含形成於基底161中/上的導電特徵(例如導電線及通孔)。如圖9中所說明，基底161具有導電接墊163，所述導電接墊163形成於基底161的上部表面及下部表面上，導電接墊163電耦接至基底161的導電特徵。一或多個半導體晶粒162藉由例如是打線167電耦接至導電接墊163。在基底161上方及半導體晶粒162周圍形成可包括環氧樹脂、有機聚合物、聚合物或其類似者的模製材料165。在一些實施例中，如圖9中所說明，模製材料165與基底161相接(conterminous)。
根據一些實施例，執行回焊製程以使半導體封裝160電耦接及機械耦接至導電柱108。於導電接墊163與導電柱108之間形成導電接合件168。在一些實施例中，焊錫膏(未繪示)沈積在導電柱108的上表面上，藉由接合半導體封裝160的外部連接件與熔融焊錫膏而形成導電接合件168。圖9說明導電接合件168的上部部分168U與導電接合件168的下部部分168L之間的界面168T，其中上部部分168U可對應於半導體封裝160的外部連接件的至少一部分，而下部部分168L可對應於用於形成導電接合件168的焊錫膏的至少一部分。為簡單起見，界面168T可能未於後續圖式中說明。在一些實施例中，導電接合件168包括焊料區域、導電柱(例如在至少銅導柱的末端表面具有焊料區域的銅導柱)或任何其他合適的導電接合件。可於導電接合件168與導電柱108之間的界面處形成金屬間化合物(inter-metallic compound；IMC)169。儘管圖9中未示出，但IMC亦可形成於導電接合件168與導電接墊163之間的界面處。
儘管未說明，但可在導電接合件168經形成以自在相同處理步驟中形成的其他相鄰半導體元件(未繪示)分離半導體元件100之後執行切割製程，由此形成多個個體半導體元件(individual semiconductor device)100。隨後可自膠帶153移除個體半導體元件100。
對所揭露實施例的改變為可能的，且完全意欲包含於本揭露的範疇內。舉例而言，雖然圖9說明兩個導電柱108，但導電柱108的數目可能多於或少於兩個。另外，儘管晶粒130在圖9中說明為在半導體元件100的中間區域中且由導電柱108包圍，但晶粒130可安置於半導體元件100的周邊區域中，並且導電柱可能並未包圍晶粒130。作為另一實例，晶粒130可在形成導電柱109之前附接至金屬箔107。
圖10至圖11根據一實施例說明在各個製造階段上的半導體元件200的橫截面視圖。圖10及圖11中所說明的處理在圖7中所示的處理之後。換言之，在一些實施例中，圖1至圖7、圖10以及圖11說明用於製造半導體元件200的處理步驟。除非另有說明，否則圖10至圖11中的類似元件符號說明如圖1至圖10中的相同或類似的構件，且藉由相同或類似的形成方法形成，因此可能不再贅述。
參考圖10，在圖7的處理之後，於黏著層105中形成開口123，以暴露導電柱108的上表面。可藉由雷射鑽孔、蝕刻(例如，乾式蝕刻或濕式蝕刻)、其類似者或其組合形成開口123。儘管未繪示，但可在與半導體封裝160(參見圖11)接合之前，於開口123中形成焊錫膏。
接著，在圖11中，將半導體封裝160接合至導電柱108，以形成具有PoP結構的半導體元件200。導電接合件168形成於半導體封裝160與導電柱108之間。用於形成半導體元件200的處理與上文參考圖10所述者彼等相同或類似，因此細節可能不再贅述。
藉由將黏著層105保持在半導體元件200中，不執行用於移除黏著層105的清潔製程(參見參考圖8的論述)，因此降低處理成本且減少處理時間。由於黏著層105(例如，DAF)可具有比金屬箔106低的熱導率，用於半導體元件200的熱耗散的效率可能低於用於圖10的半導體元件100的熱耗散的效率。在一些實施例中，黏著層105由具有在例如約0.2W/(m-k)與約10W/(m-k)之間的熱導率的高熱導率介電材料形成，以至少部分地補償用於半導體元件200的熱耗散的效率損失。
圖12至圖19根據一實施例說明在各個製造階段上的半導體元件300的橫截面視圖。除非另有說明，否則圖12至圖19中的類似元件符號說明如圖1至圖10中的相同或類似的構件，且藉由相同或類似的形成方法形成，因此細節可能不再贅述。
參考圖12，於載體101上方形成諸如LTHC膜的介電層103。於介電層103上方形成導電柱109。可藉由以下步驟形成導電柱109：在介電層103上方形成晶種層(未繪示)；在晶種層上方形成經圖案化光阻(未繪示)，其中經圖案化光阻中的開口中的每一者對應於待形成的導電柱109的位置；藉由使用例如電鍍或無電鍍將例如是銅的導電材料填充於開口中；使用例如灰化或剝離製程移除光阻；以及移除晶種層上未形成導電柱109的部分。 用於形成導電柱109的其他方法亦為可能的，且完全意欲包含於本揭露的範疇內。
接著，在圖13中，半導體晶粒130的背側藉由黏著層121(例如，DAF)附接至介電層103。黏著層121可為具有約0.2W/(m-k)的低熱導率的DAF，其具有在約3μm與約10μm之間的厚度。在一些實施例中，黏著層121由具有在約0.2W/(m-k)與約10W/(m-k)之間的熱導率以及在約20μm與約50μm之間的厚度的高熱導率介電材料形成。
可選擇性地執行氧化製程以對導電柱109進行處理。氧化製程可在導電柱109的表面上方形成氧化物(例如，氧化銅)層。氧化物層可有利地增加導電柱109與隨後形成的模製材料137之間的黏著力。
接著，在圖14中，於介電層103上方形成模製材料137。模製材料137包圍晶粒130及導電柱109。可執行諸如CMP的平坦化製程以移除模製材料137於晶粒130上方的過量部分，且以獲得導電柱109、模製材料137與晶粒130的共面上表面。在一些實施例中，省略平坦化製程。
接著，在圖15中，於晶粒130、導電柱109以及模製材料137上方形成重佈線結構140。在所說明的實施例中，重佈線結構140電耦接至晶粒130及導電柱109。另外，於重佈線結構140上方形成連接件145，且連接件145電耦接至重佈線結構140。在一些實施例中，連接件145中的至少一者藉由重佈線結構140電耦接至導電柱109。儘管未說明，但可於連接件145與重佈線結構140之間形成UBM結構。
接著，參考圖16，翻轉圖15中的半導體元件300，且將連接件145附接至藉由框架151支撐的膠帶153。接著，自半導體元件300分離載體101。在載體分離製程之後，執行清潔製程以移除介電層103(例如，LTHC膜)。清潔製程可使用合適的蝕刻劑，諸如氫氯酸(HCl)，或使用在半導體製造中使用的RCA清潔製程執行。
接著，在圖17中，移除黏著層121(例如，DAF)。可執行諸如使用蝕刻氣體的電漿蝕刻製程的合適蝕刻製程以移除黏著層121，所述蝕刻氣體包括氟化氫(HF)、氧氣(O2)、其類似者或其組合。諸如氬氣(Ar)的載氣可用於運載蝕刻氣體。在移除黏著層121之後，於模製材料137中形成凹口125。如圖17中所說明，凹口125暴露晶粒130的背側。
接著參考圖18，於晶粒130的背側上方形成導熱材料171。導熱材料171填充凹口125(參見圖17)，且在模製材料137的上表面上方延伸。導熱材料171具有高熱導率，例如在約100W/(m-k)與約400W/(m-k)之間，且充當散熱片以促進晶粒130的熱耗散。因此，在本文的論述中導熱材料171亦可被稱作散熱片。
在一些實施例中，導熱材料171為金屬膏，其可包括黏著材料，諸如具有金屬填充劑(例如，銀粒子、銅粒子、鋁粒子)分散於其中的環氧樹脂，且因此，在所說明的實施例中，導熱材料171為導電的。在一些實施例中，導熱材料171為銀膏、銅膏、鋁膏或類似者。在一些實施例中，導熱材料171具有良好熱導率(例如，大於15W/(m-k))，且可另外具有高熱容量(例如約1700J/(g℃))。儘管可藉由例如使金屬膏沈積於凹口125中而形成導熱材 料171，但取決於導熱材料171的組成物(例如材料)，亦可使用諸如CVD、濺鍍、電鍍、分散、噴射、印刷、熱黏合的其他合適方法形成導熱材料171。
用於導熱材料171的材料不限於金屬膏。替代地，可使用具有良好熱導率的任何材料。作為一實例，可於凹口125中形成碳奈米管，且用作導熱材料171。碳奈米管可經形成自晶粒130的背側延伸至模製材料137的上表面上方。上文針對導熱材料171所描述的熱導率及熱容量的範圍僅出於說明的目的且並非限制，熱導率及熱容量的其他範圍為可能的，且完全意欲包含於本揭露的範圍內。
如圖18中所說明，導熱材料171具有自晶粒130的背側延伸至模製材料137的上表面137U的下部部分，且具有在模製材料137的上表面137U上方延伸的上部部分。在一實施例中，導熱材料171的上部部分的厚度D2在約10μm與約100μm之間，且導熱材料171的總厚度D1在約10μm與約150μm之間。如圖18中所說明，導熱材料171的上部部分側向延伸超出晶粒130的邊界(例如，側壁)，且在晶粒130上方形成突出物(overhang)。在一些實施例中，導熱材料171的突出部分的寬度D3在約10μm與約20μm之間。熟習此項技術者將瞭解，本文中論述的導熱材料171的尺寸是出於說明的目的且並非限制。其他尺寸亦為可能的且完全意欲包含於本揭露的範疇內。
接著參考圖19，半導體封裝160接合至導電柱109，以形成具有PoP結構的半導體元件300。導電接合件168形成於半導體封裝160與導電柱109之間。可執行回焊製程以形成導電接 合件168。可藉由回焊製程固化導熱材料171(例如，金屬膏)。用於形成半導體元件300的處理在其他方面與上文參考圖10所論述的彼等相同或類似，因此不再贅述細節。
對所揭露實施例的改變為可能的，且完全意欲包含於本揭露的範疇內。舉例而言，儘管導熱材料171的上表面說明為在圖19中的模製材料137的上表面137U與半導體封裝160的下表面161L之間，但在其它實施例中，導熱材料171的上表面可接觸半導體封裝160的下表面161L。換言之，導熱材料171可自晶粒130的背側連續延伸至半導體封裝160的下表面161L，如圖19中的點線(dotted line)172所說明。作為另一實例，導熱材料171的上表面可與模製材料137的上表面137U齊平或低於所述上表面137U(例如，更接近重佈線結構140)。
圖20根據一實施例說明在一製造階段上的半導體元件400的橫截面視圖。圖20中所說明的處理在圖16中所示的處理之後。換言之，在一些實施例中，圖12至圖16以及圖20說明用於製造半導體元件400的處理步驟。除非另有說明，否則圖12至圖16以及圖20中的類似元件符號說明如圖1至圖10中的相同或類似的構件，且藉由相同或類似的形成方法形成，因此可能不再贅述細節。
參考圖20，在分離載體101且移除介電層103(參見圖16)之後，於黏著層121(例如，DAF)上方及模製材料137上方形成導熱材料171。在一些實施例中，導熱材料171具有在約10μm與約100μm之間的厚度。如圖20中所說明，導熱材料171側向延伸超出晶粒130的邊界(例如，側壁)，且在晶粒130上方形 成突出物。在一些實施例中，導熱材料171的突出部分的寬度(類似於圖18中的D3)在約10μm與約20μm之間。
熟習此項技術者將瞭解，本文中論述的導熱材料171的尺寸是出於說明的目的且並非限制。其他尺寸亦為可能的且完全意欲包含於本揭露的範疇內。另外，所揭露的實施例的變體為可能的。舉例而言，導熱材料171的上表面可接觸半導體封裝160的下表面，可與模製材料137的上表面齊平或可比所述上表面更低(例如更接近重佈線結構140)。此等及其他變體亦為可能的，且完全意欲包含於本揭露的範疇內。
與圖19中所說明的半導體元件300相比較，圖20中的半導體元件400省略與移除黏著層121相關的處理步驟，由此減少處理步驟的數目及處理時間。例如DAF的黏著層121可具有比導熱材料171更低的熱導率。為至少部分地補償熱耗散的效率損失，黏著層121可由例如具有在約0.2W/(m-k)與約10W/(m-k)之間的熱導率的高熱導率介電材料形成。
圖21說明多個晶粒130的形成，在一些實施例中，所述多個晶粒的每一者具有附接至其背側的金屬箔107。圖21中形成的晶粒130可用於形成圖27中所說明的半導體元件500。如圖21中所說明，多個晶粒130同時形成於晶圓上(例如，在相同處理步驟中)。接著，使用黏著層185將預成型的金屬箔107附接至晶圓的背側(例如，對應於晶粒130的背側)。金屬箔107可具有在約10μm與約50μm之間的厚度，諸如30μm。如上文參考圖1所論述，金屬箔107具有高熱導率(例如，在約100W/(m-k)與約400W/(m-k)之間)且在所形成的半導體元件500(參見圖27)中充當 散熱片。因此，金屬箔107在本文論述中亦可被稱作散熱片。在一些實施例中，黏著層185為諸如DAF的介電層。如圖21中所說明，介電層187形成於金屬箔107上，其中金屬箔107在介電層187與黏著層185之間。在一些實施例中，介電層187為黏著層。
仍參考圖21，晶圓隨後附接至藉由框架181支撐的膠帶183(例如，切割膠帶)。隨後執行切割以分離多個晶粒130且形成多個個體晶粒130，其中的每一者具有附接至其背側的金屬箔107。
圖22至圖27根據一實施例說明在各個製造階段上的半導體元件500的橫截面視圖。除非另有說明，否則圖22至圖27中的類似元件符號說明如圖1至圖10中的相同或類似的構件，且藉由相同或類似的形成方法形成，因此可能不再贅述細節。
參考圖22，於載體101上方形成介電層103，所述介電層可為LTHC膜。接著，於介電層103上方形成導電柱109。可選擇性地執行氧化製程以在導電柱109上方形成氧化物層，以增大導電柱109與隨後形成的模製材料137之間的黏著力。
接著，在圖23中，藉由介電層187(例如，DAF)將具有附接至其背側(亦參見圖21)的金屬箔107的晶粒130附接至介電層103。
接著參考圖24，於介電層103上方形成模製材料137。在所說明的實例中，模製材料137包圍晶粒130、金屬箔107以及導電柱109。可執行諸如CMP的平坦化製程以移除模製材料137的過量部分，使得在導電柱109、晶粒130與模製材料137具有平面的上表面。在一些實施例中，省略平坦化製程。
接著，在圖25中，於晶粒130、導電柱109以及模製材 料137上方形成重佈線結構140。在所說明的實施例中，重佈線結構140電耦接至導電柱109及晶粒130。另外，於重佈線結構140上方形成連接件145，且連接件145電耦接至重佈線結構140。在一些實施例中，連接件145中的至少一者藉由重佈線結構140電耦接至導電柱109。儘管未說明，但可於連接件145與重佈線結構140之間形成UBM結構。
接著，參考圖26，翻轉圖25中的半導體元件500，且將連接件145附接至藉由框架151支撐的膠帶153。接著，藉由載體分離製程自半導體元件500移除載體101。在一些實施例中，在載體分離製程之後移除介電層103。可選擇性地執行清潔製程(例如，蝕刻製程)以移除介電層103的殘餘物。如圖26中所說明，在載體分離製程之後，介電層187、導電柱109以及模製材料137具有共面上表面。
接著，在圖27中，將半導體封裝160接合至導電柱109，以形成具有PoP結構的半導體元件500。導電接合件168形成於半導體封裝160與導電柱109之間。用於形成半導體元件500的處理與上文參考圖10所論述的彼等相同或類似，因此細節不再贅述。
藉由將預製金屬箔107附接至晶粒130的背側，本揭露的方法免除在載體101上方形成(例如，藉由PVD、CVD)金屬箔的需要。由於金屬箔(例如，銅箔)及載體101(例如，玻璃載體)可具有不同熱膨脹係數(coefficients of thermal expansion；CTE)，本揭露的方法減小或避免在製造期間由CTE失配引起的半導體元件500的彎曲。
圖28根據一些實施例說明構造半導體元件的方法3000的流程圖。應理解，圖28中所示的實施例方法僅為多個可能實施例方法中的實例。一般熟習此項技術者將認識到許多改變、替代方案以及修改。舉例而言，可添加、移除、置換、重新配置以及重複如圖28中所說明的各種步驟。
參考圖28，在步驟3010處，金屬箔附接至載體，其中在附接金屬箔之前預製金屬箔。在步驟3020處，於金屬箔的位於載體遠側的第一側上形成導電柱。在步驟3030處，半導體晶粒附接至金屬箔的第一側。在步驟3040處，於半導體晶粒及導電柱周圍形成模製材料。在步驟3050處，於模製材料上方形成重佈線結構。
實施例可取得下列優點。所揭露實施例中的每一者在所形成的半導體元件中形成積體散熱片(例如，金屬箔或金屬膏)。半導體元件的內置式散熱片促進晶粒130的熱耗散，因此藉由例如允許晶粒130中的電路的較高積體密度或藉由允許晶粒130在較高時脈頻率下運行來改良晶粒130的效能。另外，所揭露的方法可藉由使用預成型金屬箔代替在半導體元件製造期間形成(例如，藉由CVD、PVD)金屬層來減少製造成本及時間。額外優勢可包含減少半導體元件的彎曲。
在一實施例中，一種形成半導體元件的方法包含：將金屬箔附接至載體，其中金屬箔是在附接金屬箔之前預製；在金屬箔遠離載體的第一側上形成導電柱；將半導體晶粒附接至金屬箔的第一側；在半導體晶粒及導電柱周圍形成模製材料；以及在模製材料上方形成重佈線結構。在一實施例中，所述方法更包含在附接半導體晶粒之後及形成模製材料之前，執行蝕刻製程，其中蝕刻製程減 小導電柱的寬度。在一實施例中，蝕刻製程為濕式蝕刻製程。在一實施例中，蝕刻製程移除側向設置在導電柱與半導體晶粒之間之部分的金屬箔，且其中在半導體晶粒與載體之間之剩餘部分的金屬箔的的寬度小於半導體晶粒的寬度。在一實施例中，附接金屬箔包含使用黏著層將金屬箔附接至載體，其中所述方法更包含在形成重佈線結構之後移除載體以暴露黏著層。在一實施例中，所述方法更包含在移除載體之後移除黏著層，其中在移除黏著層之後，暴露遠離重佈線結構之導電柱的上表面及遠離重佈線結構之模製材料的上表面；以及將半導體封裝接合至導電柱的上表面。在一實施例中，所述方法更包含在移除載體之後，在黏著層中形成開口，開口暴露遠離重佈線結構之導電柱的上表面；以及將半導體封裝接合至導電柱。在一實施例中，所述方法更包含在附接金屬箔之前在載體上方形成介電層，所述金屬箔附接至所述介電層。在一實施例中，附接半導體晶粒包含使用介電層將半導體晶粒附接至金屬箔的第一側，其中介電層的熱導率在約0.2W/(m-k)至約10W/(m-k)之間。
在一實施例中，形成半導體元件的方法包含：在載體的第一側上方形成導電柱；將晶粒的背側附接至載體的第一側；在晶粒及導電柱周圍形成模製材料；在晶粒、導電柱以及模製材料上方形成重佈線結構；移除載體，其中在移除載體之後，暴露遠離重佈線結構之導電柱的第一表面；在晶粒的背側上方形成散熱片；以及將半導體封裝接合至導電柱的第一表面，散熱片在半導體封裝與晶粒之間。在一實施例中，形成散熱片包含在晶粒的背側上方沈積導熱材料。在一實施例中，導熱材料的熱導率在約100W/(m-k)與約 400W/(m-k)之間。在一實施例中，形成散熱片包含在晶粒的背側上方形成金屬膏。在一實施例中，附接晶粒的背側包含使用晶粒貼合膜(DAF)將晶粒的背側附接至載體的第一側面，其中金屬膏形成於DAF上方。在一實施例中，附接晶粒的背側包含使用晶粒貼合膜(DAF)將晶粒的背側附接至載體的第一側，其中所述方法更包括在移除載體之後，移除DAF以暴露晶粒的背側，其中金屬膏形成於晶粒的背側上。在一實施例中，散熱片接觸面向晶粒之半導體封裝的第一側。
在一實施例中，半導體元件包含：重佈線結構；晶粒，其中晶粒的第一側附接至重佈線結構的第一側；模製材料，在重佈線結構的第一側面及晶粒周圍；以及散熱片，附接至與晶粒的第一側相對的晶粒的第二側，其中遠離重佈線結構之散熱片的第一側比遠離重佈線結構之模製材料的第一表面更接近重佈線結構。在一實施例中，散熱片為金屬箔。在一實施例中，半導體元件更包含第一介電層，附接至散熱片的第一側，其中遠離散熱片之第一介電層的第一表面與模製材料的第一表面齊平。在一實施例中，第一介電層的熱導率在約1W/(m-k)與約10W/(m-k)之間。
前文概述若干實施例的特徵，使得熟習此項技術者可更佳地理解本揭露的態樣。熟習此項技術者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他處理程序及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且熟習此項技術者可在不脫離本揭露的精神及範疇的情況下在本文中進行改變、替代及更改。

Claims (14)

  1. 一種形成半導體元件的方法，包括：金屬箔附接至載體，其中所述金屬箔是在附接所述金屬箔之前預製；在所述金屬箔遠離所述載體的第一側上形成導電柱；將半導體晶粒附接至所述金屬箔的所述第一側；在所述半導體晶粒及所述導電柱周圍形成模製材料；以及在所述模製材料上方形成重佈線結構。
  2. 如申請專利範圍第1項所述的形成半導體元件的方法，更包括：在附接所述半導體晶粒之後及形成所述模製材料之前，執行蝕刻製程，其中所述蝕刻製程減小所述導電柱的寬度。
  3. 如申請專利範圍第2項所述的形成半導體元件的方法，其中所述蝕刻製程為濕式蝕刻製程；或其中所述蝕刻製程移除側向設置在所述導電柱與所述半導體晶粒之間之部分的所述金屬箔，且其中在所述半導體晶粒與所述載體之間之剩餘部分的所述金屬箔的寬度小於所述半導體晶粒的寬度。
  4. 如申請專利範圍第1項所述的形成半導體元件的方法，其中附接所述金屬箔包括使用黏著層將所述金屬箔附接至所述載體，其中所述方法更包括在形成所述重佈線結構之後移除所述載體以暴露所述黏著層。
  5. 如申請專利範圍第4項所述的形成半導體元件的方法，其中所述方法更包括：在移除所述載體之後移除所述黏著層，其中在移除所述黏著層之後，暴露遠離所述重佈線結構之所述導電柱的上表面及遠離所述重佈線結構之所述模製材料的上表面；以及將半導體封裝接合至所述導電柱的上表面。
  6. 如申請專利範圍第4項所述的形成半導體元件的方法，更包括：在移除所述載體之後，在所述黏著層中形成開口，所述開口暴露遠離所述重佈線結構之所述導電柱的上表面；以及將半導體封裝接合至所述導電柱。
  7. 如申請專利範圍第1項所述的形成半導體元件的方法，其中所述形成半導體元件的方法更包括在附接所述金屬箔之前，在所述載體上方形成介電層，所述金屬箔附接至所述介電層；或其中附接所述半導體晶粒包括使用介電層將所述半導體晶粒附接至所述金屬箔的所述第一側，其中所述介電層的熱導率在約0.2W/(m-k)至約10W/(m-k)之間。
  8. 一種形成半導體元件的方法，包括：在載體的第一側上方形成導電柱；使用晶粒貼合膜，將晶粒的背側附接至所述載體的所述第一側；在所述晶粒與所述導電柱周圍形成模製材料；在所述晶粒、所述導電柱以及所述模製材料上方形成重佈線結構；移除所述載體，其中在移除所述載體之後，暴露遠離所述重佈線結構之所述導電柱的第一表面；在所述晶粒的所述背側上的所述晶粒貼合膜上方形成散熱片；以及將半導體封裝接合至所述導電柱的所述第一表面，所述散熱片在所述半導體封裝與所述晶粒之間，其中所述散熱片與所述半導體封裝之間具有間隔。
  9. 一種形成半導體元件的方法，包括：在載體的第一側上方形成導電柱；使用晶粒貼合膜，將晶粒的背側附接至所述載體的所述第一側；在所述晶粒與所述導電柱周圍形成模製材料；在所述晶粒、所述導電柱以及所述模製材料上方形成重佈線結構；移除所述載體，其中在移除所述載體之後，暴露遠離所述重佈線結構之所述導電柱的第一表面；移除所述晶粒貼合膜以暴露所述晶粒的所述背側，其中所述模製材料具有相對的第一表面以及第二表面，其中所述第一表面比所述第二表面遠離所述重佈線結構，且所述晶粒的所述背側較所述模製材料的所述第一表面更接近所述重佈線結構；在所述晶粒的所述背側上方形成散熱片；以及將半導體封裝接合至所述導電柱的所述第一表面，所述散熱片在所述半導體封裝與所述晶粒之間。
  10. 如申請專利範圍第8項或第9項所述的形成半導體元件的方法，其中形成所述散熱片包括在所述晶粒的所述背側上方沈積導熱材料；或其中形成所述散熱片包括在所述晶粒的所述背側上方形成金屬膏；或其中所述散熱片接觸面向所述晶粒之所述半導體封裝的第一側。
  11. 如申請專利範圍第10項所述的形成半導體元件的方法，其中所述導熱材料的熱導率在約100W/(m-k)與約400W/(m-k)之間。
  12. 一種半導體元件，包括：重佈線結構；晶粒，其中所述晶粒的第一側附接至所述重佈線結構的第一側；導電柱，設置於所述重佈線結構的所述第一側上；模製材料，在所述重佈線結構的所述第一側上及所述晶粒周圍，且具有相對的第一表面以及第二表面，其中所述第一表面比所述第二表面遠離所述重佈線結構，且所述第一表面共面於所述導電柱的相對於所述重佈線結構的表面；以及散熱片，附接至與所述晶粒的所述第一側相對的所述晶粒的第二側，其中所述散熱片具有相對的第一側與第二側，所述散熱片的所述第一側比所述散熱片的所述第二側遠離所述重佈線結構，且所述散熱片的所述第一側比所述模製材料的所述第一表面更接近所述重佈線結構。
  13. 如申請專利範圍第12項所述的半導體元件，其中所述散熱片為金屬箔；或其中所述半導體元件更包括第一介電層，附接至所述散熱片的所述第一側，其中遠離所述散熱片之所述第一介電層的第一表面與所述模製材料的所述第一表面齊平。
  14. 如申請專利範圍第13項所述的半導體元件，其中所述第一介電層的熱導率在約1W/(m-k)與約10W/(m-k)之間。
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