TWI660507B - 半導體裝置與其形成方法 - Google Patents

半導體裝置與其形成方法 Download PDF

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TWI660507B
TWI660507B TW106130130A TW106130130A TWI660507B TW I660507 B TWI660507 B TW I660507B TW 106130130 A TW106130130 A TW 106130130A TW 106130130 A TW106130130 A TW 106130130A TW I660507 B TWI660507 B TW I660507B
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semiconductor
semiconductor device
fins
growth condition
substrate
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TW106130130A
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TW201839994A (zh
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李宜靜
游政衛
周立維
紫微 郭
游明華
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例揭露半導體裝置與其形成方法。半導體裝置包括基板、基板上的兩個半導體鰭狀物、以及兩個半導體鰭狀物上的半導體結構。半導體結構包含兩個下部與一上部。兩個下部分別直接位於兩個半導體鰭狀物上。上部位於兩個下部上。上部的下表面具有弧狀的剖面形狀。

Description

半導體裝置與其形成方法
本發明實施例關於半導體裝置，更特別關於磊晶結構與其形成方法。
半導體積體電路產業已經歷指數成長。積體電路材料與設計的技術進展，使每一代的積體電路比前一代的積體電路具有更小且更複雜的電路。在積體電路進化中，其功能密度(如單位晶片面積所具有的內連線裝置數目)通常隨著幾何尺寸(如製程所能產生的最小構件或線路)減少而增加。尺寸縮小的製程通常有利於增加產能及降低相關成本。尺寸縮小亦增加形成積體電路之製程複雜性。
舉例來說，當半導體裝置持續縮小，可採用磊晶的半導體材料作為應力的源極/汲極結構(如應力區)，以增加載子移動率並改善裝置效能。具有應力區的金氧半場效電晶體的形成方法，通常為磊晶成長矽以作為用於n型裝置之隆起的源極/汲極結構，以及磊晶成長矽鍺以作為用於p型裝置之隆起源極/汲極結構。為進一步改善電晶體裝置的效能，可採用多種技術調整源極/汲極結構的形狀、設置、與材料。雖然形成源極/汲極的現有方法已適用於其發展目的，但仍無法完全適用於所有方面。舉例來說，在電晶體尺寸縮小時，源極/汲極接 點電阻對電路效能的影響更加顯著。目前亟需降低源極/汲極接點的電阻，以減少能耗並增加電路速度。
本發明一實施例提供之半導體裝置，包括：基板；兩個半導體鰭狀物位於基板上；以及半導體結構位於兩個半導體鰭狀物上，其中：半導體結構包含兩個下部與上部；兩個下部分別直接位於兩個半導體鰭狀物上；上部位於兩個下部上；以及上部的下表面具有弧狀的剖面形狀。
本發明一實施例提供之半導體裝置，包括：基板；兩個半導體鰭狀物位於基板上；半導體結構位於兩個半導體鰭狀物上，其中：半導體結構包含兩個下部與上部；兩個下部分別位於兩個半導體鰭狀物上；上部位於兩個下部上，且物理連接至兩個下部；以及上部的下表面在垂直於鰭狀物長度方向的平面中具有弧狀的形狀；以及介電層位於基板上，其中介電層至少部份地圍繞半導體結構的該些兩個下部。
本發明一實施例提供之半導體裝置的形成方法，包括：提供裝置，裝置具有基板與自基板延伸的至少兩個鰭狀物；蝕刻至少兩個鰭狀物，以形成至少兩個溝槽；磊晶成長多個第一半導體結構於至少兩個溝槽中；在第一成長條件中磊晶成長多個第二半導體結構於第一半導體結構上，其中第二半導體結構橫向地合併以形成合併部份；在合併部份的厚度達到目標尺寸後，在第二成長條件中磊晶成長第二半導體結構，以形成合併部份的下表面中的弧狀形狀，且第一成長條件與第二成長條件不同；以及進行蝕刻製程，以減少第二半導體結構的寬 度。
a1、a2、d、e‧‧‧高度
b‧‧‧跨度
c‧‧‧寬度
h、v‧‧‧厚度
p‧‧‧鰭狀物間距
q‧‧‧深度
S1、S2、S3‧‧‧側部尺寸
S11、S22、S33‧‧‧高度
t‧‧‧厚度
1-1、2-2、3-3‧‧‧線段
100‧‧‧半導體裝置
102‧‧‧基板
102'、115、124‧‧‧上表面
102a、102b‧‧‧區域
104‧‧‧隔離結構
106、146‧‧‧鰭狀物
106a‧‧‧源極/汲極區
106b‧‧‧通道區
108、108a‧‧‧閘極堆疊
110‧‧‧介電層
114‧‧‧溝槽
116‧‧‧凹陷
117、125‧‧‧下表面
122、152‧‧‧磊晶結構
122L、152L‧‧‧下部
122U、152U‧‧‧上部
126、128‧‧‧導電結構
126a、128a‧‧‧阻障層
126b、128b‧‧‧導體
127‧‧‧溝槽
130‧‧‧層間介電層
150‧‧‧虛線
200‧‧‧方法
202、204、206、208、210、212、214、216‧‧‧步驟
第1A、1B、1C、1D、與1E圖係本發明多種實施例中，半導體裝置的剖視圖。
第2圖係本發明多種實施例中，半導體裝置的形成方法其流程圖。
第3圖係一實施例中，依據第2圖之方法製作之半導體裝置於製程的中間階段之透視圖。
第4A、4B、4C、5A、5B、5C、6A、6B、7A、7B、8A、8B、9A、9B、10A、10B、11A、11B、12A、12B、13A、與13B圖係一些實施例中，依據第2圖之方法形成之目標半導體裝置的剖視圖。
下述揭露內容提供許多不同實施例或實例以實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明的多個實例可採用重複標號及/或符號使說明簡化及明確，但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對 用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
本發明多種實施例關於半導體裝置與其形成方法。特別的是，本發明實施例關於包含場效電晶體(如具有鰭狀通道之場效電晶體，即鰭狀場效電晶體)其隆起的源極/汲極結構之形成方法。在一些實施例中，本發明提供之隆起的源極/汲極結構由多重磊晶結構合併而成，其中隆起的源極/汲極結構具有弧狀下表面。此外，隆起的源極/汲極結構可具有平坦或近似平坦的上表面。在蝕刻隆起的源極/汲極結構以形成導電結構(如源極/汲極接點)時，弧狀下表面可讓隆起的源極/汲極結構具有大體積，有助於降低隆起的源極/汲極結構以及導電結構之將的界面電阻。
第1A圖係本發明多種實施例中，半導體裝置100的剖視圖。半導體裝置100可為積體電路製程之中間裝置或其部份，其可包含靜態隨機存取記憶體及/或邏輯電路；被動構件如電阻、電容、或電感；主動構件如p型場效電晶體、n型場效電晶體、鰭狀場效電晶體、金氧半場效電晶體、與互補式金氧半電晶體、雙極性電晶體、高壓電晶體、高頻電晶體；其他記憶單元；或上述之組合。此外，本發明多種實施例中提供多種結構包含電晶體、鰭狀物、閘極堆疊、裝置區、或其他結構以簡化並有助於理解，但這些結構並未限縮實施例至任何種類的裝置、任何數目的裝置、任何數目的區域、或任何結構或區域的設置方式。即使多種實施例以鰭狀場效電晶體作說明，其他 實施例中的半導體裝置100亦可為平面的場效電晶體裝置或其他多閘裝置。
第1A圖係半導體裝置100之源極/汲極區的剖視圖。如第1A圖所示的此實施例中，半導體裝置100包含基板102、基板102上的隔離結構104、以及基板102上的多個鰭狀物106(第1A圖中的數目為2個)。鰭狀物106的沿著長軸方向延伸，且長軸垂直於x-z平面。雖然未圖示，但部份的鰭狀物106可突出高於隔離結構104。在此實施例中，半導體裝置100包含磊晶結構122。磊晶結構122包含上部122U與下部122L(第1A圖中的數目為2個)。下部122L位於個別的鰭狀物106上，且鰭狀物側壁的介電層110圍繞至少部份的下部122L。在此實施例中，沿著z方向(鰭狀物高度的方向)之下部122L，低於鰭狀物側壁的介電層110。下部122L經由上部122U彼此物理連接。上部122U之上表面124平坦或近似平坦。在一實施例中，上表面124實質上平行於基板102的上表面102'。在此實施例中，上部122U的下表面125在x-z平面的剖視圖為弧狀。半導體裝置100的多種結構將進一步說明如下。
在此實施例中，基板102為矽基板。在其他實施例中，基板102可包含另一半導體元素如鍺；半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；半導體合金如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或上述之組合。在又一實施例中，基板102為絕緣層上半導體，比如具有埋置介電層。在實施例中，基板102包含用以形成主動裝置的主動區，比如p型井與n型井。
鰭狀物106可為用於形成p型場效電晶體的p型鰭狀物，或用於形成n型場效電晶體的n型鰭狀物。鰭狀物106可與基板102包含實質上相同的半導體材料。雖然未圖示於第1A圖中，每一鰭狀物106包含兩個源極/汲極區與夾設其中的一個通道區。第1A圖係沿著半導體裝置100之鰭狀物106的一源極/汲極區之剖視圖。鰭狀物106之間隔有隔離結構104。隔離結構104可包含氧化矽、氮化矽、氮氧化矽、摻雜氟的矽酸鹽玻璃、低介電常數之介電材料、及/或其他合適的絕緣材料。在一些實施例中，隔離結構104可為淺溝槽隔離結構。介電層110位於隔離結構上，並與鰭狀物106的源極/汲極區相鄰。介電層110至少部份地圍繞下部122L。在一實施例中，介電層110包括氮化物如氮化矽、氮氧化矽、或氮碳化矽。上部122U位於介電層110與下部122L上。
在一實施例中，下部122L與上部122U各自包含摻雜n型摻質如磷或砷的矽，以用於形成n型場效電晶體裝置。此外，上部122U比下部122L包含較高濃度的n型摻質。在一例中，上部122U包含摻雜磷的矽，其摻雜濃度介於1e21cm-3至5e21cm-3之間；而下部122L包含摻雜磷的矽，其摻雜濃度介於1e20cm-3至1e21cm-3之間。在另一實施例中，下部122L與上部各自包含摻雜p型摻質如硼或銦的矽鍺，以用於形成p型場效電晶體裝置。在一實施例中，上部122U比下部122L包含較高濃度的p型摻質。
在第1A圖所示的實施例中，沿著鰭狀物之寬度方向(比如x方向)的鰭狀物106具有鰭狀物間距p。鰭狀物間距p亦 為下部122L的間距。在實施例中，鰭狀物間距p可依製程節點調整，以形成磊晶結構122的特定形狀。若鰭狀物間距p過小，則上部122U可能在磊晶製程中的早期合併，並傾向成長為菱形，而非具有平坦上表面與弧狀下表面的形狀。若鰭狀物間距p過大，則上部122U可能無法合併。在一例中，鰭狀物間距p調整為介於30nm至50nm之間。此外，上部122U具有垂直的厚度h(沿著z方向)，其為下表面125之弧狀峰至上表面124之間的距離。在一例中，厚度h介於25nm至55nm之間。在多種實施例中，介電層110之高度d(沿著z方向)介於5nm至25nm之間。如下述說明，高度d對磊晶結構122的多種形狀與尺寸造成影響。每一下部122L沿著x方向的寬度c，係由近似下部122L的半高處量測。在一些實施例中，寬度c可介於6nm至15nm之間。此外，一些實施例中的每一下部122L其沿著z方向的高度e，可介於3nm至15nm之間。
如第1A圖所示，上部122U、側壁的介電層110、與隔離結構104之間具有空間。層間介電層可完全或部份地填入這些空間(未圖示於第1A圖中，但可參考第13A圖中的層間介電層130)。在一實施例中，層間介電層與側壁的介電層110包含不同的材料。舉例來說，層間介電層可包含四乙氧基矽烷氧化物、摻雜或未摻雜的矽酸鹽玻璃、或熔融氧化矽玻璃，而側壁的介電層110包含氮化物。
弧狀的下表面125可朝遠離基板102的方向向上延伸，如第1A圖所示。在另一實施例中，弧狀的下表面125可朝基板102的方向向下延伸，如第1D圖所示並說明如下。在此實 施例中，上述弧沿著x方向具有跨度b，且沿著z方向具有高度a1。在鰭狀物間距p介於30nm至50nm之間的例子中，跨度b介於約20nm至40nm之間，且高度a1介於約0至10nm之間。在此實施例中，下表面125具有淺弧狀，比如弧的高度/跨度比例(a1/b)小於0.5。在一實施例中，上述比例a1/b小於0.25。小的高度/跨度比例之優點與效應，將搭配第1B圖進一步清楚說明。
如第1B圖所示的一實施例中，半導體裝置100更包含導電結構126形成於磊晶結構122上。特別是在此實施例中，導電結構將部份地埋置於磊晶結構122的上部122U中。在此實施例中，導電結構126包含阻障層126a與阻障層126a上的導體126b(如金屬)。舉例來說，導體126b可包含鋁、鎢、銅、鈷、上述之組合、或其他合適材料。阻障層126a可包含金屬氮化物如氮化鉭或氮化鈦。導電結構126可包含額外層狀物。在另一實施例中，導電結構126包含摻雜的多晶矽。導電結構126可為源極/汲極接點或源極/汲極局部內連線線路。導電結構126的形成方法包括蝕刻溝槽至磊晶結構中，並沉積導電結構126的層狀物至溝槽中。蝕刻至磊晶結構126中的溝槽可具有深度q，其小於上部122U的厚度h(沿著z方向)。在一些實施例中，深度q介於15nm至25nm之間。雖然未圖示，但一些實施例之導電結構126與磊晶結構122之間可具有矽化物結構。
在多種實施例中，導電結構126與磊晶結構122之間的大界面面積，可比習知結構具有更低的接點電阻。習知的磊晶結構通常具有菱形的剖面輪廓，且彼此之間隔離(未合併)，或者合併成尖拱狀如第1B圖所示的虛線150。隔離的磊晶 結構，無法如合併的磊晶結構一樣提供大界面面積。合併的磊晶結構若為尖拱狀，則無法在蝕刻時提供足夠體積，比如在形成用以沉積導電結構126之溝槽的蝕刻步驟。舉例來說，當磊晶結構其垂直的厚度v小於溝槽的深度q，則蝕穿磊晶結構。若蝕穿磊晶結構，導電結構126的一些區域將不會接觸磊晶結構，造成接點電阻增加。
在現今的製程節點中如電晶體形貌的深寬比增加的情況下，過蝕刻會變得更嚴重。深寬比指的是電晶體形貌峰(如閘極堆疊)的高度，與相鄰兩峰之間的空間之間的比例。在一些例子中，隨著裝置的積體程度增加，此深寬比大於或等於10。在用於源極/汲極接點或局部源極/汲極內連線線路的蝕刻時，可調整用於此過蝕刻的蝕刻化學品或蝕刻時間，使源極/汲極結構可位於電晶體形貌的底部。磊晶結構中具有尖拱可能無法提供足夠的的體積以承受過蝕刻。相反地，弧狀的下表面125與高度/跨度比例小(如小於或等於0.25)，有利於增加合併的磊晶結構122之體積以承受過蝕刻。
第1C圖係另一實施例之半導體裝置100，其下表面125為平坦或近似平坦。此實施例的其他方面與第1B圖相同或類似。
第1D圖係又一實施例之半導體裝置100，其下表面125為向下延伸的弧狀。弧沿著x方向具有跨度b，且沿著z方向具有高度a2。在一些實施例中，弧的高度/跨度比例(a2/b)小於0.5，比如小於0.25。在實施例中，跨度b介於20nm至40nm之間，而高度a2介於0至10nm之間。此實施例的其他方面與第1B圖相 同或類似。在第1B、1C、與1D圖中，導電結構126完全或部份地埋置於上部122U中，然而本發明實施例並不侷限於此。在一些其他實施例中，導電結構126可位於磊晶結構122的上表面124上。
第1E圖係另一實施例之半導體裝置100，其包含相鄰的區域102a與102b。區域102a包含多種鰭狀物106與磊晶結構122如前述。區域102b包含鰭狀物146與鰭狀物146上的磊晶結構152。磊晶結構152包含下部152L與下部152L上的上部152U。介電層110至少部份地圍繞下部152L。在此實施例中，下部152L低於沿著z方向之鰭狀物側壁的介電層110。上部152U位於介電層110上。在此實施例中，半導體裝置100包含導電結構128，其與磊晶結構122與152之間具有界面。導電結構128包含阻障層128a與阻障層128a上的導體128b(如金屬)。阻障層128a與導體128b可分別與前述之阻障層126a與導體126b具有相同或類似的組成。在此實施例中，磊晶結構152具有菱形的剖面輪廓，且部份的導電結構128位於磊晶結構152之側部上。特別的是此實施例中，部份的導電結構128位於磊晶結構的上部122U與152U之間，並低於磊晶結構的上部122U及/或磊晶結構的上部152U其最寬部份(沿著x方向)。在另一實施例中，區域102b可包含磊晶結構，其形狀與磊晶結構122類似(比如具有平坦或近似平坦的上表面與弧狀的下表面)。在一實施例中，區域102a中的結構形成n型電晶體(如n型金氧半電晶體)，而區域102b中的結構形成p型電晶體(如p型金氧半電晶體)。在其他實施例中，區域102a中的結構形成p型電晶體(如p型金氧半電 晶體)，而區域102b中的結構形成n型電晶體(如n型金氧半電晶體)。
第2圖係本發明多種實施例中，形成半導體裝置(如半導體裝置100)之方法200的流程圖。方法200僅用以舉例，而非侷限本發明至申請專利範圍未實際限縮的內容。在方法200之前、之中、與之後可進行額外步驟，且其他實施例可取代、省略、或調整方法200的一些步驟。在本發明多種實施例中，將搭配第3至13B圖中半導體裝置100的透視圖與剖視圖說明方法200。
在第2圖之方法200的步驟202中，在中間製程階段接收半導體裝置100。第3圖係此半導體裝置100的透視圖。第4A、4B、與4C圖為此製程階段後，半導體裝置100分別沿著第3圖之線段1-1、2-2、與3-3的剖視圖。線段1-1沿著鰭狀物106之源極/汲極區中的x-z面切割半導體裝置100。線段2-2沿著鰭狀物106之長度方向的x-y面切割半導體裝置100。線段3-3沿著鰭狀物106之外的y-z面切割半導體裝置100。如第3、4A、4B、與4C圖所示，半導體裝置100包含基板102、基板102上的隔離結構104、以及自基板102延伸穿過隔離區104的兩個鰭狀物106。兩個鰭狀物106各自具有兩個源極/汲極區106a與夾設於源極/汲極區106a之間的通道區106b。半導體裝置100更包含閘極堆疊108緊鄰鰭狀物106的通道區106b。特別的是，閘極堆疊108緊鄰鰭狀物106的多重側壁，以形成多閘極裝置(此例為鰭狀場效電晶體)。
鰭狀物106的製作方法可採用合適製程，包括光微 影與蝕刻製程。光微影製程可包含形成光阻於基板102上、對光阻曝光圖案、進行曝光後烘烤製程、以及顯影光阻以形成含光阻的遮罩單元。接著採用遮罩單元並蝕刻凹陷至基板102中，以保留鰭狀物106於基板102上。蝕刻製程可包含乾蝕刻、濕蝕刻、反應性離子蝕刻、及/或其他合適製程。舉例來說，乾蝕刻製程可採用含氧氣體、含氟氣體(如CF4、SF6、CH2F2、CHF3、及/或C2F6)、含氯氣體(如Cl2、CHCl3、CCl4、及/或BCl3)、含溴氣體(如HBr及/或CHBr3)、含碘氣體、其他合適氣體及/或電漿、或上述之組合。舉例來說，濕蝕刻製程可包含在下述濕式蝕刻劑中進行蝕刻：稀氫氟酸、氫氧化鉀溶液、氨、含氫氟酸、硝酸、及/或醋酸的溶液、或其他合適的濕式蝕刻劑。鰭狀物106的形成方法亦可採用雙重圖案化的微影製程。用以形成鰭狀物106的方法之多種其他實施例可為合適方法。
隔離結構104的形成方法可為蝕刻溝槽於基板102中，比如鰭狀物106之形成製程的一部份。接著可將隔離材料填入溝槽，再進行化學機械研磨製程。此外亦可採用其他隔離結構如場氧化物、局部氧化矽、及/或其他合適結構。隔離結構104可包含多層結構，比如具有一或多個熱氧化襯墊層。
閘極堆疊108包含閘極介電層與閘極層。閘極介電層可包含氧化矽或高介電常數介電材料如氧化鉿、氧化鋯、氧化鑭、氧化鈦、氧化釔、或鈦酸鍶。閘極介電層的形成方法可為化學氧化、熱氧化、原子層沉積、化學氣相沉積、及/或其他合適方法。在一實施例中，閘極層包含多晶矽，且其形成方法可為合適沉積製程如低壓化學氣相沉積或電漿增強化學氣 相沉積。在一些實施例中，閘極層包含n型或p型功函數層與金屬填充層。舉例來說，n型功函數層可為具有足夠低的有效功函數的金屬如鈦、鋁、碳化鉭、氮碳化鉭、氮化鉭矽、或上述之組合。舉例來說，p型功函數層可為具有足夠高的有效功函數的金屬如氮化鈦、氮化鉭、釕、鉬、鎢、鉑、或上述之組合。舉例來說，金屬填充層可包含鋁、鎢、鈷、銅、及/或其他合適材料。閘極層的形成方法可為化學氣相沉積、物理氣相沉積、電鍍、及/或其他合適製程。在一些實施例中，閘極堆疊108為犧牲閘極結構，比如用於最終閘極堆疊的占位者。在一些實施例中，閘極堆疊108包含界面層於閘極介電層與鰭狀物106之間。界面層可包含介電材料如氧化矽或氮氧化矽，且其形成方法可為化學氧化、熱氧化、原子層沉積、化學氣相沉積、及/或其他合適介電物的形成方法。閘極堆疊108可包含其他層如硬遮罩層。
在第2圖之方法200的步驟204中，形成介電層110於個別源極/汲極區106a中的鰭狀物106之側壁上。第5A、5B、與5C圖為此製程階段後，半導體裝置100分別沿著第3圖之線段1-1、2-2、與3-3的剖視圖。如第5A、5B、與5C圖中，介電層110可包含單層或多層結構，且可包含介電材料如氮化矽或氮氧化矽。介電層110的形成方法可為化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、熱沉積、或其他合適方法。在此實施例中，介電層110亦可位於閘極堆疊108的側壁上。在一實施例中，步驟204包含在沉積製程後進行蝕刻製程。舉例來說，可毯覆性地沉積介電材料於半導體裝置100上，以覆蓋隔離結 構104、鰭狀物106、與閘極堆疊108。接著可進行非等向蝕刻製程，以自隔離結構104、鰭狀物106、與閘極堆疊108的上表面移除部份的介電材料，以保留部份的介電材料於鰭狀物106及閘極堆疊108的側壁上，此即介電層110。在實施例中，鰭狀物106之側壁上的介電層110其高度近似於5nm至25nm之間。
在第2圖之方法200之步驟206中，選擇性地蝕刻鰭狀物106的源極/汲極區106a以形成溝槽114於其中。第6A與6B圖為此製程階段後，半導體裝置100分別沿著第3圖之線段1-1與2-2的剖視圖。如第6A與6B圖所示，此實施例蝕刻鰭狀物106至低於隔離結構104的上表面。步驟206可包含一或多道的光微影製程與蝕刻製程。舉例來說，光微影製程可形成遮罩單元，以覆蓋半導體裝置100不需蝕刻的部份。遮罩單元提供開口，可用以蝕刻鰭狀物106。鰭狀物106的蝕刻方法可為乾蝕刻製程、濕蝕刻製程、或其他蝕刻技術。在此實施例中，蝕刻製程係選擇性地調整以移除鰭狀物106的材料，且實質上不改變閘極堆疊108、介電層110、與隔離結構104。步驟206形成四個溝槽114於兩個閘極堆疊108的每一側上。每一溝槽114可具有錐形的剖面輪廓(在x-z面中)，其底部寬度大於頂部寬度。在此蝕刻製程後，可採用清潔化學品進行清潔製程以清潔溝槽114，使溝槽中的多種表面準備好進行後續的磊晶成長製程。清潔化學品可為氫氟酸溶劑、稀釋的氫氟酸溶液、或其他合適的清潔溶液。
在第2圖之方法200的步驟208中，分別成長四個磊晶結構的下部122L至四個溝槽114的每一者中，如第7A與7B圖 所示。磊晶結構122L部份地填入個別溝槽114中。磊晶成長製程可為採用矽為主的前驅物之低壓化學氣相沉積製程、選擇性磊晶成長製程、或循渾沉積與蝕刻製程。舉例來說，矽結晶的成長方法可為採用二氯矽烷(SiH2Cl2)的低壓化學氣相沉積。在另一例中，矽鍺結晶的形成方法可為採用氯化氫作為蝕刻氣體，並採用鍺烷(GeH4)與氫(H2)的氣體混合物(包含約1%至約10%的GeH4於H2中)作為沉積氣體的循環沉積與蝕刻製程。介電層110的高度調整為促進成長磊晶結構的下部122L至所需高度，而不會有太多的橫向成長。在多種實施例中，磊晶結構的下部122L成長的高度介於3nm至15nm之間。磊晶結構的下部122L包含的半導體材料，適於形成隆起的源極/汲極結構。在一實施例中，磊晶結構的下部122L包含摻雜一或多種p型摻質如硼或銦的矽鍺。在一實施例中，磊晶結構的下部122L包含摻雜一或多種n型摻質如磷或砷的矽。可在磊晶成長製程時進行臨場摻雜，或者另外進行非臨場摻雜。
在第2圖之方法200之步驟210中，成長磊晶結構的上部122U於磊晶結構的下部122L上(見第8A與8B圖)。在此實施例中，磊晶結構的上部122U其成長的半導體材料與下部122L相同，差別在兩者的摻質濃度不同。舉例來說，磊晶結構的下部122L與上部122U可各自包含摻雜n型摻質的矽，但磊晶結構的上部122U具有較高濃度的n型摻質。在另一例中，磊晶結構的下部122L與上部122U可各自包含摻雜p型摻質的矽鍺，但磊晶結構的上部122U具有較高濃度的p型摻質。與磊晶結構的下部122L之形成方法類似，磊晶結構的上部122U之形成方法可採 用低壓化學氣相沉積、選擇性磊晶成長、或循環沉積與蝕刻技術。第8A與8B圖為此製程階段中，半導體裝置100分別沿著第3圖之線段1-1與2-2的剖視圖。
如第8A與8B圖所示，磊晶結構的上部122U填入個別溝槽114中的剩餘空間，並在成長超出個別溝槽114時進一步橫向擴大。由於磊晶結構122沿著不同晶向(比如矽結晶的晶向[100]、[111]、與[110])的成長速率不同，當磊晶結構的上部122U成長的更高更寬時將開始合併，如第8A圖所示。如第8A圖所示，磊晶結構的上部122U合併成相連的磊晶結構，其亦稱作磊晶結構的上部122U以方便說明。磊晶結構的上部122U其合併部份在近似中間處具有垂直的厚度t，且在合併部份的相反兩側上具有側部尺寸S1(自第6A圖之溝槽114的側壁沿著x方向量測而得)。
在製程階段中，磊晶結構的上部122U不具有平坦的上表面與淺弧狀的下表面。相反地，上部122U具有弧狀的上表面115及凹陷116，以及具有大高度/跨度比例之上凹狀的下表面117。舉例來說，下表面117的高度/跨度比例大於0.5。本發明實施例發現在相同的磊晶成長條件下成長磊晶結構的上部122U，不會使其具有平坦的上表面與淺弧狀的下表面。
在第2圖之方法200的步驟212中，改變磊晶結構的上部122U之成長條件，並持續成長磊晶結構的上部122U，使其具有第9A圖所示之實質上平坦的上表面124與淺弧狀的下表面125。第9A圖係半導體裝置100沿著第3圖之線段1-1的剖視圖。第9B圖係此製程階段中，半導體裝置100沿著第3圖之線段 2-2的剖視圖。磊晶結構的上部122U在鰭狀物106之上表面下具有高度S11，且在鰭狀物106之上表面上具有高度S22。在多種實施例中，高度S11可大於、小於、或等於高度S22。在一實施例中，高度S11介於45nm至65nm之間。在一實施例中，當磊晶結構的上部122U其合併部份達到目標尺寸時，方法200自步驟210切換至步驟212。舉例來說，當上部122U沿著x方向的橫向尺寸達到至少1.5倍的鰭狀物間距p，或者上部122U的垂直厚度t達到目標尺寸的範圍(比如5nm至10nm之間)，即可進行上述切換。
在一實施例中，步驟212與步驟210採用不同的沉積前驅物或不同的蝕刻氣體。在另一實施例中，步驟212與步驟210採用不同的蝕刻氣體(種類或數量)，採用相同的沉積前驅物。在另一實施例中，步驟212與210的溫度不同。步驟212其成長條件造成的晶向[100]與[111]的成長速率比例，大於步驟210其晶向[100]與[111]的成長速率比例。舉例來說，步驟210可調整為傾向在晶向[111]成長，以形成磊晶結構122的合併部份。步驟212可調整為傾向在晶向[100]成長，以填入凹陷116與下表面117(見第8A圖)。本發明實施例發現達到上述結構的多種條件。舉例來說，當溫度介於650℃至720℃之間時，沿著晶向[100]的結晶矽其成長速率，大於或等於沿著晶向[111]的結晶矽其成長速率。一些其他成長條件將說明如下。
在一實施例中，步驟210採用二氯矽烷(SiH2Cl2)作為前軀物，以成長磊晶結構的上部122U如矽結晶。在此實施例中，步驟212添加矽烷至前驅物中，使晶向[100]中的矽具有更 高的成長(沉積)速率。在一實施例中，矽烷為SiH4。在一實施例中，步驟中的SiH4與SiH2Cl2之比例介於約0.005至約0.05之間。在另一實施例中，步驟210與212均採用氯化氫作為蝕刻氣體，而步驟212降低氯化氫氣體的流速以降低其對[100]晶向的蝕刻效果。
在另一實施例中，步驟210採用GeH4與H2的沉積氣體與氯化氫的蝕刻氣體之混合物，以成長磊晶結構的上部122U如矽鍺結晶。在此實施例中，步驟212降低氯化氫的流速，使[100]晶向中的矽鍺比其他晶向中的矽鍺具有更快的成長速率。在一實施例中，步驟212中的氯化氫流速介於約100標準立方公分/分鐘至約400標準立方公分/分鐘之間。
在多種實施例中，步驟210與212的壓力介於200torr至350torr之間。
藉由步驟208、210、與212的優點，半導體裝置100其隆起的源極/汲極結構(如磊晶結構122)具有淺弧狀的下表面125與平坦或近似平坦的上表面124。淺弧狀的下表面125可為第1A至1D圖所示的任何形狀。
在一實施例中，側壁的介電層110之高度亦可用以控制上部122U的體積(見步驟204的相關內容)。舉例來說，當側壁的介電層110較低，則上部122U較早合併，造成上部122U沿著z方向的厚度較大。另一方面，當側壁的介電層110較高，則上部122U較晚合併，造成上部122U沿著z方向的厚度較小。
如第9A圖所示的一些實施例中，步驟212橫向擴大磊晶結構的上部122U。舉例來說，側部尺寸S2改變成大於側部 尺寸S1。這是因為這些實施例之步驟212中的成長條件，並未完全抑制磊晶結構122沿著晶向[110]成長。在一些例子中，不需擴大側部，因為這可能縮短相鄰的源極/汲極區，造成裝置失效。舉例來說，當磊晶結構122為部份的靜態隨機存取記憶單元時，裝置密度可能高且需嚴格控制相鄰的靜態隨機存取記憶單元之間的空間。在此實施例中，第2圖之方法200進行步驟214以修整磊晶結構122的側部尺寸。
在一實施例中，步驟214對半導體裝置100進行蝕刻製程。蝕刻製程調整為縮小磊晶結構122的寬度(沿著x方向)，而不大幅影響磊晶結構122的厚度(沿著z方向)。在一實施例中，蝕刻製程採用GeH4氣體與氯化氫氣體的混合物作為蝕刻劑。在又一實施例中，蝕刻劑中GeH4與氯化氫的比例調整為介於0.5至1.2之間。舉例來說，GeH4與氯化氫的比例之調整方法，可為控制GeH4氣體與氯化氫氣體導入製程腔室中的流速，且上述兩者之流速比例介於0.5至1.2之間。可在磊晶成長磊晶結構122的相同腔室中，臨場進行上述蝕刻製程。在其他實施例中，可非臨場地進行蝕刻製程。在一實施例中，蝕刻製程的溫度可介於650℃至750℃之間，且壓力可介於5torr至100torr之間。在多種實施例中，步驟214的蝕刻化學品、溫度、與壓力可調整為減少磊晶結構122的寬度，而不明顯地減少磊晶結構122的厚度。如此一來，磊晶結構的側部尺寸將縮小至S3(S3<S2)，如第10A圖所示。在一實施例中，側部尺寸S3甚至小於側部尺寸S1。此外，在此製作階段中，磊晶結構的上部122U高出鰭狀物106之上表面的高度，因蝕刻製程而可由S22縮小至 S33(S33<S22)。在一實施例中，高度S33介於3nm至12nm之間。
在步驟216中，第2圖之方法200對半導體裝置100進行後續製程。此步驟包括多種製程。在一例中，可形成矽化物或鍺矽化物於磊晶結構的上部122U上。舉例來說，矽化物如鎳矽化物的形成方法，可為沉積金屬層於磊晶結構的上部122U上、回火金屬層使其與磊晶結構的上部122U中的矽反應形成金屬矽化物、以及之後移除未反應的金屬層。
在另一例中，步驟216將閘極堆疊108置換為最終的閘極堆疊108a，如第11B圖所示。在此例中，第3至10B圖的閘極堆疊108為占位者，其具有虛置的閘極介電層(如氧化矽)與虛置的閘極層(如多晶矽)；而閘極堆疊108a為高介電常數之介電層與金屬閘極的組合，其具有高介電常數的閘極介電層、適當n型或p型功函數的層狀物、以及金屬填充層。高介電常數之閘極介電層、功函數層、以及金屬填充層可採用合適材料，如上述第3圖的相關內容。在此例中，步驟216可沉積層間介電層130於基板102上以覆蓋基板上的形貌(見第11A與11B圖)。層間介電層130可包含的材料為四乙氧矽烷的氧化物、摻雜或未摻雜的矽酸鹽玻璃、熔融氧化矽玻璃、及/或其他合適的介電材料。層間介電層130的沉積方法可為電漿增強化學氣相沉積製程、可流動的化學氣相沉積、或其他合適的沉積技術。在一些實施例中，層間介電層130可填入弧狀的下表面125、隔離結構104、與鰭狀物的兩個相對側壁之介電層110之間的空間。在其他實施例中，層間介電層130可不流動至上述空間中，以形成孔洞(或開口)於弧狀的下表面125下。在一些實施例中，在沉 積層間介電層130之前，可先沉積接點蝕刻停止層(未圖示)於磊晶結構122及隔離結構104上，且接點蝕刻停止層可具有介電材料如氮化矽。在沉積層間介電層130之後，步驟216採用一或多道蝕刻製程移除閘極堆疊108，並採用一或多道沉積製程形成最終的閘極堆疊108a以取代閘極堆疊108，即得第11A與11B圖所示的半導體裝置100。
在一例中，步驟216形成導電結構126，其部份埋置於磊晶的結構的上部122U中，如第13A與13B圖所示。此步驟關於多種製程。舉例來說，步驟216可進行一或多道微影製程與蝕刻製程以形成穿過層間介電層130的溝槽127(或接觸孔)，如第12A與12B圖所示。溝槽127露出磊晶結構的上部122U。若在磊晶結構122U上進行矽化製程，則溝槽127露出磊晶結構122U上的矽化物或鍺矽化物。在此實施例中，溝槽127延伸於磊晶結構的上部122U中且具有深度q。在高密度積體電路中，裝置形貌的深寬比(比如閘極堆疊108a的高度與相鄰之閘極堆疊之間相隔的距離之間的比例)可高達超過10：1。為確保橫越積體電路之寬廣區域的導電結構126與磊晶結構122之間的接觸良好，在形成溝槽127時需進行過蝕刻。舉例來說，積體電路在此處之溝槽其深度q可介於15nm至25nm之間。在習知裝置中，磊晶結構的下表面為尖拱狀，如第12A圖所示之虛線150，而溝槽127穿過磊晶結構。上述習知結構會縮小導電結構126與磊晶結構之間的界面面積。在此實施例中，磊晶結構122形成以具有淺弧狀的下表面125，有利於增加磊晶結構122的厚度h。在多種實施例中，厚度h設計為大於溝槽的深度q。舉例 來說，厚度h設計為大於或等於25nm。在一實施例中，步驟216可進一步形成矽化物或鍺矽化物於磊晶結構122U的露出部份上。舉例來說，矽化物的形成方法可為沉積金屬層(如鎳)於磊晶結構122U的露出部份上，回火金屬層使金屬層與磊晶結構122U中的矽反應形成金屬矽化物，之後再移除未反應的金屬層。
步驟216接著沉積阻障層126a於溝槽127的側壁與底部上，以避免導體126b的材料擴散至相鄰結構中。在不同實施例中，上述溝槽127的底部可包含或不含矽化物。在一例中，阻障層包含介電材料如氮化鉭或氮化鈦。步驟216接著沉積導體126b如金屬，以填入溝槽127中的剩餘空間。在此實施例中，導電結構126包含阻障層126a與導體126b。沉積阻障層與金屬層的方法，可採用順應性或非順應性的沉積製程。磊晶結構的上部122U其大體積，造成導電結構126與下方的磊晶結構的上部122U之間的大界面，有利於降低源極/汲極接點電阻。形成第1E圖所示之結構的方法，同樣可用於上述步驟。
本發明的一或多個實施例提供許多優點至半導體裝置與其形成方法，不過這些優點並非用於侷限本發明。舉例來說，隆起的源極/汲極結構可成長為具有淺弧狀的下表面與實質上平坦的上表面。上述結構有利於在後續製程步驟中，增加隆起的源極/汲極結構以承受過蝕刻。上述結構的實質效應為導電結構(如源極/汲極接點或源極/汲極內連線線路)與隆起的源極/汲極結構之間的界面面積增加且接點電阻降低。本發明多種實施例可簡單地整合至現有製程中。
本發明一實施例關於半導體裝置，其包括：基板；兩個半導體鰭狀物位於基板上；以及半導體結構位於兩個半導體鰭狀物上。半導體結構包含兩個下部與上部。兩個下部分別直接位於兩個半導體鰭狀物上。上部位於兩個下部上。上部的下表面具有弧狀的剖面形狀。
本發明另一實施例關於半導體裝置的形成方法，包括：提供裝置，包含基板與自基板延伸的兩個鰭狀物；蝕刻鰭狀物，以形成兩個溝槽；磊晶成長多個第一半導體結構於溝槽中；在第一成長條件中，磊晶成長多個第二半導體結構於第一半導體結構上，其中第二半導體結構橫向地合併形成合併部份；以及在合併部份的尺寸達到目標尺寸後，在第二成長條件中磊晶成長該二半導體結構，其中在第二成長條件中的第二半導體結構於晶向[100]與[111]之間的成長速率比例，大於在第一成長條件中的第二半導體結構於晶向[100]與[111]之間的成長速率比例。
本發明另一實施例關於半導體裝置的形成方法，其包括：提供裝置，裝置具有基板與自基板延伸的至少兩個鰭狀物。上述方法亦包括蝕刻至少兩個鰭狀物，以形成至少兩個溝槽；以及磊晶成長多個第一半導體結構於至少兩個溝槽中。上述方法亦包括在第一成長條件中磊晶成長多個第二半導體結構於第一半導體結構上，其中第二半導體結構橫向地合併以形成合併部份。在合併部份的厚度達到目標尺寸後，上述方法更包括在第二成長條件中磊晶成長第二半導體結構，以形成合併部份的下表面中的弧狀形狀，且第一成長條件與第二成長條 件不同。上述方法更包括進行蝕刻製程，以減少第二半導體結構的寬度。
本發明已以數個實施例揭露如上，以利本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者可採用本發明為基礎，設計或調整其他製程與結構，用以實施實施例的相同目的，及/或達到實施例的相同優點。本技術領域中具有通常知識者應理解上述等效置換並未偏離本發明之精神與範疇，並可在未偏離本發明之精神與範疇下進行這些不同的改變、置換、與調整。

Claims (15)

  1. 一種半導體裝置，包括：一基板；兩個半導體鰭狀物位於該基板上；以及一半導體結構位於該些兩個半導體鰭狀物上，其中：該半導體結構包含兩個下部與一上部；該些兩個下部分別直接位於該些兩個半導體鰭狀物上，且該些兩個下部的一中間部分具有一頂點並從該中間部分的兩側向上彎曲；該上部位於該些兩個下部上；以及該上部的下表面具有弧狀的剖面形狀。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該弧狀的剖面形狀包括朝遠離該基板的方向向上延伸的弧。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該弧其高度與跨度之間的比例小於0.5。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該弧狀的剖面形狀包含朝該基板向下延伸的弧。
  5. 如申請專利範圍第4項所述之半導體裝置，其中該弧其高度與跨度之間的比例小於0.5。
  6. 如申請專利範圍第1、2、或4項所述之半導體裝置，更包括：一導體部份地埋置於該半導體結構之上部中。
  7. 一種半導體裝置的形成方法，包括：提供一裝置，包含一基板與自該基板延伸的兩個鰭狀物；蝕刻該些鰭狀物，以形成兩個溝槽；磊晶成長多個第一半導體結構於該些溝槽中；在一第一成長條件中，磊晶成長多個第二半導體結構於該些第一半導體結構上，其中該些第二半導體結構橫向地合併形成一合併部份；以及在合併部份的尺寸達到目標尺寸後，在一第二成長條件中磊晶成長該些第二半導體結構，其中在該第二成長條件中的該些第二半導體結構於晶向[100]與[111]之間的成長速率比例，大於在該第一成長條件中的該些第二半導體結構於晶向[100]與[111]之間的成長速率比例。
  8. 如申請專利範圍第7項所述之半導體裝置的形成方法，其中第二成長條件的溫度介於650℃至720℃之間。
  9. 如申請專利範圍第7或8項所述之半導體裝置的形成方法，更包括：在該第二成長條件中磊晶成長該些第二半導體結構之後，進行一蝕刻製程以減少該些第二半導體結構的寬度。
  10. 如申請專利範圍第9項所述之半導體裝置的形成方法，其中該些第二半導體結構包括矽，該第一成長條件採用的前驅物包括二氯矽烷，且該第二成長條件添加矽烷至前驅物中。
  11. 如申請專利範圍第10項所述之半導體裝置的形成方法，其中該蝕刻製程採用的蝕刻劑包括鍺烷與氯化氫。
  12. 一種半導體裝置的形成方法，包括：提供一裝置，該裝置具有一基板與自該基板延伸的至少兩個鰭狀物；蝕刻該些至少兩個鰭狀物，以形成至少兩個溝槽；磊晶成長多個第一半導體結構於該些至少兩個溝槽中；在一第一成長條件中磊晶成長多個第二半導體結構於該些第一半導體結構上，其中該些第二半導體結構橫向地合併以形成一合併部份；在該合併部份的厚度達到一目標尺寸後，在一第二成長條件中磊晶成長該些第二半導體結構，以形成該合併部份的下表面中的一弧狀形狀，且該第一成長條件與該第二成長條件不同，其中該弧狀形狀的一中間部分具有一頂點並從該中間部分的兩側向下彎曲；以及進行一蝕刻製程，以減少該些第二半導體結構的寬度。
  13. 如申請專利範圍第12項所述之半導體裝置的形成方法，其中該些第二半導體結構包含矽，該第一成長條件採用包含二氯化矽的一前驅物，該第二成長條件採用該前驅物與矽烷，且該蝕刻製程採用的蝕刻劑包含鍺烷與氯化氫。
  14. 如申請專利範圍第13項所述之半導體裝置的形成方法，其中該蝕刻劑中的鍺烷與氯化氫之比例介於0.5至1.2之間。
  15. 如申請專利範圍第12或13項所述之半導體裝置的形成方法，更包括形成一導電結構，且該導電結構部份地埋置於該第二半導體結構中。
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