TWI648789B - 複合屏蔽自對準的溝槽mosfet及其製備方法 - Google Patents

複合屏蔽自對準的溝槽mosfet及其製備方法 Download PDF

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TWI648789B
TWI648789B TW106130228A TW106130228A TWI648789B TW I648789 B TWI648789 B TW I648789B TW 106130228 A TW106130228 A TW 106130228A TW 106130228 A TW106130228 A TW 106130228A TW I648789 B TWI648789 B TW I648789B
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燮光 雷
虹 常
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大陸商萬國半導體（澳門）股份有限公司
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Abstract

本發明係揭露一種溝槽MOSFET組件的製備方法，包含在半導體基板中，利用遮罩，同時製備一個窄溝槽和一個寬溝槽，以限定窄溝槽和寬溝槽，在半導體基板上方製備一個絕緣層，帶有填滿窄溝槽的第一部分，以及部分填充寬溝槽的第二部分，從寬溝槽上完全除去第二部分，保留用第一部分填充的窄溝槽，製備一個閘極電極，在半導體基板的頂部製備一個本體區，在一部分本體區中製備一個絕緣區，從窄溝槽上除去第一部分氮化物，並且藉由填充窄溝槽中的第二導電材料，製備一個接觸插頭。

Description

複合屏蔽自對準的溝槽MOSFET及其製備方法
本發明關於MOSFET組件，更確切地說是關於高密度溝槽MOSFET組件及其相同組件的製備方法。
場效應電晶體(FET)為半導體電晶體組件，其中電絕緣閘極所加電壓控制源極和汲極之間的電流流動。FET的一個示例是金屬氧化物半導體FET(MOSFET)，其中閘極電極藉由氧化絕緣物，與半導體本體區絕緣。通常來說，MOSFET可以具有一個平面閘極結構或溝槽閘極結構。含有溝槽閘極結構的MOSFET組件為高電流、低壓轉換應用，提供優於平面電晶體的重要優勢。MOSFET組件的溝槽閘極通常包含一個從源極延伸到汲極的溝槽，具有側壁和底面，每個都內襯一層熱生長的二氧化矽。內襯的溝槽可以用摻雜的多晶矽填充。溝槽閘極的結構允許較小收縮的電流，從而提供較低的比導通電阻值。使溝槽MOSFET具有吸引力的另一個特徵是電流垂直流經MOSFET通道，沿溝槽的垂直側壁延伸，從源極底部開始，穿過電晶體的本體，延伸到下方的汲極。這樣可以製備更小的晶胞間距，較高的晶胞密度。藉由製備更加緊密的電晶體，增大晶胞密度的問題之一在於對準公差。對準公差是在對準過 程中補償差異所需的多餘量。目前光刻技術的對準公差落在300Å-500Å或30nm-50nm的範圍內。
另外，高密度溝槽MOSFET組件通常包含一個接觸溝槽，用於接觸到源極和本體區。製備高密度溝槽MOSFET組件的傳統技術使用兩個獨立的遮罩，用於製備閘極溝槽和接觸溝槽。確切地說，利用一個閘極溝槽遮罩，製備垂直閘極溝槽。在一個單獨製程中，形成閘極溝槽之後，利用溝槽接觸遮罩，在同一個基板上製備接觸溝槽。
然而，由於尺寸越來越小的高密度MOSFET組件要求閘極溝槽和附近的接觸溝槽之間控制得當的間距，因此當使用兩個遮罩製備垂直MOSFET結構時，會發生遮罩重疊。
正是在這樣的背景下，提出了本發明的實施例。
本發明的目的在於提供一種複合屏蔽自對準的溝槽MOSFET，提出了基於自對準技術的多種方法，以解決遮罩重疊問題。
為了達到上述目的，本發明藉由以下技術方案實現：
一種溝槽MOSFET組件的製備方法，其包含下列步驟：在半導體基板中利用遮罩，同時製備交替的窄溝槽和寬溝槽，其中遮罩限定了窄溝槽和寬溝槽；在半導體基板上方製備第一絕緣層，其中第一絕緣層具有填滿窄溝槽的第一部分，以及部分填充寬溝槽的第二部分；從寬溝槽上完全除去第一絕緣層的第二部分，保留用第一 絕緣層的第一部分填充的窄溝槽；在寬溝槽中製備一個絕緣閘電極；在半導體基板的頂部中製備一個本體區；在一部分本體區中製備一個源極區；從窄溝槽上完全除去第一絕緣層的第一部分；以及藉由用導電材料填充窄溝槽製備一個導電插頭。
上述的方法中，其中利用遮罩，在半導體基板中同時製備窄溝槽和寬溝槽，包含：在半導體基板的表面上製備一個硬遮罩層；形成硬遮罩層的圖案，以製備帶有寬開口和窄開口的遮罩，對應寬溝槽和窄溝槽；以及在半導體基板中，藉由遮罩中的寬開口和窄開口，同時刻蝕窄溝槽和寬溝槽。
上述的方法中，其中硬遮罩層為氧化物-氮化物-氧化物(ONO)層。
上述的方法中，還包含沿窄溝槽和寬溝槽的內表面，在製備第一絕緣層之前，製備第二絕緣層。
上述的方法中，其中第一絕緣層包含氮化物層，第二絕緣層包含氧化物層。
上述的方法中，其中從寬溝槽上完全除去第一絕緣層的第二部分，並且保留用第一絕緣層的第一部分填充的窄溝槽，包含各向異 性刻蝕氮化層。
上述的方法中，其中製備閘極電極包含：將寬溝槽刻蝕到預設的深度，其中第一絕緣層的第一部分保護窄溝槽不被刻蝕；以及在寬溝槽中填充導電材料。
上述的方法中，其中閘極電極包含多晶矽。
上述的方法中，還包含沿寬溝槽的內表面，在導電材料填充寬溝槽之前，製備一個閘極絕緣層。
上述的方法中，其中從窄溝槽上除去絕緣層的第一部分，包含：在第一絕緣層的第一部分和閘極電極上方，製備一個第二絕緣層；藉由接觸遮罩中的開口刻蝕第二絕緣層；從窄溝槽上刻蝕第一絕緣層的第一部分；以及注入摻雜物，在窄溝槽的底部附近形成一個接觸區。
上述的方法中，其中製備接觸插頭包含：用勢壘材料內襯窄溝槽的內表面；用導電材料填充窄溝槽的剩餘部分；以及回刻導電材料。
上述的方法中，其中勢壘材料為鈦(Ti)或氮化鈦(TiN)。
上述的方法中，其中導電材料包含鎢(W)。
上述的方法中，還包含在接觸插頭和電介質層上方製備一個金屬層，其中金屬層與導電插頭電接觸。
上述的方法中，其中金屬層為鋁(Al)或鋁銅(AlCu)或AlSi或AlSiCu。
一種溝槽MOSFET組件，其包含：一個半導體基板；一個窄溝槽，在半導體基板中，到第一預設深度；一個寬溝槽，在半導體基板中，到第二預設深度；一個本體區，在半導體基板頂部；以及一個源極區，在一部分本體區中，其中窄溝槽和寬溝槽之間的間距不依賴於寬溝槽和窄溝槽之間的對準公差，並且受光刻分辨率限制。
上述的組件中，其中光刻分辨率約為10nm至50nm。
本發明與習知技術相比具有以下優點：藉由基於自對準技術的多種方法，以解決遮罩重疊問題。
100‧‧‧MOSFET組件
102‧‧‧半導體基板
104‧‧‧硬遮罩
104a‧‧‧底部氧化層
104b‧‧‧氮化層
104c‧‧‧頂部氧化層
106‧‧‧接觸溝槽
108‧‧‧閘極溝槽
110‧‧‧氧化層
112‧‧‧氮化層
112a‧‧‧氮化物
114‧‧‧閘極氧化層
116‧‧‧閘極多晶矽結構
118‧‧‧本體區
120‧‧‧源極區
122‧‧‧電介質層
124‧‧‧接觸區
126‧‧‧勢壘金屬
128‧‧‧導電材料
130‧‧‧金屬層
圖1A至圖1T表示本發明的一個實施例，MOSFET組件的閘極溝槽和接觸溝槽的製備技術的剖面示意圖。
以下結合圖式，藉由詳細說明一個較佳的具體實施例，對 本發明做進一步闡述。
本發明提出了基於自對準技術的多種方法，以解決遮罩重疊問題。提出的一種方法包含利用交替的氧化物和氮化物閉鎖平面或側壁墊片的各種結構，創建自對準到閘極溝槽的接觸遮罩。提出的另一種方法利用一個遮罩，限定閘極和接觸溝槽，在閘極溝槽的刻蝕過程中，保護帶有抗蝕性的接觸溝槽。抗蝕劑為了填充接觸溝槽，避免進入閘極溝槽，閘極和接觸溝槽不能排佈過密，閘極和接觸溝槽之間的間距至少為兩個對準公差。從而藉由接觸溝槽和閘極溝槽之間的對準公差，限制本發明方法中的晶胞間距。
本發明的各個方面提出了使用一種單獨的遮罩，限定閘極和接觸溝槽的技術。另外，本發明的各個方面允許接觸和閘極溝槽之間的間距僅由光致抗蝕劑工具的性能限定。依據本發明的一個實施例，圖1A至圖1T表示一種表示製備技術。
如圖1A所示，為一MOSFET組件100的初始形態，該技術使用一個半導體基板102作為初始材料。在一些實施例中，基板102可以是N-型矽晶圓，對於N-通道組件來說，帶有N-型外延層生長在它上面，對於P-通道組件來說，帶有P-型外延層生長在它上面。利用習知技術，在半導體基板102的表面上，製備一個硬遮罩104。在一些實施例中，硬遮罩104可以是氧化物-氮化物-氧化物(ONO)層。更確切地說，硬遮罩104包含兩種不同絕緣物材料的交替層，每個都可以抵抗刻蝕另一個的刻蝕技術。ONO層104包含從底部到頂部：一個底部氧化層104a、一個氮化層104b和一個頂部氧化層104c。然後，在ONO層104上使用光致抗蝕劑(圖中沒有表示出)，並形成圖案，以限定接觸和閘極溝槽。帶圖案的光致抗蝕劑包含在接觸溝槽和閘極溝槽位置處的開 口。如圖1B所示，進行ONO刻蝕，刻蝕掉在光致抗蝕劑中藉由開口暴露於刻蝕劑的那部分ONO層104。除去光致抗蝕劑之後，ONO層104的剩餘部分用作遮罩，向下刻蝕下方的半導體基板102的未覆蓋部分，以便同時製備交替的接觸溝槽106和閘極溝槽108，如圖1C所示。半導體製備領域中的通常知識者應能理解，鑒於矽刻蝕負載因子的特性，較寬的溝槽開口產生比較窄的溝槽開口更深的溝槽。由於閘極溝槽開口比接觸開口更寬，所製成的閘極溝槽108比接觸溝槽106刻蝕得更深，如圖1C所示。然後，沿溝槽的內表面生長一個絕緣屏蔽氧化層110，如圖1D所示。屏蔽氧化層110用作在後續過程中氮刻蝕的刻蝕終點。
然後，如圖1E所示，沉積一個氮化層112，其中窄溝槽(即接觸溝槽106)完全填滿，但寬溝槽(即閘極溝槽108)不完全填滿。根據接觸溝槽的寬度，氮化層112的厚度必須足夠厚，才能填充接觸溝槽，但沒有完全填充閘極溝槽108。在一些實施例中，對於0.1μm至0.5μm深的接觸溝槽來說，氮化層111的厚度可以在500Å至2000Å左右。放置氮化物之後，進行各向異性刻蝕，如圖1F所示，從寬溝槽(即閘極溝槽108)上除去所有的氮化物，但保留氮化物112a填充的窄溝槽(即接觸溝槽106)。屏蔽氧化層110作為氮化物的刻蝕終點。此後，在圖1G中，除去屏蔽氧化層110。在圖1H中，進行閘極溝槽上的刻蝕。在半導體基板102中刻蝕閘極溝槽108到更深處，同時用接觸溝槽106中的氮化物112a保護接觸溝槽106不被閘極溝槽刻蝕。而且，雖然上述示例包含氧化層110和氮化物材料112a，但是本發明所屬領域中的通常知識者應理解起作用的是一個絕緣層110可抵抗刻蝕其他絕緣層112的刻蝕過程，反之亦然。
然後，生長出一個犧牲氧化層(圖中沒有表示出)，並除去，以改善矽表面。如圖1I所示，在溝槽108的側壁和底部，形成一個 閘極氧化層114。放置導電材料填充在溝槽中。在一些實施例中，導電材料可以是原位摻雜或未摻雜的多晶矽。導電材料的厚度要足夠完全填滿閘極溝槽108。如圖1J所示，回刻導電材料，形成閘極多晶矽結構116。在一些實施例中，閘極多晶矽結構116的表面可以凹陷到半導體基板102頂部下方的0.05μm至0.2μm左右。
如圖1K和圖1L所示，分別進行本體注入和本體擴散。對本體注入，使用本體遮罩(圖中沒有表示出)。在圖1K中，將摻雜物注入到半導體基板102的頂部。摻雜離子的導電類型與基板102的摻雜類型相反。在一些實施例中，對於N-通道組件來說，摻雜離子可以是硼離子。在一些實施例中，對於P-通道組件來說，摻雜離子可以是磷或砷離子。如圖1L所示，利用熱激活摻雜原子，驅使摻雜物擴散，形成本體區118。
然後，如圖1M和圖1N所示，分別進行源極注入和源極擴散。在圖1M所示的源極注入中，對於帶有源極遮罩(圖中沒有表示出)的源極注入來說，進行大傾斜角注入。在一些實施例中，對於N-通道組件來說，注入砷離子，形成源極區。還可選擇，對於P-通道組件來說，注入硼離子，形成源極區。如圖1N所示，進行標準的擴散技藝，在本體區118內構成源極區120。
如圖1O所示，在半導體基板102上方，放置一個電介質層122，例如氧化物。在一些實施例中，藉由低溫氧化物技藝和一層含有硼酸的矽玻璃(BPSG)，製備電介質層122。
在電介質層122上，使用接觸光致抗蝕劑(圖中沒有表示出)，並利用未覆蓋接觸溝槽106的開口形成圖案。如圖1P所示，回刻電介質層122未被覆蓋的部分，氮化物112a的表面作為刻蝕終點，使刻 蝕停止。在圖1Q中，除去接觸溝槽中氮化物112a。利用接觸注入的標準技術，在接觸溝槽106的底部附近形成接觸區124，如圖1R所示，從而使接觸區124更加重摻雜。進行後續刻蝕，沿接觸溝槽106的內表面除去屏蔽氧化層110，如圖1S所示。
然後，如圖1T所示，首先用勢壘金屬126內襯接觸溝槽106的內表面。在一些實施例中，勢壘金屬可以是鈦(Ti)或氮化鈦(TiN)。導電材料128(例如鎢(W))可以在接觸溝槽106中層沉積，隨後向上回刻到電介質層122的表面，以形成導電插頭128，如圖1T所示。最後，在半導體基板102上方沉積一個金屬層130，如圖1T所示。在一些實施例中，金屬層130可以是鋁(Al)或鋁銅(AlCu)。
本發明的各個方面使用一個單獨的遮罩，在半導體基板中同時製備一個接觸溝槽106和一個閘極溝槽108，如圖1B和1C所示。另外，本發明的各個方面提出了在額外的閘極溝槽刻蝕過程中，取消對接觸溝槽106提供額外保護的必要性，其原因在於較窄的接觸溝槽106仍然用電介質材料(氮化物112a)填充，而藉由各向異性的回刻，除去閘極溝槽108中的電介質材料，如圖1E和1F所示。另外，本發明的各個方面允許接觸溝槽和閘極溝槽之間的較小間距，僅由光刻的分辨率限制，並且允許製備高密度MOSFET組件。目前光刻技術的分辨率範圍為5nm至20nm。
儘管本發明關於某些較佳的版本已經做了詳細的敘述，但是仍可能存在各種不同的修正、變化和等效情況。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的申請專利範圍及其全部等效內容。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲 明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個項目的數量。除非用“意思是”明確指出限定功能，否則所附的申請專利範圍並不應認為是意義-加-功能的侷限。

Claims (16)

  1. 一種溝槽MOSFET組件的製備方法，其包含下列步驟：在半導體基板中利用遮罩，同時製備交替的窄溝槽和寬溝槽，其中遮罩限定了窄溝槽和寬溝槽；在半導體基板上方製備第一絕緣層，其中第一絕緣層具有填滿窄溝槽的第一部分，以及部分填充寬溝槽的第二部分；從寬溝槽上完全除去第一絕緣層的第二部分，保留用第一絕緣層的第一部分填充的窄溝槽；在寬溝槽中製備一個絕緣閘電極；在半導體基板的頂部中製備一個本體區；在一部分本體區中製備一個源極區；從窄溝槽上完全除去第一絕緣層的第一部分；以及藉由用導電材料填充窄溝槽製備一個導電插頭，並且該導電插頭電接觸源極區。
  2. 如申請專利範圍第1項所述之製備方法，其中利用遮罩，在半導體基板中同時製備窄溝槽和寬溝槽，包含：在半導體基板的表面上製備一個硬遮罩層；形成硬遮罩層的圖案，以製備帶有寬開口和窄開口的遮罩，對應寬溝槽和窄溝槽；以及在半導體基板中，藉由遮罩中的寬開口和窄開口，同時刻蝕窄溝槽和寬溝槽。
  3. 如申請專利範圍第2項所述之製備方法，其中硬遮罩層為氧化物-氮化物-氧化物(ONO)層。
  4. 如申請專利範圍第1項所述之製備方法，其更包含沿窄溝槽和寬溝槽的內表面，在製備第一絕緣層之前，製備第二絕緣層。
  5. 如申請專利範圍第1項所述之製備方法，其中第一絕緣層包含氮化物層，第二絕緣層包含氧化物層。
  6. 如申請專利範圍第1項所述之製備方法，其中從寬溝槽上完全除去第一絕緣層的第二部分，並且保留用第一絕緣層的第一部分填充的窄溝槽，包含各向異性刻蝕氮化層。
  7. 如申請專利範圍第1項所述之製備方法，其中製備閘極電極包含：將寬溝槽刻蝕到預設的深度，其中第一絕緣層的第一部分保護窄溝槽不被刻蝕；以及在寬溝槽中填充導電材料。
  8. 如申請專利範圍第7項所述之製備方法，其中閘極電極包含多晶矽。
  9. 如申請專利範圍第7項所述之製備方法，其更包含沿寬溝槽的內表面，在導電材料填充寬溝槽之前，製備一個閘極絕緣層。
  10. 如申請專利範圍第1項所述之製備方法，其中從窄溝槽上除去絕緣層的第一部分，包含：在第一絕緣層的第一部分和閘極電極上方，製備一個第二絕緣層；藉由接觸遮罩中的開口刻蝕第二絕緣層；從窄溝槽上刻蝕第一絕緣層的第一部分；以及注入摻雜物，在窄溝槽的底部附近形成一個接觸區。
  11. 如申請專利範圍第1項所述之製備方法，其中製備接觸插頭包含：用勢壘材料內襯窄溝槽的內表面；用導電材料填充窄溝槽的剩餘部分；以及回刻導電材料。
  12. 如申請專利範圍第11項所述之製備方法，其中勢壘材料為鈦(Ti)或氮化鈦(TiN)。
  13. 如申請專利範圍第11項所述之製備方法，其中導電材料包含鎢(W)。
  14. 如申請專利範圍第1項所述之製備方法，其更包含在接觸插頭和電介質層上方製備一個金屬層，其中金屬層與導電插頭電接觸。
  15. 如申請專利範圍第14項所述之製備方法，其中金屬層為鋁(Al)或鋁銅(AlCu)或AlSi或AlSiCu。
  16. 一種溝槽MOSFET組件，其包含：一個半導體基板；一個窄溝槽，在半導體基板中，到第一預設深度；一個寬溝槽，在半導體基板中，到第二預設深度；一個本體區，在半導體基板頂部；以及一個源極區，在一部分本體區中，其中窄溝槽和寬溝槽之間的間距不依賴於寬溝槽和窄溝槽之間的對準公差，並且受光刻分辨率限制；其中光刻分辨率約為10nm至50nm。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10714580B2 (en) * 2018-02-07 2020-07-14 Alpha And Omega Semiconductor (Cayman) Ltd. Source ballasting for p-channel trench MOSFET
US11251297B2 (en) 2018-03-01 2022-02-15 Ipower Semiconductor Shielded gate trench MOSFET devices
US10777661B2 (en) 2018-03-01 2020-09-15 Ipower Semiconductor Method of manufacturing shielded gate trench MOSFET devices
US10998438B2 (en) 2018-03-01 2021-05-04 Ipower Semiconductor Self-aligned trench MOSFET structures and methods
CN110379850B (zh) * 2018-04-13 2023-01-31 璟茂科技股份有限公司 沟槽式功率晶体管制法
CN109119477B (zh) * 2018-08-28 2021-11-05 上海华虹宏力半导体制造有限公司 沟槽栅mosfet及其制造方法
US11469313B2 (en) 2020-01-16 2022-10-11 Ipower Semiconductor Self-aligned trench MOSFET and IGBT structures and methods of fabrication
CN113540234A (zh) * 2020-04-10 2021-10-22 南京紫竹微电子有限公司 自对准的沟槽式场效应晶体管及其制备方法
CN113394184B (zh) * 2021-06-09 2022-06-17 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080179662A1 (en) * 2007-01-28 2008-07-31 Force-Mos Technology Corporation Closed trench MOSFET with floating trench rings as termination
US20110233667A1 (en) * 2010-03-24 2011-09-29 Alpha And Omega Semiconductor Incorporated Dual gate oxide trench mosfet with channel stop trench and three or four masks process
US20150115356A1 (en) * 2013-10-30 2015-04-30 Infineon Technologies Ag Method for Manufacturing a Vertical Semiconductor Device and Vertical Semiconductor Device

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7151036B1 (en) 2002-07-29 2006-12-19 Vishay-Siliconix Precision high-frequency capacitor formed on semiconductor substrate
US6538300B1 (en) 2000-09-14 2003-03-25 Vishay Intertechnology, Inc. Precision high-frequency capacitor formed on semiconductor substrate
US6509233B2 (en) 2000-10-13 2003-01-21 Siliconix Incorporated Method of making trench-gated MOSFET having cesium gate oxide layer
US6838722B2 (en) 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
US20050280133A1 (en) 2004-06-21 2005-12-22 Alpha & Omega Semiconductor Multiple device package
US7667264B2 (en) 2004-09-27 2010-02-23 Alpha And Omega Semiconductor Limited Shallow source MOSFET
DE102004057791B4 (de) 2004-11-30 2018-12-13 Infineon Technologies Ag Trenchtransistor sowie Verfahren zu dessen Herstellung
US7285822B2 (en) 2005-02-11 2007-10-23 Alpha & Omega Semiconductor, Inc. Power MOS device
US8362547B2 (en) 2005-02-11 2013-01-29 Alpha & Omega Semiconductor Limited MOS device with Schottky barrier controlling layer
US7449354B2 (en) 2006-01-05 2008-11-11 Fairchild Semiconductor Corporation Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch
KR100745917B1 (ko) 2006-01-23 2007-08-02 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US8236651B2 (en) 2009-08-14 2012-08-07 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET device and fabrication
US8193580B2 (en) 2009-08-14 2012-06-05 Alpha And Omega Semiconductor, Inc. Shielded gate trench MOSFET device and fabrication
US7902597B2 (en) 2006-03-22 2011-03-08 Samsung Electronics Co., Ltd. Transistors with laterally extended active regions and methods of fabricating same
US7767526B1 (en) 2009-01-29 2010-08-03 Alpha & Omega Semiconductor Incorporated High density trench MOSFET with single mask pre-defined gate and contact trenches
TWI396240B (zh) * 2009-05-08 2013-05-11 Anpec Electronics Corp 製造功率半導體元件的方法
US8299494B2 (en) 2009-06-12 2012-10-30 Alpha & Omega Semiconductor, Inc. Nanotube semiconductor devices
US7910486B2 (en) 2009-06-12 2011-03-22 Alpha & Omega Semiconductor, Inc. Method for forming nanotube semiconductor devices
US20110049580A1 (en) 2009-08-28 2011-03-03 Sik Lui Hybrid Packaged Gate Controlled Semiconductor Switching Device Using GaN MESFET
US8252647B2 (en) 2009-08-31 2012-08-28 Alpha & Omega Semiconductor Incorporated Fabrication of trench DMOS device having thick bottom shielding oxide
US8187939B2 (en) * 2009-09-23 2012-05-29 Alpha & Omega Semiconductor Incorporated Direct contact in trench with three-mask shield gate process
US8431457B2 (en) * 2010-03-11 2013-04-30 Alpha And Omega Semiconductor Incorporated Method for fabricating a shielded gate trench MOS with improved source pickup layout
US8367501B2 (en) * 2010-03-24 2013-02-05 Alpha & Omega Semiconductor, Inc. Oxide terminated trench MOSFET with three or four masks
US8669613B2 (en) 2010-09-29 2014-03-11 Alpha & Omega Semiconductor, Inc. Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method
US9246347B2 (en) 2010-09-29 2016-01-26 Alpha And Omega Semiconductor Incorporated Battery charging circuit with serial connection of MOSFET and an enhancement mode JFET configured as reverse blocking diode with low forward voltage drop
US8580667B2 (en) 2010-12-14 2013-11-12 Alpha And Omega Semiconductor Incorporated Self aligned trench MOSFET with integrated diode
US8476676B2 (en) 2011-01-20 2013-07-02 Alpha And Omega Semiconductor Incorporated Trench poly ESD formation for trench MOS and SGT
US8933506B2 (en) 2011-01-31 2015-01-13 Alpha And Omega Semiconductor Incorporated Diode structures with controlled injection efficiency for fast switching
US8431470B2 (en) 2011-04-04 2013-04-30 Alpha And Omega Semiconductor Incorporated Approach to integrate Schottky in MOSFET
US8502302B2 (en) 2011-05-02 2013-08-06 Alpha And Omega Semiconductor Incorporated Integrating Schottky diode into power MOSFET
US9171917B2 (en) 2011-05-31 2015-10-27 Alpha And Omega Semiconductor Incorporated Edge termination configurations for high voltage semiconductor power devices
US8829603B2 (en) 2011-08-18 2014-09-09 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET package
US8759908B2 (en) 2011-11-01 2014-06-24 Alpha And Omega Semiconductor Incorporated Two-dimensional shielded gate transistor device and method of manufacture
US20130224919A1 (en) 2012-02-28 2013-08-29 Yongping Ding Method for making gate-oxide with step-graded thickness in trenched dmos device for reduced gate-to-drain capacitance
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
US9230957B2 (en) 2013-03-11 2016-01-05 Alpha And Omega Semiconductor Incorporated Integrated snubber in a single poly MOSFET
US9136377B2 (en) 2013-03-11 2015-09-15 Alpha & Omega Semiconductor, Inc. High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method
US9887283B2 (en) 2013-05-10 2018-02-06 Alpha And Omega Semiconductor Incorporated Process method and structure for high voltage MOSFETs
US9755052B2 (en) 2013-05-10 2017-09-05 Alpha And Omega Semiconductor Incorporated Process method and structure for high voltage MOSFETS
US9123805B2 (en) 2013-11-14 2015-09-01 Alpha And Omega Semiconductor Incorporated Method to manufacture short channel trench MOSFET
US9190478B2 (en) 2013-12-22 2015-11-17 Alpha And Omega Semiconductor Incorporated Method for forming dual oxide trench gate power MOSFET using oxide filled trench
US9595587B2 (en) 2014-04-23 2017-03-14 Alpha And Omega Semiconductor Incorporated Split poly connection via through-poly-contact (TPC) in split-gate based power MOSFETs
US9570460B2 (en) * 2014-07-29 2017-02-14 Sandisk Technologies Llc Spacer passivation for high-aspect ratio opening film removal and cleaning
CN104241386B (zh) * 2014-09-25 2017-02-01 无锡新洁能股份有限公司 具有低特征导通电阻的功率mosfet器件及其制造方法
US9484452B2 (en) 2014-12-10 2016-11-01 Alpha And Omega Semiconductor Incorporated Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs
US9281368B1 (en) 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080179662A1 (en) * 2007-01-28 2008-07-31 Force-Mos Technology Corporation Closed trench MOSFET with floating trench rings as termination
US20110233667A1 (en) * 2010-03-24 2011-09-29 Alpha And Omega Semiconductor Incorporated Dual gate oxide trench mosfet with channel stop trench and three or four masks process
US20150115356A1 (en) * 2013-10-30 2015-04-30 Infineon Technologies Ag Method for Manufacturing a Vertical Semiconductor Device and Vertical Semiconductor Device

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