TWI633492B - 接觸式智慧卡、身份識別卡、銀行卡、智慧卡觸板及接觸式智慧卡的製造方法 - Google Patents
接觸式智慧卡、身份識別卡、銀行卡、智慧卡觸板及接觸式智慧卡的製造方法 Download PDFInfo
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- TWI633492B TWI633492B TW103113387A TW103113387A TWI633492B TW I633492 B TWI633492 B TW I633492B TW 103113387 A TW103113387 A TW 103113387A TW 103113387 A TW103113387 A TW 103113387A TW I633492 B TWI633492 B TW I633492B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
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- G06K19/02—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the selection of materials, e.g. to avoid wear during transport through the machine
- G06K19/022—Processes or apparatus therefor
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- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
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Abstract
本發明涉及接觸式智慧卡、使用該卡的用戶身份識別卡、銀行卡、智慧卡觸板、及防止或限止該觸板的非貴金屬晶片端子連接表面氧化的方法。本發明實施例提供的接觸式智慧卡包括智慧卡觸板和集成電路晶片。智慧卡觸板包括電路基板、設於電路基板的第一側的讀卡器接觸元件、以及設於電路基板的背對第一側的第二側的晶片連接元件。讀卡器接觸元件具有貴金屬導電表面,晶片連接元件具有非貴金屬的晶片端子連接表面。集成電路晶片裝設於電路基板的第二側並與晶片端子連接表面電連接。
Description
本發明涉及具有智慧卡觸板和集成電路晶片的接觸式智慧卡、具有該種智慧卡的用戶身份識別卡(SIM)和/或銀行卡、防止或限制該種智慧卡觸板的非貴金屬晶片端子連接表面氧化的方法、以及該智慧卡觸板。
智慧卡觸板已衆所周知並被應用於移動通訊設備中的用戶身份識別卡(SIM)、銀行卡以及其他領域中。該種被熟知的觸板在兩側(讀卡器接觸側和晶片安裝側)覆蓋有金。金提供了抗腐蝕和抗氧化的特性,並實現晶片安裝側與所用的集成電路(IC)晶片之間的引線鍵合連接(wire-bonded connections)。
然而,在智慧卡觸板的兩側均使用貴金屬增加了製造成本,並且加速了寶貴自然資源的消耗。
因此,本發明力圖提供一種解決這個問題的方案。
本發明的一方面提供一種接觸式智慧卡,包括智慧卡觸板和集成電路晶片。所述智慧卡觸板包括電路基板、設於所述電路基板的第一側的讀卡器接觸元件、以及設於所述電路基板的背對所述第一側的第二側的晶片連接元件。所述讀卡器接觸元件具有貴金屬導電表面,所述晶片連接元件具有非貴金屬的晶片端子連接表面,所述集成電路晶片裝設於所述電路基板的第二側並與所述晶片端子連接表面電連接。
較佳的,所述貴金屬是金或者含金。
較佳的,還包括覆蓋所述晶片端子連接表面和所述貴金屬導電表面至少其中之一的至少一個腐蝕保護層。
較佳的,所述至少一個腐蝕保護層或每個所述腐蝕保護層是有機金屬導電層。
較佳的,所述至少一個腐蝕保護層或每個所述腐蝕保護層是基於巰基的。
較佳的,所述至少一個腐蝕保護層或每個所述腐蝕保護層是自組裝單層。
較佳的,所述集成電路晶片被倒裝式安裝於所述晶片連接元件。
較佳的,還包括連接所述集成電路晶片和所述晶片連接元件的多數個導電凸起。
較佳的,所述凸起為尖頭的或扁平的。
較佳的,所述凸起設於所述晶片連接元件的第一層上。
本發明的另一方面提供一種用戶身份識別卡,包括載板和上述任一種接觸式智慧卡,所述智慧卡由所述載板承載。
本發明的再一方面提供一種銀行卡,包括載板和上述任一種接觸式智慧卡,所述智慧卡由所述載板承載。
本發明的第四方面提供一種防止或限制智慧卡觸板的非貴金屬晶片端子連接表面氧化的方法,包括步驟:在使用倒裝晶片安裝技術安裝集成電路晶片之前,在整個非貴金屬晶片端子連接表面上形成有機導電腐蝕保護層。
較佳的,所述腐蝕保護層連續覆蓋在整個非貴金屬晶片端子連接表面上從而形成連接不斷的覆蓋隔離層。
本發明的第五方面提供一種智慧卡觸板,包括電路基板以及由所述電路基板承載的電路,所述電路包括設於所述電路基板的第一側的讀卡器接觸元件、以及設於所述電路基板的背對所述第一側的第二側的晶片連接元件。所述讀卡器接觸元件具有貴金屬導電表面,所述晶片連接元件具有非貴金屬的晶片端子連接表面。
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。
10,100,101‧‧‧智慧卡觸板
200,300‧‧‧集成電路晶片
12‧‧‧電路基板
14‧‧‧讀卡器接觸元件
16‧‧‧讀卡器接觸側
18‧‧‧晶片連接元件
36‧‧‧晶片端子連接表面
138,148‧‧‧腐蝕保護層
204,304‧‧‧凸起
19‧‧‧導電線路
20‧‧‧晶片安裝側
21‧‧‧晶片的端子
22‧‧‧柔性塑膠載體條
23‧‧‧觸板端子
24‧‧‧基板側導電層
26,126‧‧‧中間導電層
28,128‧‧‧外部導電層
30‧‧‧讀卡器接觸表面
32‧‧‧第二基板側導電層
34‧‧‧第二外部導電層
140‧‧‧材料
142‧‧‧外表面
144‧‧‧自組裝單層
146‧‧‧覆蓋隔離表面
150‧‧‧滾動傳輸系統
152,154‧‧‧步驟
160‧‧‧粘合劑
202,302‧‧‧焊盤
C1-C8‧‧‧觸體
第1圖顯示了本發明第一實施例提供的智慧卡觸板。
第2圖顯示了第1圖所示的智慧卡觸板的讀卡器接觸側。
第3圖顯示了第1圖所示的智慧卡觸板的倒裝晶片安裝側。
第4圖是第2圖所示智慧卡觸板的沿線A-A的截面圖。
第5圖示出本發明第二實施例提供的智慧卡觸板的截面圖。
第6圖是智慧卡觸板的滾動式製造方法的流程圖。
第7圖示出依據第5圖的智慧卡觸板以及以一種方法倒裝式安裝的集成電路晶片的截面示意圖。
第8圖示出依據第5圖的智慧卡觸板以及以另一種方法倒裝式安裝的集成電路晶片的截面示意圖。
下麵結合圖式對本發明進行詳細說明。
參考第1圖到第4圖,本發明第一實施例的智慧卡觸板10包括電路基板12。電路基板12具有背對而設的讀卡器接觸側16和晶片安裝側20。電路基板12的讀卡器接觸側16設有讀卡器接觸元件14。電路基板12的晶片安裝側20設有晶片連接元件18(較佳的為倒裝晶片連接元件)。電路基板12較佳的為柔性的和/或可成像的。電路基板12可以印刷有電路、或者可以印刷電路或者可以附加電路。
較佳的,電路基板12是例如可由聚對苯二甲酸乙二醇酯(PET)形成的柔性塑膠載體條22,厚度在55到95微米之間(更佳的為75微米)。柔性塑膠載體條22可以是可透光的。在本實施例中載體條22是透明的。
電路基板12是可成像的,即基板能在其表面或內部承載或
具有電路圖形。特別地,電路基板12較佳的為印刷電路薄膜,但也可使用可形成電路圖形的其他類型的基板。
儘管電路基板較佳的是柔性的,但也可以使用非柔性的電路基板。
讀卡器接觸元件14包括若干導電覆蓋層(較佳採用電鍍方式形成),包括基板側導電層24,中間導電層26、及外部導電層28。基板側導電層24形成在電路基板12的讀卡器接觸面16上。本實施例中,基板側導電層24由銅構成或含銅。基板側導電層24的厚度較佳的在5微米到25微米之間,更佳的,是或大約是10微米。
中間導電層26形成在基板側導電層24上。在本實施例中,中間導電層26由鎳組成或包含鎳的成分。中間導電層26與基板側導電層24連續不斷的接觸,較佳厚度在1微米到4微米之間,更佳的是2.5微米或大約2.5微米。
外部導電層28形成在中間導電層26上,從而形成讀卡器接觸表面30。本實施例中,導電層28由金構成或含金。類似地,該外部導電層28與中間導電層26連續不斷的接觸,較佳厚度在0.02微米到0.08微米之間,更佳的,是或大約是0.045微米。
本實施例中,讀卡器接觸元件14的各層都較佳的為金屬材質。根據需要,還可以設置更多中間層。
讀卡器接觸元件14設有觸體(contact)C1-C8。較佳採用蝕刻的工藝形成所述觸體。在本實施例中,濕法蝕刻工藝可被方便地使用。雖然本實施例提供了8個觸體,但也可根據需要使用多於或少於8個觸體。
示例性的對本實施例中各觸體C1-C8的功能描述如下。第一觸體C1,被稱為電源位(VCC),用於接電源,為卡中的微處理晶片供電;第二觸體C2,被稱為複位鍵(RST),用作複位元功能,介面設備可通過此觸體向智慧卡的微處理晶片發出信號啟動複位元指令序列;第三觸體C3,被稱為時鐘信號位(CLK),通過此觸體可將時鐘信號提供到微處理晶片,控制運行速度以及為介面設備與智慧卡之間的數據通信提供共同的架構;第四觸體C4,被稱為預留功能位(RFU),是為將來使用預留的;第五
觸體C5,被稱為接地位(GND),用於在介面設備和智慧卡之間提供公共地;第六觸體C6,被稱為編程電壓位(VPP),提供編程電源連接用於對第一代智慧卡的電可擦只讀存儲器(EEPROM)進行編程;第七觸體C7,也叫輸入/輸出位(I/O),作為輸入/輸出埠,在讀卡器和智慧卡之間提供半雙工傳輸通信通道;第八觸體C8,也是預留功能位(RFU),是為未來使用預留出來的。可以重新配置觸體C1-C8以便提供替代的功能,或者也可以根據需要互換各個觸體的功能。
晶片連接元件18也包括若干導電覆蓋層,該若干導電覆蓋層形成導電線路19,該導電線路19從集成電路(IC)晶片的端子21延伸到觸板端子23,觸板端子23穿過柔性塑膠載體條22到達對應的觸體C1-C8,可以採用電鍍的工藝方便地形成導電覆蓋層。電路基板12的晶片安裝側20形成第二基板側導電層32。在本實施例中導電層32由銅構成或含銅。第二基板側導電層32的厚度較佳的在5微米到25微米之間,更佳的,是或大約是10微米。
第二外部導電層34形成在第二基板側導電層32上,從而形成晶片端子連接表面36。在本實施例中第二外部導電層34由鎳構成或含鎳,而不是由金構成或含金。第二外部導電層34與第二基板側導電層32連續不斷地接觸,厚度較佳的在1微米到4微米之間,更佳的,是或大約是2.5微米。
儘管本實施例中讀卡器接觸表面30是金的或者含金(主要因為金對環境物質的低反應性以及其具有的美感),但是其他任何合適的導電貴金屬(較佳如鉑一樣的貴金屬),都可以考慮使用。同樣的,連接集成電路(IC)晶片端子的晶片端子連接表面36可以是鎳的或含鎳。當然,也可以使用其他任何合適的抗腐蝕抗氧化的導電性非貴金屬。
較佳的,可以使用倒裝晶片安裝方式將集成電路(IC)晶片的各端子安裝到晶片端子連接表面36上。可以理解,也可使用其他安裝方式。集成電路晶片的主體可粘結到電路基板12。
參考第5圖,本發明第二實施例的智慧卡觸板10也包括電路基板12(較佳的為柔性的和/或可成像的)、電路基板12的讀卡器接觸側
16的讀卡器接觸元件14、電路基板12的晶片安裝側20的晶片連接元件18,晶片安裝側20與讀卡器接觸側16背對而設。本實施例中,使用相同的圖式標記表示與前一實施例相似或相同的特徵,並略去對相同特徵的具體描述。
晶片連接元件18包括第二基板側導電層32(較佳的由銅構成或含銅)。由鎳構成或含鎳的導電層形成第二中間導電層126。第二外部導電層128是腐蝕保護層138。本實施例中,腐蝕保護層138由有機無孔材料140(較佳的為基於巰基的材料)形成。材料140連續不斷地形成在第二中間導電層126的整個外表面142上。腐蝕保護層138可形成晶片連接元件18的一部份,或者是在晶片連接元件18上形成的獨立的結構。
腐蝕保護層138可以是自組裝單層(self-assembled mono layer)144,從而提供連續的覆蓋隔離表面146。儘管腐蝕保護層138較佳的是導電的,作為替代,視實際需要,腐蝕保護層138也可以是不導電的。
之所以推薦使用有機無孔基於巰基的材料140是因為這種材料可導電、可透射(本實施例中為透明的),且人接觸這種材料時不會過敏。這種腐蝕保護層138保持了與其覆蓋的第二中間導電層126一樣的導電性。此外,該有機金屬腐蝕保護層138緩和了形成自組裝單層144過程中產生的鎳的氧化。蠕變腐蝕是一種導致電氣元件過早損壞的已知現象,其原因在於大氣環境中彌漫著越來越多的硫化物。本發明中的腐蝕保護層138形成了一個隔離層以阻止該有害影響。一種合適的可用於此腐蝕保護層的材料可從設於美國馬薩諸賽州梅休因市的Parlex公司獲得,產品代碼為N019292。當然,也可以根據需要使用其他適合的導電性腐蝕保護材料。
雖然不是必須的,但是,在讀卡器接觸元件14的外部導電層28上覆蓋一層第二腐蝕保護層148也是有好處的。好處在於可以減小由金構成或含金的外部導電層28的厚度,同時維持外形的美觀。另外,還有一個好處就是使用這種腐蝕保護層148來降低貴金屬導電層28暴露在含硫環境中所導致的腐蝕效應。本實施例中,第二腐蝕保護層148是導電的,可具有前述的腐蝕保護層138同樣的特徵。然而,第二腐蝕保護層148不一定必須是有機金屬的。
此外,由於基板側的非貴金屬和導電層24、26通過半電池反應形成原電池(galvanic cell),第二腐蝕保護層148的使用可以減少讀卡器接觸元件14的電化屬性(galvanic nature)。
參考第6圖,較佳地,採用卷對卷工藝(roll-to-roll)以在載體條22上形成若干智慧卡觸板的方式製造該種智慧卡觸板10。柔性載體條22由滾動傳輸系統150送入,通過分級處理形成讀卡器接觸元件14和晶片連接元件18。參考步驟152和154,可以首先形成讀卡器接觸元件14和晶片連接元件18其中之一,之後形成另一個。然而,也可以在通過滾動傳輸系統150送入載體條22的過程中同時形成讀卡器接觸元件14和晶片連接元件18。
一旦例如通過衝壓從載體條22脫離,每個智慧卡觸板10可以被獨立地安裝在適當的載體上從而形成所需的智慧卡(例如電信用戶識別卡(SIM)或銀行卡)。
第7圖和第8圖示出依據本發明第二實施例的智慧卡觸板以及以兩種不同方法倒裝式安裝的集成電路晶片。
第7圖中,智慧卡觸板100具有第一倒裝晶片200。第一倒裝晶片200包括多數個焊盤202。每個晶片焊盤202連接至一個導電的柱形凸起204。較佳的,柱形凸起204是尖頭的,與晶片連接元件18點接觸而形成電連接。為防止或避免滑動,使用粘合劑160將倒裝晶片200固定至智慧卡觸板100。較佳的,粘合劑160呈糊狀或是薄膜層。較佳的,出於成本考慮,粘合劑160是不導電的。然而,即使比較貴,仍然可以使用各向異性(Z軸)的導電粘合劑。粘合劑160使柱形凸起204與晶片連接元件18保持接觸。
作為另一種選擇,可以使用第8圖所示的智慧卡觸板101。智慧卡觸板101具有第二倒裝晶片300。第二倒裝晶片300也包括多數個晶片焊盤302,每個焊盤302連接至一個導電扁平凸起304。本實施例中,扁平凸起304呈薄型,與前面的柱狀凸起204相較矮。扁平凸起304抵靠或設於晶片連接元件18的外部導電層128上,由此與最外層形成面接觸,從
而將晶片300與晶片連接元件18電連接。同樣,較佳地可使用粘合劑160固定第二倒裝晶片300,以使扁平凸起304與晶片連接元件18保持接觸。
本實施例中,柔性電路基板12的讀卡器接觸側16較佳的具有四層結構,分別是基板側導電層24、非貴金屬中間導電層26、貴金屬外部導電層28、以及第二腐蝕保護層148。
然而,由於本實施例中具有腐蝕保護層148,即使沒有非貴金屬中間導電層26,也可能有效電連接倒裝晶片300和讀卡器接觸元件14。不設非貴金屬中間導電層26可相應地降低智慧卡觸板的成本。
較佳的,如果在形成智慧卡觸板的同時將倒裝晶片200、300裝設至電路基板12,粘合劑160可代替腐蝕保護層138起到防止後續的中間導電層126被氧化或腐蝕的作用,這樣可以簡化智慧卡觸板的結構。如果粘合劑160用於此目的,那麽貴金屬外部導電層28仍然需要第二腐蝕保護層148。
由此,如果將集成電路晶片裝至晶片連接元件所使用的粘合劑滿足前面所提及的要求,那麽粘合劑160可以是合適的腐蝕保護層。
依據本發明的實施例,提供不再需要那麽多貴金屬的智慧卡觸板成為可能。進一步的,貴金屬可只使用在讀卡器接觸面。此外,提供具有非貴金屬晶片端子連接面的智慧卡觸板也成為可能,在安裝集成電路晶片IC之前,晶片端子連接面不會或基本上不會被腐蝕或氧化。
以上實施例的描述僅以一個例子說明,對於本領域的具有通常知識者來書,在不脫離本發明所附權利要求的前提下,還可以做出若干改進和變形。
Claims (15)
- 一種接觸式智慧卡,包括智慧卡觸板(10,100,101)和集成電路晶片(200,300),所述智慧卡觸板(10,100,101)包括電路基板(12)、設於所述電路基板(12)的第一側(16)的讀卡器接觸元件(14)、以及設於所述電路基板(12)的背對所述第一側(16)的第二側(20)的晶片連接元件(18);所述電路基板(12)為柔性塑料基板,所述讀卡器接觸元件(14)具有貴金屬導電表面(28),所述晶片連接元件(18)具有非貴金屬的晶片端子連接表面(36),所述集成電路晶片(200,300)裝設於所述電路基板(12)的第二側(20)並與所述晶片端子連接表面(36)電連接,所述貴金屬導電表面(28)與所述非貴金屬的晶片端子連接表面(36)採用卷對卷工藝在所述電路基板(12)上同時形成。
- 如請求項1所述的接觸式智慧卡,所述貴金屬是金或者含金。
- 如請求項1所述的接觸式智慧卡,還包括覆蓋所述晶片端子連接表面(36)和所述貴金屬導電表面(28)至少其中之一的至少一個腐蝕保護層(138,148)。
- 如請求項3所述的接觸式智慧卡,所述至少一個腐蝕保護層或每個所述腐蝕保護層(138,148)是有機金屬導電層。
- 如請求項3所述的接觸式智慧卡,所述至少一個腐蝕保護層或每個所述腐蝕保護層(138,148)是基於巰基的。
- 如請求項3所述的接觸式智慧卡,所述至少一個腐蝕保護層或每個所述腐蝕保護層(138,148)是自組裝單層。
- 如以上任一權利要求所述的接觸式智慧卡,所述集成電路晶片(200,300)被倒裝式安裝於所述晶片連接元件(18)。
- 如請求項7所述的接觸式智慧卡,還包括連接所述集成電路晶片(200,300)和所述晶片連接元件(18)的多數个導電凸起(204,304)。
- 如請求項8所述的接觸式智慧卡,所述凸起為尖頭的或扁平的。
- 如請求項9所述的接觸式智慧卡,其特徵在於,所述凸起(204,302)設於所述晶片連接元件(18)的第一層(34,128,138)上。
- 一種用戶身份識別卡,包括載板和如請求項1-10任一項所述的接觸式智慧卡,所述智慧卡由所述載板承載。
- 一種銀行卡,包括載板和如請求項1-10任一項所述的接觸式智慧卡,所述智慧卡由所述載板承載。
- 一種接觸式智慧卡的製造方法,該方法包括步驟:在電路基板(12)上採用卷對卷工藝同時形成貴金屬導電表面(28)與非貴金屬的晶片端子連接表面(36),在使用倒裝晶片安裝技術安裝集成電路晶片(200,300)之前,在整個非貴金屬晶片端子連接表面(36)上形成有機導電腐蝕保護層(138)。
- 如請求項13所述的方法,所述腐蝕保護層連續覆蓋在整個非貴金屬晶片端子連接表面(36)上從而形成連接不斷的覆蓋隔離層。
- 一種智慧卡觸板(10,100,101),包括電路基板(12)以及由所述電路基板(12)承載的電路,所述電路包括設於所述電路基板(12)的第一側(16)的讀卡器接觸元件(14)、以及設於所述電路基板(12)的背對所述第一側(16)的第二側(20)的晶片連接元件(18);所述電路基板(12)為柔性塑料基板,所述讀卡器接觸元件(14)具有貴金屬導電表面(28),所述晶片連接元件(18)具有非貴金屬的晶片端子連接表面(36),所述貴金屬導電表面(28)與所述非貴金屬的晶片端子連接表面(36)採用卷對卷工藝在所述電路基板(12)上同時形成。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6288905B1 (en) * | 1999-04-15 | 2001-09-11 | Amerasia International Technology Inc. | Contact module, as for a smart card, and method for making same |
CN1323505A (zh) * | 1998-10-15 | 2001-11-21 | 阿梅拉西亚国际技术公司 | 一种具有嵌入电子装置的物件及其制作方法 |
TW200941861A (en) * | 2007-12-10 | 2009-10-01 | Renesas Tech Corp | Sim adapter and sim card |
CN102117929A (zh) * | 2010-01-05 | 2011-07-06 | 三星Sdi株式会社 | 二次电池和智能卡 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61123990A (ja) * | 1984-11-05 | 1986-06-11 | Casio Comput Co Ltd | Icカ−ド |
FR2584235B1 (fr) * | 1985-06-26 | 1988-04-22 | Bull Sa | Procede de montage d'un circuit integre sur un support, dispositif en resultant et son application a une carte a microcircuits electroniques |
JPS6259096A (ja) * | 1985-09-10 | 1987-03-14 | カシオ計算機株式会社 | Icカ−ド |
JPH0569691A (ja) * | 1991-09-17 | 1993-03-23 | Fujitsu General Ltd | Icカード |
DE19632113C1 (de) * | 1996-08-08 | 1998-02-19 | Siemens Ag | Chipkarte, Verfahren zur Herstellung einer Chipkarte und Halbleiterchip zur Verwendung in einer Chipkarte |
DE10016715C1 (de) * | 2000-04-04 | 2001-09-06 | Infineon Technologies Ag | Herstellungsverfahren für laminierte Chipkarten |
DE10139395A1 (de) * | 2001-08-10 | 2003-03-06 | Infineon Technologies Ag | Kontaktierung von Halbleiterchips in Chipkarten |
US6433359B1 (en) * | 2001-09-06 | 2002-08-13 | 3M Innovative Properties Company | Surface modifying layers for organic thin film transistors |
KR100723491B1 (ko) * | 2005-07-14 | 2007-05-30 | 삼성전자주식회사 | 범용 인쇄 회로 기판 및 이를 사용한 스마트 카드 |
EP1785916B1 (de) * | 2005-11-14 | 2009-08-19 | Tyco Electronics France SAS | Smartcard-Körper, Smartcard und Herstellungsverfahren |
DE102006060719A1 (de) * | 2006-12-21 | 2008-06-26 | Infineon Technologies Ag | Chipkartenmodul und Verfahren zur Herstellung eines Chipkartenmoduls |
US8249655B2 (en) * | 2008-12-18 | 2012-08-21 | At&T Intellectual Property I, L.P. | Universal serial bus based subscriber identity module |
CN101770600A (zh) * | 2009-12-31 | 2010-07-07 | 北京握奇数据系统有限公司 | 一种非接触式智能卡及其制作方法 |
KR20140047077A (ko) * | 2011-06-23 | 2014-04-21 | 엑스탤릭 코포레이션 | 전착 코팅을 포함하는 인쇄 회로 기판 및 관련 물품 |
CN102395247A (zh) | 2011-10-10 | 2012-03-28 | 青岛琴岛控制器有限公司 | 单面镀金的pcb线路板 |
CN102360447A (zh) * | 2011-11-01 | 2012-02-22 | 上海祯显电子科技有限公司 | 一种薄膜基板 |
-
2014
- 2014-04-08 CN CN201420167064.6U patent/CN203894790U/zh not_active Expired - Lifetime
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1323505A (zh) * | 1998-10-15 | 2001-11-21 | 阿梅拉西亚国际技术公司 | 一种具有嵌入电子装置的物件及其制作方法 |
US6288905B1 (en) * | 1999-04-15 | 2001-09-11 | Amerasia International Technology Inc. | Contact module, as for a smart card, and method for making same |
TW200941861A (en) * | 2007-12-10 | 2009-10-01 | Renesas Tech Corp | Sim adapter and sim card |
CN102117929A (zh) * | 2010-01-05 | 2011-07-06 | 三星Sdi株式会社 | 二次电池和智能卡 |
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